1//=- X86SchedIceLake.td - X86 Ice Lake Scheduling ------------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Ice Lake to support 10// instruction scheduling and other instruction cost heuristics. 11// 12// TODO: This is mainly a copy X86SchedSkylakeServer.td, but allows us to 13// iteratively improve scheduling handling toward better modelling the 14// Ice Lake (Sunny/Cypress Cove) microarchitecture. 15// 16//===----------------------------------------------------------------------===// 17 18def IceLakeModel : SchedMachineModel { 19 // All x86 instructions are modeled as a single micro-op, and Ice Lake can 20 // decode 6 instructions per cycle. 21 let IssueWidth = 6; 22 let MicroOpBufferSize = 224; // Based on the reorder buffer. 23 let LoadLatency = 5; 24 let MispredictPenalty = 14; 25 26 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 27 let LoopMicroOpBufferSize = 50; 28 29 // This flag is set to allow the scheduler to assign a default model to 30 // unrecognized opcodes. 31 let CompleteModel = 0; 32} 33 34let SchedModel = IceLakeModel in { 35 36// Ice Lake can issue micro-ops to 8 different ports in one cycle. 37 38// Ports 0, 1, 5, and 6 handle all computation. 39// Ports 4 and 9 gets the data half of stores. Store data can be available later 40// than the store address, but since we don't model the latency of stores, we 41// can ignore that. 42// Ports 2 and 3 are identical. They handle loads and address calculations. 43// Ports 7 and 8 are identical. They handle stores address calculations. 44def ICXPort0 : ProcResource<1>; 45def ICXPort1 : ProcResource<1>; 46def ICXPort2 : ProcResource<1>; 47def ICXPort3 : ProcResource<1>; 48def ICXPort4 : ProcResource<1>; 49def ICXPort5 : ProcResource<1>; 50def ICXPort6 : ProcResource<1>; 51def ICXPort7 : ProcResource<1>; 52def ICXPort8 : ProcResource<1>; 53def ICXPort9 : ProcResource<1>; 54 55// Many micro-ops are capable of issuing on multiple ports. 56def ICXPort01 : ProcResGroup<[ICXPort0, ICXPort1]>; 57def ICXPort23 : ProcResGroup<[ICXPort2, ICXPort3]>; 58def ICXPort237 : ProcResGroup<[ICXPort2, ICXPort3, ICXPort7]>; 59def ICXPort04 : ProcResGroup<[ICXPort0, ICXPort4]>; 60def ICXPort05 : ProcResGroup<[ICXPort0, ICXPort5]>; 61def ICXPort06 : ProcResGroup<[ICXPort0, ICXPort6]>; 62def ICXPort15 : ProcResGroup<[ICXPort1, ICXPort5]>; 63def ICXPort16 : ProcResGroup<[ICXPort1, ICXPort6]>; 64def ICXPort49 : ProcResGroup<[ICXPort4, ICXPort9]>; 65def ICXPort56 : ProcResGroup<[ICXPort5, ICXPort6]>; 66def ICXPort78 : ProcResGroup<[ICXPort7, ICXPort8]>; 67def ICXPort015 : ProcResGroup<[ICXPort0, ICXPort1, ICXPort5]>; 68def ICXPort056 : ProcResGroup<[ICXPort0, ICXPort5, ICXPort6]>; 69def ICXPort0156: ProcResGroup<[ICXPort0, ICXPort1, ICXPort5, ICXPort6]>; 70 71def ICXDivider : ProcResource<1>; // Integer division issued on port 0. 72// FP division and sqrt on port 0. 73def ICXFPDivider : ProcResource<1>; 74 75// 60 Entry Unified Scheduler 76def ICXPortAny : ProcResGroup<[ICXPort0, ICXPort1, ICXPort2, ICXPort3, ICXPort4, 77 ICXPort5, ICXPort6, ICXPort7, ICXPort8, ICXPort9]> { 78 let BufferSize=60; 79} 80 81// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 82// cycles after the memory operand. 83def : ReadAdvance<ReadAfterLd, 5>; 84 85// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 86// until 5/6/7 cycles after the memory operand. 87def : ReadAdvance<ReadAfterVecLd, 5>; 88def : ReadAdvance<ReadAfterVecXLd, 6>; 89def : ReadAdvance<ReadAfterVecYLd, 7>; 90 91def : ReadAdvance<ReadInt2Fpu, 0>; 92 93// Many SchedWrites are defined in pairs with and without a folded load. 94// Instructions with folded loads are usually micro-fused, so they only appear 95// as two micro-ops when queued in the reservation station. 96// This multiclass defines the resource usage for variants with and without 97// folded loads. 98multiclass ICXWriteResPair<X86FoldableSchedWrite SchedRW, 99 list<ProcResourceKind> ExePorts, 100 int Lat, list<int> Res = [1], int UOps = 1, 101 int LoadLat = 5> { 102 // Register variant is using a single cycle on ExePort. 103 def : WriteRes<SchedRW, ExePorts> { 104 let Latency = Lat; 105 let ResourceCycles = Res; 106 let NumMicroOps = UOps; 107 } 108 109 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 110 // the latency (default = 5). 111 def : WriteRes<SchedRW.Folded, !listconcat([ICXPort23], ExePorts)> { 112 let Latency = !add(Lat, LoadLat); 113 let ResourceCycles = !listconcat([1], Res); 114 let NumMicroOps = !add(UOps, 1); 115 } 116} 117 118// A folded store needs a cycle on port 4 for the store data, and an extra port 119// 2/3/7 cycle to recompute the address. 120def : WriteRes<WriteRMW, [ICXPort237,ICXPort4]>; 121 122// Arithmetic. 123defm : ICXWriteResPair<WriteALU, [ICXPort0156], 1>; // Simple integer ALU op. 124defm : ICXWriteResPair<WriteADC, [ICXPort06], 1>; // Integer ALU + flags op. 125 126// Integer multiplication. 127defm : ICXWriteResPair<WriteIMul8, [ICXPort1], 3>; 128defm : ICXWriteResPair<WriteIMul16, [ICXPort1,ICXPort06,ICXPort0156], 4, [1,1,2], 4>; 129defm : X86WriteRes<WriteIMul16Imm, [ICXPort1,ICXPort0156], 4, [1,1], 2>; 130defm : X86WriteRes<WriteIMul16ImmLd, [ICXPort1,ICXPort0156,ICXPort23], 8, [1,1,1], 3>; 131defm : X86WriteRes<WriteIMul16Reg, [ICXPort1], 3, [1], 1>; 132defm : X86WriteRes<WriteIMul16RegLd, [ICXPort1,ICXPort0156,ICXPort23], 8, [1,1,1], 3>; 133defm : ICXWriteResPair<WriteIMul32, [ICXPort1,ICXPort06,ICXPort0156], 4, [1,1,1], 3>; 134defm : ICXWriteResPair<WriteMULX32, [ICXPort1,ICXPort06,ICXPort0156], 3, [1,1,1], 3>; 135defm : ICXWriteResPair<WriteIMul32Imm, [ICXPort1], 3>; 136defm : ICXWriteResPair<WriteIMul32Reg, [ICXPort1], 3>; 137defm : ICXWriteResPair<WriteIMul64, [ICXPort1,ICXPort5], 4, [1,1], 2>; 138defm : ICXWriteResPair<WriteMULX64, [ICXPort1,ICXPort5], 3, [1,1], 2>; 139defm : ICXWriteResPair<WriteIMul64Imm, [ICXPort1], 3>; 140defm : ICXWriteResPair<WriteIMul64Reg, [ICXPort1], 3>; 141def ICXWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 142def : WriteRes<WriteIMulHLd, []> { 143 let Latency = !add(ICXWriteIMulH.Latency, SkylakeServerModel.LoadLatency); 144} 145 146defm : X86WriteRes<WriteBSWAP32, [ICXPort15], 1, [1], 1>; 147defm : X86WriteRes<WriteBSWAP64, [ICXPort06, ICXPort15], 2, [1,1], 2>; 148defm : X86WriteRes<WriteCMPXCHG,[ICXPort06, ICXPort0156], 5, [2,3], 5>; 149defm : X86WriteRes<WriteCMPXCHGRMW,[ICXPort23,ICXPort06,ICXPort0156,ICXPort237,ICXPort4], 8, [1,2,1,1,1], 6>; 150defm : X86WriteRes<WriteXCHG, [ICXPort0156], 2, [3], 3>; 151 152// TODO: Why isn't the ICXDivider used? 153defm : ICXWriteResPair<WriteDiv8, [ICXPort0, ICXDivider], 25, [1,10], 1, 4>; 154defm : X86WriteRes<WriteDiv16, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 155defm : X86WriteRes<WriteDiv32, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 156defm : X86WriteRes<WriteDiv64, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 157defm : X86WriteRes<WriteDiv16Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 158defm : X86WriteRes<WriteDiv32Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 159defm : X86WriteRes<WriteDiv64Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 160 161defm : X86WriteRes<WriteIDiv8, [ICXPort0, ICXDivider], 25, [1,10], 1>; 162defm : X86WriteRes<WriteIDiv16, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 163defm : X86WriteRes<WriteIDiv32, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 164defm : X86WriteRes<WriteIDiv64, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 165defm : X86WriteRes<WriteIDiv8Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 166defm : X86WriteRes<WriteIDiv16Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 167defm : X86WriteRes<WriteIDiv32Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 168defm : X86WriteRes<WriteIDiv64Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 169 170defm : ICXWriteResPair<WriteCRC32, [ICXPort1], 3>; 171 172def : WriteRes<WriteLEA, [ICXPort15]>; // LEA instructions can't fold loads. 173 174defm : ICXWriteResPair<WriteCMOV, [ICXPort06], 1, [1], 1>; // Conditional move. 175defm : X86WriteRes<WriteFCMOV, [ICXPort1], 3, [1], 1>; // x87 conditional move. 176def : WriteRes<WriteSETCC, [ICXPort06]>; // Setcc. 177def : WriteRes<WriteSETCCStore, [ICXPort06,ICXPort4,ICXPort237]> { 178 let Latency = 2; 179 let NumMicroOps = 3; 180} 181defm : X86WriteRes<WriteLAHFSAHF, [ICXPort06], 1, [1], 1>; 182defm : X86WriteRes<WriteBitTest, [ICXPort06], 1, [1], 1>; 183defm : X86WriteRes<WriteBitTestImmLd, [ICXPort06,ICXPort23], 6, [1,1], 2>; 184defm : X86WriteRes<WriteBitTestRegLd, [ICXPort0156,ICXPort23], 6, [1,1], 2>; 185defm : X86WriteRes<WriteBitTestSet, [ICXPort06], 1, [1], 1>; 186defm : X86WriteRes<WriteBitTestSetImmLd, [ICXPort06,ICXPort23], 5, [1,1], 3>; 187defm : X86WriteRes<WriteBitTestSetRegLd, [ICXPort0156,ICXPort23], 5, [1,1], 2>; 188 189// Integer shifts and rotates. 190defm : ICXWriteResPair<WriteShift, [ICXPort06], 1>; 191defm : ICXWriteResPair<WriteShiftCL, [ICXPort06], 3, [3], 3>; 192defm : ICXWriteResPair<WriteRotate, [ICXPort06], 1, [1], 1>; 193defm : ICXWriteResPair<WriteRotateCL, [ICXPort06], 3, [3], 3>; 194 195// SHLD/SHRD. 196defm : X86WriteRes<WriteSHDrri, [ICXPort1], 3, [1], 1>; 197defm : X86WriteRes<WriteSHDrrcl,[ICXPort1,ICXPort06,ICXPort0156], 6, [1, 2, 1], 4>; 198defm : X86WriteRes<WriteSHDmri, [ICXPort1,ICXPort23,ICXPort237,ICXPort0156], 9, [1, 1, 1, 1], 4>; 199defm : X86WriteRes<WriteSHDmrcl,[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort0156], 11, [1, 1, 1, 2, 1], 6>; 200 201// Bit counts. 202defm : ICXWriteResPair<WriteBSF, [ICXPort1], 3>; 203defm : ICXWriteResPair<WriteBSR, [ICXPort1], 3>; 204defm : ICXWriteResPair<WriteLZCNT, [ICXPort1], 3>; 205defm : ICXWriteResPair<WriteTZCNT, [ICXPort1], 3>; 206defm : ICXWriteResPair<WritePOPCNT, [ICXPort1], 3>; 207 208// BMI1 BEXTR/BLS, BMI2 BZHI 209defm : ICXWriteResPair<WriteBEXTR, [ICXPort06,ICXPort15], 2, [1,1], 2>; 210defm : ICXWriteResPair<WriteBLS, [ICXPort15], 1>; 211defm : ICXWriteResPair<WriteBZHI, [ICXPort15], 1>; 212 213// Loads, stores, and moves, not folded with other operations. 214defm : X86WriteRes<WriteLoad, [ICXPort23], 5, [1], 1>; 215defm : X86WriteRes<WriteStore, [ICXPort237, ICXPort4], 1, [1,1], 1>; 216defm : X86WriteRes<WriteStoreNT, [ICXPort237, ICXPort4], 1, [1,1], 2>; 217defm : X86WriteRes<WriteMove, [ICXPort0156], 1, [1], 1>; 218 219// Model the effect of clobbering the read-write mask operand of the GATHER operation. 220// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 221defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 222 223// Idioms that clear a register, like xorps %xmm0, %xmm0. 224// These can often bypass execution ports completely. 225def : WriteRes<WriteZero, []>; 226 227// Branches don't produce values, so they have no latency, but they still 228// consume resources. Indirect branches can fold loads. 229defm : ICXWriteResPair<WriteJump, [ICXPort06], 1>; 230 231// Floating point. This covers both scalar and vector operations. 232defm : X86WriteRes<WriteFLD0, [ICXPort05], 1, [1], 1>; 233defm : X86WriteRes<WriteFLD1, [ICXPort05], 1, [2], 2>; 234defm : X86WriteRes<WriteFLDC, [ICXPort05], 1, [2], 2>; 235defm : X86WriteRes<WriteFLoad, [ICXPort23], 5, [1], 1>; 236defm : X86WriteRes<WriteFLoadX, [ICXPort23], 6, [1], 1>; 237defm : X86WriteRes<WriteFLoadY, [ICXPort23], 7, [1], 1>; 238defm : X86WriteRes<WriteFMaskedLoad, [ICXPort23,ICXPort015], 7, [1,1], 2>; 239defm : X86WriteRes<WriteFMaskedLoadY, [ICXPort23,ICXPort015], 8, [1,1], 2>; 240defm : X86WriteRes<WriteFStore, [ICXPort237,ICXPort4], 1, [1,1], 2>; 241defm : X86WriteRes<WriteFStoreX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 242defm : X86WriteRes<WriteFStoreY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 243defm : X86WriteRes<WriteFStoreNT, [ICXPort237,ICXPort4], 1, [1,1], 2>; 244defm : X86WriteRes<WriteFStoreNTX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 245defm : X86WriteRes<WriteFStoreNTY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 246 247defm : X86WriteRes<WriteFMaskedStore32, [ICXPort237,ICXPort0], 2, [1,1], 2>; 248defm : X86WriteRes<WriteFMaskedStore32Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 249defm : X86WriteRes<WriteFMaskedStore64, [ICXPort237,ICXPort0], 2, [1,1], 2>; 250defm : X86WriteRes<WriteFMaskedStore64Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 251 252defm : X86WriteRes<WriteFMove, [ICXPort015], 1, [1], 1>; 253defm : X86WriteRes<WriteFMoveX, [ICXPort015], 1, [1], 1>; 254defm : X86WriteRes<WriteFMoveY, [ICXPort015], 1, [1], 1>; 255defm : X86WriteRes<WriteEMMS, [ICXPort05,ICXPort0156], 10, [9,1], 10>; 256 257defm : ICXWriteResPair<WriteFAdd, [ICXPort01], 4, [1], 1, 5>; // Floating point add/sub. 258defm : ICXWriteResPair<WriteFAddX, [ICXPort01], 4, [1], 1, 6>; 259defm : ICXWriteResPair<WriteFAddY, [ICXPort01], 4, [1], 1, 7>; 260defm : ICXWriteResPair<WriteFAddZ, [ICXPort05], 4, [1], 1, 7>; 261defm : ICXWriteResPair<WriteFAdd64, [ICXPort01], 4, [1], 1, 5>; // Floating point double add/sub. 262defm : ICXWriteResPair<WriteFAdd64X, [ICXPort01], 4, [1], 1, 6>; 263defm : ICXWriteResPair<WriteFAdd64Y, [ICXPort01], 4, [1], 1, 7>; 264defm : ICXWriteResPair<WriteFAdd64Z, [ICXPort05], 4, [1], 1, 7>; 265 266defm : ICXWriteResPair<WriteFCmp, [ICXPort01], 4, [1], 1, 5>; // Floating point compare. 267defm : ICXWriteResPair<WriteFCmpX, [ICXPort01], 4, [1], 1, 6>; 268defm : ICXWriteResPair<WriteFCmpY, [ICXPort01], 4, [1], 1, 7>; 269defm : ICXWriteResPair<WriteFCmpZ, [ICXPort05], 4, [1], 1, 7>; 270defm : ICXWriteResPair<WriteFCmp64, [ICXPort01], 4, [1], 1, 5>; // Floating point double compare. 271defm : ICXWriteResPair<WriteFCmp64X, [ICXPort01], 4, [1], 1, 6>; 272defm : ICXWriteResPair<WriteFCmp64Y, [ICXPort01], 4, [1], 1, 7>; 273defm : ICXWriteResPair<WriteFCmp64Z, [ICXPort05], 4, [1], 1, 7>; 274 275defm : ICXWriteResPair<WriteFCom, [ICXPort0], 2>; // Floating point compare to flags (X87). 276defm : ICXWriteResPair<WriteFComX, [ICXPort0], 2>; // Floating point compare to flags (SSE). 277 278defm : ICXWriteResPair<WriteFMul, [ICXPort01], 4, [1], 1, 5>; // Floating point multiplication. 279defm : ICXWriteResPair<WriteFMulX, [ICXPort01], 4, [1], 1, 6>; 280defm : ICXWriteResPair<WriteFMulY, [ICXPort01], 4, [1], 1, 7>; 281defm : ICXWriteResPair<WriteFMulZ, [ICXPort05], 4, [1], 1, 7>; 282defm : ICXWriteResPair<WriteFMul64, [ICXPort01], 4, [1], 1, 5>; // Floating point double multiplication. 283defm : ICXWriteResPair<WriteFMul64X, [ICXPort01], 4, [1], 1, 6>; 284defm : ICXWriteResPair<WriteFMul64Y, [ICXPort01], 4, [1], 1, 7>; 285defm : ICXWriteResPair<WriteFMul64Z, [ICXPort05], 4, [1], 1, 7>; 286 287defm : ICXWriteResPair<WriteFDiv, [ICXPort0,ICXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 288//defm : ICXWriteResPair<WriteFDivX, [ICXPort0,ICXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles. 289defm : ICXWriteResPair<WriteFDivY, [ICXPort0,ICXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles. 290defm : ICXWriteResPair<WriteFDivZ, [ICXPort0,ICXPort5,ICXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles. 291//defm : ICXWriteResPair<WriteFDiv64, [ICXPort0,ICXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 292//defm : ICXWriteResPair<WriteFDiv64X, [ICXPort0,ICXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles. 293//defm : ICXWriteResPair<WriteFDiv64Y, [ICXPort0,ICXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles. 294defm : ICXWriteResPair<WriteFDiv64Z, [ICXPort0,ICXPort5,ICXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles. 295 296defm : ICXWriteResPair<WriteFSqrt, [ICXPort0,ICXFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 297defm : ICXWriteResPair<WriteFSqrtX, [ICXPort0,ICXFPDivider], 12, [1,3], 1, 6>; 298defm : ICXWriteResPair<WriteFSqrtY, [ICXPort0,ICXFPDivider], 12, [1,6], 1, 7>; 299defm : ICXWriteResPair<WriteFSqrtZ, [ICXPort0,ICXPort5,ICXFPDivider], 20, [2,1,12], 3, 7>; 300defm : ICXWriteResPair<WriteFSqrt64, [ICXPort0,ICXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 301defm : ICXWriteResPair<WriteFSqrt64X, [ICXPort0,ICXFPDivider], 18, [1,6], 1, 6>; 302defm : ICXWriteResPair<WriteFSqrt64Y, [ICXPort0,ICXFPDivider], 18, [1,12],1, 7>; 303defm : ICXWriteResPair<WriteFSqrt64Z, [ICXPort0,ICXPort5,ICXFPDivider], 32, [2,1,24], 3, 7>; 304defm : ICXWriteResPair<WriteFSqrt80, [ICXPort0,ICXFPDivider], 21, [1,7]>; // Floating point long double square root. 305 306defm : ICXWriteResPair<WriteFRcp, [ICXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 307defm : ICXWriteResPair<WriteFRcpX, [ICXPort0], 4, [1], 1, 6>; 308defm : ICXWriteResPair<WriteFRcpY, [ICXPort0], 4, [1], 1, 7>; 309defm : ICXWriteResPair<WriteFRcpZ, [ICXPort0,ICXPort5], 4, [2,1], 3, 7>; 310 311defm : ICXWriteResPair<WriteFRsqrt, [ICXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 312defm : ICXWriteResPair<WriteFRsqrtX,[ICXPort0], 4, [1], 1, 6>; 313defm : ICXWriteResPair<WriteFRsqrtY,[ICXPort0], 4, [1], 1, 7>; 314defm : ICXWriteResPair<WriteFRsqrtZ,[ICXPort0,ICXPort5], 9, [2,1], 3, 7>; 315 316defm : ICXWriteResPair<WriteFMA, [ICXPort01], 4, [1], 1, 5>; // Fused Multiply Add. 317defm : ICXWriteResPair<WriteFMAX, [ICXPort01], 4, [1], 1, 6>; 318defm : ICXWriteResPair<WriteFMAY, [ICXPort01], 4, [1], 1, 7>; 319defm : ICXWriteResPair<WriteFMAZ, [ICXPort05], 4, [1], 1, 7>; 320defm : ICXWriteResPair<WriteDPPD, [ICXPort5,ICXPort015], 9, [1,2], 3, 6>; // Floating point double dot product. 321defm : ICXWriteResPair<WriteDPPS, [ICXPort5,ICXPort015], 13, [1,3], 4, 6>; 322defm : ICXWriteResPair<WriteDPPSY,[ICXPort5,ICXPort015], 13, [1,3], 4, 7>; 323defm : ICXWriteResPair<WriteDPPSZ,[ICXPort5,ICXPort015], 13, [1,3], 4, 7>; 324defm : ICXWriteResPair<WriteFSign, [ICXPort0], 1>; // Floating point fabs/fchs. 325defm : ICXWriteResPair<WriteFRnd, [ICXPort01], 8, [2], 2, 6>; // Floating point rounding. 326defm : ICXWriteResPair<WriteFRndY, [ICXPort01], 8, [2], 2, 7>; 327defm : ICXWriteResPair<WriteFRndZ, [ICXPort05], 8, [2], 2, 7>; 328defm : ICXWriteResPair<WriteFLogic, [ICXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 329defm : ICXWriteResPair<WriteFLogicY, [ICXPort015], 1, [1], 1, 7>; 330defm : ICXWriteResPair<WriteFLogicZ, [ICXPort05], 1, [1], 1, 7>; 331defm : ICXWriteResPair<WriteFTest, [ICXPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 332defm : ICXWriteResPair<WriteFTestY, [ICXPort0], 2, [1], 1, 7>; 333defm : ICXWriteResPair<WriteFTestZ, [ICXPort0], 2, [1], 1, 7>; 334defm : ICXWriteResPair<WriteFShuffle, [ICXPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 335defm : ICXWriteResPair<WriteFShuffleY, [ICXPort5], 1, [1], 1, 7>; 336defm : ICXWriteResPair<WriteFShuffleZ, [ICXPort5], 1, [1], 1, 7>; 337defm : ICXWriteResPair<WriteFVarShuffle, [ICXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles. 338defm : ICXWriteResPair<WriteFVarShuffleY, [ICXPort5], 1, [1], 1, 7>; 339defm : ICXWriteResPair<WriteFVarShuffleZ, [ICXPort5], 1, [1], 1, 7>; 340defm : ICXWriteResPair<WriteFBlend, [ICXPort015], 1, [1], 1, 6>; // Floating point vector blends. 341defm : ICXWriteResPair<WriteFBlendY,[ICXPort015], 1, [1], 1, 7>; 342defm : ICXWriteResPair<WriteFBlendZ,[ICXPort015], 1, [1], 1, 7>; 343defm : ICXWriteResPair<WriteFVarBlend, [ICXPort015], 2, [2], 2, 6>; // Fp vector variable blends. 344defm : ICXWriteResPair<WriteFVarBlendY,[ICXPort015], 2, [2], 2, 7>; 345defm : ICXWriteResPair<WriteFVarBlendZ,[ICXPort015], 2, [2], 2, 7>; 346 347// FMA Scheduling helper class. 348// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 349 350// Vector integer operations. 351defm : X86WriteRes<WriteVecLoad, [ICXPort23], 5, [1], 1>; 352defm : X86WriteRes<WriteVecLoadX, [ICXPort23], 6, [1], 1>; 353defm : X86WriteRes<WriteVecLoadY, [ICXPort23], 7, [1], 1>; 354defm : X86WriteRes<WriteVecLoadNT, [ICXPort23], 6, [1], 1>; 355defm : X86WriteRes<WriteVecLoadNTY, [ICXPort23], 7, [1], 1>; 356defm : X86WriteRes<WriteVecMaskedLoad, [ICXPort23,ICXPort015], 7, [1,1], 2>; 357defm : X86WriteRes<WriteVecMaskedLoadY, [ICXPort23,ICXPort015], 8, [1,1], 2>; 358defm : X86WriteRes<WriteVecStore, [ICXPort237,ICXPort4], 1, [1,1], 2>; 359defm : X86WriteRes<WriteVecStoreX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 360defm : X86WriteRes<WriteVecStoreY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 361defm : X86WriteRes<WriteVecStoreNT, [ICXPort237,ICXPort4], 1, [1,1], 2>; 362defm : X86WriteRes<WriteVecStoreNTY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 363defm : X86WriteRes<WriteVecMaskedStore32, [ICXPort237,ICXPort0], 2, [1,1], 2>; 364defm : X86WriteRes<WriteVecMaskedStore32Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 365defm : X86WriteRes<WriteVecMaskedStore64, [ICXPort237,ICXPort0], 2, [1,1], 2>; 366defm : X86WriteRes<WriteVecMaskedStore64Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 367defm : X86WriteRes<WriteVecMove, [ICXPort05], 1, [1], 1>; 368defm : X86WriteRes<WriteVecMoveX, [ICXPort015], 1, [1], 1>; 369defm : X86WriteRes<WriteVecMoveY, [ICXPort015], 1, [1], 1>; 370defm : X86WriteRes<WriteVecMoveToGpr, [ICXPort0], 2, [1], 1>; 371defm : X86WriteRes<WriteVecMoveFromGpr, [ICXPort5], 1, [1], 1>; 372 373defm : ICXWriteResPair<WriteVecALU, [ICXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 374defm : ICXWriteResPair<WriteVecALUX, [ICXPort01], 1, [1], 1, 6>; 375defm : ICXWriteResPair<WriteVecALUY, [ICXPort01], 1, [1], 1, 7>; 376defm : ICXWriteResPair<WriteVecALUZ, [ICXPort0], 1, [1], 1, 7>; 377defm : ICXWriteResPair<WriteVecLogic, [ICXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 378defm : ICXWriteResPair<WriteVecLogicX,[ICXPort015], 1, [1], 1, 6>; 379defm : ICXWriteResPair<WriteVecLogicY,[ICXPort015], 1, [1], 1, 7>; 380defm : ICXWriteResPair<WriteVecLogicZ,[ICXPort05], 1, [1], 1, 7>; 381defm : ICXWriteResPair<WriteVecTest, [ICXPort0,ICXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 382defm : ICXWriteResPair<WriteVecTestY, [ICXPort0,ICXPort5], 3, [1,1], 2, 7>; 383defm : ICXWriteResPair<WriteVecTestZ, [ICXPort0,ICXPort5], 3, [1,1], 2, 7>; 384defm : ICXWriteResPair<WriteVecIMul, [ICXPort0], 5, [1], 1, 5>; // Vector integer multiply. 385defm : ICXWriteResPair<WriteVecIMulX, [ICXPort01], 5, [1], 1, 6>; 386defm : ICXWriteResPair<WriteVecIMulY, [ICXPort01], 5, [1], 1, 7>; 387defm : ICXWriteResPair<WriteVecIMulZ, [ICXPort05], 5, [1], 1, 7>; 388defm : ICXWriteResPair<WritePMULLD, [ICXPort01], 10, [2], 2, 6>; // Vector PMULLD. 389defm : ICXWriteResPair<WritePMULLDY, [ICXPort01], 10, [2], 2, 7>; 390defm : ICXWriteResPair<WritePMULLDZ, [ICXPort05], 10, [2], 2, 7>; 391defm : ICXWriteResPair<WriteShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector shuffles. 392defm : ICXWriteResPair<WriteShuffleX, [ICXPort5], 1, [1], 1, 6>; 393defm : ICXWriteResPair<WriteShuffleY, [ICXPort5], 1, [1], 1, 7>; 394defm : ICXWriteResPair<WriteShuffleZ, [ICXPort5], 1, [1], 1, 7>; 395defm : ICXWriteResPair<WriteVarShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector variable shuffles. 396defm : ICXWriteResPair<WriteVarShuffleX, [ICXPort5], 1, [1], 1, 6>; 397defm : ICXWriteResPair<WriteVarShuffleY, [ICXPort5], 1, [1], 1, 7>; 398defm : ICXWriteResPair<WriteVarShuffleZ, [ICXPort5], 1, [1], 1, 7>; 399defm : ICXWriteResPair<WriteBlend, [ICXPort5], 1, [1], 1, 6>; // Vector blends. 400defm : ICXWriteResPair<WriteBlendY,[ICXPort5], 1, [1], 1, 7>; 401defm : ICXWriteResPair<WriteBlendZ,[ICXPort5], 1, [1], 1, 7>; 402defm : ICXWriteResPair<WriteVarBlend, [ICXPort015], 2, [2], 2, 6>; // Vector variable blends. 403defm : ICXWriteResPair<WriteVarBlendY,[ICXPort015], 2, [2], 2, 6>; 404defm : ICXWriteResPair<WriteVarBlendZ,[ICXPort05], 2, [1], 1, 6>; 405defm : ICXWriteResPair<WriteMPSAD, [ICXPort5], 4, [2], 2, 6>; // Vector MPSAD. 406defm : ICXWriteResPair<WriteMPSADY, [ICXPort5], 4, [2], 2, 7>; 407defm : ICXWriteResPair<WriteMPSADZ, [ICXPort5], 4, [2], 2, 7>; 408defm : ICXWriteResPair<WritePSADBW, [ICXPort5], 3, [1], 1, 5>; // Vector PSADBW. 409defm : ICXWriteResPair<WritePSADBWX, [ICXPort5], 3, [1], 1, 6>; 410defm : ICXWriteResPair<WritePSADBWY, [ICXPort5], 3, [1], 1, 7>; 411defm : ICXWriteResPair<WritePSADBWZ, [ICXPort5], 3, [1], 1, 7>; 412defm : ICXWriteResPair<WritePHMINPOS, [ICXPort0], 4, [1], 1, 6>; // Vector PHMINPOS. 413 414// Vector integer shifts. 415defm : ICXWriteResPair<WriteVecShift, [ICXPort0], 1, [1], 1, 5>; 416defm : X86WriteRes<WriteVecShiftX, [ICXPort5,ICXPort01], 2, [1,1], 2>; 417defm : X86WriteRes<WriteVecShiftY, [ICXPort5,ICXPort01], 4, [1,1], 2>; 418defm : X86WriteRes<WriteVecShiftZ, [ICXPort5,ICXPort0], 4, [1,1], 2>; 419defm : X86WriteRes<WriteVecShiftXLd, [ICXPort01,ICXPort23], 7, [1,1], 2>; 420defm : X86WriteRes<WriteVecShiftYLd, [ICXPort01,ICXPort23], 8, [1,1], 2>; 421defm : X86WriteRes<WriteVecShiftZLd, [ICXPort0,ICXPort23], 8, [1,1], 2>; 422 423defm : ICXWriteResPair<WriteVecShiftImm, [ICXPort0], 1, [1], 1, 5>; 424defm : ICXWriteResPair<WriteVecShiftImmX, [ICXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts. 425defm : ICXWriteResPair<WriteVecShiftImmY, [ICXPort01], 1, [1], 1, 7>; 426defm : ICXWriteResPair<WriteVecShiftImmZ, [ICXPort0], 1, [1], 1, 7>; 427defm : ICXWriteResPair<WriteVarVecShift, [ICXPort01], 1, [1], 1, 6>; // Variable vector shifts. 428defm : ICXWriteResPair<WriteVarVecShiftY, [ICXPort01], 1, [1], 1, 7>; 429defm : ICXWriteResPair<WriteVarVecShiftZ, [ICXPort0], 1, [1], 1, 7>; 430 431// Vector insert/extract operations. 432def : WriteRes<WriteVecInsert, [ICXPort5]> { 433 let Latency = 2; 434 let NumMicroOps = 2; 435 let ResourceCycles = [2]; 436} 437def : WriteRes<WriteVecInsertLd, [ICXPort5,ICXPort23]> { 438 let Latency = 6; 439 let NumMicroOps = 2; 440} 441def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 442 443def : WriteRes<WriteVecExtract, [ICXPort0,ICXPort5]> { 444 let Latency = 3; 445 let NumMicroOps = 2; 446} 447def : WriteRes<WriteVecExtractSt, [ICXPort4,ICXPort5,ICXPort237]> { 448 let Latency = 2; 449 let NumMicroOps = 3; 450} 451 452// Conversion between integer and float. 453defm : ICXWriteResPair<WriteCvtSS2I, [ICXPort01], 6, [2], 2>; // Needs more work: DD vs DQ. 454defm : ICXWriteResPair<WriteCvtPS2I, [ICXPort01], 3>; 455defm : ICXWriteResPair<WriteCvtPS2IY, [ICXPort01], 3>; 456defm : ICXWriteResPair<WriteCvtPS2IZ, [ICXPort05], 3>; 457defm : ICXWriteResPair<WriteCvtSD2I, [ICXPort01], 6, [2], 2>; 458defm : ICXWriteResPair<WriteCvtPD2I, [ICXPort01], 3>; 459defm : ICXWriteResPair<WriteCvtPD2IY, [ICXPort01], 3>; 460defm : ICXWriteResPair<WriteCvtPD2IZ, [ICXPort05], 3>; 461 462defm : ICXWriteResPair<WriteCvtI2SS, [ICXPort1], 4>; 463defm : ICXWriteResPair<WriteCvtI2PS, [ICXPort01], 4>; 464defm : ICXWriteResPair<WriteCvtI2PSY, [ICXPort01], 4>; 465defm : ICXWriteResPair<WriteCvtI2PSZ, [ICXPort05], 4>; // Needs more work: DD vs DQ. 466defm : ICXWriteResPair<WriteCvtI2SD, [ICXPort1], 4>; 467defm : ICXWriteResPair<WriteCvtI2PD, [ICXPort01], 4>; 468defm : ICXWriteResPair<WriteCvtI2PDY, [ICXPort01], 4>; 469defm : ICXWriteResPair<WriteCvtI2PDZ, [ICXPort05], 4>; 470 471defm : ICXWriteResPair<WriteCvtSS2SD, [ICXPort1], 3>; 472defm : ICXWriteResPair<WriteCvtPS2PD, [ICXPort1], 3>; 473defm : ICXWriteResPair<WriteCvtPS2PDY, [ICXPort5,ICXPort01], 3, [1,1], 2>; 474defm : ICXWriteResPair<WriteCvtPS2PDZ, [ICXPort05], 3, [2], 2>; 475defm : ICXWriteResPair<WriteCvtSD2SS, [ICXPort1], 3>; 476defm : ICXWriteResPair<WriteCvtPD2PS, [ICXPort1], 3>; 477defm : ICXWriteResPair<WriteCvtPD2PSY, [ICXPort5,ICXPort01], 3, [1,1], 2>; 478defm : ICXWriteResPair<WriteCvtPD2PSZ, [ICXPort05], 3, [2], 2>; 479 480defm : X86WriteRes<WriteCvtPH2PS, [ICXPort5,ICXPort01], 5, [1,1], 2>; 481defm : X86WriteRes<WriteCvtPH2PSY, [ICXPort5,ICXPort01], 7, [1,1], 2>; 482defm : X86WriteRes<WriteCvtPH2PSZ, [ICXPort5,ICXPort0], 7, [1,1], 2>; 483defm : X86WriteRes<WriteCvtPH2PSLd, [ICXPort23,ICXPort01], 9, [1,1], 2>; 484defm : X86WriteRes<WriteCvtPH2PSYLd, [ICXPort23,ICXPort01], 10, [1,1], 2>; 485defm : X86WriteRes<WriteCvtPH2PSZLd, [ICXPort23,ICXPort05], 10, [1,1], 2>; 486 487defm : X86WriteRes<WriteCvtPS2PH, [ICXPort5,ICXPort01], 5, [1,1], 2>; 488defm : X86WriteRes<WriteCvtPS2PHY, [ICXPort5,ICXPort01], 7, [1,1], 2>; 489defm : X86WriteRes<WriteCvtPS2PHZ, [ICXPort5,ICXPort05], 7, [1,1], 2>; 490defm : X86WriteRes<WriteCvtPS2PHSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort01], 6, [1,1,1,1], 4>; 491defm : X86WriteRes<WriteCvtPS2PHYSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort01], 8, [1,1,1,1], 4>; 492defm : X86WriteRes<WriteCvtPS2PHZSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort05], 8, [1,1,1,1], 4>; 493 494// Strings instructions. 495 496// Packed Compare Implicit Length Strings, Return Mask 497def : WriteRes<WritePCmpIStrM, [ICXPort0]> { 498 let Latency = 10; 499 let NumMicroOps = 3; 500 let ResourceCycles = [3]; 501} 502def : WriteRes<WritePCmpIStrMLd, [ICXPort0, ICXPort23]> { 503 let Latency = 16; 504 let NumMicroOps = 4; 505 let ResourceCycles = [3,1]; 506} 507 508// Packed Compare Explicit Length Strings, Return Mask 509def : WriteRes<WritePCmpEStrM, [ICXPort0, ICXPort5, ICXPort015, ICXPort0156]> { 510 let Latency = 19; 511 let NumMicroOps = 9; 512 let ResourceCycles = [4,3,1,1]; 513} 514def : WriteRes<WritePCmpEStrMLd, [ICXPort0, ICXPort5, ICXPort23, ICXPort015, ICXPort0156]> { 515 let Latency = 25; 516 let NumMicroOps = 10; 517 let ResourceCycles = [4,3,1,1,1]; 518} 519 520// Packed Compare Implicit Length Strings, Return Index 521def : WriteRes<WritePCmpIStrI, [ICXPort0]> { 522 let Latency = 10; 523 let NumMicroOps = 3; 524 let ResourceCycles = [3]; 525} 526def : WriteRes<WritePCmpIStrILd, [ICXPort0, ICXPort23]> { 527 let Latency = 16; 528 let NumMicroOps = 4; 529 let ResourceCycles = [3,1]; 530} 531 532// Packed Compare Explicit Length Strings, Return Index 533def : WriteRes<WritePCmpEStrI, [ICXPort0,ICXPort5,ICXPort0156]> { 534 let Latency = 18; 535 let NumMicroOps = 8; 536 let ResourceCycles = [4,3,1]; 537} 538def : WriteRes<WritePCmpEStrILd, [ICXPort0, ICXPort5, ICXPort23, ICXPort0156]> { 539 let Latency = 24; 540 let NumMicroOps = 9; 541 let ResourceCycles = [4,3,1,1]; 542} 543 544// MOVMSK Instructions. 545def : WriteRes<WriteFMOVMSK, [ICXPort0]> { let Latency = 2; } 546def : WriteRes<WriteVecMOVMSK, [ICXPort0]> { let Latency = 2; } 547def : WriteRes<WriteVecMOVMSKY, [ICXPort0]> { let Latency = 2; } 548def : WriteRes<WriteMMXMOVMSK, [ICXPort0]> { let Latency = 2; } 549 550// AES instructions. 551def : WriteRes<WriteAESDecEnc, [ICXPort0]> { // Decryption, encryption. 552 let Latency = 4; 553 let NumMicroOps = 1; 554 let ResourceCycles = [1]; 555} 556def : WriteRes<WriteAESDecEncLd, [ICXPort0, ICXPort23]> { 557 let Latency = 10; 558 let NumMicroOps = 2; 559 let ResourceCycles = [1,1]; 560} 561 562def : WriteRes<WriteAESIMC, [ICXPort0]> { // InvMixColumn. 563 let Latency = 8; 564 let NumMicroOps = 2; 565 let ResourceCycles = [2]; 566} 567def : WriteRes<WriteAESIMCLd, [ICXPort0, ICXPort23]> { 568 let Latency = 14; 569 let NumMicroOps = 3; 570 let ResourceCycles = [2,1]; 571} 572 573def : WriteRes<WriteAESKeyGen, [ICXPort0,ICXPort5,ICXPort015]> { // Key Generation. 574 let Latency = 20; 575 let NumMicroOps = 11; 576 let ResourceCycles = [3,6,2]; 577} 578def : WriteRes<WriteAESKeyGenLd, [ICXPort0,ICXPort5,ICXPort23,ICXPort015]> { 579 let Latency = 25; 580 let NumMicroOps = 11; 581 let ResourceCycles = [3,6,1,1]; 582} 583 584// Carry-less multiplication instructions. 585def : WriteRes<WriteCLMul, [ICXPort5]> { 586 let Latency = 6; 587 let NumMicroOps = 1; 588 let ResourceCycles = [1]; 589} 590def : WriteRes<WriteCLMulLd, [ICXPort5, ICXPort23]> { 591 let Latency = 12; 592 let NumMicroOps = 2; 593 let ResourceCycles = [1,1]; 594} 595 596// Catch-all for expensive system instructions. 597def : WriteRes<WriteSystem, [ICXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 598 599// AVX2. 600defm : ICXWriteResPair<WriteFShuffle256, [ICXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 601defm : ICXWriteResPair<WriteFVarShuffle256, [ICXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 602defm : ICXWriteResPair<WriteShuffle256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 603defm : ICXWriteResPair<WriteVPMOV256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move. 604defm : ICXWriteResPair<WriteVarShuffle256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 605 606// Old microcoded instructions that nobody use. 607def : WriteRes<WriteMicrocoded, [ICXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 608 609// Fence instructions. 610def : WriteRes<WriteFence, [ICXPort23, ICXPort4]>; 611 612// Load/store MXCSR. 613def : WriteRes<WriteLDMXCSR, [ICXPort0,ICXPort23,ICXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 614def : WriteRes<WriteSTMXCSR, [ICXPort4,ICXPort5,ICXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 615 616// Nop, not very useful expect it provides a model for nops! 617def : WriteRes<WriteNop, []>; 618 619//////////////////////////////////////////////////////////////////////////////// 620// Horizontal add/sub instructions. 621//////////////////////////////////////////////////////////////////////////////// 622 623defm : ICXWriteResPair<WriteFHAdd, [ICXPort5,ICXPort015], 6, [2,1], 3, 6>; 624defm : ICXWriteResPair<WriteFHAddY, [ICXPort5,ICXPort015], 6, [2,1], 3, 7>; 625defm : ICXWriteResPair<WritePHAdd, [ICXPort5,ICXPort05], 3, [2,1], 3, 5>; 626defm : ICXWriteResPair<WritePHAddX, [ICXPort5,ICXPort015], 3, [2,1], 3, 6>; 627defm : ICXWriteResPair<WritePHAddY, [ICXPort5,ICXPort015], 3, [2,1], 3, 7>; 628 629// Remaining instrs. 630 631def ICXWriteResGroup1 : SchedWriteRes<[ICXPort0]> { 632 let Latency = 1; 633 let NumMicroOps = 1; 634 let ResourceCycles = [1]; 635} 636def: InstRW<[ICXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr", 637 "KANDN(B|D|Q|W)rr", 638 "KMOV(B|D|Q|W)kk", 639 "KNOT(B|D|Q|W)rr", 640 "KOR(B|D|Q|W)rr", 641 "KXNOR(B|D|Q|W)rr", 642 "KXOR(B|D|Q|W)rr", 643 "KSET0(B|D|Q|W)", // Same as KXOR 644 "KSET1(B|D|Q|W)", // Same as KXNOR 645 "MMX_PADDS(B|W)irr", 646 "MMX_PADDUS(B|W)irr", 647 "MMX_PAVG(B|W)irr", 648 "MMX_PCMPEQ(B|D|W)irr", 649 "MMX_PCMPGT(B|D|W)irr", 650 "MMX_P(MAX|MIN)SWirr", 651 "MMX_P(MAX|MIN)UBirr", 652 "MMX_PSUBS(B|W)irr", 653 "MMX_PSUBUS(B|W)irr", 654 "VPMOVB2M(Z|Z128|Z256)rr", 655 "VPMOVD2M(Z|Z128|Z256)rr", 656 "VPMOVQ2M(Z|Z128|Z256)rr", 657 "VPMOVW2M(Z|Z128|Z256)rr")>; 658 659def ICXWriteResGroup3 : SchedWriteRes<[ICXPort5]> { 660 let Latency = 1; 661 let NumMicroOps = 1; 662 let ResourceCycles = [1]; 663} 664def: InstRW<[ICXWriteResGroup3], (instregex "COM(P?)_FST0r", 665 "KMOV(B|D|Q|W)kr", 666 "UCOM_F(P?)r")>; 667 668def ICXWriteResGroup4 : SchedWriteRes<[ICXPort6]> { 669 let Latency = 1; 670 let NumMicroOps = 1; 671 let ResourceCycles = [1]; 672} 673def: InstRW<[ICXWriteResGroup4], (instregex "JMP(16|32|64)r")>; 674 675def ICXWriteResGroup6 : SchedWriteRes<[ICXPort05]> { 676 let Latency = 1; 677 let NumMicroOps = 1; 678 let ResourceCycles = [1]; 679} 680def: InstRW<[ICXWriteResGroup6], (instrs FINCSTP, FNOP)>; 681 682def ICXWriteResGroup7 : SchedWriteRes<[ICXPort06]> { 683 let Latency = 1; 684 let NumMicroOps = 1; 685 let ResourceCycles = [1]; 686} 687def: InstRW<[ICXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 688 689def ICXWriteResGroup8 : SchedWriteRes<[ICXPort15]> { 690 let Latency = 1; 691 let NumMicroOps = 1; 692 let ResourceCycles = [1]; 693} 694def: InstRW<[ICXWriteResGroup8], (instregex "ANDN(32|64)rr")>; 695 696def ICXWriteResGroup9 : SchedWriteRes<[ICXPort015]> { 697 let Latency = 1; 698 let NumMicroOps = 1; 699 let ResourceCycles = [1]; 700} 701def: InstRW<[ICXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr", 702 "VBLENDMPS(Z128|Z256)rr", 703 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr", 704 "(V?)PADD(B|D|Q|W)rr", 705 "VPBLENDD(Y?)rri", 706 "VPBLENDMB(Z128|Z256)rr", 707 "VPBLENDMD(Z128|Z256)rr", 708 "VPBLENDMQ(Z128|Z256)rr", 709 "VPBLENDMW(Z128|Z256)rr", 710 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk", 711 "VPTERNLOGD(Z|Z128|Z256)rri", 712 "VPTERNLOGQ(Z|Z128|Z256)rri")>; 713 714def ICXWriteResGroup10 : SchedWriteRes<[ICXPort0156]> { 715 let Latency = 1; 716 let NumMicroOps = 1; 717 let ResourceCycles = [1]; 718} 719def: InstRW<[ICXWriteResGroup10], (instrs CBW, CWDE, CDQE, 720 CMC, STC, 721 SGDT64m, 722 SIDT64m, 723 SMSW16m, 724 STRm, 725 SYSCALL)>; 726 727def ICXWriteResGroup11 : SchedWriteRes<[ICXPort4,ICXPort237]> { 728 let Latency = 1; 729 let NumMicroOps = 2; 730 let ResourceCycles = [1,1]; 731} 732def: InstRW<[ICXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 733def: InstRW<[ICXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk", 734 "ST_FP(32|64|80)m")>; 735 736def ICXWriteResGroup13 : SchedWriteRes<[ICXPort5]> { 737 let Latency = 2; 738 let NumMicroOps = 2; 739 let ResourceCycles = [2]; 740} 741def: InstRW<[ICXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 742 743def ICXWriteResGroup14 : SchedWriteRes<[ICXPort05]> { 744 let Latency = 2; 745 let NumMicroOps = 2; 746 let ResourceCycles = [2]; 747} 748def: InstRW<[ICXWriteResGroup14], (instrs FDECSTP, 749 MMX_MOVDQ2Qrr)>; 750 751def ICXWriteResGroup17 : SchedWriteRes<[ICXPort0156]> { 752 let Latency = 2; 753 let NumMicroOps = 2; 754 let ResourceCycles = [2]; 755} 756def: InstRW<[ICXWriteResGroup17], (instrs LFENCE, 757 WAIT, 758 XGETBV)>; 759 760def ICXWriteResGroup20 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 761 let Latency = 2; 762 let NumMicroOps = 2; 763 let ResourceCycles = [1,1]; 764} 765def: InstRW<[ICXWriteResGroup20], (instregex "CLFLUSH")>; 766 767def ICXWriteResGroup21 : SchedWriteRes<[ICXPort237,ICXPort0156]> { 768 let Latency = 2; 769 let NumMicroOps = 2; 770 let ResourceCycles = [1,1]; 771} 772def: InstRW<[ICXWriteResGroup21], (instrs SFENCE)>; 773 774def ICXWriteResGroup23 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 775 let Latency = 2; 776 let NumMicroOps = 2; 777 let ResourceCycles = [1,1]; 778} 779def: InstRW<[ICXWriteResGroup23], (instrs CWD, 780 JCXZ, JECXZ, JRCXZ, 781 ADC8i8, SBB8i8, 782 ADC16i16, SBB16i16, 783 ADC32i32, SBB32i32, 784 ADC64i32, SBB64i32)>; 785 786def ICXWriteResGroup25 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort237]> { 787 let Latency = 2; 788 let NumMicroOps = 3; 789 let ResourceCycles = [1,1,1]; 790} 791def: InstRW<[ICXWriteResGroup25], (instrs FNSTCW16m)>; 792 793def ICXWriteResGroup27 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort15]> { 794 let Latency = 2; 795 let NumMicroOps = 3; 796 let ResourceCycles = [1,1,1]; 797} 798def: InstRW<[ICXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 799 800def ICXWriteResGroup28 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort0156]> { 801 let Latency = 2; 802 let NumMicroOps = 3; 803 let ResourceCycles = [1,1,1]; 804} 805def: InstRW<[ICXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 806 STOSB, STOSL, STOSQ, STOSW)>; 807def: InstRW<[ICXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 808 809def ICXWriteResGroup29 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort15]> { 810 let Latency = 2; 811 let NumMicroOps = 5; 812 let ResourceCycles = [2,2,1]; 813} 814def: InstRW<[ICXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>; 815 816def ICXWriteResGroup30 : SchedWriteRes<[ICXPort0]> { 817 let Latency = 3; 818 let NumMicroOps = 1; 819 let ResourceCycles = [1]; 820} 821def: InstRW<[ICXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk", 822 "KORTEST(B|D|Q|W)rr", 823 "KTEST(B|D|Q|W)rr")>; 824 825def ICXWriteResGroup31 : SchedWriteRes<[ICXPort1]> { 826 let Latency = 3; 827 let NumMicroOps = 1; 828 let ResourceCycles = [1]; 829} 830def: InstRW<[ICXWriteResGroup31], (instregex "PDEP(32|64)rr", 831 "PEXT(32|64)rr")>; 832 833def ICXWriteResGroup32 : SchedWriteRes<[ICXPort5]> { 834 let Latency = 3; 835 let NumMicroOps = 1; 836 let ResourceCycles = [1]; 837} 838def: InstRW<[ICXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined. 839def: InstRW<[ICXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 840 "VALIGND(Z|Z128|Z256)rri", 841 "VALIGNQ(Z|Z128|Z256)rri", 842 "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined. 843 "VPBROADCAST(B|W)rr", 844 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>; 845 846def ICXWriteResGroup33 : SchedWriteRes<[ICXPort5]> { 847 let Latency = 4; 848 let NumMicroOps = 1; 849 let ResourceCycles = [1]; 850} 851def: InstRW<[ICXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr", 852 "KSHIFTL(B|D|Q|W)ri", 853 "KSHIFTR(B|D|Q|W)ri", 854 "KUNPCK(BW|DQ|WD)rr", 855 "VCMPPD(Z|Z128|Z256)rri", 856 "VCMPPS(Z|Z128|Z256)rri", 857 "VCMP(SD|SS)Zrr", 858 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr", 859 "VFPCLASS(SD|SS)Zrr", 860 "VPCMPB(Z|Z128|Z256)rri", 861 "VPCMPD(Z|Z128|Z256)rri", 862 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr", 863 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr", 864 "VPCMPQ(Z|Z128|Z256)rri", 865 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri", 866 "VPCMPW(Z|Z128|Z256)rri", 867 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>; 868 869def ICXWriteResGroup34 : SchedWriteRes<[ICXPort0,ICXPort0156]> { 870 let Latency = 3; 871 let NumMicroOps = 2; 872 let ResourceCycles = [1,1]; 873} 874def: InstRW<[ICXWriteResGroup34], (instrs FNSTSW16r)>; 875 876def ICXWriteResGroup37 : SchedWriteRes<[ICXPort0,ICXPort5]> { 877 let Latency = 3; 878 let NumMicroOps = 3; 879 let ResourceCycles = [1,2]; 880} 881def: InstRW<[ICXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>; 882 883def ICXWriteResGroup38 : SchedWriteRes<[ICXPort5,ICXPort01]> { 884 let Latency = 3; 885 let NumMicroOps = 3; 886 let ResourceCycles = [2,1]; 887} 888def: InstRW<[ICXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>; 889 890def ICXWriteResGroup41 : SchedWriteRes<[ICXPort5,ICXPort0156]> { 891 let Latency = 3; 892 let NumMicroOps = 3; 893 let ResourceCycles = [2,1]; 894} 895def: InstRW<[ICXWriteResGroup41], (instrs MMX_PACKSSDWirr, 896 MMX_PACKSSWBirr, 897 MMX_PACKUSWBirr)>; 898 899def ICXWriteResGroup42 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 900 let Latency = 3; 901 let NumMicroOps = 3; 902 let ResourceCycles = [1,2]; 903} 904def: InstRW<[ICXWriteResGroup42], (instregex "CLD")>; 905 906def ICXWriteResGroup43 : SchedWriteRes<[ICXPort237,ICXPort0156]> { 907 let Latency = 3; 908 let NumMicroOps = 3; 909 let ResourceCycles = [1,2]; 910} 911def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>; 912 913def ICXWriteResGroup44 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 914 let Latency = 3; 915 let NumMicroOps = 3; 916 let ResourceCycles = [1,2]; 917} 918def: InstRW<[ICXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)", 919 "RCR(8|16|32|64)r(1|i)")>; 920 921def ICXWriteResGroup45 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237]> { 922 let Latency = 3; 923 let NumMicroOps = 3; 924 let ResourceCycles = [1,1,1]; 925} 926def: InstRW<[ICXWriteResGroup45], (instrs FNSTSWm)>; 927 928def ICXWriteResGroup47 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort237,ICXPort0156]> { 929 let Latency = 3; 930 let NumMicroOps = 4; 931 let ResourceCycles = [1,1,1,1]; 932} 933def: InstRW<[ICXWriteResGroup47], (instregex "CALL(16|32|64)r")>; 934 935def ICXWriteResGroup48 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort06,ICXPort0156]> { 936 let Latency = 3; 937 let NumMicroOps = 4; 938 let ResourceCycles = [1,1,1,1]; 939} 940def: InstRW<[ICXWriteResGroup48], (instrs CALL64pcrel32)>; 941 942def ICXWriteResGroup49 : SchedWriteRes<[ICXPort0]> { 943 let Latency = 4; 944 let NumMicroOps = 1; 945 let ResourceCycles = [1]; 946} 947def: InstRW<[ICXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 948 949def ICXWriteResGroup50 : SchedWriteRes<[ICXPort01]> { 950 let Latency = 4; 951 let NumMicroOps = 1; 952 let ResourceCycles = [1]; 953} 954def: InstRW<[ICXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr", 955 "(V?)CVTDQ2PSrr", 956 "VCVTPD2QQ(Z128|Z256)rr", 957 "VCVTPD2UQQ(Z128|Z256)rr", 958 "VCVTPS2DQ(Y|Z128|Z256)rr", 959 "(V?)CVTPS2DQrr", 960 "VCVTPS2UDQ(Z128|Z256)rr", 961 "VCVTQQ2PD(Z128|Z256)rr", 962 "VCVTTPD2QQ(Z128|Z256)rr", 963 "VCVTTPD2UQQ(Z128|Z256)rr", 964 "VCVTTPS2DQ(Z128|Z256)rr", 965 "(V?)CVTTPS2DQrr", 966 "VCVTTPS2UDQ(Z128|Z256)rr", 967 "VCVTUDQ2PS(Z128|Z256)rr", 968 "VCVTUQQ2PD(Z128|Z256)rr")>; 969 970def ICXWriteResGroup50z : SchedWriteRes<[ICXPort05]> { 971 let Latency = 4; 972 let NumMicroOps = 1; 973 let ResourceCycles = [1]; 974} 975def: InstRW<[ICXWriteResGroup50z], (instrs VCVTDQ2PSZrr, 976 VCVTPD2QQZrr, 977 VCVTPD2UQQZrr, 978 VCVTPS2DQZrr, 979 VCVTPS2UDQZrr, 980 VCVTQQ2PDZrr, 981 VCVTTPD2QQZrr, 982 VCVTTPD2UQQZrr, 983 VCVTTPS2DQZrr, 984 VCVTTPS2UDQZrr, 985 VCVTUDQ2PSZrr, 986 VCVTUQQ2PDZrr)>; 987 988def ICXWriteResGroup51 : SchedWriteRes<[ICXPort5]> { 989 let Latency = 4; 990 let NumMicroOps = 2; 991 let ResourceCycles = [2]; 992} 993def: InstRW<[ICXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr", 994 "VEXPANDPS(Z|Z128|Z256)rr", 995 "VPEXPANDD(Z|Z128|Z256)rr", 996 "VPEXPANDQ(Z|Z128|Z256)rr", 997 "VPMOVDB(Z|Z128|Z256)rr", 998 "VPMOVDW(Z|Z128|Z256)rr", 999 "VPMOVQB(Z|Z128|Z256)rr", 1000 "VPMOVQW(Z|Z128|Z256)rr", 1001 "VPMOVSDB(Z|Z128|Z256)rr", 1002 "VPMOVSDW(Z|Z128|Z256)rr", 1003 "VPMOVSQB(Z|Z128|Z256)rr", 1004 "VPMOVSQD(Z|Z128|Z256)rr", 1005 "VPMOVSQW(Z|Z128|Z256)rr", 1006 "VPMOVSWB(Z|Z128|Z256)rr", 1007 "VPMOVUSDB(Z|Z128|Z256)rr", 1008 "VPMOVUSDW(Z|Z128|Z256)rr", 1009 "VPMOVUSQB(Z|Z128|Z256)rr", 1010 "VPMOVUSQD(Z|Z128|Z256)rr", 1011 "VPMOVUSWB(Z|Z128|Z256)rr", 1012 "VPMOVWB(Z|Z128|Z256)rr")>; 1013 1014def ICXWriteResGroup54 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1015 let Latency = 4; 1016 let NumMicroOps = 3; 1017 let ResourceCycles = [1,1,1]; 1018} 1019def: InstRW<[ICXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m", 1020 "IST_F(16|32)m", 1021 "VPMOVQD(Z|Z128|Z256)mr(b?)")>; 1022 1023def ICXWriteResGroup55 : SchedWriteRes<[ICXPort0156]> { 1024 let Latency = 4; 1025 let NumMicroOps = 4; 1026 let ResourceCycles = [4]; 1027} 1028def: InstRW<[ICXWriteResGroup55], (instrs FNCLEX)>; 1029 1030def ICXWriteResGroup56 : SchedWriteRes<[]> { 1031 let Latency = 0; 1032 let NumMicroOps = 4; 1033 let ResourceCycles = []; 1034} 1035def: InstRW<[ICXWriteResGroup56], (instrs VZEROUPPER)>; 1036 1037def ICXWriteResGroup57 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort0156]> { 1038 let Latency = 4; 1039 let NumMicroOps = 4; 1040 let ResourceCycles = [1,1,2]; 1041} 1042def: InstRW<[ICXWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 1043 1044def ICXWriteResGroup58 : SchedWriteRes<[ICXPort23]> { 1045 let Latency = 5; 1046 let NumMicroOps = 1; 1047 let ResourceCycles = [1]; 1048} 1049def: InstRW<[ICXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)", 1050 "MOVZX(16|32|64)rm(8|16)", 1051 "(V?)MOVDDUPrm")>; // TODO: Should this be ICXWriteResGroup71? 1052 1053def ICXWriteResGroup61 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1054 let Latency = 5; 1055 let NumMicroOps = 2; 1056 let ResourceCycles = [1,1]; 1057} 1058def: InstRW<[ICXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr", 1059 "MMX_CVT(T?)PS2PIirr", 1060 "VCVTDQ2PDZ128rr", 1061 "VCVTPD2DQZ128rr", 1062 "(V?)CVT(T?)PD2DQrr", 1063 "VCVTPD2PSZ128rr", 1064 "(V?)CVTPD2PSrr", 1065 "VCVTPD2UDQZ128rr", 1066 "VCVTPS2PDZ128rr", 1067 "(V?)CVTPS2PDrr", 1068 "VCVTPS2QQZ128rr", 1069 "VCVTPS2UQQZ128rr", 1070 "VCVTQQ2PSZ128rr", 1071 "(V?)CVTSD2SS(Z?)rr", 1072 "(V?)CVTSI(64)?2SDrr", 1073 "VCVTSI2SSZrr", 1074 "(V?)CVTSI2SSrr", 1075 "VCVTSI(64)?2SDZrr", 1076 "VCVTSS2SDZrr", 1077 "(V?)CVTSS2SDrr", 1078 "VCVTTPD2DQZ128rr", 1079 "VCVTTPD2UDQZ128rr", 1080 "VCVTTPS2QQZ128rr", 1081 "VCVTTPS2UQQZ128rr", 1082 "VCVTUDQ2PDZ128rr", 1083 "VCVTUQQ2PSZ128rr", 1084 "VCVTUSI2SSZrr", 1085 "VCVTUSI(64)?2SDZrr")>; 1086 1087def ICXWriteResGroup62 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1088 let Latency = 5; 1089 let NumMicroOps = 3; 1090 let ResourceCycles = [2,1]; 1091} 1092def: InstRW<[ICXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>; 1093 1094def ICXWriteResGroup63 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06]> { 1095 let Latency = 5; 1096 let NumMicroOps = 3; 1097 let ResourceCycles = [1,1,1]; 1098} 1099def: InstRW<[ICXWriteResGroup63], (instregex "STR(16|32|64)r")>; 1100 1101def ICXWriteResGroup65 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort015]> { 1102 let Latency = 5; 1103 let NumMicroOps = 3; 1104 let ResourceCycles = [1,1,1]; 1105} 1106def: InstRW<[ICXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)", 1107 "VCVTPS2PHZ256mr(b?)", 1108 "VCVTPS2PHZmr(b?)")>; 1109 1110def ICXWriteResGroup66 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1111 let Latency = 5; 1112 let NumMicroOps = 4; 1113 let ResourceCycles = [1,2,1]; 1114} 1115def: InstRW<[ICXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)", 1116 "VPMOVDW(Z|Z128|Z256)mr(b?)", 1117 "VPMOVQB(Z|Z128|Z256)mr(b?)", 1118 "VPMOVQW(Z|Z128|Z256)mr(b?)", 1119 "VPMOVSDB(Z|Z128|Z256)mr(b?)", 1120 "VPMOVSDW(Z|Z128|Z256)mr(b?)", 1121 "VPMOVSQB(Z|Z128|Z256)mr(b?)", 1122 "VPMOVSQD(Z|Z128|Z256)mr(b?)", 1123 "VPMOVSQW(Z|Z128|Z256)mr(b?)", 1124 "VPMOVSWB(Z|Z128|Z256)mr(b?)", 1125 "VPMOVUSDB(Z|Z128|Z256)mr(b?)", 1126 "VPMOVUSDW(Z|Z128|Z256)mr(b?)", 1127 "VPMOVUSQB(Z|Z128|Z256)mr(b?)", 1128 "VPMOVUSQD(Z|Z128|Z256)mr(b?)", 1129 "VPMOVUSQW(Z|Z128|Z256)mr(b?)", 1130 "VPMOVUSWB(Z|Z128|Z256)mr(b?)", 1131 "VPMOVWB(Z|Z128|Z256)mr(b?)")>; 1132 1133def ICXWriteResGroup67 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 1134 let Latency = 5; 1135 let NumMicroOps = 5; 1136 let ResourceCycles = [1,4]; 1137} 1138def: InstRW<[ICXWriteResGroup67], (instrs XSETBV)>; 1139 1140def ICXWriteResGroup69 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort0156]> { 1141 let Latency = 5; 1142 let NumMicroOps = 6; 1143 let ResourceCycles = [1,1,4]; 1144} 1145def: InstRW<[ICXWriteResGroup69], (instregex "PUSHF(16|64)")>; 1146 1147def ICXWriteResGroup71 : SchedWriteRes<[ICXPort23]> { 1148 let Latency = 6; 1149 let NumMicroOps = 1; 1150 let ResourceCycles = [1]; 1151} 1152def: InstRW<[ICXWriteResGroup71], (instrs VBROADCASTSSrm, 1153 VPBROADCASTDrm, 1154 VPBROADCASTQrm, 1155 VMOVSHDUPrm, 1156 VMOVSLDUPrm, 1157 MOVSHDUPrm, 1158 MOVSLDUPrm)>; 1159 1160def ICXWriteResGroup72 : SchedWriteRes<[ICXPort5]> { 1161 let Latency = 6; 1162 let NumMicroOps = 2; 1163 let ResourceCycles = [2]; 1164} 1165def: InstRW<[ICXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>; 1166def: InstRW<[ICXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr", 1167 "VCOMPRESSPS(Z|Z128|Z256)rr", 1168 "VPCOMPRESSD(Z|Z128|Z256)rr", 1169 "VPCOMPRESSQ(Z|Z128|Z256)rr", 1170 "VPERMW(Z|Z128|Z256)rr")>; 1171 1172def ICXWriteResGroup73 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1173 let Latency = 6; 1174 let NumMicroOps = 2; 1175 let ResourceCycles = [1,1]; 1176} 1177def: InstRW<[ICXWriteResGroup73], (instrs MMX_PADDSBirm, 1178 MMX_PADDSWirm, 1179 MMX_PADDUSBirm, 1180 MMX_PADDUSWirm, 1181 MMX_PAVGBirm, 1182 MMX_PAVGWirm, 1183 MMX_PCMPEQBirm, 1184 MMX_PCMPEQDirm, 1185 MMX_PCMPEQWirm, 1186 MMX_PCMPGTBirm, 1187 MMX_PCMPGTDirm, 1188 MMX_PCMPGTWirm, 1189 MMX_PMAXSWirm, 1190 MMX_PMAXUBirm, 1191 MMX_PMINSWirm, 1192 MMX_PMINUBirm, 1193 MMX_PSUBSBirm, 1194 MMX_PSUBSWirm, 1195 MMX_PSUBUSBirm, 1196 MMX_PSUBUSWirm)>; 1197 1198def ICXWriteResGroup76 : SchedWriteRes<[ICXPort6,ICXPort23]> { 1199 let Latency = 6; 1200 let NumMicroOps = 2; 1201 let ResourceCycles = [1,1]; 1202} 1203def: InstRW<[ICXWriteResGroup76], (instrs FARJMP64m)>; 1204def: InstRW<[ICXWriteResGroup76], (instregex "JMP(16|32|64)m")>; 1205 1206def ICXWriteResGroup79 : SchedWriteRes<[ICXPort23,ICXPort15]> { 1207 let Latency = 6; 1208 let NumMicroOps = 2; 1209 let ResourceCycles = [1,1]; 1210} 1211def: InstRW<[ICXWriteResGroup79], (instregex "ANDN(32|64)rm", 1212 "MOVBE(16|32|64)rm")>; 1213 1214def ICXWriteResGroup80 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1215 let Latency = 6; 1216 let NumMicroOps = 2; 1217 let ResourceCycles = [1,1]; 1218} 1219def: InstRW<[ICXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>; 1220def: InstRW<[ICXWriteResGroup80], (instrs VMOVDI2PDIZrm)>; 1221 1222def ICXWriteResGroup81 : SchedWriteRes<[ICXPort23,ICXPort0156]> { 1223 let Latency = 6; 1224 let NumMicroOps = 2; 1225 let ResourceCycles = [1,1]; 1226} 1227def: InstRW<[ICXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>; 1228def: InstRW<[ICXWriteResGroup81], (instregex "POP(16|32|64)rmr")>; 1229 1230def ICXWriteResGroup82 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1231 let Latency = 6; 1232 let NumMicroOps = 3; 1233 let ResourceCycles = [2,1]; 1234} 1235def: InstRW<[ICXWriteResGroup82], (instregex "(V?)CVTSI642SSrr", 1236 "VCVTSI642SSZrr", 1237 "VCVTUSI642SSZrr")>; 1238 1239def ICXWriteResGroup84 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06,ICXPort0156]> { 1240 let Latency = 6; 1241 let NumMicroOps = 4; 1242 let ResourceCycles = [1,1,1,1]; 1243} 1244def: InstRW<[ICXWriteResGroup84], (instregex "SLDT(16|32|64)r")>; 1245 1246def ICXWriteResGroup86 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1247 let Latency = 6; 1248 let NumMicroOps = 4; 1249 let ResourceCycles = [1,1,1,1]; 1250} 1251def: InstRW<[ICXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)", 1252 "SHL(8|16|32|64)m(1|i)", 1253 "SHR(8|16|32|64)m(1|i)")>; 1254 1255def ICXWriteResGroup87 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort0156]> { 1256 let Latency = 6; 1257 let NumMicroOps = 4; 1258 let ResourceCycles = [1,1,1,1]; 1259} 1260def: InstRW<[ICXWriteResGroup87], (instregex "POP(16|32|64)rmm", 1261 "PUSH(16|32|64)rmm")>; 1262 1263def ICXWriteResGroup88 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 1264 let Latency = 6; 1265 let NumMicroOps = 6; 1266 let ResourceCycles = [1,5]; 1267} 1268def: InstRW<[ICXWriteResGroup88], (instrs STD)>; 1269 1270def ICXWriteResGroup89 : SchedWriteRes<[ICXPort23]> { 1271 let Latency = 7; 1272 let NumMicroOps = 1; 1273 let ResourceCycles = [1]; 1274} 1275def: InstRW<[ICXWriteResGroup89], (instregex "LD_F(32|64|80)m")>; 1276def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128, 1277 VBROADCASTI128, 1278 VBROADCASTSDYrm, 1279 VBROADCASTSSYrm, 1280 VMOVDDUPYrm, 1281 VMOVSHDUPYrm, 1282 VMOVSLDUPYrm, 1283 VPBROADCASTDYrm, 1284 VPBROADCASTQYrm)>; 1285 1286def ICXWriteResGroup90 : SchedWriteRes<[ICXPort01,ICXPort5]> { 1287 let Latency = 7; 1288 let NumMicroOps = 2; 1289 let ResourceCycles = [1,1]; 1290} 1291def: InstRW<[ICXWriteResGroup90], (instrs VCVTDQ2PDYrr)>; 1292 1293def ICXWriteResGroup92 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1294 let Latency = 7; 1295 let NumMicroOps = 2; 1296 let ResourceCycles = [1,1]; 1297} 1298def: InstRW<[ICXWriteResGroup92], (instregex "VMOVSDZrm(b?)", 1299 "VMOVSSZrm(b?)")>; 1300 1301def ICXWriteResGroup92a : SchedWriteRes<[ICXPort5,ICXPort23]> { 1302 let Latency = 6; 1303 let NumMicroOps = 2; 1304 let ResourceCycles = [1,1]; 1305} 1306def: InstRW<[ICXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm", 1307 "(V?)PMOV(SX|ZX)BQrm", 1308 "(V?)PMOV(SX|ZX)BWrm", 1309 "(V?)PMOV(SX|ZX)DQrm", 1310 "(V?)PMOV(SX|ZX)WDrm", 1311 "(V?)PMOV(SX|ZX)WQrm")>; 1312 1313def ICXWriteResGroup93 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1314 let Latency = 7; 1315 let NumMicroOps = 2; 1316 let ResourceCycles = [1,1]; 1317} 1318def: InstRW<[ICXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr", 1319 "VCVTPD2DQ(Y|Z256)rr", 1320 "VCVTPD2PS(Y|Z256)rr", 1321 "VCVTPD2UDQZ256rr", 1322 "VCVTPS2PD(Y|Z256)rr", 1323 "VCVTPS2QQZ256rr", 1324 "VCVTPS2UQQZ256rr", 1325 "VCVTQQ2PSZ256rr", 1326 "VCVTTPD2DQ(Y|Z256)rr", 1327 "VCVTTPD2UDQZ256rr", 1328 "VCVTTPS2QQZ256rr", 1329 "VCVTTPS2UQQZ256rr", 1330 "VCVTUDQ2PDZ256rr", 1331 "VCVTUQQ2PSZ256rr")>; 1332 1333def ICXWriteResGroup93z : SchedWriteRes<[ICXPort5,ICXPort05]> { 1334 let Latency = 7; 1335 let NumMicroOps = 2; 1336 let ResourceCycles = [1,1]; 1337} 1338def: InstRW<[ICXWriteResGroup93z], (instrs VCVTDQ2PDZrr, 1339 VCVTPD2DQZrr, 1340 VCVTPD2PSZrr, 1341 VCVTPD2UDQZrr, 1342 VCVTPS2PDZrr, 1343 VCVTPS2QQZrr, 1344 VCVTPS2UQQZrr, 1345 VCVTQQ2PSZrr, 1346 VCVTTPD2DQZrr, 1347 VCVTTPD2UDQZrr, 1348 VCVTTPS2QQZrr, 1349 VCVTTPS2UQQZrr, 1350 VCVTUDQ2PDZrr, 1351 VCVTUQQ2PSZrr)>; 1352 1353def ICXWriteResGroup95 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1354 let Latency = 7; 1355 let NumMicroOps = 2; 1356 let ResourceCycles = [1,1]; 1357} 1358def: InstRW<[ICXWriteResGroup95], (instrs VMOVNTDQAZ128rm, 1359 VPBLENDDrmi)>; 1360def: InstRW<[ICXWriteResGroup95, ReadAfterVecXLd], 1361 (instregex "VBLENDMPDZ128rm(b?)", 1362 "VBLENDMPSZ128rm(b?)", 1363 "VBROADCASTI32X2Z128rm(b?)", 1364 "VBROADCASTSSZ128rm(b?)", 1365 "VINSERT(F|I)128rm", 1366 "VMOVAPDZ128rm(b?)", 1367 "VMOVAPSZ128rm(b?)", 1368 "VMOVDDUPZ128rm(b?)", 1369 "VMOVDQA32Z128rm(b?)", 1370 "VMOVDQA64Z128rm(b?)", 1371 "VMOVDQU16Z128rm(b?)", 1372 "VMOVDQU32Z128rm(b?)", 1373 "VMOVDQU64Z128rm(b?)", 1374 "VMOVDQU8Z128rm(b?)", 1375 "VMOVSHDUPZ128rm(b?)", 1376 "VMOVSLDUPZ128rm(b?)", 1377 "VMOVUPDZ128rm(b?)", 1378 "VMOVUPSZ128rm(b?)", 1379 "VPADD(B|D|Q|W)Z128rm(b?)", 1380 "(V?)PADD(B|D|Q|W)rm", 1381 "VPBLENDM(B|D|Q|W)Z128rm(b?)", 1382 "VPBROADCASTDZ128rm(b?)", 1383 "VPBROADCASTQZ128rm(b?)", 1384 "VPSUB(B|D|Q|W)Z128rm(b?)", 1385 "(V?)PSUB(B|D|Q|W)rm", 1386 "VPTERNLOGDZ128rm(b?)i", 1387 "VPTERNLOGQZ128rm(b?)i")>; 1388 1389def ICXWriteResGroup96 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1390 let Latency = 7; 1391 let NumMicroOps = 3; 1392 let ResourceCycles = [2,1]; 1393} 1394def: InstRW<[ICXWriteResGroup96], (instrs MMX_PACKSSDWirm, 1395 MMX_PACKSSWBirm, 1396 MMX_PACKUSWBirm)>; 1397 1398def ICXWriteResGroup97 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1399 let Latency = 7; 1400 let NumMicroOps = 3; 1401 let ResourceCycles = [2,1]; 1402} 1403def: InstRW<[ICXWriteResGroup97], (instregex "VPERMI2W128rr", 1404 "VPERMI2W256rr", 1405 "VPERMI2Wrr", 1406 "VPERMT2W128rr", 1407 "VPERMT2W256rr", 1408 "VPERMT2Wrr")>; 1409 1410def ICXWriteResGroup99 : SchedWriteRes<[ICXPort23,ICXPort0156]> { 1411 let Latency = 7; 1412 let NumMicroOps = 3; 1413 let ResourceCycles = [1,2]; 1414} 1415def: InstRW<[ICXWriteResGroup99], (instrs LEAVE, LEAVE64, 1416 SCASB, SCASL, SCASQ, SCASW)>; 1417 1418def ICXWriteResGroup100 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort015]> { 1419 let Latency = 7; 1420 let NumMicroOps = 3; 1421 let ResourceCycles = [1,1,1]; 1422} 1423def: InstRW<[ICXWriteResGroup100], (instregex "VCVTSS2USI64Zrr", 1424 "(V?)CVTSS2SI64(Z?)rr", 1425 "(V?)CVTTSS2SI64(Z?)rr", 1426 "VCVTTSS2USI64Zrr")>; 1427 1428def ICXWriteResGroup101 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05]> { 1429 let Latency = 7; 1430 let NumMicroOps = 3; 1431 let ResourceCycles = [1,1,1]; 1432} 1433def: InstRW<[ICXWriteResGroup101], (instrs FLDCW16m)>; 1434 1435def ICXWriteResGroup103 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort0156]> { 1436 let Latency = 7; 1437 let NumMicroOps = 3; 1438 let ResourceCycles = [1,1,1]; 1439} 1440def: InstRW<[ICXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; 1441 1442def ICXWriteResGroup104 : SchedWriteRes<[ICXPort6,ICXPort23,ICXPort0156]> { 1443 let Latency = 7; 1444 let NumMicroOps = 3; 1445 let ResourceCycles = [1,1,1]; 1446} 1447def: InstRW<[ICXWriteResGroup104], (instrs LRET64, RET64)>; 1448 1449def ICXWriteResGroup106 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1450 let Latency = 7; 1451 let NumMicroOps = 4; 1452 let ResourceCycles = [1,2,1]; 1453} 1454def: InstRW<[ICXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", 1455 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)", 1456 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)", 1457 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>; 1458 1459def ICXWriteResGroup107 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1460 let Latency = 7; 1461 let NumMicroOps = 5; 1462 let ResourceCycles = [1,1,1,2]; 1463} 1464def: InstRW<[ICXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)", 1465 "ROR(8|16|32|64)m(1|i)")>; 1466 1467def ICXWriteResGroup107_1 : SchedWriteRes<[ICXPort06]> { 1468 let Latency = 2; 1469 let NumMicroOps = 2; 1470 let ResourceCycles = [2]; 1471} 1472def: InstRW<[ICXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1473 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1474 1475def ICXWriteResGroup108 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort0156]> { 1476 let Latency = 7; 1477 let NumMicroOps = 5; 1478 let ResourceCycles = [1,1,1,2]; 1479} 1480def: InstRW<[ICXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>; 1481 1482def ICXWriteResGroup109 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 1483 let Latency = 7; 1484 let NumMicroOps = 5; 1485 let ResourceCycles = [1,1,1,1,1]; 1486} 1487def: InstRW<[ICXWriteResGroup109], (instregex "CALL(16|32|64)m")>; 1488def: InstRW<[ICXWriteResGroup109], (instrs FARCALL64m)>; 1489 1490def ICXWriteResGroup110 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1491 let Latency = 7; 1492 let NumMicroOps = 7; 1493 let ResourceCycles = [1,2,2,2]; 1494} 1495def: InstRW<[ICXWriteResGroup110], (instrs VPSCATTERDQZ128mr, 1496 VPSCATTERQQZ128mr, 1497 VSCATTERDPDZ128mr, 1498 VSCATTERQPDZ128mr)>; 1499 1500def ICXWriteResGroup111 : SchedWriteRes<[ICXPort6,ICXPort06,ICXPort15,ICXPort0156]> { 1501 let Latency = 7; 1502 let NumMicroOps = 7; 1503 let ResourceCycles = [1,3,1,2]; 1504} 1505def: InstRW<[ICXWriteResGroup111], (instrs LOOP)>; 1506 1507def ICXWriteResGroup112 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1508 let Latency = 7; 1509 let NumMicroOps = 11; 1510 let ResourceCycles = [1,4,4,2]; 1511} 1512def: InstRW<[ICXWriteResGroup112], (instrs VPSCATTERDQZ256mr, 1513 VPSCATTERQQZ256mr, 1514 VSCATTERDPDZ256mr, 1515 VSCATTERQPDZ256mr)>; 1516 1517def ICXWriteResGroup113 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1518 let Latency = 7; 1519 let NumMicroOps = 19; 1520 let ResourceCycles = [1,8,8,2]; 1521} 1522def: InstRW<[ICXWriteResGroup113], (instrs VPSCATTERDQZmr, 1523 VPSCATTERQQZmr, 1524 VSCATTERDPDZmr, 1525 VSCATTERQPDZmr)>; 1526 1527def ICXWriteResGroup114 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1528 let Latency = 7; 1529 let NumMicroOps = 36; 1530 let ResourceCycles = [1,16,1,16,2]; 1531} 1532def: InstRW<[ICXWriteResGroup114], (instrs VSCATTERDPSZmr)>; 1533 1534def ICXWriteResGroup118 : SchedWriteRes<[ICXPort1,ICXPort23]> { 1535 let Latency = 8; 1536 let NumMicroOps = 2; 1537 let ResourceCycles = [1,1]; 1538} 1539def: InstRW<[ICXWriteResGroup118], (instregex "PDEP(32|64)rm", 1540 "PEXT(32|64)rm")>; 1541 1542def ICXWriteResGroup119 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1543 let Latency = 8; 1544 let NumMicroOps = 2; 1545 let ResourceCycles = [1,1]; 1546} 1547def: InstRW<[ICXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", 1548 "VPBROADCASTB(Z|Z256)rm(b?)", 1549 "VPBROADCASTW(Z|Z256)rm(b?)")>; 1550def: InstRW<[ICXWriteResGroup119], (instrs VPBROADCASTBYrm, 1551 VPBROADCASTWYrm, 1552 VPMOVSXBDYrm, 1553 VPMOVSXBQYrm, 1554 VPMOVSXWQYrm)>; 1555 1556def ICXWriteResGroup121 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1557 let Latency = 8; 1558 let NumMicroOps = 2; 1559 let ResourceCycles = [1,1]; 1560} 1561def: InstRW<[ICXWriteResGroup121], (instrs VMOVNTDQAZ256rm, 1562 VPBLENDDYrmi)>; 1563def: InstRW<[ICXWriteResGroup121, ReadAfterVecYLd], 1564 (instregex "VBLENDMPD(Z|Z256)rm(b?)", 1565 "VBLENDMPS(Z|Z256)rm(b?)", 1566 "VBROADCASTF32X2Z256rm(b?)", 1567 "VBROADCASTF32X2Zrm(b?)", 1568 "VBROADCASTF32X4Z256rm(b?)", 1569 "VBROADCASTF32X4rm(b?)", 1570 "VBROADCASTF32X8rm(b?)", 1571 "VBROADCASTF64X2Z128rm(b?)", 1572 "VBROADCASTF64X2rm(b?)", 1573 "VBROADCASTF64X4rm(b?)", 1574 "VBROADCASTI32X2Z256rm(b?)", 1575 "VBROADCASTI32X2Zrm(b?)", 1576 "VBROADCASTI32X4Z256rm(b?)", 1577 "VBROADCASTI32X4rm(b?)", 1578 "VBROADCASTI32X8rm(b?)", 1579 "VBROADCASTI64X2Z128rm(b?)", 1580 "VBROADCASTI64X2rm(b?)", 1581 "VBROADCASTI64X4rm(b?)", 1582 "VBROADCASTSD(Z|Z256)rm(b?)", 1583 "VBROADCASTSS(Z|Z256)rm(b?)", 1584 "VINSERTF32x4(Z|Z256)rm(b?)", 1585 "VINSERTF32x8Zrm(b?)", 1586 "VINSERTF64x2(Z|Z256)rm(b?)", 1587 "VINSERTF64x4Zrm(b?)", 1588 "VINSERTI32x4(Z|Z256)rm(b?)", 1589 "VINSERTI32x8Zrm(b?)", 1590 "VINSERTI64x2(Z|Z256)rm(b?)", 1591 "VINSERTI64x4Zrm(b?)", 1592 "VMOVAPD(Z|Z256)rm(b?)", 1593 "VMOVAPS(Z|Z256)rm(b?)", 1594 "VMOVDDUP(Z|Z256)rm(b?)", 1595 "VMOVDQA32(Z|Z256)rm(b?)", 1596 "VMOVDQA64(Z|Z256)rm(b?)", 1597 "VMOVDQU16(Z|Z256)rm(b?)", 1598 "VMOVDQU32(Z|Z256)rm(b?)", 1599 "VMOVDQU64(Z|Z256)rm(b?)", 1600 "VMOVDQU8(Z|Z256)rm(b?)", 1601 "VMOVSHDUP(Z|Z256)rm(b?)", 1602 "VMOVSLDUP(Z|Z256)rm(b?)", 1603 "VMOVUPD(Z|Z256)rm(b?)", 1604 "VMOVUPS(Z|Z256)rm(b?)", 1605 "VPADD(B|D|Q|W)Yrm", 1606 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)", 1607 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)", 1608 "VPBROADCASTD(Z|Z256)rm(b?)", 1609 "VPBROADCASTQ(Z|Z256)rm(b?)", 1610 "VPSUB(B|D|Q|W)Yrm", 1611 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)", 1612 "VPTERNLOGD(Z|Z256)rm(b?)i", 1613 "VPTERNLOGQ(Z|Z256)rm(b?)i")>; 1614 1615def ICXWriteResGroup123 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 1616 let Latency = 8; 1617 let NumMicroOps = 4; 1618 let ResourceCycles = [1,2,1]; 1619} 1620def: InstRW<[ICXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1621 1622def ICXWriteResGroup127 : SchedWriteRes<[ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1623 let Latency = 8; 1624 let NumMicroOps = 5; 1625 let ResourceCycles = [1,1,1,2]; 1626} 1627def: InstRW<[ICXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)", 1628 "RCR(8|16|32|64)m(1|i)")>; 1629 1630def ICXWriteResGroup128 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1631 let Latency = 8; 1632 let NumMicroOps = 6; 1633 let ResourceCycles = [1,1,1,3]; 1634} 1635def: InstRW<[ICXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL", 1636 "ROR(8|16|32|64)mCL", 1637 "SAR(8|16|32|64)mCL", 1638 "SHL(8|16|32|64)mCL", 1639 "SHR(8|16|32|64)mCL")>; 1640 1641def ICXWriteResGroup130 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1642 let Latency = 8; 1643 let NumMicroOps = 6; 1644 let ResourceCycles = [1,1,1,2,1]; 1645} 1646def: SchedAlias<WriteADCRMW, ICXWriteResGroup130>; 1647 1648def ICXWriteResGroup131 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1649 let Latency = 8; 1650 let NumMicroOps = 8; 1651 let ResourceCycles = [1,2,1,2,2]; 1652} 1653def: InstRW<[ICXWriteResGroup131], (instrs VPSCATTERQDZ128mr, 1654 VPSCATTERQDZ256mr, 1655 VSCATTERQPSZ128mr, 1656 VSCATTERQPSZ256mr)>; 1657 1658def ICXWriteResGroup132 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1659 let Latency = 8; 1660 let NumMicroOps = 12; 1661 let ResourceCycles = [1,4,1,4,2]; 1662} 1663def: InstRW<[ICXWriteResGroup132], (instrs VPSCATTERDDZ128mr, 1664 VSCATTERDPSZ128mr)>; 1665 1666def ICXWriteResGroup133 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1667 let Latency = 8; 1668 let NumMicroOps = 20; 1669 let ResourceCycles = [1,8,1,8,2]; 1670} 1671def: InstRW<[ICXWriteResGroup133], (instrs VPSCATTERDDZ256mr, 1672 VSCATTERDPSZ256mr)>; 1673 1674def ICXWriteResGroup134 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1675 let Latency = 8; 1676 let NumMicroOps = 36; 1677 let ResourceCycles = [1,16,1,16,2]; 1678} 1679def: InstRW<[ICXWriteResGroup134], (instrs VPSCATTERDDZmr)>; 1680 1681def ICXWriteResGroup135 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1682 let Latency = 9; 1683 let NumMicroOps = 2; 1684 let ResourceCycles = [1,1]; 1685} 1686def: InstRW<[ICXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>; 1687 1688def ICXWriteResGroup136 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1689 let Latency = 9; 1690 let NumMicroOps = 2; 1691 let ResourceCycles = [1,1]; 1692} 1693def: InstRW<[ICXWriteResGroup136], (instrs VPMOVSXBWYrm, 1694 VPMOVSXDQYrm, 1695 VPMOVSXWDYrm, 1696 VPMOVZXWDYrm)>; 1697def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i", 1698 "VFPCLASSSDZrm(b?)", 1699 "VFPCLASSSSZrm(b?)", 1700 "(V?)PCMPGTQrm", 1701 "VPERMI2D128rm(b?)", 1702 "VPERMI2PD128rm(b?)", 1703 "VPERMI2PS128rm(b?)", 1704 "VPERMI2Q128rm(b?)", 1705 "VPERMT2D128rm(b?)", 1706 "VPERMT2PD128rm(b?)", 1707 "VPERMT2PS128rm(b?)", 1708 "VPERMT2Q128rm(b?)", 1709 "VPMAXSQZ128rm(b?)", 1710 "VPMAXUQZ128rm(b?)", 1711 "VPMINSQZ128rm(b?)", 1712 "VPMINUQZ128rm(b?)", 1713 "VPMOVSXBDZ128rm(b?)", 1714 "VPMOVSXBQZ128rm(b?)", 1715 "VPMOVSXBWZ128rm(b?)", 1716 "VPMOVSXDQZ128rm(b?)", 1717 "VPMOVSXWDZ128rm(b?)", 1718 "VPMOVSXWQZ128rm(b?)", 1719 "VPMOVZXBDZ128rm(b?)", 1720 "VPMOVZXBQZ128rm(b?)", 1721 "VPMOVZXBWZ128rm(b?)", 1722 "VPMOVZXDQZ128rm(b?)", 1723 "VPMOVZXWDZ128rm(b?)", 1724 "VPMOVZXWQZ128rm(b?)")>; 1725 1726def ICXWriteResGroup136_2 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1727 let Latency = 10; 1728 let NumMicroOps = 2; 1729 let ResourceCycles = [1,1]; 1730} 1731def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i", 1732 "VCMP(SD|SS)Zrm", 1733 "VFPCLASSPDZ128rm(b?)", 1734 "VFPCLASSPSZ128rm(b?)", 1735 "VPCMPBZ128rmi(b?)", 1736 "VPCMPDZ128rmi(b?)", 1737 "VPCMPEQ(B|D|Q|W)Z128rm(b?)", 1738 "VPCMPGT(B|D|Q|W)Z128rm(b?)", 1739 "VPCMPQZ128rmi(b?)", 1740 "VPCMPU(B|D|Q|W)Z128rmi(b?)", 1741 "VPCMPWZ128rmi(b?)", 1742 "VPTESTMBZ128rm(b?)", 1743 "VPTESTMDZ128rm(b?)", 1744 "VPTESTMQZ128rm(b?)", 1745 "VPTESTMWZ128rm(b?)", 1746 "VPTESTNMBZ128rm(b?)", 1747 "VPTESTNMDZ128rm(b?)", 1748 "VPTESTNMQZ128rm(b?)", 1749 "VPTESTNMWZ128rm(b?)")>; 1750 1751def ICXWriteResGroup137 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1752 let Latency = 9; 1753 let NumMicroOps = 2; 1754 let ResourceCycles = [1,1]; 1755} 1756def: InstRW<[ICXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm", 1757 "(V?)CVTPS2PDrm")>; 1758 1759def ICXWriteResGroup143 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> { 1760 let Latency = 9; 1761 let NumMicroOps = 4; 1762 let ResourceCycles = [2,1,1]; 1763} 1764def: InstRW<[ICXWriteResGroup143], (instregex "(V?)PHADDSWrm", 1765 "(V?)PHSUBSWrm")>; 1766 1767def ICXWriteResGroup146 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> { 1768 let Latency = 9; 1769 let NumMicroOps = 5; 1770 let ResourceCycles = [1,2,1,1]; 1771} 1772def: InstRW<[ICXWriteResGroup146], (instregex "LAR(16|32|64)rm", 1773 "LSL(16|32|64)rm")>; 1774 1775def ICXWriteResGroup148 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1776 let Latency = 10; 1777 let NumMicroOps = 2; 1778 let ResourceCycles = [1,1]; 1779} 1780def: InstRW<[ICXWriteResGroup148], (instrs VPCMPGTQYrm)>; 1781def: InstRW<[ICXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1782 "ILD_F(16|32|64)m", 1783 "VALIGND(Z|Z256)rm(b?)i", 1784 "VALIGNQ(Z|Z256)rm(b?)i", 1785 "VPMAXSQ(Z|Z256)rm(b?)", 1786 "VPMAXUQ(Z|Z256)rm(b?)", 1787 "VPMINSQ(Z|Z256)rm(b?)", 1788 "VPMINUQ(Z|Z256)rm(b?)")>; 1789 1790def ICXWriteResGroup148_2 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1791 let Latency = 11; 1792 let NumMicroOps = 2; 1793 let ResourceCycles = [1,1]; 1794} 1795def: InstRW<[ICXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i", 1796 "VCMPPS(Z|Z256)rm(b?)i", 1797 "VFPCLASSPD(Z|Z256)rm(b?)", 1798 "VFPCLASSPS(Z|Z256)rm(b?)", 1799 "VPCMPB(Z|Z256)rmi(b?)", 1800 "VPCMPD(Z|Z256)rmi(b?)", 1801 "VPCMPEQB(Z|Z256)rm(b?)", 1802 "VPCMPEQD(Z|Z256)rm(b?)", 1803 "VPCMPEQQ(Z|Z256)rm(b?)", 1804 "VPCMPEQW(Z|Z256)rm(b?)", 1805 "VPCMPGTB(Z|Z256)rm(b?)", 1806 "VPCMPGTD(Z|Z256)rm(b?)", 1807 "VPCMPGTQ(Z|Z256)rm(b?)", 1808 "VPCMPGTW(Z|Z256)rm(b?)", 1809 "VPCMPQ(Z|Z256)rmi(b?)", 1810 "VPCMPU(B|D|Q|W)Z256rmi(b?)", 1811 "VPCMPU(B|D|Q|W)Zrmi(b?)", 1812 "VPCMPW(Z|Z256)rmi(b?)", 1813 "VPTESTM(B|D|Q|W)Z256rm(b?)", 1814 "VPTESTM(B|D|Q|W)Zrm(b?)", 1815 "VPTESTNM(B|D|Q|W)Z256rm(b?)", 1816 "VPTESTNM(B|D|Q|W)Zrm(b?)")>; 1817 1818def ICXWriteResGroup149 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1819 let Latency = 10; 1820 let NumMicroOps = 2; 1821 let ResourceCycles = [1,1]; 1822} 1823def: InstRW<[ICXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)", 1824 "VCVTDQ2PSZ128rm(b?)", 1825 "(V?)CVTDQ2PSrm", 1826 "VCVTPD2QQZ128rm(b?)", 1827 "VCVTPD2UQQZ128rm(b?)", 1828 "VCVTPH2PSZ128rm(b?)", 1829 "VCVTPS2DQZ128rm(b?)", 1830 "(V?)CVTPS2DQrm", 1831 "VCVTPS2PDZ128rm(b?)", 1832 "VCVTPS2QQZ128rm(b?)", 1833 "VCVTPS2UDQZ128rm(b?)", 1834 "VCVTPS2UQQZ128rm(b?)", 1835 "VCVTQQ2PDZ128rm(b?)", 1836 "VCVTQQ2PSZ128rm(b?)", 1837 "VCVTSS2SDZrm", 1838 "(V?)CVTSS2SDrm", 1839 "VCVTTPD2QQZ128rm(b?)", 1840 "VCVTTPD2UQQZ128rm(b?)", 1841 "VCVTTPS2DQZ128rm(b?)", 1842 "(V?)CVTTPS2DQrm", 1843 "VCVTTPS2QQZ128rm(b?)", 1844 "VCVTTPS2UDQZ128rm(b?)", 1845 "VCVTTPS2UQQZ128rm(b?)", 1846 "VCVTUDQ2PDZ128rm(b?)", 1847 "VCVTUDQ2PSZ128rm(b?)", 1848 "VCVTUQQ2PDZ128rm(b?)", 1849 "VCVTUQQ2PSZ128rm(b?)")>; 1850 1851def ICXWriteResGroup151 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1852 let Latency = 10; 1853 let NumMicroOps = 3; 1854 let ResourceCycles = [2,1]; 1855} 1856def: InstRW<[ICXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)", 1857 "VEXPANDPSZ128rm(b?)", 1858 "VPEXPANDDZ128rm(b?)", 1859 "VPEXPANDQZ128rm(b?)")>; 1860 1861def ICXWriteResGroup153 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 1862 let Latency = 10; 1863 let NumMicroOps = 3; 1864 let ResourceCycles = [1,1,1]; 1865} 1866def: InstRW<[ICXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>; 1867 1868def ICXWriteResGroup154 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> { 1869 let Latency = 10; 1870 let NumMicroOps = 4; 1871 let ResourceCycles = [2,1,1]; 1872} 1873def: InstRW<[ICXWriteResGroup154], (instrs VPHADDSWYrm, 1874 VPHSUBSWYrm)>; 1875 1876def ICXWriteResGroup157 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1877 let Latency = 10; 1878 let NumMicroOps = 8; 1879 let ResourceCycles = [1,1,1,1,1,3]; 1880} 1881def: InstRW<[ICXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>; 1882 1883def ICXWriteResGroup159 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { 1884 let Latency = 11; 1885 let NumMicroOps = 1; 1886 let ResourceCycles = [1,3]; 1887} 1888def : SchedAlias<WriteFDivX, ICXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair 1889 1890def ICXWriteResGroup160 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1891 let Latency = 11; 1892 let NumMicroOps = 2; 1893 let ResourceCycles = [1,1]; 1894} 1895def: InstRW<[ICXWriteResGroup160], (instregex "MUL_F(32|64)m")>; 1896 1897def ICXWriteResGroup161 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1898 let Latency = 11; 1899 let NumMicroOps = 2; 1900 let ResourceCycles = [1,1]; 1901} 1902def: InstRW<[ICXWriteResGroup161], (instrs VCVTDQ2PSYrm, 1903 VCVTPS2PDYrm)>; 1904def: InstRW<[ICXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)", 1905 "VCVTPH2PS(Z|Z256)rm(b?)", 1906 "VCVTPS2PD(Z|Z256)rm(b?)", 1907 "VCVTQQ2PD(Z|Z256)rm(b?)", 1908 "VCVTQQ2PSZ256rm(b?)", 1909 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", 1910 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", 1911 "VCVT(T?)PS2DQYrm", 1912 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", 1913 "VCVT(T?)PS2QQZ256rm(b?)", 1914 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", 1915 "VCVT(T?)PS2UQQZ256rm(b?)", 1916 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)", 1917 "VCVTUQQ2PD(Z|Z256)rm(b?)", 1918 "VCVTUQQ2PSZ256rm(b?)")>; 1919 1920def ICXWriteResGroup162 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1921 let Latency = 11; 1922 let NumMicroOps = 3; 1923 let ResourceCycles = [2,1]; 1924} 1925def: InstRW<[ICXWriteResGroup162], (instregex "FICOM(P?)(16|32)m", 1926 "VEXPANDPD(Z|Z256)rm(b?)", 1927 "VEXPANDPS(Z|Z256)rm(b?)", 1928 "VPEXPANDD(Z|Z256)rm(b?)", 1929 "VPEXPANDQ(Z|Z256)rm(b?)")>; 1930 1931def ICXWriteResGroup163 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1932 let Latency = 11; 1933 let NumMicroOps = 3; 1934 let ResourceCycles = [1,2]; 1935} 1936def: InstRW<[ICXWriteResGroup163], (instregex "VCVTSD2SSZrm")>; 1937 1938def ICXWriteResGroup164 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 1939 let Latency = 11; 1940 let NumMicroOps = 3; 1941 let ResourceCycles = [1,1,1]; 1942} 1943def: InstRW<[ICXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>; 1944 1945def ICXWriteResGroup166 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 1946 let Latency = 11; 1947 let NumMicroOps = 3; 1948 let ResourceCycles = [1,1,1]; 1949} 1950def: InstRW<[ICXWriteResGroup166], (instrs CVTPD2PSrm, 1951 CVTPD2DQrm, 1952 CVTTPD2DQrm, 1953 MMX_CVTPD2PIirm, 1954 MMX_CVTTPD2PIirm)>; 1955 1956def ICXWriteResGroup167 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 1957 let Latency = 11; 1958 let NumMicroOps = 4; 1959 let ResourceCycles = [2,1,1]; 1960} 1961def: InstRW<[ICXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>; 1962 1963def ICXWriteResGroup169 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> { 1964 let Latency = 11; 1965 let NumMicroOps = 7; 1966 let ResourceCycles = [2,3,2]; 1967} 1968def: InstRW<[ICXWriteResGroup169], (instregex "RCL(16|32|64)rCL", 1969 "RCR(16|32|64)rCL")>; 1970 1971def ICXWriteResGroup170 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> { 1972 let Latency = 11; 1973 let NumMicroOps = 9; 1974 let ResourceCycles = [1,5,1,2]; 1975} 1976def: InstRW<[ICXWriteResGroup170], (instrs RCL8rCL)>; 1977 1978def ICXWriteResGroup171 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 1979 let Latency = 11; 1980 let NumMicroOps = 11; 1981 let ResourceCycles = [2,9]; 1982} 1983def: InstRW<[ICXWriteResGroup171], (instrs LOOPE, LOOPNE)>; 1984 1985def ICXWriteResGroup174 : SchedWriteRes<[ICXPort01]> { 1986 let Latency = 15; 1987 let NumMicroOps = 3; 1988 let ResourceCycles = [3]; 1989} 1990def: InstRW<[ICXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>; 1991 1992def ICXWriteResGroup174z : SchedWriteRes<[ICXPort05]> { 1993 let Latency = 15; 1994 let NumMicroOps = 3; 1995 let ResourceCycles = [3]; 1996} 1997def: InstRW<[ICXWriteResGroup174z], (instregex "VPMULLQZrr")>; 1998 1999def ICXWriteResGroup175 : SchedWriteRes<[ICXPort5,ICXPort23]> { 2000 let Latency = 12; 2001 let NumMicroOps = 3; 2002 let ResourceCycles = [2,1]; 2003} 2004def: InstRW<[ICXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>; 2005 2006def ICXWriteResGroup176 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015]> { 2007 let Latency = 12; 2008 let NumMicroOps = 3; 2009 let ResourceCycles = [1,1,1]; 2010} 2011def: InstRW<[ICXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", 2012 "VCVT(T?)SS2USI64Zrm(b?)")>; 2013 2014def ICXWriteResGroup177 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2015 let Latency = 12; 2016 let NumMicroOps = 3; 2017 let ResourceCycles = [1,1,1]; 2018} 2019def: InstRW<[ICXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", 2020 "VCVT(T?)PS2UQQZrm(b?)")>; 2021 2022def ICXWriteResGroup179 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23,ICXPort015]> { 2023 let Latency = 12; 2024 let NumMicroOps = 4; 2025 let ResourceCycles = [1,1,1,1]; 2026} 2027def: InstRW<[ICXWriteResGroup179], (instregex "CVTTSS2SI64rm")>; 2028 2029def ICXWriteResGroup180 : SchedWriteRes<[ICXPort5,ICXPort23]> { 2030 let Latency = 13; 2031 let NumMicroOps = 3; 2032 let ResourceCycles = [2,1]; 2033} 2034def: InstRW<[ICXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m", 2035 "VPERMWZ256rm(b?)", 2036 "VPERMWZrm(b?)")>; 2037 2038def ICXWriteResGroup181 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2039 let Latency = 13; 2040 let NumMicroOps = 3; 2041 let ResourceCycles = [1,1,1]; 2042} 2043def: InstRW<[ICXWriteResGroup181], (instrs VCVTDQ2PDYrm)>; 2044 2045def ICXWriteResGroup183 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2046 let Latency = 13; 2047 let NumMicroOps = 4; 2048 let ResourceCycles = [2,1,1]; 2049} 2050def: InstRW<[ICXWriteResGroup183], (instregex "VPERMI2W128rm(b?)", 2051 "VPERMT2W128rm(b?)")>; 2052 2053def ICXWriteResGroup184 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { 2054 let Latency = 14; 2055 let NumMicroOps = 1; 2056 let ResourceCycles = [1,3]; 2057} 2058def : SchedAlias<WriteFDiv64, ICXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2059def : SchedAlias<WriteFDiv64X, ICXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2060 2061def ICXWriteResGroup184_1 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { 2062 let Latency = 14; 2063 let NumMicroOps = 1; 2064 let ResourceCycles = [1,5]; 2065} 2066def : SchedAlias<WriteFDiv64Y, ICXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair 2067 2068def ICXWriteResGroup187 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2069 let Latency = 14; 2070 let NumMicroOps = 3; 2071 let ResourceCycles = [1,1,1]; 2072} 2073def: InstRW<[ICXWriteResGroup187], (instregex "MUL_FI(16|32)m")>; 2074 2075def ICXWriteResGroup188 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2076 let Latency = 14; 2077 let NumMicroOps = 3; 2078 let ResourceCycles = [1,1,1]; 2079} 2080def: InstRW<[ICXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)", 2081 "VCVTPD2PSZrm(b?)", 2082 "VCVTPD2UDQZrm(b?)", 2083 "VCVTQQ2PSZrm(b?)", 2084 "VCVTTPD2DQZrm(b?)", 2085 "VCVTTPD2UDQZrm(b?)", 2086 "VCVTUQQ2PSZrm(b?)")>; 2087 2088def ICXWriteResGroup189 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2089 let Latency = 14; 2090 let NumMicroOps = 4; 2091 let ResourceCycles = [2,1,1]; 2092} 2093def: InstRW<[ICXWriteResGroup189], (instregex "VPERMI2W256rm(b?)", 2094 "VPERMI2Wrm(b?)", 2095 "VPERMT2W256rm(b?)", 2096 "VPERMT2Wrm(b?)")>; 2097 2098def ICXWriteResGroup190 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> { 2099 let Latency = 14; 2100 let NumMicroOps = 10; 2101 let ResourceCycles = [2,4,1,3]; 2102} 2103def: InstRW<[ICXWriteResGroup190], (instrs RCR8rCL)>; 2104 2105def ICXWriteResGroup191 : SchedWriteRes<[ICXPort0]> { 2106 let Latency = 15; 2107 let NumMicroOps = 1; 2108 let ResourceCycles = [1]; 2109} 2110def: InstRW<[ICXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 2111 2112def ICXWriteResGroup194 : SchedWriteRes<[ICXPort1,ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2113 let Latency = 15; 2114 let NumMicroOps = 8; 2115 let ResourceCycles = [1,2,2,1,2]; 2116} 2117def: InstRW<[ICXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>; 2118 2119def ICXWriteResGroup195 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2120 let Latency = 15; 2121 let NumMicroOps = 10; 2122 let ResourceCycles = [1,1,1,5,1,1]; 2123} 2124def: InstRW<[ICXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>; 2125 2126def ICXWriteResGroup199 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2127 let Latency = 16; 2128 let NumMicroOps = 14; 2129 let ResourceCycles = [1,1,1,4,2,5]; 2130} 2131def: InstRW<[ICXWriteResGroup199], (instrs CMPXCHG8B)>; 2132 2133def ICXWriteResGroup200 : SchedWriteRes<[ICXPort1, ICXPort05, ICXPort6]> { 2134 let Latency = 12; 2135 let NumMicroOps = 34; 2136 let ResourceCycles = [1, 4, 5]; 2137} 2138def: InstRW<[ICXWriteResGroup200], (instrs VZEROALL)>; 2139 2140def ICXWriteResGroup201 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2141 let Latency = 17; 2142 let NumMicroOps = 2; 2143 let ResourceCycles = [1,1,5]; 2144} 2145def : SchedAlias<WriteFDivXLd, ICXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair 2146 2147def ICXWriteResGroup202 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156]> { 2148 let Latency = 17; 2149 let NumMicroOps = 15; 2150 let ResourceCycles = [2,1,2,4,2,4]; 2151} 2152def: InstRW<[ICXWriteResGroup202], (instrs XCH_F)>; 2153 2154def ICXWriteResGroup205 : SchedWriteRes<[ICXPort23,ICXPort01]> { 2155 let Latency = 21; 2156 let NumMicroOps = 4; 2157 let ResourceCycles = [1,3]; 2158} 2159def: InstRW<[ICXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>; 2160 2161def ICXWriteResGroup207 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort06,ICXPort0156]> { 2162 let Latency = 18; 2163 let NumMicroOps = 8; 2164 let ResourceCycles = [1,1,1,5]; 2165} 2166def: InstRW<[ICXWriteResGroup207], (instrs CPUID, RDTSC)>; 2167 2168def ICXWriteResGroup208 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2169 let Latency = 18; 2170 let NumMicroOps = 11; 2171 let ResourceCycles = [2,1,1,4,1,2]; 2172} 2173def: InstRW<[ICXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>; 2174 2175def ICXWriteResGroup209 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2176 let Latency = 19; 2177 let NumMicroOps = 2; 2178 let ResourceCycles = [1,1,4]; 2179} 2180def : SchedAlias<WriteFDiv64Ld, ICXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair 2181 2182def ICXWriteResGroup211 : SchedWriteRes<[ICXPort23,ICXPort01]> { 2183 let Latency = 22; 2184 let NumMicroOps = 4; 2185 let ResourceCycles = [1,3]; 2186} 2187def: InstRW<[ICXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>; 2188 2189def ICXWriteResGroup211_1 : SchedWriteRes<[ICXPort23,ICXPort05]> { 2190 let Latency = 22; 2191 let NumMicroOps = 4; 2192 let ResourceCycles = [1,3]; 2193} 2194def: InstRW<[ICXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>; 2195 2196def ICXWriteResGroup215 : SchedWriteRes<[ICXPort0]> { 2197 let Latency = 20; 2198 let NumMicroOps = 1; 2199 let ResourceCycles = [1]; 2200} 2201def: InstRW<[ICXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 2202 2203def ICXWriteResGroup216 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2204 let Latency = 20; 2205 let NumMicroOps = 2; 2206 let ResourceCycles = [1,1,4]; 2207} 2208def : SchedAlias<WriteFDiv64XLd, ICXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair 2209 2210def ICXWriteGatherEVEX2 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2211 let Latency = 17; 2212 let NumMicroOps = 5; // 2 uops perform multiple loads 2213 let ResourceCycles = [1,2,1,1]; 2214} 2215def: InstRW<[ICXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm, 2216 VGATHERDPDZ128rm, VPGATHERDQZ128rm, 2217 VGATHERQPDZ128rm, VPGATHERQQZ128rm)>; 2218 2219def ICXWriteGatherEVEX4 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2220 let Latency = 19; 2221 let NumMicroOps = 5; // 2 uops perform multiple loads 2222 let ResourceCycles = [1,4,1,1]; 2223} 2224def: InstRW<[ICXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm, 2225 VGATHERQPDZ256rm, VPGATHERQQZ256rm, 2226 VGATHERDPSZ128rm, VPGATHERDDZ128rm, 2227 VGATHERDPDZ256rm, VPGATHERDQZ256rm)>; 2228 2229def ICXWriteGatherEVEX8 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2230 let Latency = 21; 2231 let NumMicroOps = 5; // 2 uops perform multiple loads 2232 let ResourceCycles = [1,8,1,1]; 2233} 2234def: InstRW<[ICXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm, 2235 VGATHERDPDZrm, VPGATHERDQZrm, 2236 VGATHERQPDZrm, VPGATHERQQZrm, 2237 VGATHERQPSZrm, VPGATHERQDZrm)>; 2238 2239def ICXWriteGatherEVEX16 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2240 let Latency = 25; 2241 let NumMicroOps = 5; // 2 uops perform multiple loads 2242 let ResourceCycles = [1,16,1,1]; 2243} 2244def: InstRW<[ICXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>; 2245 2246def ICXWriteResGroup219 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2247 let Latency = 20; 2248 let NumMicroOps = 8; 2249 let ResourceCycles = [1,1,1,1,1,1,2]; 2250} 2251def: InstRW<[ICXWriteResGroup219], (instrs INSB, INSL, INSW)>; 2252 2253def ICXWriteResGroup220 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort0156]> { 2254 let Latency = 20; 2255 let NumMicroOps = 10; 2256 let ResourceCycles = [1,2,7]; 2257} 2258def: InstRW<[ICXWriteResGroup220], (instrs MWAITrr)>; 2259 2260def ICXWriteResGroup222 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2261 let Latency = 21; 2262 let NumMicroOps = 2; 2263 let ResourceCycles = [1,1,8]; 2264} 2265def : SchedAlias<WriteFDiv64YLd, ICXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair 2266 2267def ICXWriteResGroup223 : SchedWriteRes<[ICXPort0,ICXPort23]> { 2268 let Latency = 22; 2269 let NumMicroOps = 2; 2270 let ResourceCycles = [1,1]; 2271} 2272def: InstRW<[ICXWriteResGroup223], (instregex "DIV_F(32|64)m")>; 2273 2274def ICXWriteResGroupVEX2 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2275 let Latency = 18; 2276 let NumMicroOps = 5; // 2 uops perform multiple loads 2277 let ResourceCycles = [1,2,1,1]; 2278} 2279def: InstRW<[ICXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, 2280 VGATHERQPDrm, VPGATHERQQrm, 2281 VGATHERQPSrm, VPGATHERQDrm)>; 2282 2283def ICXWriteResGroupVEX4 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2284 let Latency = 20; 2285 let NumMicroOps = 5; // 2 uops peform multiple loads 2286 let ResourceCycles = [1,4,1,1]; 2287} 2288def: InstRW<[ICXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 2289 VGATHERDPSrm, VPGATHERDDrm, 2290 VGATHERQPDYrm, VPGATHERQQYrm, 2291 VGATHERQPSYrm, VPGATHERQDYrm)>; 2292 2293def ICXWriteResGroupVEX8 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2294 let Latency = 22; 2295 let NumMicroOps = 5; // 2 uops perform multiple loads 2296 let ResourceCycles = [1,8,1,1]; 2297} 2298def: InstRW<[ICXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 2299 2300def ICXWriteResGroup225 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2301 let Latency = 22; 2302 let NumMicroOps = 14; 2303 let ResourceCycles = [5,5,4]; 2304} 2305def: InstRW<[ICXWriteResGroup225], (instregex "VPCONFLICTDZ128rr", 2306 "VPCONFLICTQZ256rr")>; 2307 2308def ICXWriteResGroup228 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2309 let Latency = 23; 2310 let NumMicroOps = 19; 2311 let ResourceCycles = [2,1,4,1,1,4,6]; 2312} 2313def: InstRW<[ICXWriteResGroup228], (instrs CMPXCHG16B)>; 2314 2315def ICXWriteResGroup233 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2316 let Latency = 25; 2317 let NumMicroOps = 3; 2318 let ResourceCycles = [1,1,1]; 2319} 2320def: InstRW<[ICXWriteResGroup233], (instregex "DIV_FI(16|32)m")>; 2321 2322def ICXWriteResGroup239 : SchedWriteRes<[ICXPort0,ICXPort23]> { 2323 let Latency = 27; 2324 let NumMicroOps = 2; 2325 let ResourceCycles = [1,1]; 2326} 2327def: InstRW<[ICXWriteResGroup239], (instregex "DIVR_F(32|64)m")>; 2328 2329def ICXWriteResGroup242 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2330 let Latency = 29; 2331 let NumMicroOps = 15; 2332 let ResourceCycles = [5,5,1,4]; 2333} 2334def: InstRW<[ICXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>; 2335 2336def ICXWriteResGroup243 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2337 let Latency = 30; 2338 let NumMicroOps = 3; 2339 let ResourceCycles = [1,1,1]; 2340} 2341def: InstRW<[ICXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>; 2342 2343def ICXWriteResGroup247 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort06,ICXPort0156]> { 2344 let Latency = 35; 2345 let NumMicroOps = 23; 2346 let ResourceCycles = [1,5,3,4,10]; 2347} 2348def: InstRW<[ICXWriteResGroup247], (instregex "IN(8|16|32)ri", 2349 "IN(8|16|32)rr")>; 2350 2351def ICXWriteResGroup248 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2352 let Latency = 35; 2353 let NumMicroOps = 23; 2354 let ResourceCycles = [1,5,2,1,4,10]; 2355} 2356def: InstRW<[ICXWriteResGroup248], (instregex "OUT(8|16|32)ir", 2357 "OUT(8|16|32)rr")>; 2358 2359def ICXWriteResGroup249 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2360 let Latency = 37; 2361 let NumMicroOps = 21; 2362 let ResourceCycles = [9,7,5]; 2363} 2364def: InstRW<[ICXWriteResGroup249], (instregex "VPCONFLICTDZ256rr", 2365 "VPCONFLICTQZrr")>; 2366 2367def ICXWriteResGroup250 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> { 2368 let Latency = 37; 2369 let NumMicroOps = 31; 2370 let ResourceCycles = [1,8,1,21]; 2371} 2372def: InstRW<[ICXWriteResGroup250], (instregex "XRSTOR(64)?")>; 2373 2374def ICXWriteResGroup252 : SchedWriteRes<[ICXPort1,ICXPort4,ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort15,ICXPort0156]> { 2375 let Latency = 40; 2376 let NumMicroOps = 18; 2377 let ResourceCycles = [1,1,2,3,1,1,1,8]; 2378} 2379def: InstRW<[ICXWriteResGroup252], (instrs VMCLEARm)>; 2380 2381def ICXWriteResGroup253 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 2382 let Latency = 41; 2383 let NumMicroOps = 39; 2384 let ResourceCycles = [1,10,1,1,26]; 2385} 2386def: InstRW<[ICXWriteResGroup253], (instrs XSAVE64)>; 2387 2388def ICXWriteResGroup254 : SchedWriteRes<[ICXPort5,ICXPort0156]> { 2389 let Latency = 42; 2390 let NumMicroOps = 22; 2391 let ResourceCycles = [2,20]; 2392} 2393def: InstRW<[ICXWriteResGroup254], (instrs RDTSCP)>; 2394 2395def ICXWriteResGroup255 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 2396 let Latency = 42; 2397 let NumMicroOps = 40; 2398 let ResourceCycles = [1,11,1,1,26]; 2399} 2400def: InstRW<[ICXWriteResGroup255], (instrs XSAVE)>; 2401def: InstRW<[ICXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 2402 2403def ICXWriteResGroup256 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2404 let Latency = 44; 2405 let NumMicroOps = 22; 2406 let ResourceCycles = [9,7,1,5]; 2407} 2408def: InstRW<[ICXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)", 2409 "VPCONFLICTQZrm(b?)")>; 2410 2411def ICXWriteResGroup258 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05,ICXPort06,ICXPort0156]> { 2412 let Latency = 62; 2413 let NumMicroOps = 64; 2414 let ResourceCycles = [2,8,5,10,39]; 2415} 2416def: InstRW<[ICXWriteResGroup258], (instrs FLDENVm)>; 2417 2418def ICXWriteResGroup259 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> { 2419 let Latency = 63; 2420 let NumMicroOps = 88; 2421 let ResourceCycles = [4,4,31,1,2,1,45]; 2422} 2423def: InstRW<[ICXWriteResGroup259], (instrs FXRSTOR64)>; 2424 2425def ICXWriteResGroup260 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> { 2426 let Latency = 63; 2427 let NumMicroOps = 90; 2428 let ResourceCycles = [4,2,33,1,2,1,47]; 2429} 2430def: InstRW<[ICXWriteResGroup260], (instrs FXRSTOR)>; 2431 2432def ICXWriteResGroup261 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2433 let Latency = 67; 2434 let NumMicroOps = 35; 2435 let ResourceCycles = [17,11,7]; 2436} 2437def: InstRW<[ICXWriteResGroup261], (instregex "VPCONFLICTDZrr")>; 2438 2439def ICXWriteResGroup262 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2440 let Latency = 74; 2441 let NumMicroOps = 36; 2442 let ResourceCycles = [17,11,1,7]; 2443} 2444def: InstRW<[ICXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>; 2445 2446def ICXWriteResGroup263 : SchedWriteRes<[ICXPort5,ICXPort05,ICXPort0156]> { 2447 let Latency = 75; 2448 let NumMicroOps = 15; 2449 let ResourceCycles = [6,3,6]; 2450} 2451def: InstRW<[ICXWriteResGroup263], (instrs FNINIT)>; 2452 2453def ICXWriteResGroup266 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort4,ICXPort5,ICXPort6,ICXPort237,ICXPort06,ICXPort0156]> { 2454 let Latency = 106; 2455 let NumMicroOps = 100; 2456 let ResourceCycles = [9,1,11,16,1,11,21,30]; 2457} 2458def: InstRW<[ICXWriteResGroup266], (instrs FSTENVm)>; 2459 2460def ICXWriteResGroup267 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 2461 let Latency = 140; 2462 let NumMicroOps = 4; 2463 let ResourceCycles = [1,3]; 2464} 2465def: InstRW<[ICXWriteResGroup267], (instrs PAUSE)>; 2466 2467def: InstRW<[WriteZero], (instrs CLC)>; 2468 2469 2470// Instruction variants handled by the renamer. These might not need execution 2471// ports in certain conditions. 2472// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 2473// section "Skylake Pipeline" > "Register allocation and renaming". 2474// These can be investigated with llvm-exegesis, e.g. 2475// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2476// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2477 2478def ICXWriteZeroLatency : SchedWriteRes<[]> { 2479 let Latency = 0; 2480} 2481 2482def ICXWriteZeroIdiom : SchedWriteVariant<[ 2483 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2484 SchedVar<NoSchedPred, [WriteALU]> 2485]>; 2486def : InstRW<[ICXWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 2487 XOR32rr, XOR64rr)>; 2488 2489def ICXWriteFZeroIdiom : SchedWriteVariant<[ 2490 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2491 SchedVar<NoSchedPred, [WriteFLogic]> 2492]>; 2493def : InstRW<[ICXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, 2494 XORPDrr, VXORPDrr, 2495 VXORPSZ128rr, 2496 VXORPDZ128rr)>; 2497 2498def ICXWriteFZeroIdiomY : SchedWriteVariant<[ 2499 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2500 SchedVar<NoSchedPred, [WriteFLogicY]> 2501]>; 2502def : InstRW<[ICXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr, 2503 VXORPSZ256rr, VXORPDZ256rr)>; 2504 2505def ICXWriteFZeroIdiomZ : SchedWriteVariant<[ 2506 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2507 SchedVar<NoSchedPred, [WriteFLogicZ]> 2508]>; 2509def : InstRW<[ICXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>; 2510 2511def ICXWriteVZeroIdiomLogicX : SchedWriteVariant<[ 2512 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2513 SchedVar<NoSchedPred, [WriteVecLogicX]> 2514]>; 2515def : InstRW<[ICXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, 2516 VPXORDZ128rr, VPXORQZ128rr)>; 2517 2518def ICXWriteVZeroIdiomLogicY : SchedWriteVariant<[ 2519 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2520 SchedVar<NoSchedPred, [WriteVecLogicY]> 2521]>; 2522def : InstRW<[ICXWriteVZeroIdiomLogicY], (instrs VPXORYrr, 2523 VPXORDZ256rr, VPXORQZ256rr)>; 2524 2525def ICXWriteVZeroIdiomLogicZ : SchedWriteVariant<[ 2526 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2527 SchedVar<NoSchedPred, [WriteVecLogicZ]> 2528]>; 2529def : InstRW<[ICXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>; 2530 2531def ICXWriteVZeroIdiomALUX : SchedWriteVariant<[ 2532 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2533 SchedVar<NoSchedPred, [WriteVecALUX]> 2534]>; 2535def : InstRW<[ICXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 2536 PCMPGTDrr, VPCMPGTDrr, 2537 PCMPGTWrr, VPCMPGTWrr)>; 2538 2539def ICXWriteVZeroIdiomALUY : SchedWriteVariant<[ 2540 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2541 SchedVar<NoSchedPred, [WriteVecALUY]> 2542]>; 2543def : InstRW<[ICXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 2544 VPCMPGTDYrr, 2545 VPCMPGTWYrr)>; 2546 2547def ICXWritePSUB : SchedWriteRes<[ICXPort015]> { 2548 let Latency = 1; 2549 let NumMicroOps = 1; 2550 let ResourceCycles = [1]; 2551} 2552 2553def ICXWriteVZeroIdiomPSUB : SchedWriteVariant<[ 2554 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2555 SchedVar<NoSchedPred, [ICXWritePSUB]> 2556]>; 2557 2558def : InstRW<[ICXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr, 2559 PSUBDrr, VPSUBDrr, VPSUBDZ128rr, 2560 PSUBQrr, VPSUBQrr, VPSUBQZ128rr, 2561 PSUBWrr, VPSUBWrr, VPSUBWZ128rr, 2562 VPSUBBYrr, VPSUBBZ256rr, 2563 VPSUBDYrr, VPSUBDZ256rr, 2564 VPSUBQYrr, VPSUBQZ256rr, 2565 VPSUBWYrr, VPSUBWZ256rr, 2566 VPSUBBZrr, 2567 VPSUBDZrr, 2568 VPSUBQZrr, 2569 VPSUBWZrr)>; 2570def ICXWritePCMPGTQ : SchedWriteRes<[ICXPort5]> { 2571 let Latency = 3; 2572 let NumMicroOps = 1; 2573 let ResourceCycles = [1]; 2574} 2575 2576def ICXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 2577 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2578 SchedVar<NoSchedPred, [ICXWritePCMPGTQ]> 2579]>; 2580def : InstRW<[ICXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 2581 VPCMPGTQYrr)>; 2582 2583 2584// CMOVs that use both Z and C flag require an extra uop. 2585def ICXWriteCMOVA_CMOVBErr : SchedWriteRes<[ICXPort06]> { 2586 let Latency = 2; 2587 let ResourceCycles = [2]; 2588 let NumMicroOps = 2; 2589} 2590 2591def ICXWriteCMOVA_CMOVBErm : SchedWriteRes<[ICXPort23,ICXPort06]> { 2592 let Latency = 7; 2593 let ResourceCycles = [1,2]; 2594 let NumMicroOps = 3; 2595} 2596 2597def ICXCMOVA_CMOVBErr : SchedWriteVariant<[ 2598 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [ICXWriteCMOVA_CMOVBErr]>, 2599 SchedVar<NoSchedPred, [WriteCMOV]> 2600]>; 2601 2602def ICXCMOVA_CMOVBErm : SchedWriteVariant<[ 2603 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [ICXWriteCMOVA_CMOVBErm]>, 2604 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 2605]>; 2606 2607def : InstRW<[ICXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 2608def : InstRW<[ICXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 2609 2610// SETCCs that use both Z and C flag require an extra uop. 2611def ICXWriteSETA_SETBEr : SchedWriteRes<[ICXPort06]> { 2612 let Latency = 2; 2613 let ResourceCycles = [2]; 2614 let NumMicroOps = 2; 2615} 2616 2617def ICXWriteSETA_SETBEm : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort06]> { 2618 let Latency = 3; 2619 let ResourceCycles = [1,1,2]; 2620 let NumMicroOps = 4; 2621} 2622 2623def ICXSETA_SETBErr : SchedWriteVariant<[ 2624 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [ICXWriteSETA_SETBEr]>, 2625 SchedVar<NoSchedPred, [WriteSETCC]> 2626]>; 2627 2628def ICXSETA_SETBErm : SchedWriteVariant<[ 2629 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [ICXWriteSETA_SETBEm]>, 2630 SchedVar<NoSchedPred, [WriteSETCCStore]> 2631]>; 2632 2633def : InstRW<[ICXSETA_SETBErr], (instrs SETCCr)>; 2634def : InstRW<[ICXSETA_SETBErm], (instrs SETCCm)>; 2635 2636} // SchedModel 2637