xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86SchedHaswell.td (revision ec0ea6efa1ad229d75c394c1a9b9cac33af2b1d3)
1//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the machine model for Haswell to support instruction
10// scheduling and other instruction cost heuristics.
11//
12// Note that we define some instructions here that are not supported by haswell,
13// but we still have to define them because KNL uses the HSW model.
14// They are currently tagged with a comment `Unsupported = 1`.
15// FIXME: Use Unsupported = 1 once KNL has its own model.
16//
17//===----------------------------------------------------------------------===//
18
19def HaswellModel : SchedMachineModel {
20  // All x86 instructions are modeled as a single micro-op, and HW can decode 4
21  // instructions per cycle.
22  let IssueWidth = 4;
23  let MicroOpBufferSize = 192; // Based on the reorder buffer.
24  let LoadLatency = 5;
25  let MispredictPenalty = 16;
26
27  // Based on the LSD (loop-stream detector) queue size and benchmarking data.
28  let LoopMicroOpBufferSize = 50;
29
30  // This flag is set to allow the scheduler to assign a default model to
31  // unrecognized opcodes.
32  let CompleteModel = 0;
33}
34
35let SchedModel = HaswellModel in {
36
37// Haswell can issue micro-ops to 8 different ports in one cycle.
38
39// Ports 0, 1, 5, and 6 handle all computation.
40// Port 4 gets the data half of stores. Store data can be available later than
41// the store address, but since we don't model the latency of stores, we can
42// ignore that.
43// Ports 2 and 3 are identical. They handle loads and the address half of
44// stores. Port 7 can handle address calculations.
45def HWPort0 : ProcResource<1>;
46def HWPort1 : ProcResource<1>;
47def HWPort2 : ProcResource<1>;
48def HWPort3 : ProcResource<1>;
49def HWPort4 : ProcResource<1>;
50def HWPort5 : ProcResource<1>;
51def HWPort6 : ProcResource<1>;
52def HWPort7 : ProcResource<1>;
53
54// Many micro-ops are capable of issuing on multiple ports.
55def HWPort01  : ProcResGroup<[HWPort0, HWPort1]>;
56def HWPort23  : ProcResGroup<[HWPort2, HWPort3]>;
57def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
58def HWPort04  : ProcResGroup<[HWPort0, HWPort4]>;
59def HWPort05  : ProcResGroup<[HWPort0, HWPort5]>;
60def HWPort06  : ProcResGroup<[HWPort0, HWPort6]>;
61def HWPort15  : ProcResGroup<[HWPort1, HWPort5]>;
62def HWPort16  : ProcResGroup<[HWPort1, HWPort6]>;
63def HWPort56  : ProcResGroup<[HWPort5, HWPort6]>;
64def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
65def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
66def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
67
68// 60 Entry Unified Scheduler
69def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
70                              HWPort5, HWPort6, HWPort7]> {
71  let BufferSize=60;
72}
73
74// Integer division issued on port 0.
75def HWDivider : ProcResource<1>;
76// FP division and sqrt on port 0.
77def HWFPDivider : ProcResource<1>;
78
79// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
80// cycles after the memory operand.
81def : ReadAdvance<ReadAfterLd, 5>;
82
83// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
84// until 5/6/7 cycles after the memory operand.
85def : ReadAdvance<ReadAfterVecLd, 5>;
86def : ReadAdvance<ReadAfterVecXLd, 6>;
87def : ReadAdvance<ReadAfterVecYLd, 7>;
88
89def : ReadAdvance<ReadInt2Fpu, 0>;
90
91// Many SchedWrites are defined in pairs with and without a folded load.
92// Instructions with folded loads are usually micro-fused, so they only appear
93// as two micro-ops when queued in the reservation station.
94// This multiclass defines the resource usage for variants with and without
95// folded loads.
96multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
97                          list<ProcResourceKind> ExePorts,
98                          int Lat, list<int> Res = [1], int UOps = 1,
99                          int LoadLat = 5> {
100  // Register variant is using a single cycle on ExePort.
101  def : WriteRes<SchedRW, ExePorts> {
102    let Latency = Lat;
103    let ResourceCycles = Res;
104    let NumMicroOps = UOps;
105  }
106
107  // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
108  // the latency (default = 5).
109  def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> {
110    let Latency = !add(Lat, LoadLat);
111    let ResourceCycles = !listconcat([1], Res);
112    let NumMicroOps = !add(UOps, 1);
113  }
114}
115
116// A folded store needs a cycle on port 4 for the store data, and an extra port
117// 2/3/7 cycle to recompute the address.
118def : WriteRes<WriteRMW, [HWPort237,HWPort4]>;
119
120// Store_addr on 237.
121// Store_data on 4.
122defm : X86WriteRes<WriteStore,   [HWPort237, HWPort4], 1, [1,1], 1>;
123defm : X86WriteRes<WriteStoreNT, [HWPort237, HWPort4], 1, [1,1], 2>;
124defm : X86WriteRes<WriteLoad,    [HWPort23], 5, [1], 1>;
125defm : X86WriteRes<WriteMove,    [HWPort0156], 1, [1], 1>;
126def  : WriteRes<WriteZero,       []>;
127
128// Model the effect of clobbering the read-write mask operand of the GATHER operation.
129// Does not cost anything by itself, only has latency, matching that of the WriteLoad,
130defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
131
132// Arithmetic.
133defm : HWWriteResPair<WriteALU,    [HWPort0156], 1>;
134defm : HWWriteResPair<WriteADC,    [HWPort06, HWPort0156], 2, [1,1], 2>;
135
136// Integer multiplication.
137defm : HWWriteResPair<WriteIMul8,     [HWPort1],   3>;
138defm : HWWriteResPair<WriteIMul16,    [HWPort1,HWPort06,HWPort0156], 4, [1,1,2], 4>;
139defm : X86WriteRes<WriteIMul16Imm,    [HWPort1,HWPort0156], 4, [1,1], 2>;
140defm : X86WriteRes<WriteIMul16ImmLd,  [HWPort1,HWPort0156,HWPort23], 8, [1,1,1], 3>;
141defm : HWWriteResPair<WriteIMul16Reg, [HWPort1],   3>;
142defm : HWWriteResPair<WriteIMul32,    [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>;
143defm : HWWriteResPair<WriteIMul32Imm, [HWPort1],   3>;
144defm : HWWriteResPair<WriteIMul32Reg, [HWPort1],   3>;
145defm : HWWriteResPair<WriteIMul64,    [HWPort1,HWPort6], 4, [1,1], 2>;
146defm : HWWriteResPair<WriteIMul64Imm, [HWPort1],   3>;
147defm : HWWriteResPair<WriteIMul64Reg, [HWPort1],   3>;
148def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
149
150defm : X86WriteRes<WriteBSWAP32,   [HWPort15], 1, [1], 1>;
151defm : X86WriteRes<WriteBSWAP64,   [HWPort06, HWPort15], 2, [1,1], 2>;
152defm : X86WriteRes<WriteCMPXCHG,[HWPort06, HWPort0156], 5, [2,3], 5>;
153defm : X86WriteRes<WriteCMPXCHGRMW,[HWPort23,HWPort06,HWPort0156,HWPort237,HWPort4], 9, [1,2,1,1,1], 6>;
154defm : X86WriteRes<WriteXCHG, [HWPort0156], 2, [3], 3>;
155
156// Integer shifts and rotates.
157defm : HWWriteResPair<WriteShift,    [HWPort06],  1>;
158defm : HWWriteResPair<WriteShiftCL,  [HWPort06, HWPort0156],  3, [2,1], 3>;
159defm : HWWriteResPair<WriteRotate,   [HWPort06],  1, [1], 1>;
160defm : HWWriteResPair<WriteRotateCL, [HWPort06, HWPort0156],  3, [2,1], 3>;
161
162// SHLD/SHRD.
163defm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>;
164defm : X86WriteRes<WriteSHDrrcl,[HWPort1, HWPort06, HWPort0156], 6, [1, 1, 2], 4>;
165defm : X86WriteRes<WriteSHDmri, [HWPort1, HWPort23, HWPort237, HWPort0156], 10, [1, 1, 1, 1], 4>;
166defm : X86WriteRes<WriteSHDmrcl,[HWPort1, HWPort23, HWPort237, HWPort06, HWPort0156], 12, [1, 1, 1, 1, 2], 6>;
167
168defm : HWWriteResPair<WriteJump,   [HWPort06],  1>;
169defm : HWWriteResPair<WriteCRC32,  [HWPort1],   3>;
170
171defm : HWWriteResPair<WriteCMOV,  [HWPort06,HWPort0156], 2, [1,1], 2>; // Conditional move.
172defm : X86WriteRes<WriteFCMOV, [HWPort1], 3, [1], 1>; // x87 conditional move.
173def  : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
174def  : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> {
175  let Latency = 2;
176  let NumMicroOps = 3;
177}
178
179defm : X86WriteRes<WriteLAHFSAHF,        [HWPort06], 1, [1], 1>;
180defm : X86WriteRes<WriteBitTest,         [HWPort06], 1, [1], 1>;
181defm : X86WriteRes<WriteBitTestImmLd,    [HWPort06,HWPort23], 6, [1,1], 2>;
182defm : X86WriteRes<WriteBitTestRegLd,    [], 1, [], 10>;
183defm : X86WriteRes<WriteBitTestSet,      [HWPort06], 1, [1], 1>;
184defm : X86WriteRes<WriteBitTestSetImmLd, [HWPort06,HWPort23], 6, [1,1], 3>;
185//defm : X86WriteRes<WriteBitTestSetRegLd, [], 1, [], 11>;
186
187// This is for simple LEAs with one or two input operands.
188// The complex ones can only execute on port 1, and they require two cycles on
189// the port to read all inputs. We don't model that.
190def : WriteRes<WriteLEA, [HWPort15]>;
191
192// Bit counts.
193defm : HWWriteResPair<WriteBSF, [HWPort1], 3>;
194defm : HWWriteResPair<WriteBSR, [HWPort1], 3>;
195defm : HWWriteResPair<WriteLZCNT,          [HWPort1], 3>;
196defm : HWWriteResPair<WriteTZCNT,          [HWPort1], 3>;
197defm : HWWriteResPair<WritePOPCNT,         [HWPort1], 3>;
198
199// BMI1 BEXTR/BLS, BMI2 BZHI
200defm : HWWriteResPair<WriteBEXTR, [HWPort06,HWPort15], 2, [1,1], 2>;
201defm : HWWriteResPair<WriteBLS,   [HWPort15], 1>;
202defm : HWWriteResPair<WriteBZHI,  [HWPort15], 1>;
203
204// TODO: Why isn't the HWDivider used?
205defm : X86WriteRes<WriteDiv8,     [HWPort0,HWPort1,HWPort5,HWPort6], 22, [], 9>;
206defm : X86WriteRes<WriteDiv16,    [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;
207defm : X86WriteRes<WriteDiv32,    [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;
208defm : X86WriteRes<WriteDiv64,    [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;
209defm : X86WriteRes<WriteDiv8Ld,   [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
210defm : X86WriteRes<WriteDiv16Ld,  [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
211defm : X86WriteRes<WriteDiv32Ld,  [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
212defm : X86WriteRes<WriteDiv64Ld,  [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
213
214defm : X86WriteRes<WriteIDiv8,    [HWPort0,HWPort1,HWPort5,HWPort6], 23, [], 9>;
215defm : X86WriteRes<WriteIDiv16,   [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;
216defm : X86WriteRes<WriteIDiv32,   [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;
217defm : X86WriteRes<WriteIDiv64,   [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;
218defm : X86WriteRes<WriteIDiv8Ld,  [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
219defm : X86WriteRes<WriteIDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
220defm : X86WriteRes<WriteIDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
221defm : X86WriteRes<WriteIDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
222
223// Scalar and vector floating point.
224defm : X86WriteRes<WriteFLD0,          [HWPort01], 1, [1], 1>;
225defm : X86WriteRes<WriteFLD1,          [HWPort01], 1, [2], 2>;
226defm : X86WriteRes<WriteFLDC,          [HWPort01], 1, [2], 2>;
227defm : X86WriteRes<WriteFLoad,         [HWPort23], 5, [1], 1>;
228defm : X86WriteRes<WriteFLoadX,        [HWPort23], 6, [1], 1>;
229defm : X86WriteRes<WriteFLoadY,        [HWPort23], 7, [1], 1>;
230defm : X86WriteRes<WriteFMaskedLoad,   [HWPort23,HWPort5], 8, [1,2], 3>;
231defm : X86WriteRes<WriteFMaskedLoadY,  [HWPort23,HWPort5], 9, [1,2], 3>;
232defm : X86WriteRes<WriteFStore,        [HWPort237,HWPort4], 1, [1,1], 2>;
233defm : X86WriteRes<WriteFStoreX,       [HWPort237,HWPort4], 1, [1,1], 2>;
234defm : X86WriteRes<WriteFStoreY,       [HWPort237,HWPort4], 1, [1,1], 2>;
235defm : X86WriteRes<WriteFStoreNT,      [HWPort237,HWPort4], 1, [1,1], 2>;
236defm : X86WriteRes<WriteFStoreNTX,     [HWPort237,HWPort4], 1, [1,1], 2>;
237defm : X86WriteRes<WriteFStoreNTY,     [HWPort237,HWPort4], 1, [1,1], 2>;
238
239defm : X86WriteRes<WriteFMaskedStore32,  [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
240defm : X86WriteRes<WriteFMaskedStore32Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
241defm : X86WriteRes<WriteFMaskedStore64,  [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
242defm : X86WriteRes<WriteFMaskedStore64Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
243
244defm : X86WriteRes<WriteFMove,         [HWPort5], 1, [1], 1>;
245defm : X86WriteRes<WriteFMoveX,        [HWPort5], 1, [1], 1>;
246defm : X86WriteRes<WriteFMoveY,        [HWPort5], 1, [1], 1>;
247defm : X86WriteRes<WriteEMMS,          [HWPort01,HWPort15,HWPort015,HWPort0156], 31, [8,1,21,1], 31>;
248
249defm : HWWriteResPair<WriteFAdd,    [HWPort1],  3, [1], 1, 5>;
250defm : HWWriteResPair<WriteFAddX,   [HWPort1],  3, [1], 1, 6>;
251defm : HWWriteResPair<WriteFAddY,   [HWPort1],  3, [1], 1, 7>;
252defm : HWWriteResPair<WriteFAddZ,   [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
253defm : HWWriteResPair<WriteFAdd64,  [HWPort1],  3, [1], 1, 5>;
254defm : HWWriteResPair<WriteFAdd64X, [HWPort1],  3, [1], 1, 6>;
255defm : HWWriteResPair<WriteFAdd64Y, [HWPort1],  3, [1], 1, 7>;
256defm : HWWriteResPair<WriteFAdd64Z, [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
257
258defm : HWWriteResPair<WriteFCmp,    [HWPort1],  3, [1], 1, 5>;
259defm : HWWriteResPair<WriteFCmpX,   [HWPort1],  3, [1], 1, 6>;
260defm : HWWriteResPair<WriteFCmpY,   [HWPort1],  3, [1], 1, 7>;
261defm : HWWriteResPair<WriteFCmpZ,   [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
262defm : HWWriteResPair<WriteFCmp64,  [HWPort1],  3, [1], 1, 5>;
263defm : HWWriteResPair<WriteFCmp64X, [HWPort1],  3, [1], 1, 6>;
264defm : HWWriteResPair<WriteFCmp64Y, [HWPort1],  3, [1], 1, 7>;
265defm : HWWriteResPair<WriteFCmp64Z, [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
266
267defm : HWWriteResPair<WriteFCom,    [HWPort1],  3>;
268defm : HWWriteResPair<WriteFComX,   [HWPort1],  3>;
269
270defm : HWWriteResPair<WriteFMul,    [HWPort01],  5, [1], 1, 5>;
271defm : HWWriteResPair<WriteFMulX,   [HWPort01],  5, [1], 1, 6>;
272defm : HWWriteResPair<WriteFMulY,   [HWPort01],  5, [1], 1, 7>;
273defm : HWWriteResPair<WriteFMulZ,   [HWPort01],  5, [1], 1, 7>; // Unsupported = 1
274defm : HWWriteResPair<WriteFMul64,  [HWPort01],  5, [1], 1, 5>;
275defm : HWWriteResPair<WriteFMul64X, [HWPort01],  5, [1], 1, 6>;
276defm : HWWriteResPair<WriteFMul64Y, [HWPort01],  5, [1], 1, 7>;
277defm : HWWriteResPair<WriteFMul64Z, [HWPort01],  5, [1], 1, 7>; // Unsupported = 1
278
279defm : HWWriteResPair<WriteFDiv,    [HWPort0,HWFPDivider], 13, [1,7], 1, 5>;
280defm : HWWriteResPair<WriteFDivX,   [HWPort0,HWFPDivider], 13, [1,7], 1, 6>;
281defm : HWWriteResPair<WriteFDivY,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>;
282defm : HWWriteResPair<WriteFDivZ,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1
283defm : HWWriteResPair<WriteFDiv64,  [HWPort0,HWFPDivider], 20, [1,14], 1, 5>;
284defm : HWWriteResPair<WriteFDiv64X, [HWPort0,HWFPDivider], 20, [1,14], 1, 6>;
285defm : HWWriteResPair<WriteFDiv64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>;
286defm : HWWriteResPair<WriteFDiv64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1
287
288defm : HWWriteResPair<WriteFRcp,   [HWPort0],  5, [1], 1, 5>;
289defm : HWWriteResPair<WriteFRcpX,  [HWPort0],  5, [1], 1, 6>;
290defm : HWWriteResPair<WriteFRcpY,  [HWPort0,HWPort015], 11, [2,1], 3, 7>;
291defm : HWWriteResPair<WriteFRcpZ,  [HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1
292
293defm : HWWriteResPair<WriteFRsqrt, [HWPort0],  5, [1], 1, 5>;
294defm : HWWriteResPair<WriteFRsqrtX,[HWPort0],  5, [1], 1, 6>;
295defm : HWWriteResPair<WriteFRsqrtY,[HWPort0,HWPort015], 11, [2,1], 3, 7>;
296defm : HWWriteResPair<WriteFRsqrtZ,[HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1
297
298defm : HWWriteResPair<WriteFSqrt,    [HWPort0,HWFPDivider], 11, [1,7], 1, 5>;
299defm : HWWriteResPair<WriteFSqrtX,   [HWPort0,HWFPDivider], 11, [1,7], 1, 6>;
300defm : HWWriteResPair<WriteFSqrtY,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>;
301defm : HWWriteResPair<WriteFSqrtZ,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1
302defm : HWWriteResPair<WriteFSqrt64,  [HWPort0,HWFPDivider], 16, [1,14], 1, 5>;
303defm : HWWriteResPair<WriteFSqrt64X, [HWPort0,HWFPDivider], 16, [1,14], 1, 6>;
304defm : HWWriteResPair<WriteFSqrt64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>;
305defm : HWWriteResPair<WriteFSqrt64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1
306defm : HWWriteResPair<WriteFSqrt80,  [HWPort0,HWFPDivider], 23, [1,17]>;
307
308defm : HWWriteResPair<WriteFMA,   [HWPort01], 5, [1], 1, 5>;
309defm : HWWriteResPair<WriteFMAX,  [HWPort01], 5, [1], 1, 6>;
310defm : HWWriteResPair<WriteFMAY,  [HWPort01], 5, [1], 1, 7>;
311defm : HWWriteResPair<WriteFMAZ,  [HWPort01], 5, [1], 1, 7>; // Unsupported = 1
312defm : HWWriteResPair<WriteDPPD,  [HWPort0,HWPort1,HWPort5],  9, [1,1,1], 3, 6>;
313defm : HWWriteResPair<WriteDPPS,  [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 6>;
314defm : HWWriteResPair<WriteDPPSY, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>;
315defm : HWWriteResPair<WriteDPPSZ, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>; // Unsupported = 1
316defm : HWWriteResPair<WriteFSign,  [HWPort0], 1>;
317defm : X86WriteRes<WriteFRnd,            [HWPort23],  6, [1],   1>;
318defm : X86WriteRes<WriteFRndY,           [HWPort23],  6, [1],   1>;
319defm : X86WriteRes<WriteFRndZ,           [HWPort23],  6, [1],   1>; // Unsupported = 1
320defm : X86WriteRes<WriteFRndLd,  [HWPort1,HWPort23], 12, [2,1], 3>;
321defm : X86WriteRes<WriteFRndYLd, [HWPort1,HWPort23], 13, [2,1], 3>;
322defm : X86WriteRes<WriteFRndZLd, [HWPort1,HWPort23], 13, [2,1], 3>; // Unsupported = 1
323defm : HWWriteResPair<WriteFLogic,  [HWPort5], 1, [1], 1, 6>;
324defm : HWWriteResPair<WriteFLogicY, [HWPort5], 1, [1], 1, 7>;
325defm : HWWriteResPair<WriteFLogicZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
326defm : HWWriteResPair<WriteFTest,   [HWPort0], 1, [1], 1, 6>;
327defm : HWWriteResPair<WriteFTestY,  [HWPort0], 1, [1], 1, 7>;
328defm : HWWriteResPair<WriteFTestZ,  [HWPort0], 1, [1], 1, 7>; // Unsupported = 1
329defm : HWWriteResPair<WriteFShuffle,  [HWPort5], 1, [1], 1, 6>;
330defm : HWWriteResPair<WriteFShuffleY, [HWPort5], 1, [1], 1, 7>;
331defm : HWWriteResPair<WriteFShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
332defm : HWWriteResPair<WriteFVarShuffle,  [HWPort5], 1, [1], 1, 6>;
333defm : HWWriteResPair<WriteFVarShuffleY, [HWPort5], 1, [1], 1, 7>;
334defm : HWWriteResPair<WriteFVarShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
335defm : HWWriteResPair<WriteFBlend,  [HWPort015], 1, [1], 1, 6>;
336defm : HWWriteResPair<WriteFBlendY, [HWPort015], 1, [1], 1, 7>;
337defm : HWWriteResPair<WriteFBlendZ, [HWPort015], 1, [1], 1, 7>; // Unsupported = 1
338defm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3, [1], 1, 7>;
339defm : HWWriteResPair<WriteFVarShuffle256, [HWPort5], 3, [1], 1, 7>;
340defm : HWWriteResPair<WriteFVarBlend,  [HWPort5], 2, [2], 2, 6>;
341defm : HWWriteResPair<WriteFVarBlendY, [HWPort5], 2, [2], 2, 7>;
342defm : HWWriteResPair<WriteFVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1
343
344// Conversion between integer and float.
345defm : HWWriteResPair<WriteCvtSD2I,   [HWPort1], 3>;
346defm : HWWriteResPair<WriteCvtPD2I,   [HWPort1], 3>;
347defm : HWWriteResPair<WriteCvtPD2IY,  [HWPort1], 3>;
348defm : HWWriteResPair<WriteCvtPD2IZ,  [HWPort1], 3>; // Unsupported = 1
349defm : HWWriteResPair<WriteCvtSS2I,   [HWPort1], 3>;
350defm : HWWriteResPair<WriteCvtPS2I,   [HWPort1], 3>;
351defm : HWWriteResPair<WriteCvtPS2IY,  [HWPort1], 3>;
352defm : HWWriteResPair<WriteCvtPS2IZ,  [HWPort1], 3>; // Unsupported = 1
353
354defm : HWWriteResPair<WriteCvtI2SD,   [HWPort1], 4>;
355defm : HWWriteResPair<WriteCvtI2PD,   [HWPort1], 4>;
356defm : HWWriteResPair<WriteCvtI2PDY,  [HWPort1], 4>;
357defm : HWWriteResPair<WriteCvtI2PDZ,  [HWPort1], 4>; // Unsupported = 1
358defm : HWWriteResPair<WriteCvtI2SS,   [HWPort1], 4>;
359defm : HWWriteResPair<WriteCvtI2PS,   [HWPort1], 4>;
360defm : HWWriteResPair<WriteCvtI2PSY,  [HWPort1], 4>;
361defm : HWWriteResPair<WriteCvtI2PSZ,  [HWPort1], 4>; // Unsupported = 1
362
363defm : HWWriteResPair<WriteCvtSS2SD,  [HWPort1], 3>;
364defm : HWWriteResPair<WriteCvtPS2PD,  [HWPort1], 3>;
365defm : HWWriteResPair<WriteCvtPS2PDY, [HWPort1], 3>;
366defm : HWWriteResPair<WriteCvtPS2PDZ, [HWPort1], 3>; // Unsupported = 1
367defm : HWWriteResPair<WriteCvtSD2SS,  [HWPort1], 3>;
368defm : HWWriteResPair<WriteCvtPD2PS,  [HWPort1], 3>;
369defm : HWWriteResPair<WriteCvtPD2PSY, [HWPort1], 3>;
370defm : HWWriteResPair<WriteCvtPD2PSZ, [HWPort1], 3>; // Unsupported = 1
371
372defm : X86WriteRes<WriteCvtPH2PS,     [HWPort0,HWPort5], 2, [1,1], 2>;
373defm : X86WriteRes<WriteCvtPH2PSY,    [HWPort0,HWPort5], 2, [1,1], 2>;
374defm : X86WriteRes<WriteCvtPH2PSZ,    [HWPort0,HWPort5], 2, [1,1], 2>; // Unsupported = 1
375defm : X86WriteRes<WriteCvtPH2PSLd,  [HWPort0,HWPort23], 6, [1,1], 2>;
376defm : X86WriteRes<WriteCvtPH2PSYLd, [HWPort0,HWPort23], 7, [1,1], 2>;
377defm : X86WriteRes<WriteCvtPH2PSZLd, [HWPort0,HWPort23], 7, [1,1], 2>; // Unsupported = 1
378
379defm : X86WriteRes<WriteCvtPS2PH,    [HWPort1,HWPort5], 4, [1,1], 2>;
380defm : X86WriteRes<WriteCvtPS2PHY,   [HWPort1,HWPort5], 6, [1,1], 2>;
381defm : X86WriteRes<WriteCvtPS2PHZ,   [HWPort1,HWPort5], 6, [1,1], 2>; // Unsupported = 1
382defm : X86WriteRes<WriteCvtPS2PHSt,  [HWPort1,HWPort4,HWPort5,HWPort237], 5, [1,1,1,1], 4>;
383defm : X86WriteRes<WriteCvtPS2PHYSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>;
384defm : X86WriteRes<WriteCvtPS2PHZSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; // Unsupported = 1
385
386// Vector integer operations.
387defm : X86WriteRes<WriteVecLoad,         [HWPort23], 5, [1], 1>;
388defm : X86WriteRes<WriteVecLoadX,        [HWPort23], 6, [1], 1>;
389defm : X86WriteRes<WriteVecLoadY,        [HWPort23], 7, [1], 1>;
390defm : X86WriteRes<WriteVecLoadNT,       [HWPort23], 6, [1], 1>;
391defm : X86WriteRes<WriteVecLoadNTY,      [HWPort23], 7, [1], 1>;
392defm : X86WriteRes<WriteVecMaskedLoad,   [HWPort23,HWPort5], 8, [1,2], 3>;
393defm : X86WriteRes<WriteVecMaskedLoadY,  [HWPort23,HWPort5], 9, [1,2], 3>;
394defm : X86WriteRes<WriteVecStore,        [HWPort237,HWPort4], 1, [1,1], 2>;
395defm : X86WriteRes<WriteVecStoreX,       [HWPort237,HWPort4], 1, [1,1], 2>;
396defm : X86WriteRes<WriteVecStoreY,       [HWPort237,HWPort4], 1, [1,1], 2>;
397defm : X86WriteRes<WriteVecStoreNT,      [HWPort237,HWPort4], 1, [1,1], 2>;
398defm : X86WriteRes<WriteVecStoreNTY,     [HWPort237,HWPort4], 1, [1,1], 2>;
399defm : X86WriteRes<WriteVecMaskedStore32,  [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
400defm : X86WriteRes<WriteVecMaskedStore32Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
401defm : X86WriteRes<WriteVecMaskedStore64,  [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
402defm : X86WriteRes<WriteVecMaskedStore64Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
403defm : X86WriteRes<WriteVecMove,         [HWPort015], 1, [1], 1>;
404defm : X86WriteRes<WriteVecMoveX,        [HWPort015], 1, [1], 1>;
405defm : X86WriteRes<WriteVecMoveY,        [HWPort015], 1, [1], 1>;
406defm : X86WriteRes<WriteVecMoveToGpr,    [HWPort0], 1, [1], 1>;
407defm : X86WriteRes<WriteVecMoveFromGpr,  [HWPort5], 1, [1], 1>;
408
409defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 5>;
410defm : HWWriteResPair<WriteVecLogicX,[HWPort015], 1, [1], 1, 6>;
411defm : HWWriteResPair<WriteVecLogicY,[HWPort015], 1, [1], 1, 7>;
412defm : HWWriteResPair<WriteVecLogicZ,[HWPort015], 1, [1], 1, 7>; // Unsupported = 1
413defm : HWWriteResPair<WriteVecTest,  [HWPort0,HWPort5], 2, [1,1], 2, 6>;
414defm : HWWriteResPair<WriteVecTestY, [HWPort0,HWPort5], 4, [1,1], 2, 7>;
415defm : HWWriteResPair<WriteVecTestZ, [HWPort0,HWPort5], 4, [1,1], 2, 7>; // Unsupported = 1
416defm : HWWriteResPair<WriteVecALU,   [HWPort15],  1, [1], 1, 5>;
417defm : HWWriteResPair<WriteVecALUX,  [HWPort15],  1, [1], 1, 6>;
418defm : HWWriteResPair<WriteVecALUY,  [HWPort15],  1, [1], 1, 7>;
419defm : HWWriteResPair<WriteVecALUZ,  [HWPort15],  1, [1], 1, 7>; // Unsupported = 1
420defm : HWWriteResPair<WriteVecIMul,  [HWPort0],  5, [1], 1, 5>;
421defm : HWWriteResPair<WriteVecIMulX, [HWPort0],  5, [1], 1, 6>;
422defm : HWWriteResPair<WriteVecIMulY, [HWPort0],  5, [1], 1, 7>;
423defm : HWWriteResPair<WriteVecIMulZ, [HWPort0],  5, [1], 1, 7>; // Unsupported = 1
424defm : HWWriteResPair<WritePMULLD,   [HWPort0], 10, [2], 2, 6>;
425defm : HWWriteResPair<WritePMULLDY,  [HWPort0], 10, [2], 2, 7>;
426defm : HWWriteResPair<WritePMULLDZ,  [HWPort0], 10, [2], 2, 7>; // Unsupported = 1
427defm : HWWriteResPair<WriteShuffle,  [HWPort5],  1, [1], 1, 5>;
428defm : HWWriteResPair<WriteShuffleX, [HWPort5],  1, [1], 1, 6>;
429defm : HWWriteResPair<WriteShuffleY, [HWPort5],  1, [1], 1, 7>;
430defm : HWWriteResPair<WriteShuffleZ, [HWPort5],  1, [1], 1, 7>; // Unsupported = 1
431defm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1, [1], 1, 5>;
432defm : HWWriteResPair<WriteVarShuffleX,[HWPort5], 1, [1], 1, 6>;
433defm : HWWriteResPair<WriteVarShuffleY,[HWPort5], 1, [1], 1, 7>;
434defm : HWWriteResPair<WriteVarShuffleZ,[HWPort5], 1, [1], 1, 7>; // Unsupported = 1
435defm : HWWriteResPair<WriteBlend,  [HWPort5], 1, [1], 1, 6>;
436defm : HWWriteResPair<WriteBlendY, [HWPort5], 1, [1], 1, 7>;
437defm : HWWriteResPair<WriteBlendZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
438defm : HWWriteResPair<WriteShuffle256, [HWPort5], 3, [1], 1, 7>;
439defm : HWWriteResPair<WriteVPMOV256, [HWPort5], 3, [1], 1, 7>;
440defm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3, [1], 1, 7>;
441defm : HWWriteResPair<WriteVarBlend,  [HWPort5], 2, [2], 2, 6>;
442defm : HWWriteResPair<WriteVarBlendY, [HWPort5], 2, [2], 2, 7>;
443defm : HWWriteResPair<WriteVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1
444defm : HWWriteResPair<WriteMPSAD,  [HWPort0, HWPort5], 7, [1, 2], 3, 6>;
445defm : HWWriteResPair<WriteMPSADY, [HWPort0, HWPort5], 7, [1, 2], 3, 7>;
446defm : HWWriteResPair<WriteMPSADZ, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; // Unsupported = 1
447defm : HWWriteResPair<WritePSADBW,  [HWPort0], 5, [1], 1, 5>;
448defm : HWWriteResPair<WritePSADBWX, [HWPort0], 5, [1], 1, 6>;
449defm : HWWriteResPair<WritePSADBWY, [HWPort0], 5, [1], 1, 7>;
450defm : HWWriteResPair<WritePSADBWZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1
451defm : HWWriteResPair<WritePHMINPOS, [HWPort0],  5, [1], 1, 6>;
452
453// Vector integer shifts.
454defm : HWWriteResPair<WriteVecShift,     [HWPort0], 1, [1], 1, 5>;
455defm : HWWriteResPair<WriteVecShiftX,    [HWPort0,HWPort5],  2, [1,1], 2, 6>;
456defm : X86WriteRes<WriteVecShiftY,       [HWPort0,HWPort5],  4, [1,1], 2>;
457defm : X86WriteRes<WriteVecShiftZ,       [HWPort0,HWPort5],  4, [1,1], 2>; // Unsupported = 1
458defm : X86WriteRes<WriteVecShiftYLd,     [HWPort0,HWPort23], 8, [1,1], 2>;
459defm : X86WriteRes<WriteVecShiftZLd,     [HWPort0,HWPort23], 8, [1,1], 2>; // Unsupported = 1
460
461defm : HWWriteResPair<WriteVecShiftImm,  [HWPort0], 1, [1], 1, 5>;
462defm : HWWriteResPair<WriteVecShiftImmX, [HWPort0], 1, [1], 1, 6>;
463defm : HWWriteResPair<WriteVecShiftImmY, [HWPort0], 1, [1], 1, 7>;
464defm : HWWriteResPair<WriteVecShiftImmZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1
465defm : HWWriteResPair<WriteVarVecShift,  [HWPort0, HWPort5], 3, [2,1], 3, 6>;
466defm : HWWriteResPair<WriteVarVecShiftY, [HWPort0, HWPort5], 3, [2,1], 3, 7>;
467defm : HWWriteResPair<WriteVarVecShiftZ, [HWPort0, HWPort5], 3, [2,1], 3, 7>; // Unsupported = 1
468
469// Vector insert/extract operations.
470def : WriteRes<WriteVecInsert, [HWPort5]> {
471  let Latency = 2;
472  let NumMicroOps = 2;
473  let ResourceCycles = [2];
474}
475def : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> {
476  let Latency = 6;
477  let NumMicroOps = 2;
478}
479def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
480
481def : WriteRes<WriteVecExtract, [HWPort0,HWPort5]> {
482  let Latency = 2;
483  let NumMicroOps = 2;
484}
485def : WriteRes<WriteVecExtractSt, [HWPort4,HWPort5,HWPort237]> {
486  let Latency = 2;
487  let NumMicroOps = 3;
488}
489
490// String instructions.
491
492// Packed Compare Implicit Length Strings, Return Mask
493def : WriteRes<WritePCmpIStrM, [HWPort0]> {
494  let Latency = 11;
495  let NumMicroOps = 3;
496  let ResourceCycles = [3];
497}
498def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
499  let Latency = 17;
500  let NumMicroOps = 4;
501  let ResourceCycles = [3,1];
502}
503
504// Packed Compare Explicit Length Strings, Return Mask
505def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> {
506  let Latency = 19;
507  let NumMicroOps = 9;
508  let ResourceCycles = [4,3,1,1];
509}
510def : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> {
511  let Latency = 25;
512  let NumMicroOps = 10;
513  let ResourceCycles = [4,3,1,1,1];
514}
515
516// Packed Compare Implicit Length Strings, Return Index
517def : WriteRes<WritePCmpIStrI, [HWPort0]> {
518  let Latency = 11;
519  let NumMicroOps = 3;
520  let ResourceCycles = [3];
521}
522def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
523  let Latency = 17;
524  let NumMicroOps = 4;
525  let ResourceCycles = [3,1];
526}
527
528// Packed Compare Explicit Length Strings, Return Index
529def : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> {
530  let Latency = 18;
531  let NumMicroOps = 8;
532  let ResourceCycles = [4,3,1];
533}
534def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> {
535  let Latency = 24;
536  let NumMicroOps = 9;
537  let ResourceCycles = [4,3,1,1];
538}
539
540// MOVMSK Instructions.
541def : WriteRes<WriteFMOVMSK,    [HWPort0]> { let Latency = 3; }
542def : WriteRes<WriteVecMOVMSK,  [HWPort0]> { let Latency = 3; }
543def : WriteRes<WriteVecMOVMSKY, [HWPort0]> { let Latency = 3; }
544def : WriteRes<WriteMMXMOVMSK,  [HWPort0]> { let Latency = 1; }
545
546// AES Instructions.
547def : WriteRes<WriteAESDecEnc, [HWPort5]> {
548  let Latency = 7;
549  let NumMicroOps = 1;
550  let ResourceCycles = [1];
551}
552def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
553  let Latency = 13;
554  let NumMicroOps = 2;
555  let ResourceCycles = [1,1];
556}
557
558def : WriteRes<WriteAESIMC, [HWPort5]> {
559  let Latency = 14;
560  let NumMicroOps = 2;
561  let ResourceCycles = [2];
562}
563def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
564  let Latency = 20;
565  let NumMicroOps = 3;
566  let ResourceCycles = [2,1];
567}
568
569def : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> {
570  let Latency = 29;
571  let NumMicroOps = 11;
572  let ResourceCycles = [2,7,2];
573}
574def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> {
575  let Latency = 34;
576  let NumMicroOps = 11;
577  let ResourceCycles = [2,7,1,1];
578}
579
580// Carry-less multiplication instructions.
581def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
582  let Latency = 11;
583  let NumMicroOps = 3;
584  let ResourceCycles = [2,1];
585}
586def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
587  let Latency = 17;
588  let NumMicroOps = 4;
589  let ResourceCycles = [2,1,1];
590}
591
592// Load/store MXCSR.
593def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
594def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
595
596def : WriteRes<WriteSystem,     [HWPort0156]> { let Latency = 100; }
597def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
598def : WriteRes<WriteFence,  [HWPort23, HWPort4]>;
599def : WriteRes<WriteNop, []>;
600
601//================ Exceptions ================//
602
603//-- Specific Scheduling Models --//
604
605// Starting with P0.
606def HWWriteP0 : SchedWriteRes<[HWPort0]>;
607
608def HWWriteP01 : SchedWriteRes<[HWPort01]>;
609
610def HWWrite2P01 : SchedWriteRes<[HWPort01]> {
611  let NumMicroOps = 2;
612}
613def HWWrite3P01 : SchedWriteRes<[HWPort01]> {
614  let NumMicroOps = 3;
615}
616
617def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
618  let NumMicroOps = 2;
619}
620
621def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
622  let NumMicroOps = 3;
623  let ResourceCycles = [2, 1];
624}
625
626// Starting with P1.
627def HWWriteP1 : SchedWriteRes<[HWPort1]>;
628
629
630def HWWrite2P1 : SchedWriteRes<[HWPort1]> {
631  let NumMicroOps = 2;
632  let ResourceCycles = [2];
633}
634
635// Notation:
636// - r: register.
637// - mm: 64 bit mmx register.
638// - x = 128 bit xmm register.
639// - (x)mm = mmx or xmm register.
640// - y = 256 bit ymm register.
641// - v = any vector register.
642// - m = memory.
643
644//=== Integer Instructions ===//
645//-- Move instructions --//
646
647// XLAT.
648def HWWriteXLAT : SchedWriteRes<[]> {
649  let Latency = 7;
650  let NumMicroOps = 3;
651}
652def : InstRW<[HWWriteXLAT], (instrs XLAT)>;
653
654// PUSHA.
655def HWWritePushA : SchedWriteRes<[]> {
656  let NumMicroOps = 19;
657}
658def : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>;
659
660// POPA.
661def HWWritePopA : SchedWriteRes<[]> {
662  let NumMicroOps = 18;
663}
664def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>;
665
666//-- Arithmetic instructions --//
667
668// BTR BTS BTC.
669// m,r.
670def HWWriteBTRSCmr : SchedWriteRes<[]> {
671  let NumMicroOps = 11;
672}
673def : SchedAlias<WriteBitTestSetRegRMW, HWWriteBTRSCmr>;
674
675//-- Control transfer instructions --//
676
677// CALL.
678// i.
679def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
680  let NumMicroOps = 4;
681  let ResourceCycles = [1, 2, 1];
682}
683def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
684
685// BOUND.
686// r,m.
687def HWWriteBOUND : SchedWriteRes<[]> {
688  let NumMicroOps = 15;
689}
690def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>;
691
692// INTO.
693def HWWriteINTO : SchedWriteRes<[]> {
694  let NumMicroOps = 4;
695}
696def : InstRW<[HWWriteINTO], (instrs INTO)>;
697
698//-- String instructions --//
699
700// LODSB/W.
701def : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>;
702
703// LODSD/Q.
704def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>;
705
706// MOVS.
707def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
708  let Latency = 4;
709  let NumMicroOps = 5;
710  let ResourceCycles = [2, 1, 2];
711}
712def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
713
714// CMPS.
715def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
716  let Latency = 4;
717  let NumMicroOps = 5;
718  let ResourceCycles = [2, 3];
719}
720def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
721
722//-- Other --//
723
724// RDPMC.f
725def HWWriteRDPMC : SchedWriteRes<[]> {
726  let NumMicroOps = 34;
727}
728def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>;
729
730// RDRAND.
731def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
732  let NumMicroOps = 17;
733  let ResourceCycles = [1, 16];
734}
735def : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
736
737//=== Floating Point x87 Instructions ===//
738//-- Move instructions --//
739
740// FLD.
741// m80.
742def : InstRW<[HWWriteP01], (instrs LD_Frr)>;
743
744// FBLD.
745// m80.
746def HWWriteFBLD : SchedWriteRes<[]> {
747  let Latency = 47;
748  let NumMicroOps = 43;
749}
750def : InstRW<[HWWriteFBLD], (instrs FBLDm)>;
751
752// FST(P).
753// r.
754def : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>;
755
756// FFREE.
757def : InstRW<[HWWriteP01], (instregex "FFREE")>;
758
759// FNSAVE.
760def HWWriteFNSAVE : SchedWriteRes<[]> {
761  let NumMicroOps = 147;
762}
763def : InstRW<[HWWriteFNSAVE], (instrs FSAVEm)>;
764
765// FRSTOR.
766def HWWriteFRSTOR : SchedWriteRes<[]> {
767  let NumMicroOps = 90;
768}
769def : InstRW<[HWWriteFRSTOR], (instrs FRSTORm)>;
770
771//-- Arithmetic instructions --//
772
773// FCOMPP FUCOMPP.
774// r.
775def : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>;
776
777// FCOMI(P) FUCOMI(P).
778// m.
779def : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
780
781// FTST.
782def : InstRW<[HWWriteP1], (instregex "TST_F")>;
783
784// FXAM.
785def : InstRW<[HWWrite2P1], (instrs XAM_F)>;
786
787// FPREM.
788def HWWriteFPREM : SchedWriteRes<[]> {
789  let Latency = 19;
790  let NumMicroOps = 28;
791}
792def : InstRW<[HWWriteFPREM], (instrs FPREM)>;
793
794// FPREM1.
795def HWWriteFPREM1 : SchedWriteRes<[]> {
796  let Latency = 27;
797  let NumMicroOps = 41;
798}
799def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>;
800
801// FRNDINT.
802def HWWriteFRNDINT : SchedWriteRes<[]> {
803  let Latency = 11;
804  let NumMicroOps = 17;
805}
806def : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>;
807
808//-- Math instructions --//
809
810// FSCALE.
811def HWWriteFSCALE : SchedWriteRes<[]> {
812  let Latency = 75; // 49-125
813  let NumMicroOps = 50; // 25-75
814}
815def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>;
816
817// FXTRACT.
818def HWWriteFXTRACT : SchedWriteRes<[]> {
819  let Latency = 15;
820  let NumMicroOps = 17;
821}
822def : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>;
823
824////////////////////////////////////////////////////////////////////////////////
825// Horizontal add/sub  instructions.
826////////////////////////////////////////////////////////////////////////////////
827
828defm : HWWriteResPair<WriteFHAdd,  [HWPort1, HWPort5], 5, [1,2], 3, 6>;
829defm : HWWriteResPair<WriteFHAddY, [HWPort1, HWPort5], 5, [1,2], 3, 7>;
830defm : HWWriteResPair<WritePHAdd,  [HWPort5, HWPort15], 3, [2,1], 3, 5>;
831defm : HWWriteResPair<WritePHAddX, [HWPort5, HWPort15], 3, [2,1], 3, 6>;
832defm : HWWriteResPair<WritePHAddY, [HWPort5, HWPort15], 3, [2,1], 3, 7>;
833
834//=== Floating Point XMM and YMM Instructions ===//
835
836// Remaining instrs.
837
838def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> {
839  let Latency = 6;
840  let NumMicroOps = 1;
841  let ResourceCycles = [1];
842}
843def: InstRW<[HWWriteResGroup0], (instrs VBROADCASTSSrm)>;
844def: InstRW<[HWWriteResGroup0], (instregex "(V?)MOVSHDUPrm",
845                                           "(V?)MOVSLDUPrm",
846                                           "VPBROADCAST(D|Q)rm")>;
847
848def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {
849  let Latency = 7;
850  let NumMicroOps = 1;
851  let ResourceCycles = [1];
852}
853def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128,
854                                          VBROADCASTI128,
855                                          VBROADCASTSDYrm,
856                                          VBROADCASTSSYrm,
857                                          VMOVDDUPYrm,
858                                          VMOVSHDUPYrm,
859                                          VMOVSLDUPYrm)>;
860def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m",
861                                             "VPBROADCAST(D|Q)Yrm")>;
862
863def HWWriteResGroup0_2 : SchedWriteRes<[HWPort23]> {
864  let Latency = 5;
865  let NumMicroOps = 1;
866  let ResourceCycles = [1];
867}
868def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm(8|16|32)",
869                                             "MOVZX(16|32|64)rm(8|16)",
870                                             "(V?)MOVDDUPrm")>;
871
872def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
873  let Latency = 1;
874  let NumMicroOps = 2;
875  let ResourceCycles = [1,1];
876}
877def: InstRW<[HWWriteResGroup1], (instrs FBSTPm, VMPTRSTm)>;
878def: InstRW<[HWWriteResGroup1], (instregex "ST_FP(32|64|80)m")>;
879
880def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
881  let Latency = 1;
882  let NumMicroOps = 1;
883  let ResourceCycles = [1];
884}
885def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr",
886                                           "VPSRLVQ(Y?)rr")>;
887
888def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {
889  let Latency = 1;
890  let NumMicroOps = 1;
891  let ResourceCycles = [1];
892}
893def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r",
894                                           "UCOM_F(P?)r")>;
895
896def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
897  let Latency = 1;
898  let NumMicroOps = 1;
899  let ResourceCycles = [1];
900}
901def: InstRW<[HWWriteResGroup4], (instrs MMX_MOVQ2DQrr)>;
902
903def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
904  let Latency = 1;
905  let NumMicroOps = 1;
906  let ResourceCycles = [1];
907}
908def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>;
909
910def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> {
911  let Latency = 1;
912  let NumMicroOps = 1;
913  let ResourceCycles = [1];
914}
915def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>;
916
917def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {
918  let Latency = 1;
919  let NumMicroOps = 1;
920  let ResourceCycles = [1];
921}
922def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>;
923
924def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
925  let Latency = 1;
926  let NumMicroOps = 1;
927  let ResourceCycles = [1];
928}
929def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>;
930
931def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
932  let Latency = 1;
933  let NumMicroOps = 1;
934  let ResourceCycles = [1];
935}
936def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>;
937
938def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
939  let Latency = 1;
940  let NumMicroOps = 1;
941  let ResourceCycles = [1];
942}
943def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE,
944                                         CMC, STC,
945                                         SGDT64m,
946                                         SIDT64m,
947                                         SMSW16m,
948                                         STRm,
949                                         SYSCALL)>;
950
951def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
952  let Latency = 6;
953  let NumMicroOps = 2;
954  let ResourceCycles = [1,1];
955}
956def: InstRW<[HWWriteResGroup11], (instregex "(V?)CVTPS2PDrm")>;
957
958def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> {
959  let Latency = 7;
960  let NumMicroOps = 2;
961  let ResourceCycles = [1,1];
962}
963def: InstRW<[HWWriteResGroup11_1], (instrs VPSLLVQrm, VPSRLVQrm)>;
964def: InstRW<[HWWriteResGroup11_1], (instregex "(V?)CVTSS2SDrm")>;
965
966def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> {
967  let Latency = 8;
968  let NumMicroOps = 2;
969  let ResourceCycles = [1,1];
970}
971def: InstRW<[HWWriteResGroup11_2], (instrs VPSLLVQYrm, VPSRLVQYrm)>;
972
973def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
974  let Latency = 8;
975  let NumMicroOps = 2;
976  let ResourceCycles = [1,1];
977}
978def: InstRW<[HWWriteResGroup12], (instrs MMX_CVTPI2PSirm)>;
979def: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>;
980
981def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> {
982  let Latency = 6;
983  let NumMicroOps = 2;
984  let ResourceCycles = [1,1];
985}
986def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm",
987                                            "(V?)PMOV(SX|ZX)BQrm",
988                                            "(V?)PMOV(SX|ZX)BWrm",
989                                            "(V?)PMOV(SX|ZX)DQrm",
990                                            "(V?)PMOV(SX|ZX)WDrm",
991                                            "(V?)PMOV(SX|ZX)WQrm")>;
992
993def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> {
994  let Latency = 8;
995  let NumMicroOps = 2;
996  let ResourceCycles = [1,1];
997}
998def: InstRW<[HWWriteResGroup13_1], (instrs VPMOVSXBDYrm,
999                                           VPMOVSXBQYrm,
1000                                           VPMOVSXWQYrm)>;
1001
1002def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
1003  let Latency = 6;
1004  let NumMicroOps = 2;
1005  let ResourceCycles = [1,1];
1006}
1007def: InstRW<[HWWriteResGroup14], (instrs FARJMP64m)>;
1008def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>;
1009
1010def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
1011  let Latency = 6;
1012  let NumMicroOps = 2;
1013  let ResourceCycles = [1,1];
1014}
1015def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",
1016                                            "MOVBE(16|32|64)rm")>;
1017
1018def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> {
1019  let Latency = 7;
1020  let NumMicroOps = 2;
1021  let ResourceCycles = [1,1];
1022}
1023def: InstRW<[HWWriteResGroup17], (instrs VINSERTF128rm,
1024                                         VINSERTI128rm,
1025                                         VPBLENDDrmi)>;
1026
1027def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> {
1028  let Latency = 8;
1029  let NumMicroOps = 2;
1030  let ResourceCycles = [1,1];
1031}
1032def: InstRW<[HWWriteResGroup17_2], (instrs VPBLENDDYrmi)>;
1033
1034def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
1035  let Latency = 6;
1036  let NumMicroOps = 2;
1037  let ResourceCycles = [1,1];
1038}
1039def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>;
1040def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;
1041
1042def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
1043  let Latency = 2;
1044  let NumMicroOps = 2;
1045  let ResourceCycles = [1,1];
1046}
1047def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>;
1048
1049def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
1050  let Latency = 2;
1051  let NumMicroOps = 3;
1052  let ResourceCycles = [1,1,1];
1053}
1054def: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>;
1055
1056def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> {
1057  let Latency = 2;
1058  let NumMicroOps = 3;
1059  let ResourceCycles = [1,1,1];
1060}
1061def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>;
1062
1063def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
1064  let Latency = 2;
1065  let NumMicroOps = 3;
1066  let ResourceCycles = [1,1,1];
1067}
1068def: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>;
1069
1070def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
1071  let Latency = 2;
1072  let NumMicroOps = 3;
1073  let ResourceCycles = [1,1,1];
1074}
1075def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
1076                                         STOSB, STOSL, STOSQ, STOSW)>;
1077def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr")>;
1078
1079def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
1080  let Latency = 7;
1081  let NumMicroOps = 4;
1082  let ResourceCycles = [1,1,1,1];
1083}
1084def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)",
1085                                            "SHL(8|16|32|64)m(1|i)",
1086                                            "SHR(8|16|32|64)m(1|i)")>;
1087
1088def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1089  let Latency = 7;
1090  let NumMicroOps = 4;
1091  let ResourceCycles = [1,1,1,1];
1092}
1093def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm",
1094                                            "PUSH(16|32|64)rmm")>;
1095
1096def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> {
1097  let Latency = 2;
1098  let NumMicroOps = 2;
1099  let ResourceCycles = [2];
1100}
1101def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>;
1102
1103def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
1104  let Latency = 2;
1105  let NumMicroOps = 2;
1106  let ResourceCycles = [2];
1107}
1108def: InstRW<[HWWriteResGroup30], (instrs LFENCE,
1109                                         MFENCE,
1110                                         WAIT,
1111                                         XGETBV)>;
1112
1113def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> {
1114  let Latency = 2;
1115  let NumMicroOps = 2;
1116  let ResourceCycles = [1,1];
1117}
1118def: InstRW<[HWWriteResGroup31], (instregex "(V?)CVTPS2PDrr",
1119                                            "(V?)CVTSS2SDrr")>;
1120
1121def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> {
1122  let Latency = 2;
1123  let NumMicroOps = 2;
1124  let ResourceCycles = [1,1];
1125}
1126def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>;
1127
1128def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> {
1129  let Latency = 2;
1130  let NumMicroOps = 2;
1131  let ResourceCycles = [1,1];
1132}
1133def: InstRW<[HWWriteResGroup33], (instrs MMX_MOVDQ2Qrr)>;
1134
1135def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
1136  let Latency = 2;
1137  let NumMicroOps = 2;
1138  let ResourceCycles = [1,1];
1139}
1140def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>;
1141
1142def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> {
1143  let Latency = 7;
1144  let NumMicroOps = 3;
1145  let ResourceCycles = [2,1];
1146}
1147def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWirm,
1148                                           MMX_PACKSSWBirm,
1149                                           MMX_PACKUSWBirm)>;
1150
1151def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> {
1152  let Latency = 7;
1153  let NumMicroOps = 3;
1154  let ResourceCycles = [1,2];
1155}
1156def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64,
1157                                         SCASB, SCASL, SCASQ, SCASW)>;
1158
1159def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> {
1160  let Latency = 7;
1161  let NumMicroOps = 3;
1162  let ResourceCycles = [1,1,1];
1163}
1164def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>;
1165
1166def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
1167  let Latency = 7;
1168  let NumMicroOps = 3;
1169  let ResourceCycles = [1,1,1];
1170}
1171def: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>;
1172
1173def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
1174  let Latency = 3;
1175  let NumMicroOps = 4;
1176  let ResourceCycles = [1,1,1,1];
1177}
1178def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>;
1179
1180def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
1181  let Latency = 3;
1182  let NumMicroOps = 4;
1183  let ResourceCycles = [1,1,1,1];
1184}
1185def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>;
1186
1187def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
1188  let Latency = 8;
1189  let NumMicroOps = 5;
1190  let ResourceCycles = [1,1,1,2];
1191}
1192def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)",
1193                                            "ROR(8|16|32|64)m(1|i)")>;
1194
1195def HWWriteResGroup46_1 : SchedWriteRes<[HWPort06]> {
1196  let Latency = 2;
1197  let NumMicroOps = 2;
1198  let ResourceCycles = [2];
1199}
1200def: InstRW<[HWWriteResGroup46_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1201                                           ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1202
1203def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1204  let Latency = 8;
1205  let NumMicroOps = 5;
1206  let ResourceCycles = [1,1,1,2];
1207}
1208def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>;
1209
1210def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1211  let Latency = 8;
1212  let NumMicroOps = 5;
1213  let ResourceCycles = [1,1,1,1,1];
1214}
1215def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>;
1216def: InstRW<[HWWriteResGroup48], (instrs FARCALL64m)>;
1217
1218def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {
1219  let Latency = 3;
1220  let NumMicroOps = 1;
1221  let ResourceCycles = [1];
1222}
1223def: InstRW<[HWWriteResGroup50], (instrs MMX_CVTPI2PSirr)>;
1224def: InstRW<[HWWriteResGroup50], (instregex "P(DEP|EXT)(32|64)rr",
1225                                            "(V?)CVTDQ2PS(Y?)rr")>;
1226
1227def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> {
1228  let Latency = 3;
1229  let NumMicroOps = 1;
1230  let ResourceCycles = [1];
1231}
1232def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>;
1233
1234def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> {
1235  let Latency = 9;
1236  let NumMicroOps = 2;
1237  let ResourceCycles = [1,1];
1238}
1239def: InstRW<[HWWriteResGroup52], (instregex "(V?)CVTPS2DQrm",
1240                                            "(V?)CVTTPS2DQrm")>;
1241
1242def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> {
1243  let Latency = 10;
1244  let NumMicroOps = 2;
1245  let ResourceCycles = [1,1];
1246}
1247def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1248                                              "ILD_F(16|32|64)m")>;
1249def: InstRW<[HWWriteResGroup52_1], (instrs VCVTDQ2PSYrm,
1250                                           VCVTPS2DQYrm,
1251                                           VCVTTPS2DQYrm)>;
1252
1253def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> {
1254  let Latency = 9;
1255  let NumMicroOps = 2;
1256  let ResourceCycles = [1,1];
1257}
1258def: InstRW<[HWWriteResGroup53_1], (instrs VPMOVSXBWYrm,
1259                                           VPMOVSXDQYrm,
1260                                           VPMOVSXWDYrm,
1261                                           VPMOVZXWDYrm)>;
1262
1263def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> {
1264  let Latency = 3;
1265  let NumMicroOps = 3;
1266  let ResourceCycles = [2,1];
1267}
1268def: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWirr,
1269                                         MMX_PACKSSWBirr,
1270                                         MMX_PACKUSWBirr)>;
1271
1272def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> {
1273  let Latency = 3;
1274  let NumMicroOps = 3;
1275  let ResourceCycles = [1,2];
1276}
1277def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;
1278
1279def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> {
1280  let Latency = 3;
1281  let NumMicroOps = 3;
1282  let ResourceCycles = [1,2];
1283}
1284def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r(1|i)",
1285                                            "RCR(8|16|32|64)r(1|i)")>;
1286
1287def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> {
1288  let Latency = 4;
1289  let NumMicroOps = 3;
1290  let ResourceCycles = [1,1,1];
1291}
1292def: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>;
1293
1294def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> {
1295  let Latency = 4;
1296  let NumMicroOps = 3;
1297  let ResourceCycles = [1,1,1];
1298}
1299def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m",
1300                                            "IST_F(16|32)m")>;
1301
1302def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
1303  let Latency = 9;
1304  let NumMicroOps = 5;
1305  let ResourceCycles = [1,1,1,2];
1306}
1307def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)",
1308                                            "RCR(8|16|32|64)m(1|i)")>;
1309
1310def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1311  let Latency = 9;
1312  let NumMicroOps = 6;
1313  let ResourceCycles = [1,1,1,3];
1314}
1315def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
1316
1317def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1318  let Latency = 9;
1319  let NumMicroOps = 6;
1320  let ResourceCycles = [1,1,1,2,1];
1321}
1322def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL",
1323                                            "ROR(8|16|32|64)mCL",
1324                                            "SAR(8|16|32|64)mCL",
1325                                            "SHL(8|16|32|64)mCL",
1326                                            "SHR(8|16|32|64)mCL")>;
1327def: SchedAlias<WriteADCRMW, HWWriteResGroup69>;
1328
1329def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> {
1330  let Latency = 4;
1331  let NumMicroOps = 2;
1332  let ResourceCycles = [1,1];
1333}
1334def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVT(T?)SD2SI(64)?rr",
1335                                            "(V?)CVT(T?)SS2SI(64)?rr")>;
1336
1337def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> {
1338  let Latency = 4;
1339  let NumMicroOps = 2;
1340  let ResourceCycles = [1,1];
1341}
1342def: InstRW<[HWWriteResGroup71], (instrs VCVTPS2PDYrr)>;
1343
1344def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> {
1345  let Latency = 4;
1346  let NumMicroOps = 2;
1347  let ResourceCycles = [1,1];
1348}
1349def: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>;
1350
1351def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {
1352  let Latency = 4;
1353  let NumMicroOps = 2;
1354  let ResourceCycles = [1,1];
1355}
1356def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPI2PDirr,
1357                                         MMX_CVTPD2PIirr,
1358                                         MMX_CVTPS2PIirr,
1359                                         MMX_CVTTPD2PIirr,
1360                                         MMX_CVTTPS2PIirr)>;
1361def: InstRW<[HWWriteResGroup73], (instregex "(V?)CVTDQ2PDrr",
1362                                            "(V?)CVTPD2PSrr",
1363                                            "(V?)CVTSD2SSrr",
1364                                            "(V?)CVTSI(64)?2SDrr",
1365                                            "(V?)CVTSI2SSrr",
1366                                            "(V?)CVT(T?)PD2DQrr")>;
1367
1368def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> {
1369  let Latency = 11;
1370  let NumMicroOps = 3;
1371  let ResourceCycles = [2,1];
1372}
1373def: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>;
1374
1375def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1376  let Latency = 9;
1377  let NumMicroOps = 3;
1378  let ResourceCycles = [1,1,1];
1379}
1380def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm",
1381                                            "(V?)CVTSS2SI(64)?rm",
1382                                            "(V?)CVTTSD2SI(64)?rm",
1383                                            "VCVTTSS2SI64rm",
1384                                            "(V?)CVTTSS2SIrm")>;
1385
1386def HWWriteResGroup77 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
1387  let Latency = 10;
1388  let NumMicroOps = 3;
1389  let ResourceCycles = [1,1,1];
1390}
1391def: InstRW<[HWWriteResGroup77], (instrs VCVTPS2PDYrm)>;
1392
1393def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1394  let Latency = 10;
1395  let NumMicroOps = 3;
1396  let ResourceCycles = [1,1,1];
1397}
1398def: InstRW<[HWWriteResGroup78], (instrs CVTPD2PSrm,
1399                                         CVTPD2DQrm,
1400                                         CVTTPD2DQrm,
1401                                         MMX_CVTPD2PIirm,
1402                                         MMX_CVTTPD2PIirm,
1403                                         CVTDQ2PDrm,
1404                                         VCVTDQ2PDrm)>;
1405
1406def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1407  let Latency = 9;
1408  let NumMicroOps = 3;
1409  let ResourceCycles = [1,1,1];
1410}
1411def: InstRW<[HWWriteResGroup78_1], (instrs MMX_CVTPI2PDirm,
1412                                           CVTSD2SSrm, CVTSD2SSrm_Int,
1413                                           VCVTSD2SSrm, VCVTSD2SSrm_Int)>;
1414
1415def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> {
1416  let Latency = 9;
1417  let NumMicroOps = 3;
1418  let ResourceCycles = [1,1,1];
1419}
1420def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>;
1421
1422def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> {
1423  let Latency = 4;
1424  let NumMicroOps = 4;
1425  let ResourceCycles = [4];
1426}
1427def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>;
1428
1429def HWWriteResGroup82 : SchedWriteRes<[]> {
1430  let Latency = 0;
1431  let NumMicroOps = 4;
1432  let ResourceCycles = [];
1433}
1434def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>;
1435
1436def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> {
1437  let Latency = 4;
1438  let NumMicroOps = 4;
1439  let ResourceCycles = [1,1,2];
1440}
1441def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
1442
1443def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> {
1444  let Latency = 9;
1445  let NumMicroOps = 5;
1446  let ResourceCycles = [1,2,1,1];
1447}
1448def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
1449                                            "LSL(16|32|64)rm")>;
1450
1451def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
1452  let Latency = 5;
1453  let NumMicroOps = 6;
1454  let ResourceCycles = [1,1,4];
1455}
1456def: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>;
1457
1458def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> {
1459  let Latency = 5;
1460  let NumMicroOps = 1;
1461  let ResourceCycles = [1];
1462}
1463def: InstRW<[HWWriteResGroup89], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
1464
1465def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> {
1466  let Latency = 11;
1467  let NumMicroOps = 2;
1468  let ResourceCycles = [1,1];
1469}
1470def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>;
1471
1472def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> {
1473  let Latency = 12;
1474  let NumMicroOps = 2;
1475  let ResourceCycles = [1,1];
1476}
1477def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m")>;
1478def: InstRW<[HWWriteResGroup91_3], (instrs VPCMPGTQYrm)>;
1479
1480def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> {
1481  let Latency = 5;
1482  let NumMicroOps = 3;
1483  let ResourceCycles = [1,2];
1484}
1485def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>;
1486
1487def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> {
1488  let Latency = 5;
1489  let NumMicroOps = 3;
1490  let ResourceCycles = [1,1,1];
1491}
1492def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>;
1493
1494def HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> {
1495  let Latency = 10;
1496  let NumMicroOps = 4;
1497  let ResourceCycles = [1,1,1,1];
1498}
1499def: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>;
1500
1501def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> {
1502  let Latency = 5;
1503  let NumMicroOps = 5;
1504  let ResourceCycles = [1,4];
1505}
1506def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>;
1507
1508def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> {
1509  let Latency = 5;
1510  let NumMicroOps = 5;
1511  let ResourceCycles = [1,4];
1512}
1513def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>;
1514
1515def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> {
1516  let Latency = 6;
1517  let NumMicroOps = 2;
1518  let ResourceCycles = [1,1];
1519}
1520def: InstRW<[HWWriteResGroup102], (instrs VCVTDQ2PDYrr,
1521                                          VCVTPD2PSYrr,
1522                                          VCVTPD2DQYrr,
1523                                          VCVTTPD2DQYrr)>;
1524
1525def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> {
1526  let Latency = 13;
1527  let NumMicroOps = 3;
1528  let ResourceCycles = [2,1];
1529}
1530def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1531
1532def HWWriteResGroup104 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1533  let Latency = 12;
1534  let NumMicroOps = 3;
1535  let ResourceCycles = [1,1,1];
1536}
1537def: InstRW<[HWWriteResGroup104], (instrs VCVTDQ2PDYrm)>;
1538
1539def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> {
1540  let Latency = 6;
1541  let NumMicroOps = 4;
1542  let ResourceCycles = [1,1,1,1];
1543}
1544def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>;
1545
1546def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> {
1547  let Latency = 6;
1548  let NumMicroOps = 6;
1549  let ResourceCycles = [1,5];
1550}
1551def: InstRW<[HWWriteResGroup108], (instrs STD)>;
1552
1553def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> {
1554  let Latency = 7;
1555  let NumMicroOps = 7;
1556  let ResourceCycles = [2,2,1,2];
1557}
1558def: InstRW<[HWWriteResGroup114], (instrs LOOP)>;
1559
1560def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1561  let Latency = 15;
1562  let NumMicroOps = 3;
1563  let ResourceCycles = [1,1,1];
1564}
1565def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>;
1566
1567def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1568  let Latency = 16;
1569  let NumMicroOps = 10;
1570  let ResourceCycles = [1,1,1,4,1,2];
1571}
1572def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>;
1573
1574def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
1575  let Latency = 11;
1576  let NumMicroOps = 7;
1577  let ResourceCycles = [2,2,3];
1578}
1579def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL",
1580                                             "RCR(16|32|64)rCL")>;
1581
1582def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
1583  let Latency = 11;
1584  let NumMicroOps = 9;
1585  let ResourceCycles = [1,4,1,3];
1586}
1587def: InstRW<[HWWriteResGroup130], (instrs RCL8rCL)>;
1588
1589def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> {
1590  let Latency = 11;
1591  let NumMicroOps = 11;
1592  let ResourceCycles = [2,9];
1593}
1594def: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>;
1595
1596def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1597  let Latency = 17;
1598  let NumMicroOps = 14;
1599  let ResourceCycles = [1,1,1,4,2,5];
1600}
1601def: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>;
1602
1603def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1604  let Latency = 19;
1605  let NumMicroOps = 11;
1606  let ResourceCycles = [2,1,1,3,1,3];
1607}
1608def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>;
1609
1610def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
1611  let Latency = 14;
1612  let NumMicroOps = 10;
1613  let ResourceCycles = [2,3,1,4];
1614}
1615def: InstRW<[HWWriteResGroup142], (instrs RCR8rCL)>;
1616
1617def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> {
1618  let Latency = 19;
1619  let NumMicroOps = 15;
1620  let ResourceCycles = [1,14];
1621}
1622def: InstRW<[HWWriteResGroup143], (instrs POPF16)>;
1623
1624def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1625  let Latency = 21;
1626  let NumMicroOps = 8;
1627  let ResourceCycles = [1,1,1,1,1,1,2];
1628}
1629def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>;
1630
1631def HWWriteResGroup145 : SchedWriteRes<[HWPort5, HWPort6]> {
1632  let Latency = 8;
1633  let NumMicroOps = 20;
1634  let ResourceCycles = [1,1];
1635}
1636def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>;
1637
1638def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1639  let Latency = 22;
1640  let NumMicroOps = 19;
1641  let ResourceCycles = [2,1,4,1,1,4,6];
1642}
1643def: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>;
1644
1645def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> {
1646  let Latency = 17;
1647  let NumMicroOps = 15;
1648  let ResourceCycles = [2,1,2,4,2,4];
1649}
1650def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>;
1651
1652def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> {
1653  let Latency = 18;
1654  let NumMicroOps = 8;
1655  let ResourceCycles = [1,1,1,5];
1656}
1657def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>;
1658
1659def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
1660  let Latency = 23;
1661  let NumMicroOps = 19;
1662  let ResourceCycles = [3,1,15];
1663}
1664def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>;
1665
1666def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> {
1667  let Latency = 20;
1668  let NumMicroOps = 1;
1669  let ResourceCycles = [1];
1670}
1671def: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1672
1673def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> {
1674  let Latency = 27;
1675  let NumMicroOps = 2;
1676  let ResourceCycles = [1,1];
1677}
1678def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>;
1679
1680def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> {
1681  let Latency = 20;
1682  let NumMicroOps = 10;
1683  let ResourceCycles = [1,2,7];
1684}
1685def: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>;
1686
1687def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1688  let Latency = 30;
1689  let NumMicroOps = 3;
1690  let ResourceCycles = [1,1,1];
1691}
1692def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>;
1693
1694def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> {
1695  let Latency = 24;
1696  let NumMicroOps = 1;
1697  let ResourceCycles = [1];
1698}
1699def: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1700
1701def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> {
1702  let Latency = 31;
1703  let NumMicroOps = 2;
1704  let ResourceCycles = [1,1];
1705}
1706def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>;
1707
1708def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1709  let Latency = 30;
1710  let NumMicroOps = 27;
1711  let ResourceCycles = [1,5,1,1,19];
1712}
1713def: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>;
1714
1715def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1716  let Latency = 31;
1717  let NumMicroOps = 28;
1718  let ResourceCycles = [1,6,1,1,19];
1719}
1720def: InstRW<[HWWriteResGroup165], (instrs XSAVE)>;
1721def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
1722
1723def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1724  let Latency = 34;
1725  let NumMicroOps = 3;
1726  let ResourceCycles = [1,1,1];
1727}
1728def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>;
1729
1730def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> {
1731  let Latency = 35;
1732  let NumMicroOps = 23;
1733  let ResourceCycles = [1,5,3,4,10];
1734}
1735def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri",
1736                                             "IN(8|16|32)rr")>;
1737
1738def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1739  let Latency = 36;
1740  let NumMicroOps = 23;
1741  let ResourceCycles = [1,5,2,1,4,10];
1742}
1743def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir",
1744                                             "OUT(8|16|32)rr")>;
1745
1746def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> {
1747  let Latency = 41;
1748  let NumMicroOps = 18;
1749  let ResourceCycles = [1,1,2,3,1,1,1,8];
1750}
1751def: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>;
1752
1753def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> {
1754  let Latency = 42;
1755  let NumMicroOps = 22;
1756  let ResourceCycles = [2,20];
1757}
1758def: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>;
1759
1760def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> {
1761  let Latency = 61;
1762  let NumMicroOps = 64;
1763  let ResourceCycles = [2,2,8,1,10,2,39];
1764}
1765def: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>;
1766
1767def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
1768  let Latency = 64;
1769  let NumMicroOps = 88;
1770  let ResourceCycles = [4,4,31,1,2,1,45];
1771}
1772def: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>;
1773
1774def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
1775  let Latency = 64;
1776  let NumMicroOps = 90;
1777  let ResourceCycles = [4,2,33,1,2,1,47];
1778}
1779def: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>;
1780
1781def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> {
1782  let Latency = 75;
1783  let NumMicroOps = 15;
1784  let ResourceCycles = [6,3,6];
1785}
1786def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>;
1787
1788def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> {
1789  let Latency = 115;
1790  let NumMicroOps = 100;
1791  let ResourceCycles = [9,9,11,8,1,11,21,30];
1792}
1793def: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>;
1794
1795def HWWriteResGroup184 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1796  let Latency = 14;
1797  let NumMicroOps = 12;
1798  let ResourceCycles = [2,2,2,1,3,2];
1799}
1800def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm, VPGATHERDQrm)>;
1801
1802def HWWriteResGroup185 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1803  let Latency = 17;
1804  let NumMicroOps = 20;
1805  let ResourceCycles = [3,3,4,1,5,4];
1806}
1807def: InstRW<[HWWriteResGroup185], (instrs VGATHERDPDYrm, VPGATHERDQYrm)>;
1808
1809def HWWriteResGroup186 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1810  let Latency = 16;
1811  let NumMicroOps = 20;
1812  let ResourceCycles = [3,3,4,1,5,4];
1813}
1814def: InstRW<[HWWriteResGroup186], (instrs VGATHERDPSrm, VPGATHERDDrm)>;
1815
1816def HWWriteResGroup187 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1817  let Latency = 22;
1818  let NumMicroOps = 34;
1819  let ResourceCycles = [5,3,8,1,9,8];
1820}
1821def: InstRW<[HWWriteResGroup187], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>;
1822
1823def HWWriteResGroup188 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1824  let Latency = 15;
1825  let NumMicroOps = 14;
1826  let ResourceCycles = [3,3,2,1,3,2];
1827}
1828def: InstRW<[HWWriteResGroup188], (instrs VGATHERQPDrm, VPGATHERQQrm)>;
1829
1830def HWWriteResGroup189 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1831  let Latency = 17;
1832  let NumMicroOps = 22;
1833  let ResourceCycles = [5,3,4,1,5,4];
1834}
1835def: InstRW<[HWWriteResGroup189], (instrs VGATHERQPDYrm, VPGATHERQQYrm,
1836                                          VGATHERQPSYrm, VPGATHERQDYrm)>;
1837
1838def HWWriteResGroup190 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> {
1839  let Latency = 16;
1840  let NumMicroOps = 15;
1841  let ResourceCycles = [3,3,2,1,4,2];
1842}
1843def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPSrm, VPGATHERQDrm)>;
1844
1845def: InstRW<[WriteZero], (instrs CLC)>;
1846
1847
1848// Instruction variants handled by the renamer. These might not need execution
1849// ports in certain conditions.
1850// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1851// section "Haswell and Broadwell Pipeline" > "Register allocation and
1852// renaming".
1853// These can be investigated with llvm-exegesis, e.g.
1854// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1855// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1856
1857def HWWriteZeroLatency : SchedWriteRes<[]> {
1858  let Latency = 0;
1859}
1860
1861def HWWriteZeroIdiom : SchedWriteVariant<[
1862    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1863    SchedVar<NoSchedPred,                          [WriteALU]>
1864]>;
1865def : InstRW<[HWWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1866                                         XOR32rr, XOR64rr)>;
1867
1868def HWWriteFZeroIdiom : SchedWriteVariant<[
1869    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1870    SchedVar<NoSchedPred,                          [WriteFLogic]>
1871]>;
1872def : InstRW<[HWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1873                                          VXORPDrr)>;
1874
1875def HWWriteFZeroIdiomY : SchedWriteVariant<[
1876    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1877    SchedVar<NoSchedPred,                          [WriteFLogicY]>
1878]>;
1879def : InstRW<[HWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1880
1881def HWWriteVZeroIdiomLogicX : SchedWriteVariant<[
1882    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1883    SchedVar<NoSchedPred,                          [WriteVecLogicX]>
1884]>;
1885def : InstRW<[HWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1886
1887def HWWriteVZeroIdiomLogicY : SchedWriteVariant<[
1888    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1889    SchedVar<NoSchedPred,                          [WriteVecLogicY]>
1890]>;
1891def : InstRW<[HWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1892
1893def HWWriteVZeroIdiomALUX : SchedWriteVariant<[
1894    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1895    SchedVar<NoSchedPred,                          [WriteVecALUX]>
1896]>;
1897def : InstRW<[HWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
1898                                              PSUBDrr, VPSUBDrr,
1899                                              PSUBQrr, VPSUBQrr,
1900                                              PSUBWrr, VPSUBWrr,
1901                                              PCMPGTBrr, VPCMPGTBrr,
1902                                              PCMPGTDrr, VPCMPGTDrr,
1903                                              PCMPGTWrr, VPCMPGTWrr)>;
1904
1905def HWWriteVZeroIdiomALUY : SchedWriteVariant<[
1906    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1907    SchedVar<NoSchedPred,                          [WriteVecALUY]>
1908]>;
1909def : InstRW<[HWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,
1910                                              VPSUBDYrr,
1911                                              VPSUBQYrr,
1912                                              VPSUBWYrr,
1913                                              VPCMPGTBYrr,
1914                                              VPCMPGTDYrr,
1915                                              VPCMPGTWYrr)>;
1916
1917def HWWritePCMPGTQ : SchedWriteRes<[HWPort0]> {
1918  let Latency = 5;
1919  let NumMicroOps = 1;
1920  let ResourceCycles = [1];
1921}
1922
1923def HWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1924    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1925    SchedVar<NoSchedPred,                          [HWWritePCMPGTQ]>
1926]>;
1927def : InstRW<[HWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1928                                                 VPCMPGTQYrr)>;
1929
1930
1931// The 0x83 ADC/SBB opcodes have special support for immediate 0 to only require
1932// a single uop. It does not apply to the GR8 encoding. And only applies to the
1933// 8-bit immediate since using larger immediate for 0 would be silly.
1934// Unfortunately, this optimization does not apply to the AX/EAX/RAX short
1935// encodings we convert to in MCInstLowering so we exclude AX/EAX/RAX here since
1936// we schedule before that point.
1937// TODO: Should we disable using the short encodings on these CPUs?
1938def HWFastADC0 : MCSchedPredicate<
1939  CheckAll<[
1940    CheckImmOperand<2, 0>,              // Second MCOperand is Imm and has value 0.
1941    CheckNot<CheckRegOperand<1, AX>>,   // First MCOperand is not register AX
1942    CheckNot<CheckRegOperand<1, EAX>>,  // First MCOperand is not register EAX
1943    CheckNot<CheckRegOperand<1, RAX>>   // First MCOperand is not register RAX
1944  ]>
1945>;
1946
1947def HWWriteADC0 : SchedWriteRes<[HWPort06]> {
1948  let Latency = 1;
1949  let NumMicroOps = 1;
1950  let ResourceCycles = [1];
1951}
1952
1953def HWWriteADC : SchedWriteVariant<[
1954  SchedVar<HWFastADC0, [HWWriteADC0]>,
1955  SchedVar<NoSchedPred, [WriteADC]>
1956]>;
1957
1958def : InstRW<[HWWriteADC], (instrs ADC16ri8, ADC32ri8, ADC64ri8,
1959                                      SBB16ri8, SBB32ri8, SBB64ri8)>;
1960
1961// CMOVs that use both Z and C flag require an extra uop.
1962def HWWriteCMOVA_CMOVBErr : SchedWriteRes<[HWPort06,HWPort0156]> {
1963  let Latency = 3;
1964  let ResourceCycles = [1,2];
1965  let NumMicroOps = 3;
1966}
1967
1968def HWWriteCMOVA_CMOVBErm : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
1969  let Latency = 8;
1970  let ResourceCycles = [1,1,2];
1971  let NumMicroOps = 4;
1972}
1973
1974def HWCMOVA_CMOVBErr :  SchedWriteVariant<[
1975  SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [HWWriteCMOVA_CMOVBErr]>,
1976  SchedVar<NoSchedPred,                             [WriteCMOV]>
1977]>;
1978
1979def HWCMOVA_CMOVBErm :  SchedWriteVariant<[
1980  SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [HWWriteCMOVA_CMOVBErm]>,
1981  SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
1982]>;
1983
1984def : InstRW<[HWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1985def : InstRW<[HWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1986
1987// SETCCs that use both Z and C flag require an extra uop.
1988def HWWriteSETA_SETBEr : SchedWriteRes<[HWPort06,HWPort0156]> {
1989  let Latency = 2;
1990  let ResourceCycles = [1,1];
1991  let NumMicroOps = 2;
1992}
1993
1994def HWWriteSETA_SETBEm : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
1995  let Latency = 3;
1996  let ResourceCycles = [1,1,1,1];
1997  let NumMicroOps = 4;
1998}
1999
2000def HWSETA_SETBErr :  SchedWriteVariant<[
2001  SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [HWWriteSETA_SETBEr]>,
2002  SchedVar<NoSchedPred,                         [WriteSETCC]>
2003]>;
2004
2005def HWSETA_SETBErm :  SchedWriteVariant<[
2006  SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [HWWriteSETA_SETBEm]>,
2007  SchedVar<NoSchedPred,                         [WriteSETCCStore]>
2008]>;
2009
2010def : InstRW<[HWSETA_SETBErr], (instrs SETCCr)>;
2011def : InstRW<[HWSETA_SETBErm], (instrs SETCCm)>;
2012
2013} // SchedModel
2014