1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Broadwell to support instruction 10// scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def BroadwellModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and BW can decode 4 16 // instructions per cycle. 17 let IssueWidth = 4; 18 let MicroOpBufferSize = 192; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 16; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = BroadwellModel in { 31 32// Broadwell can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def BWPort0 : ProcResource<1>; 41def BWPort1 : ProcResource<1>; 42def BWPort2 : ProcResource<1>; 43def BWPort3 : ProcResource<1>; 44def BWPort4 : ProcResource<1>; 45def BWPort5 : ProcResource<1>; 46def BWPort6 : ProcResource<1>; 47def BWPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>; 51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>; 52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>; 53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>; 54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>; 55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>; 56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>; 57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>; 58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>; 59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>; 60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>; 61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>; 62 63// 60 Entry Unified Scheduler 64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4, 65 BWPort5, BWPort6, BWPort7]> { 66 let BufferSize=60; 67} 68 69// Integer division issued on port 0. 70def BWDivider : ProcResource<1>; 71// FP division and sqrt on port 0. 72def BWFPDivider : ProcResource<1>; 73 74// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 75// cycles after the memory operand. 76def : ReadAdvance<ReadAfterLd, 5>; 77 78// Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available 79// until 5/5/6 cycles after the memory operand. 80def : ReadAdvance<ReadAfterVecLd, 5>; 81def : ReadAdvance<ReadAfterVecXLd, 5>; 82def : ReadAdvance<ReadAfterVecYLd, 6>; 83 84def : ReadAdvance<ReadInt2Fpu, 0>; 85 86// Many SchedWrites are defined in pairs with and without a folded load. 87// Instructions with folded loads are usually micro-fused, so they only appear 88// as two micro-ops when queued in the reservation station. 89// This multiclass defines the resource usage for variants with and without 90// folded loads. 91multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW, 92 list<ProcResourceKind> ExePorts, 93 int Lat, list<int> Res = [1], int UOps = 1, 94 int LoadLat = 5, int LoadUOps = 1> { 95 // Register variant is using a single cycle on ExePort. 96 def : WriteRes<SchedRW, ExePorts> { 97 let Latency = Lat; 98 let ReleaseAtCycles = Res; 99 let NumMicroOps = UOps; 100 } 101 102 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 103 // the latency (default = 5). 104 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> { 105 let Latency = !add(Lat, LoadLat); 106 let ReleaseAtCycles = !listconcat([1], Res); 107 let NumMicroOps = !add(UOps, LoadUOps); 108 } 109} 110 111// A folded store needs a cycle on port 4 for the store data, and an extra port 112// 2/3/7 cycle to recompute the address. 113def : WriteRes<WriteRMW, [BWPort237,BWPort4]>; 114 115// Loads, stores, and moves, not folded with other operations. 116// Store_addr on 237. 117// Store_data on 4. 118defm : X86WriteRes<WriteStore, [BWPort237, BWPort4], 1, [1,1], 1>; 119defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>; 120defm : X86WriteRes<WriteLoad, [BWPort23], 5, [1], 1>; 121defm : X86WriteRes<WriteMove, [BWPort0156], 1, [1], 1>; 122 123// Treat misc copies as a move. 124def : InstRW<[WriteMove], (instrs COPY)>; 125 126// Idioms that clear a register, like xorps %xmm0, %xmm0. 127// These can often bypass execution ports completely. 128def : WriteRes<WriteZero, []>; 129 130// Model the effect of clobbering the read-write mask operand of the GATHER operation. 131// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 132defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 133 134// Arithmetic. 135defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op. 136defm : BWWriteResPair<WriteADC, [BWPort06], 1>; // Integer ALU + flags op. 137 138// Integer multiplication. 139defm : BWWriteResPair<WriteIMul8, [BWPort1], 3>; 140defm : BWWriteResPair<WriteIMul16, [BWPort1,BWPort06,BWPort0156], 4, [1,1,2], 4>; 141defm : X86WriteRes<WriteIMul16Imm, [BWPort1,BWPort0156], 4, [1,1], 2>; 142defm : X86WriteRes<WriteIMul16ImmLd, [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>; 143defm : BWWriteResPair<WriteIMul16Reg, [BWPort1], 3>; 144defm : BWWriteResPair<WriteIMul32, [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>; 145defm : BWWriteResPair<WriteMULX32, [BWPort1,BWPort06,BWPort0156], 3, [1,1,1], 3>; 146defm : BWWriteResPair<WriteIMul32Imm, [BWPort1], 3>; 147defm : BWWriteResPair<WriteIMul32Reg, [BWPort1], 3>; 148defm : BWWriteResPair<WriteIMul64, [BWPort1,BWPort5], 4, [1,1], 2>; 149defm : BWWriteResPair<WriteMULX64, [BWPort1,BWPort5], 3, [1,1], 2>; 150defm : BWWriteResPair<WriteIMul64Imm, [BWPort1], 3>; 151defm : BWWriteResPair<WriteIMul64Reg, [BWPort1], 3>; 152def BWWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 153def : WriteRes<WriteIMulHLd, []> { 154 let Latency = !add(BWWriteIMulH.Latency, BroadwellModel.LoadLatency); 155} 156 157defm : X86WriteRes<WriteBSWAP32, [BWPort15], 1, [1], 1>; 158defm : X86WriteRes<WriteBSWAP64, [BWPort06, BWPort15], 2, [1, 1], 2>; 159defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>; 160defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>; 161defm : X86WriteRes<WriteXCHG, [BWPort0156], 2, [3], 3>; 162 163// Integer shifts and rotates. 164defm : BWWriteResPair<WriteShift, [BWPort06], 1>; 165defm : BWWriteResPair<WriteShiftCL, [BWPort06,BWPort0156], 3, [2,1], 3>; 166defm : BWWriteResPair<WriteRotate, [BWPort06], 1, [1], 1>; 167defm : BWWriteResPair<WriteRotateCL, [BWPort06,BWPort0156], 3, [2,1], 3>; 168 169// SHLD/SHRD. 170defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>; 171defm : X86WriteRes<WriteSHDrrcl,[BWPort1,BWPort06,BWPort0156], 6, [1, 1, 2], 4>; 172defm : X86WriteRes<WriteSHDmri, [BWPort1,BWPort23,BWPort237,BWPort0156], 9, [1, 1, 1, 1], 4>; 173defm : X86WriteRes<WriteSHDmrcl,[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156], 11, [1, 1, 1, 1, 2], 6>; 174 175// Branches don't produce values, so they have no latency, but they still 176// consume resources. Indirect branches can fold loads. 177defm : BWWriteResPair<WriteJump, [BWPort06], 1>; 178 179defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>; 180 181defm : BWWriteResPair<WriteCMOV, [BWPort06], 1>; // Conditional move. 182defm : X86WriteRes<WriteFCMOV, [BWPort1], 3, [1], 1>; // x87 conditional move. 183 184def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc. 185def : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> { 186 let Latency = 2; 187 let NumMicroOps = 3; 188} 189 190defm : X86WriteRes<WriteLAHFSAHF, [BWPort06], 1, [1], 1>; 191defm : X86WriteRes<WriteBitTest, [BWPort06], 1, [1], 1>; // Bit Test instrs 192defm : X86WriteRes<WriteBitTestImmLd, [BWPort06,BWPort23], 6, [1,1], 2>; 193defm : X86WriteRes<WriteBitTestRegLd, [BWPort0156,BWPort23], 6, [1,1], 2>; 194defm : X86WriteRes<WriteBitTestSet, [BWPort06], 1, [1], 1>; // Bit Test + Set instrs 195defm : X86WriteRes<WriteBitTestSetImmLd, [BWPort06,BWPort23], 5, [1,1], 3>; 196defm : X86WriteRes<WriteBitTestSetRegLd, [BWPort0156,BWPort23], 5, [1,1], 2>; 197 198// This is for simple LEAs with one or two input operands. 199// The complex ones can only execute on port 1, and they require two cycles on 200// the port to read all inputs. We don't model that. 201def : WriteRes<WriteLEA, [BWPort15]>; 202 203// Bit counts. 204defm : BWWriteResPair<WriteBSF, [BWPort1], 3>; 205defm : BWWriteResPair<WriteBSR, [BWPort1], 3>; 206defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>; 207defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>; 208defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>; 209 210// BMI1 BEXTR/BLS, BMI2 BZHI 211defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>; 212defm : BWWriteResPair<WriteBLS, [BWPort15], 1>; 213defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>; 214 215// TODO: Why isn't the BWDivider used consistently? 216defm : X86WriteRes<WriteDiv8, [BWPort0, BWDivider], 25, [1, 10], 1>; 217defm : X86WriteRes<WriteDiv16, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 218defm : X86WriteRes<WriteDiv32, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 219defm : X86WriteRes<WriteDiv64, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 220defm : X86WriteRes<WriteDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 221defm : X86WriteRes<WriteDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 222defm : X86WriteRes<WriteDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 223defm : X86WriteRes<WriteDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 224 225defm : X86WriteRes<WriteIDiv8, [BWPort0, BWDivider], 25, [1,10], 1>; 226defm : X86WriteRes<WriteIDiv16, [BWPort0, BWDivider], 25, [1,10], 1>; 227defm : X86WriteRes<WriteIDiv32, [BWPort0, BWDivider], 25, [1,10], 1>; 228defm : X86WriteRes<WriteIDiv64, [BWPort0, BWDivider], 25, [1,10], 1>; 229defm : X86WriteRes<WriteIDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 230defm : X86WriteRes<WriteIDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 231defm : X86WriteRes<WriteIDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 232defm : X86WriteRes<WriteIDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 233 234// Floating point. This covers both scalar and vector operations. 235defm : X86WriteRes<WriteFLD0, [BWPort01], 1, [1], 1>; 236defm : X86WriteRes<WriteFLD1, [BWPort01], 1, [2], 2>; 237defm : X86WriteRes<WriteFLDC, [BWPort01], 1, [2], 2>; 238defm : X86WriteRes<WriteFLoad, [BWPort23], 5, [1], 1>; 239defm : X86WriteRes<WriteFLoadX, [BWPort23], 5, [1], 1>; 240defm : X86WriteRes<WriteFLoadY, [BWPort23], 6, [1], 1>; 241defm : X86WriteRes<WriteFMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>; 242defm : X86WriteRes<WriteFMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>; 243defm : X86WriteRes<WriteFStore, [BWPort237,BWPort4], 1, [1,1], 2>; 244defm : X86WriteRes<WriteFStoreX, [BWPort237,BWPort4], 1, [1,1], 2>; 245defm : X86WriteRes<WriteFStoreY, [BWPort237,BWPort4], 1, [1,1], 2>; 246defm : X86WriteRes<WriteFStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>; 247defm : X86WriteRes<WriteFStoreNTX, [BWPort237,BWPort4], 1, [1,1], 2>; 248defm : X86WriteRes<WriteFStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>; 249 250defm : X86WriteRes<WriteFMaskedStore32, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 251defm : X86WriteRes<WriteFMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 252defm : X86WriteRes<WriteFMaskedStore64, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 253defm : X86WriteRes<WriteFMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 254 255defm : X86WriteRes<WriteFMove, [BWPort5], 1, [1], 1>; 256defm : X86WriteRes<WriteFMoveX, [BWPort5], 1, [1], 1>; 257defm : X86WriteRes<WriteFMoveY, [BWPort5], 1, [1], 1>; 258defm : X86WriteResUnsupported<WriteFMoveZ>; 259defm : X86WriteRes<WriteEMMS, [BWPort01,BWPort15,BWPort015,BWPort0156], 31, [8,1,21,1], 31>; 260 261defm : BWWriteResPair<WriteFAdd, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub. 262defm : BWWriteResPair<WriteFAddX, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub (XMM). 263defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM). 264defm : X86WriteResPairUnsupported<WriteFAddZ>; 265defm : BWWriteResPair<WriteFAdd64, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub. 266defm : BWWriteResPair<WriteFAdd64X, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub (XMM). 267defm : BWWriteResPair<WriteFAdd64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM). 268defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 269 270defm : BWWriteResPair<WriteFCmp, [BWPort1], 3, [1], 1, 5>; // Floating point compare. 271defm : BWWriteResPair<WriteFCmpX, [BWPort1], 3, [1], 1, 5>; // Floating point compare (XMM). 272defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM). 273defm : X86WriteResPairUnsupported<WriteFCmpZ>; 274defm : BWWriteResPair<WriteFCmp64, [BWPort1], 3, [1], 1, 5>; // Floating point double compare. 275defm : BWWriteResPair<WriteFCmp64X, [BWPort1], 3, [1], 1, 5>; // Floating point double compare (XMM). 276defm : BWWriteResPair<WriteFCmp64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double compare (YMM/ZMM). 277defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 278 279defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags (X87). 280defm : BWWriteResPair<WriteFComX, [BWPort1], 3>; // Floating point compare to flags (SSE). 281 282defm : BWWriteResPair<WriteFMul, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication. 283defm : BWWriteResPair<WriteFMulX, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM). 284defm : BWWriteResPair<WriteFMulY, [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM). 285defm : X86WriteResPairUnsupported<WriteFMulZ>; 286defm : BWWriteResPair<WriteFMul64, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication. 287defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM). 288defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM). 289defm : X86WriteResPairUnsupported<WriteFMul64Z>; 290 291//defm : BWWriteResPair<WriteFDiv, [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division. 292defm : BWWriteResPair<WriteFDivX, [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM). 293defm : BWWriteResPair<WriteFDivY, [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM). 294defm : X86WriteResPairUnsupported<WriteFDivZ>; 295//defm : BWWriteResPair<WriteFDiv64, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division. 296defm : BWWriteResPair<WriteFDiv64X, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM). 297defm : BWWriteResPair<WriteFDiv64Y, [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM). 298defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 299 300defm : BWWriteResPair<WriteFRcp, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate. 301defm : BWWriteResPair<WriteFRcpX, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate (XMM). 302defm : BWWriteResPair<WriteFRcpY, [BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal estimate (YMM/ZMM). 303defm : X86WriteResPairUnsupported<WriteFRcpZ>; 304 305defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate. 306defm : BWWriteResPair<WriteFRsqrtX,[BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate (XMM). 307defm : BWWriteResPair<WriteFRsqrtY,[BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal square root estimate (YMM/ZMM). 308defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 309 310defm : X86WriteRes<WriteFSqrt, [BWPort0,BWFPDivider], 11, [1,4], 1>; // Floating point square root. 311defm : X86WriteRes<WriteFSqrtLd, [BWPort0,BWPort23,BWFPDivider], 16, [1,1,7], 2>; 312defm : BWWriteResPair<WriteFSqrtX, [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM). 313defm : BWWriteResPair<WriteFSqrtY, [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM). 314defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 315defm : X86WriteRes<WriteFSqrt64, [BWPort0,BWFPDivider], 16, [1,8], 1>; // Floating point double square root. 316defm : X86WriteRes<WriteFSqrt64Ld, [BWPort0,BWPort23,BWFPDivider], 21, [1,1,14], 2>; 317defm : BWWriteResPair<WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM). 318defm : BWWriteResPair<WriteFSqrt64Y, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM). 319defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 320defm : BWWriteResPair<WriteFSqrt80, [BWPort0,BWFPDivider], 23, [1,9]>; // Floating point long double square root. 321 322defm : BWWriteResPair<WriteFMA, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add. 323defm : BWWriteResPair<WriteFMAX, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM). 324defm : BWWriteResPair<WriteFMAY, [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM). 325defm : X86WriteResPairUnsupported<WriteFMAZ>; 326defm : BWWriteResPair<WriteDPPD, [BWPort0,BWPort1,BWPort5], 9, [1,1,1], 3, 5>; // Floating point double dot product. 327defm : BWWriteResPair<WriteDPPS, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 5>; // Floating point single dot product. 328defm : BWWriteResPair<WriteDPPSY, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 6>; // Floating point single dot product (YMM). 329defm : BWWriteResPair<WriteFSign, [BWPort5], 1>; // Floating point fabs/fchs. 330defm : X86WriteRes<WriteFRnd, [BWPort23], 6, [1], 1>; // Floating point rounding. 331defm : X86WriteRes<WriteFRndY, [BWPort23], 6, [1], 1>; // Floating point rounding (YMM/ZMM). 332defm : X86WriteResPairUnsupported<WriteFRndZ>; 333defm : X86WriteRes<WriteFRndLd, [BWPort1,BWPort23], 11, [2,1], 3>; 334defm : X86WriteRes<WriteFRndYLd, [BWPort1,BWPort23], 12, [2,1], 3>; 335defm : BWWriteResPair<WriteFLogic, [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals. 336defm : BWWriteResPair<WriteFLogicY, [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM). 337defm : X86WriteResPairUnsupported<WriteFLogicZ>; 338defm : BWWriteResPair<WriteFTest, [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions. 339defm : BWWriteResPair<WriteFTestY, [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM). 340defm : X86WriteResPairUnsupported<WriteFTestZ>; 341defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles. 342defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM). 343defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 344defm : BWWriteResPair<WriteFVarShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles. 345defm : BWWriteResPair<WriteFVarShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles. 346defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 347defm : BWWriteResPair<WriteFBlend, [BWPort015], 1, [1], 1, 5>; // Floating point vector blends. 348defm : BWWriteResPair<WriteFBlendY, [BWPort015], 1, [1], 1, 6>; // Floating point vector blends. 349defm : X86WriteResPairUnsupported<WriteFBlendZ>; 350defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles. 351defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles. 352defm : BWWriteResPair<WriteFVarBlend, [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends. 353defm : BWWriteResPair<WriteFVarBlendY, [BWPort5], 2, [2], 2, 6>; // Fp vector variable blends. 354defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 355 356// FMA Scheduling helper class. 357// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 358 359// Conversion between integer and float. 360defm : BWWriteResPair<WriteCvtSS2I, [BWPort1,BWPort0], 4, [1,1], 2, 5>; 361defm : BWWriteResPair<WriteCvtPS2I, [BWPort1], 3, [1], 1, 5>; 362defm : BWWriteResPair<WriteCvtPS2IY, [BWPort1], 3, [1], 1, 6>; 363defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 364defm : BWWriteResPair<WriteCvtSD2I, [BWPort1,BWPort0], 4, [1,1], 2, 5>; 365defm : BWWriteResPair<WriteCvtPD2I, [BWPort1,BWPort5], 4, [1,1], 2, 5>; 366defm : BWWriteResPair<WriteCvtPD2IY, [BWPort1,BWPort5], 6, [1,1], 2, 6>; 367defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 368 369defm : X86WriteRes<WriteCvtI2SS, [BWPort1,BWPort5], 4, [1,1], 2>; 370defm : X86WriteRes<WriteCvtI2SSLd, [BWPort1,BWPort23], 9, [1,1], 2>; 371defm : BWWriteResPair<WriteCvtI2PS, [BWPort1], 3>; 372defm : BWWriteResPair<WriteCvtI2PSY, [BWPort1], 3, [1], 1, 6>; 373defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 374defm : X86WriteRes<WriteCvtI2SD, [BWPort1,BWPort5], 4, [1,1], 2>; 375defm : X86WriteRes<WriteCvtI2SDLd, [BWPort1,BWPort23], 9, [1,1], 2>; 376defm : BWWriteResPair<WriteCvtI2PD, [BWPort1,BWPort5], 4, [1,1], 2, 5>; 377defm : BWWriteResPair<WriteCvtI2PDY, [BWPort1,BWPort5], 6, [1,1], 2, 5>; 378defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 379 380defm : X86WriteRes<WriteCvtSS2SD, [BWPort0,BWPort5], 2, [1,1], 2>; 381defm : X86WriteRes<WriteCvtSS2SDLd, [BWPort0,BWPort23], 6, [1,1], 2>; 382defm : X86WriteRes<WriteCvtPS2PD, [BWPort0,BWPort5], 2, [1,1], 2>; 383defm : X86WriteRes<WriteCvtPS2PDLd, [BWPort0,BWPort23], 6, [1,1], 2>; 384defm : BWWriteResPair<WriteCvtPS2PDY, [BWPort0,BWPort5], 4, [1,1], 2, 5>; 385defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 386defm : BWWriteResPair<WriteCvtSD2SS, [BWPort1,BWPort5], 4, [1,1], 2, 5>; 387defm : BWWriteResPair<WriteCvtPD2PS, [BWPort1,BWPort5], 4, [1,1], 2, 5>; 388defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1,BWPort5], 6, [1,1], 2, 6>; 389defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 390 391defm : X86WriteRes<WriteCvtPH2PS, [BWPort0,BWPort5], 2, [1,1], 2>; 392defm : X86WriteRes<WriteCvtPH2PSY, [BWPort0,BWPort5], 2, [1,1], 2>; 393defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 394defm : X86WriteRes<WriteCvtPH2PSLd, [BWPort0,BWPort23], 6, [1,1], 2>; 395defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort0,BWPort23], 6, [1,1], 2>; 396defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 397 398defm : X86WriteRes<WriteCvtPS2PH, [BWPort1,BWPort5], 4, [1,1], 2>; 399defm : X86WriteRes<WriteCvtPS2PHY, [BWPort1,BWPort5], 6, [1,1], 2>; 400defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 401defm : X86WriteRes<WriteCvtPS2PHSt, [BWPort1,BWPort4,BWPort237], 5, [1,1,1], 3>; 402defm : X86WriteRes<WriteCvtPS2PHYSt, [BWPort1,BWPort4,BWPort237], 7, [1,1,1], 3>; 403defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 404 405// Vector integer operations. 406defm : X86WriteRes<WriteVecLoad, [BWPort23], 5, [1], 1>; 407defm : X86WriteRes<WriteVecLoadX, [BWPort23], 5, [1], 1>; 408defm : X86WriteRes<WriteVecLoadY, [BWPort23], 6, [1], 1>; 409defm : X86WriteRes<WriteVecLoadNT, [BWPort23], 5, [1], 1>; 410defm : X86WriteRes<WriteVecLoadNTY, [BWPort23], 6, [1], 1>; 411defm : X86WriteRes<WriteVecMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>; 412defm : X86WriteRes<WriteVecMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>; 413defm : X86WriteRes<WriteVecStore, [BWPort237,BWPort4], 1, [1,1], 2>; 414defm : X86WriteRes<WriteVecStoreX, [BWPort237,BWPort4], 1, [1,1], 2>; 415defm : X86WriteRes<WriteVecStoreY, [BWPort237,BWPort4], 1, [1,1], 2>; 416defm : X86WriteRes<WriteVecStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>; 417defm : X86WriteRes<WriteVecStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>; 418defm : X86WriteRes<WriteVecMaskedStore32, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 419defm : X86WriteRes<WriteVecMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 420defm : X86WriteRes<WriteVecMaskedStore64, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 421defm : X86WriteRes<WriteVecMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 422defm : X86WriteRes<WriteVecMove, [BWPort015], 1, [1], 1>; 423defm : X86WriteRes<WriteVecMoveX, [BWPort015], 1, [1], 1>; 424defm : X86WriteRes<WriteVecMoveY, [BWPort015], 1, [1], 1>; 425defm : X86WriteResUnsupported<WriteVecMoveZ>; 426defm : X86WriteRes<WriteVecMoveToGpr, [BWPort0], 1, [1], 1>; 427defm : X86WriteRes<WriteVecMoveFromGpr, [BWPort5], 1, [1], 1>; 428 429defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor. 430defm : BWWriteResPair<WriteVecLogicX,[BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor. 431defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM). 432defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 433defm : BWWriteResPair<WriteVecTest, [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions. 434defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM). 435defm : X86WriteResPairUnsupported<WriteVecTestZ>; 436defm : BWWriteResPair<WriteVecALU, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 437defm : BWWriteResPair<WriteVecALUX, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 438defm : BWWriteResPair<WriteVecALUY, [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM). 439defm : X86WriteResPairUnsupported<WriteVecALUZ>; 440defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply. 441defm : BWWriteResPair<WriteVecIMulX, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply. 442defm : BWWriteResPair<WriteVecIMulY, [BWPort0], 5, [1], 1, 6>; // Vector integer multiply. 443defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 444defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // Vector PMULLD. 445defm : BWWriteResPair<WritePMULLDY, [BWPort0], 10, [2], 2, 6>; // Vector PMULLD (YMM/ZMM). 446defm : X86WriteResPairUnsupported<WritePMULLDZ>; 447defm : BWWriteResPair<WriteShuffle, [BWPort5], 1, [1], 1, 5>; // Vector shuffles. 448defm : BWWriteResPair<WriteShuffleX, [BWPort5], 1, [1], 1, 5>; // Vector shuffles. 449defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM). 450defm : X86WriteResPairUnsupported<WriteShuffleZ>; 451defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles. 452defm : BWWriteResPair<WriteVarShuffleX,[BWPort5], 1, [1], 1, 5>; // Vector variable shuffles. 453defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM). 454defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 455defm : BWWriteResPair<WriteBlend, [BWPort5], 1, [1], 1, 5>; // Vector blends. 456defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM). 457defm : X86WriteResPairUnsupported<WriteBlendZ>; 458defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector shuffles. 459defm : BWWriteResPair<WriteVPMOV256, [BWPort5], 3, [1], 1, 6>; // 256-bit width packed vector width-changing move. 460defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector variable shuffles. 461defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2], 2, 5>; // Vector variable blends. 462defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM). 463defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 464defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD. 465defm : BWWriteResPair<WriteMPSADY, [BWPort0, BWPort5], 7, [1, 2], 3, 6>; // Vector MPSAD. 466defm : X86WriteResPairUnsupported<WriteMPSADZ>; 467defm : BWWriteResPair<WritePSADBW, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW. 468defm : BWWriteResPair<WritePSADBWX, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW. 469defm : BWWriteResPair<WritePSADBWY, [BWPort0], 5, [1], 1, 6>; // Vector PSADBW (YMM/ZMM). 470defm : X86WriteResPairUnsupported<WritePSADBWZ>; 471defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS. 472 473// Vector integer shifts. 474defm : BWWriteResPair<WriteVecShift, [BWPort0], 1, [1], 1, 5>; 475defm : BWWriteResPair<WriteVecShiftX, [BWPort0,BWPort5], 2, [1,1], 2, 5>; 476defm : X86WriteRes<WriteVecShiftY, [BWPort0,BWPort5], 4, [1,1], 2>; 477defm : X86WriteRes<WriteVecShiftYLd, [BWPort0,BWPort23], 7, [1,1], 2>; 478defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 479 480defm : BWWriteResPair<WriteVecShiftImm, [BWPort0], 1, [1], 1, 5>; 481defm : BWWriteResPair<WriteVecShiftImmX, [BWPort0], 1, [1], 1, 5>; // Vector integer immediate shifts (XMM). 482defm : BWWriteResPair<WriteVecShiftImmY, [BWPort0], 1, [1], 1, 6>; // Vector integer immediate shifts (YMM/ZMM). 483defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 484defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts. 485defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM). 486defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 487 488// Vector insert/extract operations. 489def : WriteRes<WriteVecInsert, [BWPort5]> { 490 let Latency = 2; 491 let NumMicroOps = 2; 492 let ReleaseAtCycles = [2]; 493} 494def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> { 495 let Latency = 6; 496 let NumMicroOps = 2; 497} 498 499def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> { 500 let Latency = 2; 501 let NumMicroOps = 2; 502} 503def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> { 504 let Latency = 2; 505 let NumMicroOps = 3; 506} 507 508// String instructions. 509 510// Packed Compare Implicit Length Strings, Return Mask 511def : WriteRes<WritePCmpIStrM, [BWPort0]> { 512 let Latency = 11; 513 let NumMicroOps = 3; 514 let ReleaseAtCycles = [3]; 515} 516def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> { 517 let Latency = 16; 518 let NumMicroOps = 4; 519 let ReleaseAtCycles = [3,1]; 520} 521 522// Packed Compare Explicit Length Strings, Return Mask 523def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> { 524 let Latency = 19; 525 let NumMicroOps = 9; 526 let ReleaseAtCycles = [4,3,1,1]; 527} 528def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> { 529 let Latency = 24; 530 let NumMicroOps = 10; 531 let ReleaseAtCycles = [4,3,1,1,1]; 532} 533 534// Packed Compare Implicit Length Strings, Return Index 535def : WriteRes<WritePCmpIStrI, [BWPort0]> { 536 let Latency = 11; 537 let NumMicroOps = 3; 538 let ReleaseAtCycles = [3]; 539} 540def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> { 541 let Latency = 16; 542 let NumMicroOps = 4; 543 let ReleaseAtCycles = [3,1]; 544} 545 546// Packed Compare Explicit Length Strings, Return Index 547def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> { 548 let Latency = 18; 549 let NumMicroOps = 8; 550 let ReleaseAtCycles = [4,3,1]; 551} 552def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> { 553 let Latency = 23; 554 let NumMicroOps = 9; 555 let ReleaseAtCycles = [4,3,1,1]; 556} 557 558// MOVMSK Instructions. 559def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; } 560def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; } 561def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; } 562def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; } 563 564// AES Instructions. 565def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption. 566 let Latency = 7; 567 let NumMicroOps = 1; 568 let ReleaseAtCycles = [1]; 569} 570def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> { 571 let Latency = 12; 572 let NumMicroOps = 2; 573 let ReleaseAtCycles = [1,1]; 574} 575 576def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn. 577 let Latency = 14; 578 let NumMicroOps = 2; 579 let ReleaseAtCycles = [2]; 580} 581def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> { 582 let Latency = 19; 583 let NumMicroOps = 3; 584 let ReleaseAtCycles = [2,1]; 585} 586 587def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation. 588 let Latency = 29; 589 let NumMicroOps = 11; 590 let ReleaseAtCycles = [2,7,2]; 591} 592def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> { 593 let Latency = 33; 594 let NumMicroOps = 11; 595 let ReleaseAtCycles = [2,7,1,1]; 596} 597 598// Carry-less multiplication instructions. 599defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>; 600// Load/store MXCSR. 601def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; } 602def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; } 603 604// Catch-all for expensive system instructions. 605def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } 606 607// Old microcoded instructions that nobody use. 608def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } 609 610// Fence instructions. 611def : WriteRes<WriteFence, [BWPort23, BWPort4]>; 612 613// Nop, not very useful expect it provides a model for nops! 614def : WriteRes<WriteNop, []>; 615 616//////////////////////////////////////////////////////////////////////////////// 617// Horizontal add/sub instructions. 618//////////////////////////////////////////////////////////////////////////////// 619 620defm : BWWriteResPair<WriteFHAdd, [BWPort1,BWPort5], 5, [1,2], 3, 5>; 621defm : BWWriteResPair<WriteFHAddY, [BWPort1,BWPort5], 5, [1,2], 3, 6>; 622defm : BWWriteResPair<WritePHAdd, [BWPort5,BWPort15], 3, [2,1], 3, 5>; 623defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>; 624defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>; 625 626// Remaining instrs. 627 628def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> { 629 let Latency = 1; 630 let NumMicroOps = 1; 631 let ReleaseAtCycles = [1]; 632} 633def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr", 634 "VPSRLVQ(Y?)rr")>; 635 636def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> { 637 let Latency = 1; 638 let NumMicroOps = 1; 639 let ReleaseAtCycles = [1]; 640} 641def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r", 642 "UCOM_F(P?)r")>; 643 644def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> { 645 let Latency = 1; 646 let NumMicroOps = 1; 647 let ReleaseAtCycles = [1]; 648} 649def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>; 650 651def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> { 652 let Latency = 1; 653 let NumMicroOps = 1; 654 let ReleaseAtCycles = [1]; 655} 656def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>; 657 658def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> { 659 let Latency = 1; 660 let NumMicroOps = 1; 661 let ReleaseAtCycles = [1]; 662} 663def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>; 664 665def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> { 666 let Latency = 1; 667 let NumMicroOps = 1; 668 let ReleaseAtCycles = [1]; 669} 670def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>; 671 672def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> { 673 let Latency = 1; 674 let NumMicroOps = 1; 675 let ReleaseAtCycles = [1]; 676} 677def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>; 678 679def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> { 680 let Latency = 1; 681 let NumMicroOps = 1; 682 let ReleaseAtCycles = [1]; 683} 684def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>; 685 686def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> { 687 let Latency = 1; 688 let NumMicroOps = 1; 689 let ReleaseAtCycles = [1]; 690} 691def: InstRW<[BWWriteResGroup9], (instrs SGDT64m, 692 SIDT64m, 693 SMSW16m, 694 STRm, 695 SYSCALL)>; 696 697def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> { 698 let Latency = 1; 699 let NumMicroOps = 2; 700 let ReleaseAtCycles = [1,1]; 701} 702def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>; 703def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>; 704 705def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> { 706 let Latency = 2; 707 let NumMicroOps = 2; 708 let ReleaseAtCycles = [2]; 709} 710def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>; 711 712def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> { 713 let Latency = 2; 714 let NumMicroOps = 2; 715 let ReleaseAtCycles = [2]; 716} 717def: InstRW<[BWWriteResGroup14], (instrs LFENCE, 718 MFENCE, 719 WAIT, 720 XGETBV)>; 721 722def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> { 723 let Latency = 2; 724 let NumMicroOps = 2; 725 let ReleaseAtCycles = [1,1]; 726} 727def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>; 728 729def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> { 730 let Latency = 2; 731 let NumMicroOps = 2; 732 let ReleaseAtCycles = [1,1]; 733} 734def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>; 735 736def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> { 737 let Latency = 2; 738 let NumMicroOps = 2; 739 let ReleaseAtCycles = [1,1]; 740} 741def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>; 742 743def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> { 744 let Latency = 2; 745 let NumMicroOps = 2; 746 let ReleaseAtCycles = [1,1]; 747} 748def: InstRW<[BWWriteResGroup20], (instrs CWD, 749 JCXZ, JECXZ, JRCXZ, 750 ADC8i8, SBB8i8, 751 ADC16i16, SBB16i16, 752 ADC32i32, SBB32i32, 753 ADC64i32, SBB64i32)>; 754 755def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> { 756 let Latency = 2; 757 let NumMicroOps = 3; 758 let ReleaseAtCycles = [1,1,1]; 759} 760def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>; 761 762def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> { 763 let Latency = 2; 764 let NumMicroOps = 3; 765 let ReleaseAtCycles = [1,1,1]; 766} 767def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>; 768 769def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { 770 let Latency = 2; 771 let NumMicroOps = 3; 772 let ReleaseAtCycles = [1,1,1]; 773} 774def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 775 STOSB, STOSL, STOSQ, STOSW)>; 776def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>; 777 778def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> { 779 let Latency = 3; 780 let NumMicroOps = 1; 781 let ReleaseAtCycles = [1]; 782} 783def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr")>; 784 785def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> { 786 let Latency = 3; 787 let NumMicroOps = 1; 788 let ReleaseAtCycles = [1]; 789} 790def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr, 791 VPBROADCASTWrr)>; 792 793def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> { 794 let Latency = 3; 795 let NumMicroOps = 3; 796 let ReleaseAtCycles = [2,1]; 797} 798def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWrr, 799 MMX_PACKSSWBrr, 800 MMX_PACKUSWBrr)>; 801 802def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> { 803 let Latency = 3; 804 let NumMicroOps = 3; 805 let ReleaseAtCycles = [1,2]; 806} 807def: InstRW<[BWWriteResGroup34], (instregex "CLD")>; 808 809def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> { 810 let Latency = 2; 811 let NumMicroOps = 3; 812 let ReleaseAtCycles = [1,2]; 813} 814def: InstRW<[BWWriteResGroup35], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1, 815 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>; 816 817def BWWriteResGroup36 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { 818 let Latency = 5; 819 let NumMicroOps = 8; 820 let ReleaseAtCycles = [2,4,2]; 821} 822def: InstRW<[BWWriteResGroup36], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>; 823 824def BWWriteResGroup36b : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { 825 let Latency = 6; 826 let NumMicroOps = 8; 827 let ReleaseAtCycles = [2,4,2]; 828} 829def: InstRW<[BWWriteResGroup36b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>; 830 831def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> { 832 let Latency = 3; 833 let NumMicroOps = 4; 834 let ReleaseAtCycles = [1,1,1,1]; 835} 836def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>; 837 838def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { 839 let Latency = 3; 840 let NumMicroOps = 4; 841 let ReleaseAtCycles = [1,1,1,1]; 842} 843def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>; 844 845 846def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> { 847 let Latency = 4; 848 let NumMicroOps = 2; 849 let ReleaseAtCycles = [1,1]; 850} 851def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>; 852 853def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> { 854 let Latency = 4; 855 let NumMicroOps = 2; 856 let ReleaseAtCycles = [1,1]; 857} 858def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PS2PIrr")>; 859 860def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> { 861 let Latency = 4; 862 let NumMicroOps = 3; 863 let ReleaseAtCycles = [1,1,1]; 864} 865def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>; 866 867def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> { 868 let Latency = 4; 869 let NumMicroOps = 3; 870 let ReleaseAtCycles = [1,1,1]; 871} 872def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m", 873 "IST_F(16|32)m")>; 874 875def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> { 876 let Latency = 4; 877 let NumMicroOps = 4; 878 let ReleaseAtCycles = [4]; 879} 880def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>; 881 882def BWWriteResGroup46 : SchedWriteRes<[]> { 883 let Latency = 0; 884 let NumMicroOps = 4; 885 let ReleaseAtCycles = []; 886} 887def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>; 888 889def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> { 890 let Latency = 5; 891 let NumMicroOps = 1; 892 let ReleaseAtCycles = [1]; 893} 894def: InstRW<[BWWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 895 896def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> { 897 let Latency = 5; 898 let NumMicroOps = 1; 899 let ReleaseAtCycles = [1]; 900} 901def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm, 902 VMOVDDUPrm, MOVDDUPrm, 903 VMOVSHDUPrm, MOVSHDUPrm, 904 VMOVSLDUPrm, MOVSLDUPrm, 905 VPBROADCASTDrm, 906 VPBROADCASTQrm)>; 907 908def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> { 909 let Latency = 5; 910 let NumMicroOps = 3; 911 let ReleaseAtCycles = [1,2]; 912} 913def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>; 914 915def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> { 916 let Latency = 5; 917 let NumMicroOps = 3; 918 let ReleaseAtCycles = [1,1,1]; 919} 920def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>; 921 922def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> { 923 let Latency = 5; 924 let NumMicroOps = 5; 925 let ReleaseAtCycles = [1,4]; 926} 927def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>; 928 929def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> { 930 let Latency = 5; 931 let NumMicroOps = 5; 932 let ReleaseAtCycles = [1,4]; 933} 934def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>; 935 936def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { 937 let Latency = 5; 938 let NumMicroOps = 6; 939 let ReleaseAtCycles = [1,1,4]; 940} 941def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>; 942 943def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> { 944 let Latency = 6; 945 let NumMicroOps = 1; 946 let ReleaseAtCycles = [1]; 947} 948def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>; 949def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128rm, 950 VBROADCASTI128rm, 951 VBROADCASTSDYrm, 952 VBROADCASTSSYrm, 953 VMOVDDUPYrm, 954 VMOVSHDUPYrm, 955 VMOVSLDUPYrm, 956 VPBROADCASTDYrm, 957 VPBROADCASTQYrm)>; 958 959def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> { 960 let Latency = 6; 961 let NumMicroOps = 2; 962 let ReleaseAtCycles = [1,1]; 963} 964def: InstRW<[BWWriteResGroup59], (instrs VPSLLVQrm, VPSRLVQrm)>; 965 966def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> { 967 let Latency = 6; 968 let NumMicroOps = 2; 969 let ReleaseAtCycles = [1,1]; 970} 971def: InstRW<[BWWriteResGroup62], (instrs FARJMP64m)>; 972def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>; 973 974def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> { 975 let Latency = 6; 976 let NumMicroOps = 2; 977 let ReleaseAtCycles = [1,1]; 978} 979def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm", 980 "MOVBE(16|32|64)rm")>; 981 982def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> { 983 let Latency = 6; 984 let NumMicroOps = 2; 985 let ReleaseAtCycles = [1,1]; 986} 987def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm, 988 VINSERTI128rm, 989 VPBLENDDrmi)>; 990 991def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> { 992 let Latency = 6; 993 let NumMicroOps = 2; 994 let ReleaseAtCycles = [1,1]; 995} 996def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>; 997def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>; 998 999def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> { 1000 let Latency = 6; 1001 let NumMicroOps = 4; 1002 let ReleaseAtCycles = [1,1,1,1]; 1003} 1004def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>; 1005 1006def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { 1007 let Latency = 6; 1008 let NumMicroOps = 4; 1009 let ReleaseAtCycles = [1,1,1,1]; 1010} 1011def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)", 1012 "SHL(8|16|32|64)m(1|i)", 1013 "SHR(8|16|32|64)m(1|i)")>; 1014 1015def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1016 let Latency = 6; 1017 let NumMicroOps = 4; 1018 let ReleaseAtCycles = [1,1,1,1]; 1019} 1020def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm", 1021 "PUSH(16|32|64)rmm")>; 1022 1023def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> { 1024 let Latency = 6; 1025 let NumMicroOps = 6; 1026 let ReleaseAtCycles = [1,5]; 1027} 1028def: InstRW<[BWWriteResGroup71], (instrs STD)>; 1029 1030def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> { 1031 let Latency = 7; 1032 let NumMicroOps = 2; 1033 let ReleaseAtCycles = [1,1]; 1034} 1035def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm, 1036 VPSRLVQYrm)>; 1037 1038def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> { 1039 let Latency = 7; 1040 let NumMicroOps = 2; 1041 let ReleaseAtCycles = [1,1]; 1042} 1043def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>; 1044 1045def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> { 1046 let Latency = 7; 1047 let NumMicroOps = 2; 1048 let ReleaseAtCycles = [1,1]; 1049} 1050def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>; 1051 1052def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> { 1053 let Latency = 7; 1054 let NumMicroOps = 3; 1055 let ReleaseAtCycles = [2,1]; 1056} 1057def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWrm, 1058 MMX_PACKSSWBrm, 1059 MMX_PACKUSWBrm)>; 1060 1061def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> { 1062 let Latency = 7; 1063 let NumMicroOps = 3; 1064 let ReleaseAtCycles = [1,2]; 1065} 1066def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64, 1067 SCASB, SCASL, SCASQ, SCASW)>; 1068 1069def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> { 1070 let Latency = 7; 1071 let NumMicroOps = 3; 1072 let ReleaseAtCycles = [1,1,1]; 1073} 1074def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>; 1075 1076def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1077 let Latency = 7; 1078 let NumMicroOps = 3; 1079 let ReleaseAtCycles = [1,1,1]; 1080} 1081def: InstRW<[BWWriteResGroup84], (instrs LRET64, RET64)>; 1082 1083def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { 1084 let Latency = 7; 1085 let NumMicroOps = 5; 1086 let ReleaseAtCycles = [1,1,1,2]; 1087} 1088def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)", 1089 "ROR(8|16|32|64)m(1|i)")>; 1090 1091def BWWriteResGroup87_1 : SchedWriteRes<[BWPort06]> { 1092 let Latency = 2; 1093 let NumMicroOps = 2; 1094 let ReleaseAtCycles = [2]; 1095} 1096def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1097 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1098 1099def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1100 let Latency = 7; 1101 let NumMicroOps = 5; 1102 let ReleaseAtCycles = [1,1,1,2]; 1103} 1104def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>; 1105 1106def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1107 let Latency = 7; 1108 let NumMicroOps = 5; 1109 let ReleaseAtCycles = [1,1,1,1,1]; 1110} 1111def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>; 1112def: InstRW<[BWWriteResGroup89], (instrs FARCALL64m)>; 1113 1114def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> { 1115 let Latency = 7; 1116 let NumMicroOps = 7; 1117 let ReleaseAtCycles = [2,2,1,2]; 1118} 1119def: InstRW<[BWWriteResGroup90], (instrs LOOP)>; 1120 1121def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> { 1122 let Latency = 8; 1123 let NumMicroOps = 2; 1124 let ReleaseAtCycles = [1,1]; 1125} 1126def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>; 1127 1128def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> { 1129 let Latency = 8; 1130 let NumMicroOps = 2; 1131 let ReleaseAtCycles = [1,1]; 1132} 1133def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm, 1134 VPMOVSXBQYrm, 1135 VPMOVSXBWYrm, 1136 VPMOVSXDQYrm, 1137 VPMOVSXWDYrm, 1138 VPMOVSXWQYrm, 1139 VPMOVZXWDYrm)>; 1140 1141def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> { 1142 let Latency = 8; 1143 let NumMicroOps = 5; 1144 let ReleaseAtCycles = [1,1,1,2]; 1145} 1146def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)", 1147 "RCR(8|16|32|64)m(1|i)")>; 1148 1149def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1150 let Latency = 8; 1151 let NumMicroOps = 6; 1152 let ReleaseAtCycles = [1,1,1,3]; 1153} 1154def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>; 1155 1156def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1157 let Latency = 8; 1158 let NumMicroOps = 6; 1159 let ReleaseAtCycles = [1,1,1,2,1]; 1160} 1161def : SchedAlias<WriteADCRMW, BWWriteResGroup100>; 1162def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL", 1163 "ROR(8|16|32|64)mCL", 1164 "SAR(8|16|32|64)mCL", 1165 "SHL(8|16|32|64)mCL", 1166 "SHR(8|16|32|64)mCL")>; 1167 1168def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> { 1169 let Latency = 9; 1170 let NumMicroOps = 2; 1171 let ReleaseAtCycles = [1,1]; 1172} 1173def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1174 "ILD_F(16|32|64)m")>; 1175 1176def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> { 1177 let Latency = 9; 1178 let NumMicroOps = 3; 1179 let ReleaseAtCycles = [1,1,1]; 1180} 1181def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm", 1182 "VPBROADCASTW(Y?)rm")>; 1183 1184def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { 1185 let Latency = 9; 1186 let NumMicroOps = 5; 1187 let ReleaseAtCycles = [1,1,3]; 1188} 1189def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; 1190 1191def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { 1192 let Latency = 9; 1193 let NumMicroOps = 5; 1194 let ReleaseAtCycles = [1,2,1,1]; 1195} 1196def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm", 1197 "LSL(16|32|64)rm")>; 1198 1199def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> { 1200 let Latency = 10; 1201 let NumMicroOps = 2; 1202 let ReleaseAtCycles = [1,1]; 1203} 1204def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>; 1205 1206def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> { 1207 let Latency = 10; 1208 let NumMicroOps = 3; 1209 let ReleaseAtCycles = [2,1]; 1210} 1211def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>; 1212 1213def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { 1214 let Latency = 11; 1215 let NumMicroOps = 1; 1216 let ReleaseAtCycles = [1,3]; // Really 2.5 cycle throughput 1217} 1218def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair 1219 1220def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> { 1221 let Latency = 11; 1222 let NumMicroOps = 2; 1223 let ReleaseAtCycles = [1,1]; 1224} 1225def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>; 1226def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>; 1227 1228def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { 1229 let Latency = 11; 1230 let NumMicroOps = 7; 1231 let ReleaseAtCycles = [2,2,3]; 1232} 1233def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL", 1234 "RCR(16|32|64)rCL")>; 1235 1236def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { 1237 let Latency = 11; 1238 let NumMicroOps = 9; 1239 let ReleaseAtCycles = [1,4,1,3]; 1240} 1241def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>; 1242 1243def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> { 1244 let Latency = 11; 1245 let NumMicroOps = 11; 1246 let ReleaseAtCycles = [2,9]; 1247} 1248def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>; 1249def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>; 1250 1251def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> { 1252 let Latency = 12; 1253 let NumMicroOps = 3; 1254 let ReleaseAtCycles = [2,1]; 1255} 1256def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1257 1258def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { 1259 let Latency = 14; 1260 let NumMicroOps = 1; 1261 let ReleaseAtCycles = [1,4]; 1262} 1263def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair 1264 1265def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1266 let Latency = 14; 1267 let NumMicroOps = 3; 1268 let ReleaseAtCycles = [1,1,1]; 1269} 1270def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>; 1271 1272def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { 1273 let Latency = 14; 1274 let NumMicroOps = 8; 1275 let ReleaseAtCycles = [2,2,1,3]; 1276} 1277def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>; 1278 1279def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { 1280 let Latency = 14; 1281 let NumMicroOps = 10; 1282 let ReleaseAtCycles = [2,3,1,4]; 1283} 1284def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>; 1285 1286def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> { 1287 let Latency = 14; 1288 let NumMicroOps = 12; 1289 let ReleaseAtCycles = [2,1,4,5]; 1290} 1291def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>; 1292 1293def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> { 1294 let Latency = 15; 1295 let NumMicroOps = 1; 1296 let ReleaseAtCycles = [1]; 1297} 1298def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1299 1300def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1301 let Latency = 15; 1302 let NumMicroOps = 10; 1303 let ReleaseAtCycles = [1,1,1,4,1,2]; 1304} 1305def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>; 1306 1307def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { 1308 let Latency = 16; 1309 let NumMicroOps = 2; 1310 let ReleaseAtCycles = [1,1,5]; 1311} 1312def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair 1313 1314def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1315 let Latency = 16; 1316 let NumMicroOps = 14; 1317 let ReleaseAtCycles = [1,1,1,4,2,5]; 1318} 1319def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>; 1320 1321def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> { 1322 let Latency = 8; 1323 let NumMicroOps = 20; 1324 let ReleaseAtCycles = [1,1]; 1325} 1326def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>; 1327 1328def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> { 1329 let Latency = 18; 1330 let NumMicroOps = 8; 1331 let ReleaseAtCycles = [1,1,1,5]; 1332} 1333def: InstRW<[BWWriteResGroup159], (instrs CPUID)>; 1334def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>; 1335 1336def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1337 let Latency = 18; 1338 let NumMicroOps = 11; 1339 let ReleaseAtCycles = [2,1,1,3,1,3]; 1340} 1341def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>; 1342 1343def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { 1344 let Latency = 19; 1345 let NumMicroOps = 2; 1346 let ReleaseAtCycles = [1,1,8]; 1347} 1348def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair 1349 1350def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> { 1351 let Latency = 20; 1352 let NumMicroOps = 1; 1353 let ReleaseAtCycles = [1]; 1354} 1355def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1356 1357def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1358 let Latency = 20; 1359 let NumMicroOps = 8; 1360 let ReleaseAtCycles = [1,1,1,1,1,1,2]; 1361} 1362def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>; 1363 1364def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> { 1365 let Latency = 21; 1366 let NumMicroOps = 2; 1367 let ReleaseAtCycles = [1,1]; 1368} 1369def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>; 1370 1371def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1372 let Latency = 21; 1373 let NumMicroOps = 19; 1374 let ReleaseAtCycles = [2,1,4,1,1,4,6]; 1375} 1376def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>; 1377 1378def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1379 let Latency = 22; 1380 let NumMicroOps = 18; 1381 let ReleaseAtCycles = [1,1,16]; 1382} 1383def: InstRW<[BWWriteResGroup172], (instrs POPF64)>; 1384 1385def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1386 let Latency = 23; 1387 let NumMicroOps = 19; 1388 let ReleaseAtCycles = [3,1,15]; 1389} 1390def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>; 1391 1392def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1393 let Latency = 24; 1394 let NumMicroOps = 3; 1395 let ReleaseAtCycles = [1,1,1]; 1396} 1397def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>; 1398 1399def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> { 1400 let Latency = 26; 1401 let NumMicroOps = 2; 1402 let ReleaseAtCycles = [1,1]; 1403} 1404def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>; 1405 1406def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1407 let Latency = 29; 1408 let NumMicroOps = 3; 1409 let ReleaseAtCycles = [1,1,1]; 1410} 1411def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>; 1412 1413def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1414 let Latency = 17; 1415 let NumMicroOps = 7; 1416 let ReleaseAtCycles = [1,3,2,1]; 1417} 1418def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERDPDrm, VPGATHERDQrm, 1419 VGATHERQPDrm, VPGATHERQQrm)>; 1420 1421def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1422 let Latency = 18; 1423 let NumMicroOps = 9; 1424 let ReleaseAtCycles = [1,3,4,1]; 1425} 1426def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 1427 VGATHERQPDYrm, VPGATHERQQYrm)>; 1428 1429def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1430 let Latency = 19; 1431 let NumMicroOps = 9; 1432 let ReleaseAtCycles = [1,5,2,1]; 1433} 1434def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSrm, VPGATHERQDrm)>; 1435 1436def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1437 let Latency = 19; 1438 let NumMicroOps = 10; 1439 let ReleaseAtCycles = [1,4,4,1]; 1440} 1441def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPSrm, VPGATHERDDrm, 1442 VGATHERQPSYrm, VPGATHERQDYrm)>; 1443 1444def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1445 let Latency = 21; 1446 let NumMicroOps = 14; 1447 let ReleaseAtCycles = [1,4,8,1]; 1448} 1449def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 1450 1451def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1452 let Latency = 29; 1453 let NumMicroOps = 27; 1454 let ReleaseAtCycles = [1,5,1,1,19]; 1455} 1456def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>; 1457 1458def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1459 let Latency = 30; 1460 let NumMicroOps = 28; 1461 let ReleaseAtCycles = [1,6,1,1,19]; 1462} 1463def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>; 1464def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 1465 1466def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> { 1467 let Latency = 34; 1468 let NumMicroOps = 23; 1469 let ReleaseAtCycles = [1,5,3,4,10]; 1470} 1471def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri", 1472 "IN(8|16|32)rr")>; 1473 1474def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1475 let Latency = 35; 1476 let NumMicroOps = 23; 1477 let ReleaseAtCycles = [1,5,2,1,4,10]; 1478} 1479def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir", 1480 "OUT(8|16|32)rr")>; 1481 1482def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> { 1483 let Latency = 42; 1484 let NumMicroOps = 22; 1485 let ReleaseAtCycles = [2,20]; 1486} 1487def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>; 1488 1489def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> { 1490 let Latency = 60; 1491 let NumMicroOps = 64; 1492 let ReleaseAtCycles = [2,2,8,1,10,2,39]; 1493} 1494def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>; 1495 1496def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { 1497 let Latency = 63; 1498 let NumMicroOps = 88; 1499 let ReleaseAtCycles = [4,4,31,1,2,1,45]; 1500} 1501def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>; 1502 1503def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { 1504 let Latency = 63; 1505 let NumMicroOps = 90; 1506 let ReleaseAtCycles = [4,2,33,1,2,1,47]; 1507} 1508def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>; 1509 1510def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> { 1511 let Latency = 75; 1512 let NumMicroOps = 15; 1513 let ReleaseAtCycles = [6,3,6]; 1514} 1515def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>; 1516 1517def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> { 1518 let Latency = 115; 1519 let NumMicroOps = 100; 1520 let ReleaseAtCycles = [9,9,11,8,1,11,21,30]; 1521} 1522def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>; 1523 1524def: InstRW<[WriteZero], (instrs CLC)>; 1525 1526 1527// Instruction variants handled by the renamer. These might not need execution 1528// ports in certain conditions. 1529// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1530// section "Haswell and Broadwell Pipeline" > "Register allocation and 1531// renaming". 1532// These can be investigated with llvm-exegesis, e.g. 1533// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1534// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1535 1536def BWWriteZeroLatency : SchedWriteRes<[]> { 1537 let Latency = 0; 1538} 1539 1540def BWWriteZeroIdiom : SchedWriteVariant<[ 1541 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1542 SchedVar<NoSchedPred, [WriteALU]> 1543]>; 1544def : InstRW<[BWWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1545 XOR32rr, XOR64rr)>; 1546 1547def BWWriteFZeroIdiom : SchedWriteVariant<[ 1548 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1549 SchedVar<NoSchedPred, [WriteFLogic]> 1550]>; 1551def : InstRW<[BWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1552 VXORPDrr)>; 1553 1554def BWWriteFZeroIdiomY : SchedWriteVariant<[ 1555 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1556 SchedVar<NoSchedPred, [WriteFLogicY]> 1557]>; 1558def : InstRW<[BWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1559 1560def BWWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1561 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1562 SchedVar<NoSchedPred, [WriteVecLogicX]> 1563]>; 1564def : InstRW<[BWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1565 1566def BWWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1567 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1568 SchedVar<NoSchedPred, [WriteVecLogicY]> 1569]>; 1570def : InstRW<[BWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1571 1572def BWWriteVZeroIdiomALUX : SchedWriteVariant<[ 1573 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1574 SchedVar<NoSchedPred, [WriteVecALUX]> 1575]>; 1576def : InstRW<[BWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1577 PSUBDrr, VPSUBDrr, 1578 PSUBQrr, VPSUBQrr, 1579 PSUBWrr, VPSUBWrr, 1580 PCMPGTBrr, VPCMPGTBrr, 1581 PCMPGTDrr, VPCMPGTDrr, 1582 PCMPGTWrr, VPCMPGTWrr)>; 1583 1584def BWWriteVZeroIdiomALUY : SchedWriteVariant<[ 1585 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1586 SchedVar<NoSchedPred, [WriteVecALUY]> 1587]>; 1588def : InstRW<[BWWriteVZeroIdiomALUY], (instrs VPSUBBYrr, 1589 VPSUBDYrr, 1590 VPSUBQYrr, 1591 VPSUBWYrr, 1592 VPCMPGTBYrr, 1593 VPCMPGTDYrr, 1594 VPCMPGTWYrr)>; 1595 1596def BWWritePCMPGTQ : SchedWriteRes<[BWPort0]> { 1597 let Latency = 5; 1598 let NumMicroOps = 1; 1599 let ReleaseAtCycles = [1]; 1600} 1601 1602def BWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1603 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1604 SchedVar<NoSchedPred, [BWWritePCMPGTQ]> 1605]>; 1606def : InstRW<[BWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1607 VPCMPGTQYrr)>; 1608 1609 1610// CMOVs that use both Z and C flag require an extra uop. 1611def BWWriteCMOVA_CMOVBErr : SchedWriteRes<[BWPort06,BWPort0156]> { 1612 let Latency = 2; 1613 let ReleaseAtCycles = [1,1]; 1614 let NumMicroOps = 2; 1615} 1616 1617def BWWriteCMOVA_CMOVBErm : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { 1618 let Latency = 7; 1619 let ReleaseAtCycles = [1,1,1]; 1620 let NumMicroOps = 3; 1621} 1622 1623def BWCMOVA_CMOVBErr : SchedWriteVariant<[ 1624 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [BWWriteCMOVA_CMOVBErr]>, 1625 SchedVar<NoSchedPred, [WriteCMOV]> 1626]>; 1627 1628def BWCMOVA_CMOVBErm : SchedWriteVariant<[ 1629 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [BWWriteCMOVA_CMOVBErm]>, 1630 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1631]>; 1632 1633def : InstRW<[BWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1634def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1635 1636// SETCCs that use both Z and C flag require an extra uop. 1637def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> { 1638 let Latency = 2; 1639 let ReleaseAtCycles = [1,1]; 1640 let NumMicroOps = 2; 1641} 1642 1643def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { 1644 let Latency = 3; 1645 let ReleaseAtCycles = [1,1,1,1]; 1646 let NumMicroOps = 4; 1647} 1648 1649def BWSETA_SETBErr : SchedWriteVariant<[ 1650 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [BWWriteSETA_SETBEr]>, 1651 SchedVar<NoSchedPred, [WriteSETCC]> 1652]>; 1653 1654def BWSETA_SETBErm : SchedWriteVariant<[ 1655 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [BWWriteSETA_SETBEm]>, 1656 SchedVar<NoSchedPred, [WriteSETCCStore]> 1657]>; 1658 1659def : InstRW<[BWSETA_SETBErr], (instrs SETCCr)>; 1660def : InstRW<[BWSETA_SETBErm], (instrs SETCCm)>; 1661 1662/////////////////////////////////////////////////////////////////////////////// 1663// Dependency breaking instructions. 1664/////////////////////////////////////////////////////////////////////////////// 1665 1666def : IsZeroIdiomFunction<[ 1667 // GPR Zero-idioms. 1668 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>, 1669 1670 // SSE Zero-idioms. 1671 DepBreakingClass<[ 1672 // fp variants. 1673 XORPSrr, XORPDrr, 1674 1675 // int variants. 1676 PXORrr, 1677 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr, 1678 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr 1679 ], ZeroIdiomPredicate>, 1680 1681 // AVX Zero-idioms. 1682 DepBreakingClass<[ 1683 // xmm fp variants. 1684 VXORPSrr, VXORPDrr, 1685 1686 // xmm int variants. 1687 VPXORrr, 1688 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr, 1689 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr, 1690 1691 // ymm variants. 1692 VXORPSYrr, VXORPDYrr, VPXORYrr, 1693 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr, 1694 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr 1695 ], ZeroIdiomPredicate>, 1696]>; 1697 1698} // SchedModel 1699