1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Broadwell to support instruction 10// scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def BroadwellModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and BW can decode 4 16 // instructions per cycle. 17 let IssueWidth = 4; 18 let MicroOpBufferSize = 192; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 16; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = BroadwellModel in { 31 32// Broadwell can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def BWPort0 : ProcResource<1>; 41def BWPort1 : ProcResource<1>; 42def BWPort2 : ProcResource<1>; 43def BWPort3 : ProcResource<1>; 44def BWPort4 : ProcResource<1>; 45def BWPort5 : ProcResource<1>; 46def BWPort6 : ProcResource<1>; 47def BWPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>; 51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>; 52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>; 53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>; 54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>; 55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>; 56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>; 57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>; 58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>; 59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>; 60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>; 61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>; 62 63// 60 Entry Unified Scheduler 64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4, 65 BWPort5, BWPort6, BWPort7]> { 66 let BufferSize=60; 67} 68 69// Integer division issued on port 0. 70def BWDivider : ProcResource<1>; 71// FP division and sqrt on port 0. 72def BWFPDivider : ProcResource<1>; 73 74// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 75// cycles after the memory operand. 76def : ReadAdvance<ReadAfterLd, 5>; 77 78// Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available 79// until 5/5/6 cycles after the memory operand. 80def : ReadAdvance<ReadAfterVecLd, 5>; 81def : ReadAdvance<ReadAfterVecXLd, 5>; 82def : ReadAdvance<ReadAfterVecYLd, 6>; 83 84def : ReadAdvance<ReadInt2Fpu, 0>; 85 86// Many SchedWrites are defined in pairs with and without a folded load. 87// Instructions with folded loads are usually micro-fused, so they only appear 88// as two micro-ops when queued in the reservation station. 89// This multiclass defines the resource usage for variants with and without 90// folded loads. 91multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW, 92 list<ProcResourceKind> ExePorts, 93 int Lat, list<int> Res = [1], int UOps = 1, 94 int LoadLat = 5> { 95 // Register variant is using a single cycle on ExePort. 96 def : WriteRes<SchedRW, ExePorts> { 97 let Latency = Lat; 98 let ResourceCycles = Res; 99 let NumMicroOps = UOps; 100 } 101 102 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 103 // the latency (default = 5). 104 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> { 105 let Latency = !add(Lat, LoadLat); 106 let ResourceCycles = !listconcat([1], Res); 107 let NumMicroOps = !add(UOps, 1); 108 } 109} 110 111// A folded store needs a cycle on port 4 for the store data, and an extra port 112// 2/3/7 cycle to recompute the address. 113def : WriteRes<WriteRMW, [BWPort237,BWPort4]>; 114 115// Loads, stores, and moves, not folded with other operations. 116// Store_addr on 237. 117// Store_data on 4. 118defm : X86WriteRes<WriteStore, [BWPort237, BWPort4], 1, [1,1], 1>; 119defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>; 120defm : X86WriteRes<WriteLoad, [BWPort23], 5, [1], 1>; 121defm : X86WriteRes<WriteMove, [BWPort0156], 1, [1], 1>; 122 123// Treat misc copies as a move. 124def : InstRW<[WriteMove], (instrs COPY)>; 125 126// Idioms that clear a register, like xorps %xmm0, %xmm0. 127// These can often bypass execution ports completely. 128def : WriteRes<WriteZero, []>; 129 130// Model the effect of clobbering the read-write mask operand of the GATHER operation. 131// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 132defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 133 134// Arithmetic. 135defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op. 136defm : BWWriteResPair<WriteADC, [BWPort06], 1>; // Integer ALU + flags op. 137 138// Integer multiplication. 139defm : BWWriteResPair<WriteIMul8, [BWPort1], 3>; 140defm : BWWriteResPair<WriteIMul16, [BWPort1,BWPort06,BWPort0156], 4, [1,1,2], 4>; 141defm : X86WriteRes<WriteIMul16Imm, [BWPort1,BWPort0156], 4, [1,1], 2>; 142defm : X86WriteRes<WriteIMul16ImmLd, [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>; 143defm : BWWriteResPair<WriteIMul16Reg, [BWPort1], 3>; 144defm : BWWriteResPair<WriteIMul32, [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>; 145defm : BWWriteResPair<WriteMULX32, [BWPort1,BWPort06,BWPort0156], 3, [1,1,1], 3>; 146defm : BWWriteResPair<WriteIMul32Imm, [BWPort1], 3>; 147defm : BWWriteResPair<WriteIMul32Reg, [BWPort1], 3>; 148defm : BWWriteResPair<WriteIMul64, [BWPort1,BWPort5], 4, [1,1], 2>; 149defm : BWWriteResPair<WriteMULX64, [BWPort1,BWPort5], 3, [1,1], 2>; 150defm : BWWriteResPair<WriteIMul64Imm, [BWPort1], 3>; 151defm : BWWriteResPair<WriteIMul64Reg, [BWPort1], 3>; 152def BWWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 153def : WriteRes<WriteIMulHLd, []> { 154 let Latency = !add(BWWriteIMulH.Latency, BroadwellModel.LoadLatency); 155} 156 157defm : X86WriteRes<WriteBSWAP32, [BWPort15], 1, [1], 1>; 158defm : X86WriteRes<WriteBSWAP64, [BWPort06, BWPort15], 2, [1, 1], 2>; 159defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>; 160defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>; 161defm : X86WriteRes<WriteXCHG, [BWPort0156], 2, [3], 3>; 162 163// Integer shifts and rotates. 164defm : BWWriteResPair<WriteShift, [BWPort06], 1>; 165defm : BWWriteResPair<WriteShiftCL, [BWPort06,BWPort0156], 3, [2,1], 3>; 166defm : BWWriteResPair<WriteRotate, [BWPort06], 1, [1], 1>; 167defm : BWWriteResPair<WriteRotateCL, [BWPort06,BWPort0156], 3, [2,1], 3>; 168 169// SHLD/SHRD. 170defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>; 171defm : X86WriteRes<WriteSHDrrcl,[BWPort1,BWPort06,BWPort0156], 6, [1, 1, 2], 4>; 172defm : X86WriteRes<WriteSHDmri, [BWPort1,BWPort23,BWPort237,BWPort0156], 9, [1, 1, 1, 1], 4>; 173defm : X86WriteRes<WriteSHDmrcl,[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156], 11, [1, 1, 1, 1, 2], 6>; 174 175// Branches don't produce values, so they have no latency, but they still 176// consume resources. Indirect branches can fold loads. 177defm : BWWriteResPair<WriteJump, [BWPort06], 1>; 178 179defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>; 180 181defm : BWWriteResPair<WriteCMOV, [BWPort06], 1>; // Conditional move. 182defm : X86WriteRes<WriteFCMOV, [BWPort1], 3, [1], 1>; // x87 conditional move. 183 184def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc. 185def : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> { 186 let Latency = 2; 187 let NumMicroOps = 3; 188} 189 190defm : X86WriteRes<WriteLAHFSAHF, [BWPort06], 1, [1], 1>; 191defm : X86WriteRes<WriteBitTest, [BWPort06], 1, [1], 1>; // Bit Test instrs 192defm : X86WriteRes<WriteBitTestImmLd, [BWPort06,BWPort23], 6, [1,1], 2>; 193defm : X86WriteRes<WriteBitTestRegLd, [BWPort0156,BWPort23], 6, [1,1], 2>; 194defm : X86WriteRes<WriteBitTestSet, [BWPort06], 1, [1], 1>; // Bit Test + Set instrs 195defm : X86WriteRes<WriteBitTestSetImmLd, [BWPort06,BWPort23], 5, [1,1], 3>; 196defm : X86WriteRes<WriteBitTestSetRegLd, [BWPort0156,BWPort23], 5, [1,1], 2>; 197 198// This is for simple LEAs with one or two input operands. 199// The complex ones can only execute on port 1, and they require two cycles on 200// the port to read all inputs. We don't model that. 201def : WriteRes<WriteLEA, [BWPort15]>; 202 203// Bit counts. 204defm : BWWriteResPair<WriteBSF, [BWPort1], 3>; 205defm : BWWriteResPair<WriteBSR, [BWPort1], 3>; 206defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>; 207defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>; 208defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>; 209 210// BMI1 BEXTR/BLS, BMI2 BZHI 211defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>; 212defm : BWWriteResPair<WriteBLS, [BWPort15], 1>; 213defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>; 214 215// TODO: Why isn't the BWDivider used consistently? 216defm : X86WriteRes<WriteDiv8, [BWPort0, BWDivider], 25, [1, 10], 1>; 217defm : X86WriteRes<WriteDiv16, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 218defm : X86WriteRes<WriteDiv32, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 219defm : X86WriteRes<WriteDiv64, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 220defm : X86WriteRes<WriteDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 221defm : X86WriteRes<WriteDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 222defm : X86WriteRes<WriteDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 223defm : X86WriteRes<WriteDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 224 225defm : X86WriteRes<WriteIDiv8, [BWPort0, BWDivider], 25, [1,10], 1>; 226defm : X86WriteRes<WriteIDiv16, [BWPort0, BWDivider], 25, [1,10], 1>; 227defm : X86WriteRes<WriteIDiv32, [BWPort0, BWDivider], 25, [1,10], 1>; 228defm : X86WriteRes<WriteIDiv64, [BWPort0, BWDivider], 25, [1,10], 1>; 229defm : X86WriteRes<WriteIDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 230defm : X86WriteRes<WriteIDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 231defm : X86WriteRes<WriteIDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 232defm : X86WriteRes<WriteIDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 233 234// Floating point. This covers both scalar and vector operations. 235defm : X86WriteRes<WriteFLD0, [BWPort01], 1, [1], 1>; 236defm : X86WriteRes<WriteFLD1, [BWPort01], 1, [2], 2>; 237defm : X86WriteRes<WriteFLDC, [BWPort01], 1, [2], 2>; 238defm : X86WriteRes<WriteFLoad, [BWPort23], 5, [1], 1>; 239defm : X86WriteRes<WriteFLoadX, [BWPort23], 5, [1], 1>; 240defm : X86WriteRes<WriteFLoadY, [BWPort23], 6, [1], 1>; 241defm : X86WriteRes<WriteFMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>; 242defm : X86WriteRes<WriteFMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>; 243defm : X86WriteRes<WriteFStore, [BWPort237,BWPort4], 1, [1,1], 2>; 244defm : X86WriteRes<WriteFStoreX, [BWPort237,BWPort4], 1, [1,1], 2>; 245defm : X86WriteRes<WriteFStoreY, [BWPort237,BWPort4], 1, [1,1], 2>; 246defm : X86WriteRes<WriteFStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>; 247defm : X86WriteRes<WriteFStoreNTX, [BWPort237,BWPort4], 1, [1,1], 2>; 248defm : X86WriteRes<WriteFStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>; 249 250defm : X86WriteRes<WriteFMaskedStore32, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 251defm : X86WriteRes<WriteFMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 252defm : X86WriteRes<WriteFMaskedStore64, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 253defm : X86WriteRes<WriteFMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 254 255defm : X86WriteRes<WriteFMove, [BWPort5], 1, [1], 1>; 256defm : X86WriteRes<WriteFMoveX, [BWPort5], 1, [1], 1>; 257defm : X86WriteRes<WriteFMoveY, [BWPort5], 1, [1], 1>; 258defm : X86WriteResUnsupported<WriteFMoveZ>; 259defm : X86WriteRes<WriteEMMS, [BWPort01,BWPort15,BWPort015,BWPort0156], 31, [8,1,21,1], 31>; 260 261defm : BWWriteResPair<WriteFAdd, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub. 262defm : BWWriteResPair<WriteFAddX, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub (XMM). 263defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM). 264defm : X86WriteResPairUnsupported<WriteFAddZ>; 265defm : BWWriteResPair<WriteFAdd64, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub. 266defm : BWWriteResPair<WriteFAdd64X, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub (XMM). 267defm : BWWriteResPair<WriteFAdd64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM). 268defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 269 270defm : BWWriteResPair<WriteFCmp, [BWPort1], 3, [1], 1, 5>; // Floating point compare. 271defm : BWWriteResPair<WriteFCmpX, [BWPort1], 3, [1], 1, 5>; // Floating point compare (XMM). 272defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM). 273defm : X86WriteResPairUnsupported<WriteFCmpZ>; 274defm : BWWriteResPair<WriteFCmp64, [BWPort1], 3, [1], 1, 5>; // Floating point double compare. 275defm : BWWriteResPair<WriteFCmp64X, [BWPort1], 3, [1], 1, 5>; // Floating point double compare (XMM). 276defm : BWWriteResPair<WriteFCmp64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double compare (YMM/ZMM). 277defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 278 279defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags (X87). 280defm : BWWriteResPair<WriteFComX, [BWPort1], 3>; // Floating point compare to flags (SSE). 281 282defm : BWWriteResPair<WriteFMul, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication. 283defm : BWWriteResPair<WriteFMulX, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM). 284defm : BWWriteResPair<WriteFMulY, [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM). 285defm : X86WriteResPairUnsupported<WriteFMulZ>; 286defm : BWWriteResPair<WriteFMul64, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication. 287defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM). 288defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM). 289defm : X86WriteResPairUnsupported<WriteFMul64Z>; 290 291//defm : BWWriteResPair<WriteFDiv, [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division. 292defm : BWWriteResPair<WriteFDivX, [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM). 293defm : BWWriteResPair<WriteFDivY, [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM). 294defm : X86WriteResPairUnsupported<WriteFDivZ>; 295//defm : BWWriteResPair<WriteFDiv64, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division. 296defm : BWWriteResPair<WriteFDiv64X, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM). 297defm : BWWriteResPair<WriteFDiv64Y, [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM). 298defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 299 300defm : BWWriteResPair<WriteFRcp, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate. 301defm : BWWriteResPair<WriteFRcpX, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate (XMM). 302defm : BWWriteResPair<WriteFRcpY, [BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal estimate (YMM/ZMM). 303defm : X86WriteResPairUnsupported<WriteFRcpZ>; 304 305defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate. 306defm : BWWriteResPair<WriteFRsqrtX,[BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate (XMM). 307defm : BWWriteResPair<WriteFRsqrtY,[BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal square root estimate (YMM/ZMM). 308defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 309 310defm : X86WriteRes<WriteFSqrt, [BWPort0,BWFPDivider], 11, [1,4], 1>; // Floating point square root. 311defm : X86WriteRes<WriteFSqrtLd, [BWPort0,BWPort23,BWFPDivider], 16, [1,1,7], 2>; 312defm : BWWriteResPair<WriteFSqrtX, [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM). 313defm : BWWriteResPair<WriteFSqrtY, [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM). 314defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 315defm : X86WriteRes<WriteFSqrt64, [BWPort0,BWFPDivider], 16, [1,8], 1>; // Floating point double square root. 316defm : X86WriteRes<WriteFSqrt64Ld, [BWPort0,BWPort23,BWFPDivider], 21, [1,1,14], 2>; 317defm : BWWriteResPair<WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM). 318defm : BWWriteResPair<WriteFSqrt64Y, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM). 319defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 320defm : BWWriteResPair<WriteFSqrt80, [BWPort0,BWFPDivider], 23, [1,9]>; // Floating point long double square root. 321 322defm : BWWriteResPair<WriteFMA, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add. 323defm : BWWriteResPair<WriteFMAX, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM). 324defm : BWWriteResPair<WriteFMAY, [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM). 325defm : X86WriteResPairUnsupported<WriteFMAZ>; 326defm : BWWriteResPair<WriteDPPD, [BWPort0,BWPort1,BWPort5], 9, [1,1,1], 3, 5>; // Floating point double dot product. 327defm : BWWriteResPair<WriteDPPS, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 5>; // Floating point single dot product. 328defm : BWWriteResPair<WriteDPPSY, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 6>; // Floating point single dot product (YMM). 329defm : X86WriteResPairUnsupported<WriteDPPSZ>; 330defm : BWWriteResPair<WriteFSign, [BWPort5], 1>; // Floating point fabs/fchs. 331defm : X86WriteRes<WriteFRnd, [BWPort23], 6, [1], 1>; // Floating point rounding. 332defm : X86WriteRes<WriteFRndY, [BWPort23], 6, [1], 1>; // Floating point rounding (YMM/ZMM). 333defm : X86WriteResPairUnsupported<WriteFRndZ>; 334defm : X86WriteRes<WriteFRndLd, [BWPort1,BWPort23], 11, [2,1], 3>; 335defm : X86WriteRes<WriteFRndYLd, [BWPort1,BWPort23], 12, [2,1], 3>; 336defm : BWWriteResPair<WriteFLogic, [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals. 337defm : BWWriteResPair<WriteFLogicY, [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM). 338defm : X86WriteResPairUnsupported<WriteFLogicZ>; 339defm : BWWriteResPair<WriteFTest, [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions. 340defm : BWWriteResPair<WriteFTestY, [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM). 341defm : X86WriteResPairUnsupported<WriteFTestZ>; 342defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles. 343defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM). 344defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 345defm : BWWriteResPair<WriteFVarShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles. 346defm : BWWriteResPair<WriteFVarShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles. 347defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 348defm : BWWriteResPair<WriteFBlend, [BWPort015], 1, [1], 1, 5>; // Floating point vector blends. 349defm : BWWriteResPair<WriteFBlendY, [BWPort015], 1, [1], 1, 6>; // Floating point vector blends. 350defm : X86WriteResPairUnsupported<WriteFBlendZ>; 351defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles. 352defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles. 353defm : BWWriteResPair<WriteFVarBlend, [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends. 354defm : BWWriteResPair<WriteFVarBlendY, [BWPort5], 2, [2], 2, 6>; // Fp vector variable blends. 355defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 356 357// FMA Scheduling helper class. 358// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 359 360// Conversion between integer and float. 361defm : BWWriteResPair<WriteCvtSS2I, [BWPort1], 3>; 362defm : BWWriteResPair<WriteCvtPS2I, [BWPort1], 3>; 363defm : BWWriteResPair<WriteCvtPS2IY, [BWPort1], 3>; 364defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 365defm : BWWriteResPair<WriteCvtSD2I, [BWPort1], 3>; 366defm : BWWriteResPair<WriteCvtPD2I, [BWPort1], 3>; 367defm : BWWriteResPair<WriteCvtPD2IY, [BWPort1], 3>; 368defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 369 370defm : BWWriteResPair<WriteCvtI2SS, [BWPort1], 4>; 371defm : BWWriteResPair<WriteCvtI2PS, [BWPort1], 4>; 372defm : BWWriteResPair<WriteCvtI2PSY, [BWPort1], 4>; 373defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 374defm : BWWriteResPair<WriteCvtI2SD, [BWPort1], 4>; 375defm : BWWriteResPair<WriteCvtI2PD, [BWPort1], 4>; 376defm : BWWriteResPair<WriteCvtI2PDY, [BWPort1], 4>; 377defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 378 379defm : BWWriteResPair<WriteCvtSS2SD, [BWPort1], 3>; 380defm : BWWriteResPair<WriteCvtPS2PD, [BWPort1], 3>; 381defm : BWWriteResPair<WriteCvtPS2PDY, [BWPort1], 3>; 382defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 383defm : BWWriteResPair<WriteCvtSD2SS, [BWPort1], 3>; 384defm : BWWriteResPair<WriteCvtPD2PS, [BWPort1], 3>; 385defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1], 3>; 386defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 387 388defm : X86WriteRes<WriteCvtPH2PS, [BWPort0,BWPort5], 2, [1,1], 2>; 389defm : X86WriteRes<WriteCvtPH2PSY, [BWPort0,BWPort5], 2, [1,1], 2>; 390defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 391defm : X86WriteRes<WriteCvtPH2PSLd, [BWPort0,BWPort23], 6, [1,1], 2>; 392defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort0,BWPort23], 6, [1,1], 2>; 393defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 394 395defm : X86WriteRes<WriteCvtPS2PH, [BWPort1,BWPort5], 4, [1,1], 2>; 396defm : X86WriteRes<WriteCvtPS2PHY, [BWPort1,BWPort5], 6, [1,1], 2>; 397defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 398defm : X86WriteRes<WriteCvtPS2PHSt, [BWPort1,BWPort4,BWPort237], 5, [1,1,1], 3>; 399defm : X86WriteRes<WriteCvtPS2PHYSt, [BWPort1,BWPort4,BWPort237], 7, [1,1,1], 3>; 400defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 401 402// Vector integer operations. 403defm : X86WriteRes<WriteVecLoad, [BWPort23], 5, [1], 1>; 404defm : X86WriteRes<WriteVecLoadX, [BWPort23], 5, [1], 1>; 405defm : X86WriteRes<WriteVecLoadY, [BWPort23], 6, [1], 1>; 406defm : X86WriteRes<WriteVecLoadNT, [BWPort23], 5, [1], 1>; 407defm : X86WriteRes<WriteVecLoadNTY, [BWPort23], 6, [1], 1>; 408defm : X86WriteRes<WriteVecMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>; 409defm : X86WriteRes<WriteVecMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>; 410defm : X86WriteRes<WriteVecStore, [BWPort237,BWPort4], 1, [1,1], 2>; 411defm : X86WriteRes<WriteVecStoreX, [BWPort237,BWPort4], 1, [1,1], 2>; 412defm : X86WriteRes<WriteVecStoreY, [BWPort237,BWPort4], 1, [1,1], 2>; 413defm : X86WriteRes<WriteVecStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>; 414defm : X86WriteRes<WriteVecStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>; 415defm : X86WriteRes<WriteVecMaskedStore32, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 416defm : X86WriteRes<WriteVecMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 417defm : X86WriteRes<WriteVecMaskedStore64, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 418defm : X86WriteRes<WriteVecMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 419defm : X86WriteRes<WriteVecMove, [BWPort015], 1, [1], 1>; 420defm : X86WriteRes<WriteVecMoveX, [BWPort015], 1, [1], 1>; 421defm : X86WriteRes<WriteVecMoveY, [BWPort015], 1, [1], 1>; 422defm : X86WriteResUnsupported<WriteVecMoveZ>; 423defm : X86WriteRes<WriteVecMoveToGpr, [BWPort0], 1, [1], 1>; 424defm : X86WriteRes<WriteVecMoveFromGpr, [BWPort5], 1, [1], 1>; 425 426defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor. 427defm : BWWriteResPair<WriteVecLogicX,[BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor. 428defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM). 429defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 430defm : BWWriteResPair<WriteVecTest, [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions. 431defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM). 432defm : X86WriteResPairUnsupported<WriteVecTestZ>; 433defm : BWWriteResPair<WriteVecALU, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 434defm : BWWriteResPair<WriteVecALUX, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 435defm : BWWriteResPair<WriteVecALUY, [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM). 436defm : X86WriteResPairUnsupported<WriteVecALUZ>; 437defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply. 438defm : BWWriteResPair<WriteVecIMulX, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply. 439defm : BWWriteResPair<WriteVecIMulY, [BWPort0], 5, [1], 1, 6>; // Vector integer multiply. 440defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 441defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // Vector PMULLD. 442defm : BWWriteResPair<WritePMULLDY, [BWPort0], 10, [2], 2, 6>; // Vector PMULLD (YMM/ZMM). 443defm : X86WriteResPairUnsupported<WritePMULLDZ>; 444defm : BWWriteResPair<WriteShuffle, [BWPort5], 1, [1], 1, 5>; // Vector shuffles. 445defm : BWWriteResPair<WriteShuffleX, [BWPort5], 1, [1], 1, 5>; // Vector shuffles. 446defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM). 447defm : X86WriteResPairUnsupported<WriteShuffleZ>; 448defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles. 449defm : BWWriteResPair<WriteVarShuffleX,[BWPort5], 1, [1], 1, 5>; // Vector variable shuffles. 450defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM). 451defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 452defm : BWWriteResPair<WriteBlend, [BWPort5], 1, [1], 1, 5>; // Vector blends. 453defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM). 454defm : X86WriteResPairUnsupported<WriteBlendZ>; 455defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector shuffles. 456defm : BWWriteResPair<WriteVPMOV256, [BWPort5], 3, [1], 1, 6>; // 256-bit width packed vector width-changing move. 457defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector variable shuffles. 458defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2], 2, 5>; // Vector variable blends. 459defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM). 460defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 461defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD. 462defm : BWWriteResPair<WriteMPSADY, [BWPort0, BWPort5], 7, [1, 2], 3, 6>; // Vector MPSAD. 463defm : X86WriteResPairUnsupported<WriteMPSADZ>; 464defm : BWWriteResPair<WritePSADBW, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW. 465defm : BWWriteResPair<WritePSADBWX, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW. 466defm : BWWriteResPair<WritePSADBWY, [BWPort0], 5, [1], 1, 6>; // Vector PSADBW (YMM/ZMM). 467defm : X86WriteResPairUnsupported<WritePSADBWZ>; 468defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS. 469 470// Vector integer shifts. 471defm : BWWriteResPair<WriteVecShift, [BWPort0], 1, [1], 1, 5>; 472defm : BWWriteResPair<WriteVecShiftX, [BWPort0,BWPort5], 2, [1,1], 2, 5>; 473defm : X86WriteRes<WriteVecShiftY, [BWPort0,BWPort5], 4, [1,1], 2>; 474defm : X86WriteRes<WriteVecShiftYLd, [BWPort0,BWPort23], 7, [1,1], 2>; 475defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 476 477defm : BWWriteResPair<WriteVecShiftImm, [BWPort0], 1, [1], 1, 5>; 478defm : BWWriteResPair<WriteVecShiftImmX, [BWPort0], 1, [1], 1, 5>; // Vector integer immediate shifts (XMM). 479defm : BWWriteResPair<WriteVecShiftImmY, [BWPort0], 1, [1], 1, 6>; // Vector integer immediate shifts (YMM/ZMM). 480defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 481defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts. 482defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM). 483defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 484 485// Vector insert/extract operations. 486def : WriteRes<WriteVecInsert, [BWPort5]> { 487 let Latency = 2; 488 let NumMicroOps = 2; 489 let ResourceCycles = [2]; 490} 491def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> { 492 let Latency = 6; 493 let NumMicroOps = 2; 494} 495 496def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> { 497 let Latency = 2; 498 let NumMicroOps = 2; 499} 500def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> { 501 let Latency = 2; 502 let NumMicroOps = 3; 503} 504 505// String instructions. 506 507// Packed Compare Implicit Length Strings, Return Mask 508def : WriteRes<WritePCmpIStrM, [BWPort0]> { 509 let Latency = 11; 510 let NumMicroOps = 3; 511 let ResourceCycles = [3]; 512} 513def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> { 514 let Latency = 16; 515 let NumMicroOps = 4; 516 let ResourceCycles = [3,1]; 517} 518 519// Packed Compare Explicit Length Strings, Return Mask 520def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> { 521 let Latency = 19; 522 let NumMicroOps = 9; 523 let ResourceCycles = [4,3,1,1]; 524} 525def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> { 526 let Latency = 24; 527 let NumMicroOps = 10; 528 let ResourceCycles = [4,3,1,1,1]; 529} 530 531// Packed Compare Implicit Length Strings, Return Index 532def : WriteRes<WritePCmpIStrI, [BWPort0]> { 533 let Latency = 11; 534 let NumMicroOps = 3; 535 let ResourceCycles = [3]; 536} 537def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> { 538 let Latency = 16; 539 let NumMicroOps = 4; 540 let ResourceCycles = [3,1]; 541} 542 543// Packed Compare Explicit Length Strings, Return Index 544def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> { 545 let Latency = 18; 546 let NumMicroOps = 8; 547 let ResourceCycles = [4,3,1]; 548} 549def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> { 550 let Latency = 23; 551 let NumMicroOps = 9; 552 let ResourceCycles = [4,3,1,1]; 553} 554 555// MOVMSK Instructions. 556def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; } 557def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; } 558def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; } 559def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; } 560 561// AES Instructions. 562def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption. 563 let Latency = 7; 564 let NumMicroOps = 1; 565 let ResourceCycles = [1]; 566} 567def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> { 568 let Latency = 12; 569 let NumMicroOps = 2; 570 let ResourceCycles = [1,1]; 571} 572 573def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn. 574 let Latency = 14; 575 let NumMicroOps = 2; 576 let ResourceCycles = [2]; 577} 578def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> { 579 let Latency = 19; 580 let NumMicroOps = 3; 581 let ResourceCycles = [2,1]; 582} 583 584def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation. 585 let Latency = 29; 586 let NumMicroOps = 11; 587 let ResourceCycles = [2,7,2]; 588} 589def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> { 590 let Latency = 33; 591 let NumMicroOps = 11; 592 let ResourceCycles = [2,7,1,1]; 593} 594 595// Carry-less multiplication instructions. 596defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>; 597// Load/store MXCSR. 598def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 599def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 600 601// Catch-all for expensive system instructions. 602def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } 603 604// Old microcoded instructions that nobody use. 605def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } 606 607// Fence instructions. 608def : WriteRes<WriteFence, [BWPort23, BWPort4]>; 609 610// Nop, not very useful expect it provides a model for nops! 611def : WriteRes<WriteNop, []>; 612 613//////////////////////////////////////////////////////////////////////////////// 614// Horizontal add/sub instructions. 615//////////////////////////////////////////////////////////////////////////////// 616 617defm : BWWriteResPair<WriteFHAdd, [BWPort1,BWPort5], 5, [1,2], 3, 5>; 618defm : BWWriteResPair<WriteFHAddY, [BWPort1,BWPort5], 5, [1,2], 3, 6>; 619defm : BWWriteResPair<WritePHAdd, [BWPort5,BWPort15], 3, [2,1], 3, 5>; 620defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>; 621defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>; 622 623// Remaining instrs. 624 625def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> { 626 let Latency = 1; 627 let NumMicroOps = 1; 628 let ResourceCycles = [1]; 629} 630def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr", 631 "VPSRLVQ(Y?)rr")>; 632 633def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> { 634 let Latency = 1; 635 let NumMicroOps = 1; 636 let ResourceCycles = [1]; 637} 638def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r", 639 "UCOM_F(P?)r")>; 640 641def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> { 642 let Latency = 1; 643 let NumMicroOps = 1; 644 let ResourceCycles = [1]; 645} 646def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>; 647 648def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> { 649 let Latency = 1; 650 let NumMicroOps = 1; 651 let ResourceCycles = [1]; 652} 653def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>; 654 655def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> { 656 let Latency = 1; 657 let NumMicroOps = 1; 658 let ResourceCycles = [1]; 659} 660def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>; 661 662def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> { 663 let Latency = 1; 664 let NumMicroOps = 1; 665 let ResourceCycles = [1]; 666} 667def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>; 668 669def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> { 670 let Latency = 1; 671 let NumMicroOps = 1; 672 let ResourceCycles = [1]; 673} 674def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>; 675 676def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> { 677 let Latency = 1; 678 let NumMicroOps = 1; 679 let ResourceCycles = [1]; 680} 681def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>; 682 683def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> { 684 let Latency = 1; 685 let NumMicroOps = 1; 686 let ResourceCycles = [1]; 687} 688def: InstRW<[BWWriteResGroup9], (instrs SGDT64m, 689 SIDT64m, 690 SMSW16m, 691 STRm, 692 SYSCALL)>; 693 694def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> { 695 let Latency = 1; 696 let NumMicroOps = 2; 697 let ResourceCycles = [1,1]; 698} 699def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>; 700def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>; 701 702def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> { 703 let Latency = 2; 704 let NumMicroOps = 2; 705 let ResourceCycles = [2]; 706} 707def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>; 708 709def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> { 710 let Latency = 2; 711 let NumMicroOps = 2; 712 let ResourceCycles = [2]; 713} 714def: InstRW<[BWWriteResGroup14], (instrs LFENCE, 715 MFENCE, 716 WAIT, 717 XGETBV)>; 718 719def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> { 720 let Latency = 2; 721 let NumMicroOps = 2; 722 let ResourceCycles = [1,1]; 723} 724def: InstRW<[BWWriteResGroup15], (instregex "(V?)CVTPS2PDrr", 725 "(V?)CVTSS2SDrr")>; 726 727def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> { 728 let Latency = 2; 729 let NumMicroOps = 2; 730 let ResourceCycles = [1,1]; 731} 732def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>; 733 734def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> { 735 let Latency = 2; 736 let NumMicroOps = 2; 737 let ResourceCycles = [1,1]; 738} 739def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>; 740 741def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> { 742 let Latency = 2; 743 let NumMicroOps = 2; 744 let ResourceCycles = [1,1]; 745} 746def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>; 747 748def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> { 749 let Latency = 2; 750 let NumMicroOps = 2; 751 let ResourceCycles = [1,1]; 752} 753def: InstRW<[BWWriteResGroup20], (instrs CWD, 754 JCXZ, JECXZ, JRCXZ, 755 ADC8i8, SBB8i8, 756 ADC16i16, SBB16i16, 757 ADC32i32, SBB32i32, 758 ADC64i32, SBB64i32)>; 759 760def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> { 761 let Latency = 2; 762 let NumMicroOps = 3; 763 let ResourceCycles = [1,1,1]; 764} 765def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>; 766 767def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> { 768 let Latency = 2; 769 let NumMicroOps = 3; 770 let ResourceCycles = [1,1,1]; 771} 772def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>; 773 774def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { 775 let Latency = 2; 776 let NumMicroOps = 3; 777 let ResourceCycles = [1,1,1]; 778} 779def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 780 STOSB, STOSL, STOSQ, STOSW)>; 781def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>; 782 783def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> { 784 let Latency = 3; 785 let NumMicroOps = 1; 786 let ResourceCycles = [1]; 787} 788def: InstRW<[BWWriteResGroup27], (instrs MMX_CVTPI2PSrr)>; 789def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr", 790 "(V?)CVTDQ2PS(Y?)rr")>; 791 792def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> { 793 let Latency = 3; 794 let NumMicroOps = 1; 795 let ResourceCycles = [1]; 796} 797def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr, 798 VPBROADCASTWrr)>; 799 800def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> { 801 let Latency = 3; 802 let NumMicroOps = 3; 803 let ResourceCycles = [2,1]; 804} 805def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWrr, 806 MMX_PACKSSWBrr, 807 MMX_PACKUSWBrr)>; 808 809def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> { 810 let Latency = 3; 811 let NumMicroOps = 3; 812 let ResourceCycles = [1,2]; 813} 814def: InstRW<[BWWriteResGroup34], (instregex "CLD")>; 815 816def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> { 817 let Latency = 2; 818 let NumMicroOps = 3; 819 let ResourceCycles = [1,2]; 820} 821def: InstRW<[BWWriteResGroup35], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1, 822 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>; 823 824def BWWriteResGroup36 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { 825 let Latency = 5; 826 let NumMicroOps = 8; 827 let ResourceCycles = [2,4,2]; 828} 829def: InstRW<[BWWriteResGroup36], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>; 830 831def BWWriteResGroup36b : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { 832 let Latency = 6; 833 let NumMicroOps = 8; 834 let ResourceCycles = [2,4,2]; 835} 836def: InstRW<[BWWriteResGroup36b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>; 837 838def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> { 839 let Latency = 3; 840 let NumMicroOps = 4; 841 let ResourceCycles = [1,1,1,1]; 842} 843def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>; 844 845def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { 846 let Latency = 3; 847 let NumMicroOps = 4; 848 let ResourceCycles = [1,1,1,1]; 849} 850def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>; 851 852def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> { 853 let Latency = 4; 854 let NumMicroOps = 2; 855 let ResourceCycles = [1,1]; 856} 857def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr", 858 "(V?)CVT(T?)SD2SIrr", 859 "(V?)CVT(T?)SS2SI64rr", 860 "(V?)CVT(T?)SS2SIrr")>; 861 862def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> { 863 let Latency = 4; 864 let NumMicroOps = 2; 865 let ResourceCycles = [1,1]; 866} 867def: InstRW<[BWWriteResGroup40], (instrs VCVTPS2PDYrr)>; 868 869def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> { 870 let Latency = 4; 871 let NumMicroOps = 2; 872 let ResourceCycles = [1,1]; 873} 874def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>; 875 876def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> { 877 let Latency = 4; 878 let NumMicroOps = 2; 879 let ResourceCycles = [1,1]; 880} 881def: InstRW<[BWWriteResGroup42], (instrs MMX_CVTPI2PDrr)>; 882def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PD2PIrr", 883 "MMX_CVT(T?)PS2PIrr", 884 "(V?)CVTDQ2PDrr", 885 "(V?)CVTPD2PSrr", 886 "(V?)CVTSD2SSrr", 887 "(V?)CVTSI642SDrr", 888 "(V?)CVTSI2SDrr", 889 "(V?)CVTSI2SSrr", 890 "(V?)CVT(T?)PD2DQrr")>; 891 892def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> { 893 let Latency = 4; 894 let NumMicroOps = 3; 895 let ResourceCycles = [1,1,1]; 896} 897def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>; 898 899def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> { 900 let Latency = 4; 901 let NumMicroOps = 3; 902 let ResourceCycles = [1,1,1]; 903} 904def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m", 905 "IST_F(16|32)m")>; 906 907def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> { 908 let Latency = 4; 909 let NumMicroOps = 4; 910 let ResourceCycles = [4]; 911} 912def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>; 913 914def BWWriteResGroup46 : SchedWriteRes<[]> { 915 let Latency = 0; 916 let NumMicroOps = 4; 917 let ResourceCycles = []; 918} 919def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>; 920 921def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> { 922 let Latency = 5; 923 let NumMicroOps = 1; 924 let ResourceCycles = [1]; 925} 926def: InstRW<[BWWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 927 928def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> { 929 let Latency = 5; 930 let NumMicroOps = 1; 931 let ResourceCycles = [1]; 932} 933def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm(8|16|32)", 934 "MOVZX(16|32|64)rm(8|16)")>; 935def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm, 936 VMOVDDUPrm, MOVDDUPrm, 937 VMOVSHDUPrm, MOVSHDUPrm, 938 VMOVSLDUPrm, MOVSLDUPrm, 939 VPBROADCASTDrm, 940 VPBROADCASTQrm)>; 941 942def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> { 943 let Latency = 5; 944 let NumMicroOps = 3; 945 let ResourceCycles = [1,2]; 946} 947def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>; 948 949def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> { 950 let Latency = 5; 951 let NumMicroOps = 3; 952 let ResourceCycles = [1,1,1]; 953} 954def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>; 955 956def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> { 957 let Latency = 5; 958 let NumMicroOps = 5; 959 let ResourceCycles = [1,4]; 960} 961def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>; 962 963def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> { 964 let Latency = 5; 965 let NumMicroOps = 5; 966 let ResourceCycles = [1,4]; 967} 968def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>; 969 970def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { 971 let Latency = 5; 972 let NumMicroOps = 6; 973 let ResourceCycles = [1,1,4]; 974} 975def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>; 976 977def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> { 978 let Latency = 6; 979 let NumMicroOps = 1; 980 let ResourceCycles = [1]; 981} 982def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>; 983def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128, 984 VBROADCASTI128, 985 VBROADCASTSDYrm, 986 VBROADCASTSSYrm, 987 VMOVDDUPYrm, 988 VMOVSHDUPYrm, 989 VMOVSLDUPYrm, 990 VPBROADCASTDYrm, 991 VPBROADCASTQYrm)>; 992 993def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> { 994 let Latency = 6; 995 let NumMicroOps = 2; 996 let ResourceCycles = [1,1]; 997} 998def: InstRW<[BWWriteResGroup59], (instrs CVTPS2PDrm, VCVTPS2PDrm, 999 CVTSS2SDrm, VCVTSS2SDrm, 1000 CVTSS2SDrm_Int, VCVTSS2SDrm_Int, 1001 VPSLLVQrm, 1002 VPSRLVQrm)>; 1003 1004def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> { 1005 let Latency = 6; 1006 let NumMicroOps = 2; 1007 let ResourceCycles = [1,1]; 1008} 1009def: InstRW<[BWWriteResGroup60], (instrs VCVTDQ2PDYrr, 1010 VCVTPD2PSYrr, 1011 VCVTPD2DQYrr, 1012 VCVTTPD2DQYrr)>; 1013 1014def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> { 1015 let Latency = 6; 1016 let NumMicroOps = 2; 1017 let ResourceCycles = [1,1]; 1018} 1019def: InstRW<[BWWriteResGroup62], (instrs FARJMP64m)>; 1020def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>; 1021 1022def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> { 1023 let Latency = 6; 1024 let NumMicroOps = 2; 1025 let ResourceCycles = [1,1]; 1026} 1027def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm", 1028 "MOVBE(16|32|64)rm")>; 1029 1030def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> { 1031 let Latency = 6; 1032 let NumMicroOps = 2; 1033 let ResourceCycles = [1,1]; 1034} 1035def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm, 1036 VINSERTI128rm, 1037 VPBLENDDrmi)>; 1038 1039def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> { 1040 let Latency = 6; 1041 let NumMicroOps = 2; 1042 let ResourceCycles = [1,1]; 1043} 1044def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>; 1045def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>; 1046 1047def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> { 1048 let Latency = 6; 1049 let NumMicroOps = 4; 1050 let ResourceCycles = [1,1,1,1]; 1051} 1052def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>; 1053 1054def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { 1055 let Latency = 6; 1056 let NumMicroOps = 4; 1057 let ResourceCycles = [1,1,1,1]; 1058} 1059def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)", 1060 "SHL(8|16|32|64)m(1|i)", 1061 "SHR(8|16|32|64)m(1|i)")>; 1062 1063def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1064 let Latency = 6; 1065 let NumMicroOps = 4; 1066 let ResourceCycles = [1,1,1,1]; 1067} 1068def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm", 1069 "PUSH(16|32|64)rmm")>; 1070 1071def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> { 1072 let Latency = 6; 1073 let NumMicroOps = 6; 1074 let ResourceCycles = [1,5]; 1075} 1076def: InstRW<[BWWriteResGroup71], (instrs STD)>; 1077 1078def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> { 1079 let Latency = 7; 1080 let NumMicroOps = 2; 1081 let ResourceCycles = [1,1]; 1082} 1083def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm, 1084 VPSRLVQYrm)>; 1085 1086def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> { 1087 let Latency = 7; 1088 let NumMicroOps = 2; 1089 let ResourceCycles = [1,1]; 1090} 1091def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>; 1092 1093def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> { 1094 let Latency = 7; 1095 let NumMicroOps = 2; 1096 let ResourceCycles = [1,1]; 1097} 1098def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>; 1099 1100def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> { 1101 let Latency = 7; 1102 let NumMicroOps = 3; 1103 let ResourceCycles = [2,1]; 1104} 1105def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWrm, 1106 MMX_PACKSSWBrm, 1107 MMX_PACKUSWBrm)>; 1108 1109def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> { 1110 let Latency = 7; 1111 let NumMicroOps = 3; 1112 let ResourceCycles = [1,2]; 1113} 1114def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64, 1115 SCASB, SCASL, SCASQ, SCASW)>; 1116 1117def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> { 1118 let Latency = 7; 1119 let NumMicroOps = 3; 1120 let ResourceCycles = [1,1,1]; 1121} 1122def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>; 1123 1124def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1125 let Latency = 7; 1126 let NumMicroOps = 3; 1127 let ResourceCycles = [1,1,1]; 1128} 1129def: InstRW<[BWWriteResGroup84], (instrs LRET64, RET64)>; 1130 1131def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { 1132 let Latency = 7; 1133 let NumMicroOps = 5; 1134 let ResourceCycles = [1,1,1,2]; 1135} 1136def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)", 1137 "ROR(8|16|32|64)m(1|i)")>; 1138 1139def BWWriteResGroup87_1 : SchedWriteRes<[BWPort06]> { 1140 let Latency = 2; 1141 let NumMicroOps = 2; 1142 let ResourceCycles = [2]; 1143} 1144def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1145 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1146 1147def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1148 let Latency = 7; 1149 let NumMicroOps = 5; 1150 let ResourceCycles = [1,1,1,2]; 1151} 1152def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>; 1153 1154def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1155 let Latency = 7; 1156 let NumMicroOps = 5; 1157 let ResourceCycles = [1,1,1,1,1]; 1158} 1159def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>; 1160def: InstRW<[BWWriteResGroup89], (instrs FARCALL64m)>; 1161 1162def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> { 1163 let Latency = 7; 1164 let NumMicroOps = 7; 1165 let ResourceCycles = [2,2,1,2]; 1166} 1167def: InstRW<[BWWriteResGroup90], (instrs LOOP)>; 1168 1169def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> { 1170 let Latency = 8; 1171 let NumMicroOps = 2; 1172 let ResourceCycles = [1,1]; 1173} 1174def: InstRW<[BWWriteResGroup91], (instrs MMX_CVTPI2PSrm, 1175 CVTDQ2PSrm, 1176 VCVTDQ2PSrm)>; 1177def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>; 1178 1179def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> { 1180 let Latency = 8; 1181 let NumMicroOps = 2; 1182 let ResourceCycles = [1,1]; 1183} 1184def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm, 1185 VPMOVSXBQYrm, 1186 VPMOVSXBWYrm, 1187 VPMOVSXDQYrm, 1188 VPMOVSXWDYrm, 1189 VPMOVSXWQYrm, 1190 VPMOVZXWDYrm)>; 1191 1192def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> { 1193 let Latency = 8; 1194 let NumMicroOps = 5; 1195 let ResourceCycles = [1,1,1,2]; 1196} 1197def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)", 1198 "RCR(8|16|32|64)m(1|i)")>; 1199 1200def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1201 let Latency = 8; 1202 let NumMicroOps = 6; 1203 let ResourceCycles = [1,1,1,3]; 1204} 1205def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>; 1206 1207def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1208 let Latency = 8; 1209 let NumMicroOps = 6; 1210 let ResourceCycles = [1,1,1,2,1]; 1211} 1212def : SchedAlias<WriteADCRMW, BWWriteResGroup100>; 1213def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL", 1214 "ROR(8|16|32|64)mCL", 1215 "SAR(8|16|32|64)mCL", 1216 "SHL(8|16|32|64)mCL", 1217 "SHR(8|16|32|64)mCL")>; 1218 1219def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> { 1220 let Latency = 9; 1221 let NumMicroOps = 2; 1222 let ResourceCycles = [1,1]; 1223} 1224def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1225 "ILD_F(16|32|64)m")>; 1226def: InstRW<[BWWriteResGroup101], (instrs VCVTPS2DQYrm, 1227 VCVTTPS2DQYrm)>; 1228 1229def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1230 let Latency = 9; 1231 let NumMicroOps = 3; 1232 let ResourceCycles = [1,1,1]; 1233} 1234def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm", 1235 "(V?)CVT(T?)SD2SI64rm", 1236 "(V?)CVT(T?)SD2SIrm", 1237 "VCVTTSS2SI64rm", 1238 "(V?)CVTTSS2SIrm")>; 1239 1240def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> { 1241 let Latency = 9; 1242 let NumMicroOps = 3; 1243 let ResourceCycles = [1,1,1]; 1244} 1245def: InstRW<[BWWriteResGroup106], (instrs VCVTPS2PDYrm)>; 1246 1247def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { 1248 let Latency = 9; 1249 let NumMicroOps = 3; 1250 let ResourceCycles = [1,1,1]; 1251} 1252def: InstRW<[BWWriteResGroup107], (instrs CVTPD2PSrm, 1253 CVTPD2DQrm, 1254 CVTTPD2DQrm, 1255 MMX_CVTPI2PDrm)>; 1256def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVT(T?)PD2PIrm", 1257 "(V?)CVTDQ2PDrm", 1258 "(V?)CVTSD2SSrm")>; 1259 1260def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> { 1261 let Latency = 9; 1262 let NumMicroOps = 3; 1263 let ResourceCycles = [1,1,1]; 1264} 1265def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm", 1266 "VPBROADCASTW(Y?)rm")>; 1267 1268def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { 1269 let Latency = 9; 1270 let NumMicroOps = 5; 1271 let ResourceCycles = [1,1,3]; 1272} 1273def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; 1274 1275def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { 1276 let Latency = 9; 1277 let NumMicroOps = 5; 1278 let ResourceCycles = [1,2,1,1]; 1279} 1280def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm", 1281 "LSL(16|32|64)rm")>; 1282 1283def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> { 1284 let Latency = 10; 1285 let NumMicroOps = 2; 1286 let ResourceCycles = [1,1]; 1287} 1288def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>; 1289 1290def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> { 1291 let Latency = 10; 1292 let NumMicroOps = 3; 1293 let ResourceCycles = [2,1]; 1294} 1295def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>; 1296 1297def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> { 1298 let Latency = 10; 1299 let NumMicroOps = 4; 1300 let ResourceCycles = [1,1,1,1]; 1301} 1302def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>; 1303 1304def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { 1305 let Latency = 11; 1306 let NumMicroOps = 1; 1307 let ResourceCycles = [1,3]; // Really 2.5 cycle throughput 1308} 1309def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair 1310 1311def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> { 1312 let Latency = 11; 1313 let NumMicroOps = 2; 1314 let ResourceCycles = [1,1]; 1315} 1316def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>; 1317def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>; 1318 1319def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { 1320 let Latency = 11; 1321 let NumMicroOps = 3; 1322 let ResourceCycles = [1,1,1]; 1323} 1324def: InstRW<[BWWriteResGroup128], (instrs VCVTDQ2PDYrm)>; 1325 1326def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { 1327 let Latency = 11; 1328 let NumMicroOps = 7; 1329 let ResourceCycles = [2,2,3]; 1330} 1331def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL", 1332 "RCR(16|32|64)rCL")>; 1333 1334def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { 1335 let Latency = 11; 1336 let NumMicroOps = 9; 1337 let ResourceCycles = [1,4,1,3]; 1338} 1339def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>; 1340 1341def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> { 1342 let Latency = 11; 1343 let NumMicroOps = 11; 1344 let ResourceCycles = [2,9]; 1345} 1346def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>; 1347def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>; 1348 1349def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> { 1350 let Latency = 12; 1351 let NumMicroOps = 3; 1352 let ResourceCycles = [2,1]; 1353} 1354def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1355 1356def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { 1357 let Latency = 14; 1358 let NumMicroOps = 1; 1359 let ResourceCycles = [1,4]; 1360} 1361def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair 1362 1363def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1364 let Latency = 14; 1365 let NumMicroOps = 3; 1366 let ResourceCycles = [1,1,1]; 1367} 1368def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>; 1369 1370def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { 1371 let Latency = 14; 1372 let NumMicroOps = 8; 1373 let ResourceCycles = [2,2,1,3]; 1374} 1375def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>; 1376 1377def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { 1378 let Latency = 14; 1379 let NumMicroOps = 10; 1380 let ResourceCycles = [2,3,1,4]; 1381} 1382def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>; 1383 1384def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> { 1385 let Latency = 14; 1386 let NumMicroOps = 12; 1387 let ResourceCycles = [2,1,4,5]; 1388} 1389def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>; 1390 1391def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> { 1392 let Latency = 15; 1393 let NumMicroOps = 1; 1394 let ResourceCycles = [1]; 1395} 1396def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1397 1398def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1399 let Latency = 15; 1400 let NumMicroOps = 10; 1401 let ResourceCycles = [1,1,1,4,1,2]; 1402} 1403def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>; 1404 1405def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { 1406 let Latency = 16; 1407 let NumMicroOps = 2; 1408 let ResourceCycles = [1,1,5]; 1409} 1410def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair 1411 1412def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1413 let Latency = 16; 1414 let NumMicroOps = 14; 1415 let ResourceCycles = [1,1,1,4,2,5]; 1416} 1417def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>; 1418 1419def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> { 1420 let Latency = 8; 1421 let NumMicroOps = 20; 1422 let ResourceCycles = [1,1]; 1423} 1424def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>; 1425 1426def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> { 1427 let Latency = 18; 1428 let NumMicroOps = 8; 1429 let ResourceCycles = [1,1,1,5]; 1430} 1431def: InstRW<[BWWriteResGroup159], (instrs CPUID)>; 1432def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>; 1433 1434def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1435 let Latency = 18; 1436 let NumMicroOps = 11; 1437 let ResourceCycles = [2,1,1,3,1,3]; 1438} 1439def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>; 1440 1441def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { 1442 let Latency = 19; 1443 let NumMicroOps = 2; 1444 let ResourceCycles = [1,1,8]; 1445} 1446def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair 1447 1448def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> { 1449 let Latency = 20; 1450 let NumMicroOps = 1; 1451 let ResourceCycles = [1]; 1452} 1453def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1454 1455def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1456 let Latency = 20; 1457 let NumMicroOps = 8; 1458 let ResourceCycles = [1,1,1,1,1,1,2]; 1459} 1460def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>; 1461 1462def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> { 1463 let Latency = 21; 1464 let NumMicroOps = 2; 1465 let ResourceCycles = [1,1]; 1466} 1467def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>; 1468 1469def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1470 let Latency = 21; 1471 let NumMicroOps = 19; 1472 let ResourceCycles = [2,1,4,1,1,4,6]; 1473} 1474def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>; 1475 1476def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1477 let Latency = 22; 1478 let NumMicroOps = 18; 1479 let ResourceCycles = [1,1,16]; 1480} 1481def: InstRW<[BWWriteResGroup172], (instrs POPF64)>; 1482 1483def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1484 let Latency = 23; 1485 let NumMicroOps = 19; 1486 let ResourceCycles = [3,1,15]; 1487} 1488def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>; 1489 1490def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1491 let Latency = 24; 1492 let NumMicroOps = 3; 1493 let ResourceCycles = [1,1,1]; 1494} 1495def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>; 1496 1497def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> { 1498 let Latency = 26; 1499 let NumMicroOps = 2; 1500 let ResourceCycles = [1,1]; 1501} 1502def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>; 1503 1504def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1505 let Latency = 29; 1506 let NumMicroOps = 3; 1507 let ResourceCycles = [1,1,1]; 1508} 1509def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>; 1510 1511def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1512 let Latency = 17; 1513 let NumMicroOps = 7; 1514 let ResourceCycles = [1,3,2,1]; 1515} 1516def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERDPDrm, VPGATHERDQrm, 1517 VGATHERQPDrm, VPGATHERQQrm)>; 1518 1519def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1520 let Latency = 18; 1521 let NumMicroOps = 9; 1522 let ResourceCycles = [1,3,4,1]; 1523} 1524def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 1525 VGATHERQPDYrm, VPGATHERQQYrm)>; 1526 1527def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1528 let Latency = 19; 1529 let NumMicroOps = 9; 1530 let ResourceCycles = [1,5,2,1]; 1531} 1532def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSrm, VPGATHERQDrm)>; 1533 1534def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1535 let Latency = 19; 1536 let NumMicroOps = 10; 1537 let ResourceCycles = [1,4,4,1]; 1538} 1539def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPSrm, VPGATHERDDrm, 1540 VGATHERQPSYrm, VPGATHERQDYrm)>; 1541 1542def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1543 let Latency = 21; 1544 let NumMicroOps = 14; 1545 let ResourceCycles = [1,4,8,1]; 1546} 1547def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 1548 1549def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1550 let Latency = 29; 1551 let NumMicroOps = 27; 1552 let ResourceCycles = [1,5,1,1,19]; 1553} 1554def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>; 1555 1556def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1557 let Latency = 30; 1558 let NumMicroOps = 28; 1559 let ResourceCycles = [1,6,1,1,19]; 1560} 1561def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>; 1562def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 1563 1564def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> { 1565 let Latency = 34; 1566 let NumMicroOps = 23; 1567 let ResourceCycles = [1,5,3,4,10]; 1568} 1569def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri", 1570 "IN(8|16|32)rr")>; 1571 1572def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1573 let Latency = 35; 1574 let NumMicroOps = 23; 1575 let ResourceCycles = [1,5,2,1,4,10]; 1576} 1577def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir", 1578 "OUT(8|16|32)rr")>; 1579 1580def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> { 1581 let Latency = 42; 1582 let NumMicroOps = 22; 1583 let ResourceCycles = [2,20]; 1584} 1585def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>; 1586 1587def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> { 1588 let Latency = 60; 1589 let NumMicroOps = 64; 1590 let ResourceCycles = [2,2,8,1,10,2,39]; 1591} 1592def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>; 1593 1594def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { 1595 let Latency = 63; 1596 let NumMicroOps = 88; 1597 let ResourceCycles = [4,4,31,1,2,1,45]; 1598} 1599def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>; 1600 1601def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { 1602 let Latency = 63; 1603 let NumMicroOps = 90; 1604 let ResourceCycles = [4,2,33,1,2,1,47]; 1605} 1606def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>; 1607 1608def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> { 1609 let Latency = 75; 1610 let NumMicroOps = 15; 1611 let ResourceCycles = [6,3,6]; 1612} 1613def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>; 1614 1615def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> { 1616 let Latency = 115; 1617 let NumMicroOps = 100; 1618 let ResourceCycles = [9,9,11,8,1,11,21,30]; 1619} 1620def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>; 1621 1622def: InstRW<[WriteZero], (instrs CLC)>; 1623 1624 1625// Instruction variants handled by the renamer. These might not need execution 1626// ports in certain conditions. 1627// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1628// section "Haswell and Broadwell Pipeline" > "Register allocation and 1629// renaming". 1630// These can be investigated with llvm-exegesis, e.g. 1631// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1632// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1633 1634def BWWriteZeroLatency : SchedWriteRes<[]> { 1635 let Latency = 0; 1636} 1637 1638def BWWriteZeroIdiom : SchedWriteVariant<[ 1639 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1640 SchedVar<NoSchedPred, [WriteALU]> 1641]>; 1642def : InstRW<[BWWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1643 XOR32rr, XOR64rr)>; 1644 1645def BWWriteFZeroIdiom : SchedWriteVariant<[ 1646 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1647 SchedVar<NoSchedPred, [WriteFLogic]> 1648]>; 1649def : InstRW<[BWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1650 VXORPDrr)>; 1651 1652def BWWriteFZeroIdiomY : SchedWriteVariant<[ 1653 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1654 SchedVar<NoSchedPred, [WriteFLogicY]> 1655]>; 1656def : InstRW<[BWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1657 1658def BWWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1659 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1660 SchedVar<NoSchedPred, [WriteVecLogicX]> 1661]>; 1662def : InstRW<[BWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1663 1664def BWWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1665 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1666 SchedVar<NoSchedPred, [WriteVecLogicY]> 1667]>; 1668def : InstRW<[BWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1669 1670def BWWriteVZeroIdiomALUX : SchedWriteVariant<[ 1671 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1672 SchedVar<NoSchedPred, [WriteVecALUX]> 1673]>; 1674def : InstRW<[BWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1675 PSUBDrr, VPSUBDrr, 1676 PSUBQrr, VPSUBQrr, 1677 PSUBWrr, VPSUBWrr, 1678 PCMPGTBrr, VPCMPGTBrr, 1679 PCMPGTDrr, VPCMPGTDrr, 1680 PCMPGTWrr, VPCMPGTWrr)>; 1681 1682def BWWriteVZeroIdiomALUY : SchedWriteVariant<[ 1683 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1684 SchedVar<NoSchedPred, [WriteVecALUY]> 1685]>; 1686def : InstRW<[BWWriteVZeroIdiomALUY], (instrs VPSUBBYrr, 1687 VPSUBDYrr, 1688 VPSUBQYrr, 1689 VPSUBWYrr, 1690 VPCMPGTBYrr, 1691 VPCMPGTDYrr, 1692 VPCMPGTWYrr)>; 1693 1694def BWWritePCMPGTQ : SchedWriteRes<[BWPort0]> { 1695 let Latency = 5; 1696 let NumMicroOps = 1; 1697 let ResourceCycles = [1]; 1698} 1699 1700def BWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1701 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1702 SchedVar<NoSchedPred, [BWWritePCMPGTQ]> 1703]>; 1704def : InstRW<[BWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1705 VPCMPGTQYrr)>; 1706 1707 1708// CMOVs that use both Z and C flag require an extra uop. 1709def BWWriteCMOVA_CMOVBErr : SchedWriteRes<[BWPort06,BWPort0156]> { 1710 let Latency = 2; 1711 let ResourceCycles = [1,1]; 1712 let NumMicroOps = 2; 1713} 1714 1715def BWWriteCMOVA_CMOVBErm : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { 1716 let Latency = 7; 1717 let ResourceCycles = [1,1,1]; 1718 let NumMicroOps = 3; 1719} 1720 1721def BWCMOVA_CMOVBErr : SchedWriteVariant<[ 1722 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [BWWriteCMOVA_CMOVBErr]>, 1723 SchedVar<NoSchedPred, [WriteCMOV]> 1724]>; 1725 1726def BWCMOVA_CMOVBErm : SchedWriteVariant<[ 1727 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [BWWriteCMOVA_CMOVBErm]>, 1728 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1729]>; 1730 1731def : InstRW<[BWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1732def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1733 1734// SETCCs that use both Z and C flag require an extra uop. 1735def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> { 1736 let Latency = 2; 1737 let ResourceCycles = [1,1]; 1738 let NumMicroOps = 2; 1739} 1740 1741def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { 1742 let Latency = 3; 1743 let ResourceCycles = [1,1,1,1]; 1744 let NumMicroOps = 4; 1745} 1746 1747def BWSETA_SETBErr : SchedWriteVariant<[ 1748 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [BWWriteSETA_SETBEr]>, 1749 SchedVar<NoSchedPred, [WriteSETCC]> 1750]>; 1751 1752def BWSETA_SETBErm : SchedWriteVariant<[ 1753 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [BWWriteSETA_SETBEm]>, 1754 SchedVar<NoSchedPred, [WriteSETCCStore]> 1755]>; 1756 1757def : InstRW<[BWSETA_SETBErr], (instrs SETCCr)>; 1758def : InstRW<[BWSETA_SETBErm], (instrs SETCCm)>; 1759 1760/////////////////////////////////////////////////////////////////////////////// 1761// Dependency breaking instructions. 1762/////////////////////////////////////////////////////////////////////////////// 1763 1764def : IsZeroIdiomFunction<[ 1765 // GPR Zero-idioms. 1766 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>, 1767 1768 // SSE Zero-idioms. 1769 DepBreakingClass<[ 1770 // fp variants. 1771 XORPSrr, XORPDrr, 1772 1773 // int variants. 1774 PXORrr, 1775 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr, 1776 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr 1777 ], ZeroIdiomPredicate>, 1778 1779 // AVX Zero-idioms. 1780 DepBreakingClass<[ 1781 // xmm fp variants. 1782 VXORPSrr, VXORPDrr, 1783 1784 // xmm int variants. 1785 VPXORrr, 1786 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr, 1787 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr, 1788 1789 // ymm variants. 1790 VXORPSYrr, VXORPDYrr, VPXORYrr, 1791 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr, 1792 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr 1793 ], ZeroIdiomPredicate>, 1794]>; 1795 1796} // SchedModel 1797