1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Broadwell to support instruction 10// scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def BroadwellModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and BW can decode 4 16 // instructions per cycle. 17 let IssueWidth = 4; 18 let MicroOpBufferSize = 192; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 16; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = BroadwellModel in { 31 32// Broadwell can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def BWPort0 : ProcResource<1>; 41def BWPort1 : ProcResource<1>; 42def BWPort2 : ProcResource<1>; 43def BWPort3 : ProcResource<1>; 44def BWPort4 : ProcResource<1>; 45def BWPort5 : ProcResource<1>; 46def BWPort6 : ProcResource<1>; 47def BWPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>; 51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>; 52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>; 53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>; 54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>; 55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>; 56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>; 57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>; 58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>; 59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>; 60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>; 61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>; 62 63// 60 Entry Unified Scheduler 64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4, 65 BWPort5, BWPort6, BWPort7]> { 66 let BufferSize=60; 67} 68 69// Integer division issued on port 0. 70def BWDivider : ProcResource<1>; 71// FP division and sqrt on port 0. 72def BWFPDivider : ProcResource<1>; 73 74// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 75// cycles after the memory operand. 76def : ReadAdvance<ReadAfterLd, 5>; 77 78// Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available 79// until 5/5/6 cycles after the memory operand. 80def : ReadAdvance<ReadAfterVecLd, 5>; 81def : ReadAdvance<ReadAfterVecXLd, 5>; 82def : ReadAdvance<ReadAfterVecYLd, 6>; 83 84def : ReadAdvance<ReadInt2Fpu, 0>; 85 86// Many SchedWrites are defined in pairs with and without a folded load. 87// Instructions with folded loads are usually micro-fused, so they only appear 88// as two micro-ops when queued in the reservation station. 89// This multiclass defines the resource usage for variants with and without 90// folded loads. 91multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW, 92 list<ProcResourceKind> ExePorts, 93 int Lat, list<int> Res = [1], int UOps = 1, 94 int LoadLat = 5> { 95 // Register variant is using a single cycle on ExePort. 96 def : WriteRes<SchedRW, ExePorts> { 97 let Latency = Lat; 98 let ResourceCycles = Res; 99 let NumMicroOps = UOps; 100 } 101 102 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 103 // the latency (default = 5). 104 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> { 105 let Latency = !add(Lat, LoadLat); 106 let ResourceCycles = !listconcat([1], Res); 107 let NumMicroOps = !add(UOps, 1); 108 } 109} 110 111// A folded store needs a cycle on port 4 for the store data, and an extra port 112// 2/3/7 cycle to recompute the address. 113def : WriteRes<WriteRMW, [BWPort237,BWPort4]>; 114 115// Arithmetic. 116defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op. 117defm : BWWriteResPair<WriteADC, [BWPort06], 1>; // Integer ALU + flags op. 118 119// Integer multiplication. 120defm : BWWriteResPair<WriteIMul8, [BWPort1], 3>; 121defm : BWWriteResPair<WriteIMul16, [BWPort1,BWPort06,BWPort0156], 4, [1,1,2], 4>; 122defm : X86WriteRes<WriteIMul16Imm, [BWPort1,BWPort0156], 4, [1,1], 2>; 123defm : X86WriteRes<WriteIMul16ImmLd, [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>; 124defm : BWWriteResPair<WriteIMul16Reg, [BWPort1], 3>; 125defm : BWWriteResPair<WriteIMul32, [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>; 126defm : BWWriteResPair<WriteIMul32Imm, [BWPort1], 3>; 127defm : BWWriteResPair<WriteIMul32Reg, [BWPort1], 3>; 128defm : BWWriteResPair<WriteIMul64, [BWPort1,BWPort5], 4, [1,1], 2>; 129defm : BWWriteResPair<WriteIMul64Imm, [BWPort1], 3>; 130defm : BWWriteResPair<WriteIMul64Reg, [BWPort1], 3>; 131def : WriteRes<WriteIMulH, []> { let Latency = 3; } 132 133// TODO: Why isn't the BWDivider used consistently? 134defm : X86WriteRes<WriteDiv8, [BWPort0, BWDivider], 25, [1, 10], 1>; 135defm : X86WriteRes<WriteDiv16, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 136defm : X86WriteRes<WriteDiv32, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 137defm : X86WriteRes<WriteDiv64, [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>; 138defm : X86WriteRes<WriteDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 139defm : X86WriteRes<WriteDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 140defm : X86WriteRes<WriteDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 141defm : X86WriteRes<WriteDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>; 142 143defm : X86WriteRes<WriteIDiv8, [BWPort0, BWDivider], 25, [1,10], 1>; 144defm : X86WriteRes<WriteIDiv16, [BWPort0, BWDivider], 25, [1,10], 1>; 145defm : X86WriteRes<WriteIDiv32, [BWPort0, BWDivider], 25, [1,10], 1>; 146defm : X86WriteRes<WriteIDiv64, [BWPort0, BWDivider], 25, [1,10], 1>; 147defm : X86WriteRes<WriteIDiv8Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 148defm : X86WriteRes<WriteIDiv16Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 149defm : X86WriteRes<WriteIDiv32Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 150defm : X86WriteRes<WriteIDiv64Ld, [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>; 151 152defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>; 153defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>; 154defm : X86WriteRes<WriteBSWAP32, [BWPort15], 1, [1], 1>; 155defm : X86WriteRes<WriteBSWAP64, [BWPort06, BWPort15], 2, [1, 1], 2>; 156defm : X86WriteRes<WriteXCHG, [BWPort0156], 2, [3], 3>; 157 158defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>; 159 160def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads. 161 162defm : BWWriteResPair<WriteCMOV, [BWPort06], 1>; // Conditional move. 163defm : X86WriteRes<WriteFCMOV, [BWPort1], 3, [1], 1>; // x87 conditional move. 164 165def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc. 166def : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> { 167 let Latency = 2; 168 let NumMicroOps = 3; 169} 170 171defm : X86WriteRes<WriteLAHFSAHF, [BWPort06], 1, [1], 1>; 172defm : X86WriteRes<WriteBitTest, [BWPort06], 1, [1], 1>; // Bit Test instrs 173defm : X86WriteRes<WriteBitTestImmLd, [BWPort06,BWPort23], 6, [1,1], 2>; 174defm : X86WriteRes<WriteBitTestRegLd, [BWPort0156,BWPort23], 6, [1,1], 2>; 175defm : X86WriteRes<WriteBitTestSet, [BWPort06], 1, [1], 1>; // Bit Test + Set instrs 176defm : X86WriteRes<WriteBitTestSetImmLd, [BWPort06,BWPort23], 5, [1,1], 3>; 177defm : X86WriteRes<WriteBitTestSetRegLd, [BWPort0156,BWPort23], 5, [1,1], 2>; 178 179// Bit counts. 180defm : BWWriteResPair<WriteBSF, [BWPort1], 3>; 181defm : BWWriteResPair<WriteBSR, [BWPort1], 3>; 182defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>; 183defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>; 184defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>; 185 186// Integer shifts and rotates. 187defm : BWWriteResPair<WriteShift, [BWPort06], 1>; 188defm : BWWriteResPair<WriteShiftCL, [BWPort06,BWPort0156], 3, [2,1], 3>; 189defm : BWWriteResPair<WriteRotate, [BWPort06], 1, [1], 1>; 190defm : BWWriteResPair<WriteRotateCL, [BWPort06,BWPort0156], 3, [2,1], 3>; 191 192// SHLD/SHRD. 193defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>; 194defm : X86WriteRes<WriteSHDrrcl,[BWPort1,BWPort06,BWPort0156], 6, [1, 1, 2], 4>; 195defm : X86WriteRes<WriteSHDmri, [BWPort1,BWPort23,BWPort237,BWPort0156], 9, [1, 1, 1, 1], 4>; 196defm : X86WriteRes<WriteSHDmrcl,[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156], 11, [1, 1, 1, 1, 2], 6>; 197 198// BMI1 BEXTR/BLS, BMI2 BZHI 199defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>; 200defm : BWWriteResPair<WriteBLS, [BWPort15], 1>; 201defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>; 202 203// Loads, stores, and moves, not folded with other operations. 204defm : X86WriteRes<WriteLoad, [BWPort23], 5, [1], 1>; 205defm : X86WriteRes<WriteStore, [BWPort237, BWPort4], 1, [1,1], 1>; 206defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>; 207defm : X86WriteRes<WriteMove, [BWPort0156], 1, [1], 1>; 208 209// Idioms that clear a register, like xorps %xmm0, %xmm0. 210// These can often bypass execution ports completely. 211def : WriteRes<WriteZero, []>; 212 213// Treat misc copies as a move. 214def : InstRW<[WriteMove], (instrs COPY)>; 215 216// Branches don't produce values, so they have no latency, but they still 217// consume resources. Indirect branches can fold loads. 218defm : BWWriteResPair<WriteJump, [BWPort06], 1>; 219 220// Floating point. This covers both scalar and vector operations. 221defm : X86WriteRes<WriteFLD0, [BWPort01], 1, [1], 1>; 222defm : X86WriteRes<WriteFLD1, [BWPort01], 1, [2], 2>; 223defm : X86WriteRes<WriteFLDC, [BWPort01], 1, [2], 2>; 224defm : X86WriteRes<WriteFLoad, [BWPort23], 5, [1], 1>; 225defm : X86WriteRes<WriteFLoadX, [BWPort23], 5, [1], 1>; 226defm : X86WriteRes<WriteFLoadY, [BWPort23], 6, [1], 1>; 227defm : X86WriteRes<WriteFMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>; 228defm : X86WriteRes<WriteFMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>; 229defm : X86WriteRes<WriteFStore, [BWPort237,BWPort4], 1, [1,1], 2>; 230defm : X86WriteRes<WriteFStoreX, [BWPort237,BWPort4], 1, [1,1], 2>; 231defm : X86WriteRes<WriteFStoreY, [BWPort237,BWPort4], 1, [1,1], 2>; 232defm : X86WriteRes<WriteFStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>; 233defm : X86WriteRes<WriteFStoreNTX, [BWPort237,BWPort4], 1, [1,1], 2>; 234defm : X86WriteRes<WriteFStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>; 235 236defm : X86WriteRes<WriteFMaskedStore32, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 237defm : X86WriteRes<WriteFMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 238defm : X86WriteRes<WriteFMaskedStore64, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 239defm : X86WriteRes<WriteFMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 240 241defm : X86WriteRes<WriteFMove, [BWPort5], 1, [1], 1>; 242defm : X86WriteRes<WriteFMoveX, [BWPort5], 1, [1], 1>; 243defm : X86WriteRes<WriteFMoveY, [BWPort5], 1, [1], 1>; 244 245defm : BWWriteResPair<WriteFAdd, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub. 246defm : BWWriteResPair<WriteFAddX, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub (XMM). 247defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM). 248defm : X86WriteResPairUnsupported<WriteFAddZ>; 249defm : BWWriteResPair<WriteFAdd64, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub. 250defm : BWWriteResPair<WriteFAdd64X, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub (XMM). 251defm : BWWriteResPair<WriteFAdd64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM). 252defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 253 254defm : BWWriteResPair<WriteFCmp, [BWPort1], 3, [1], 1, 5>; // Floating point compare. 255defm : BWWriteResPair<WriteFCmpX, [BWPort1], 3, [1], 1, 5>; // Floating point compare (XMM). 256defm : BWWriteResPair<WriteFCmpY, [BWPort1], 3, [1], 1, 6>; // Floating point compare (YMM/ZMM). 257defm : X86WriteResPairUnsupported<WriteFCmpZ>; 258defm : BWWriteResPair<WriteFCmp64, [BWPort1], 3, [1], 1, 5>; // Floating point double compare. 259defm : BWWriteResPair<WriteFCmp64X, [BWPort1], 3, [1], 1, 5>; // Floating point double compare (XMM). 260defm : BWWriteResPair<WriteFCmp64Y, [BWPort1], 3, [1], 1, 6>; // Floating point double compare (YMM/ZMM). 261defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 262 263defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags (X87). 264defm : BWWriteResPair<WriteFComX, [BWPort1], 3>; // Floating point compare to flags (SSE). 265 266defm : BWWriteResPair<WriteFMul, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication. 267defm : BWWriteResPair<WriteFMulX, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM). 268defm : BWWriteResPair<WriteFMulY, [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM). 269defm : X86WriteResPairUnsupported<WriteFMulZ>; 270defm : BWWriteResPair<WriteFMul64, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication. 271defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM). 272defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM). 273defm : X86WriteResPairUnsupported<WriteFMul64Z>; 274 275//defm : BWWriteResPair<WriteFDiv, [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division. 276defm : BWWriteResPair<WriteFDivX, [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM). 277defm : BWWriteResPair<WriteFDivY, [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM). 278defm : X86WriteResPairUnsupported<WriteFDivZ>; 279//defm : BWWriteResPair<WriteFDiv64, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division. 280defm : BWWriteResPair<WriteFDiv64X, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM). 281defm : BWWriteResPair<WriteFDiv64Y, [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM). 282defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 283 284defm : X86WriteRes<WriteFSqrt, [BWPort0,BWFPDivider], 11, [1,4], 1>; // Floating point square root. 285defm : X86WriteRes<WriteFSqrtLd, [BWPort0,BWPort23,BWFPDivider], 16, [1,1,7], 2>; 286defm : BWWriteResPair<WriteFSqrtX, [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM). 287defm : BWWriteResPair<WriteFSqrtY, [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM). 288defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 289defm : X86WriteRes<WriteFSqrt64, [BWPort0,BWFPDivider], 16, [1,8], 1>; // Floating point double square root. 290defm : X86WriteRes<WriteFSqrt64Ld, [BWPort0,BWPort23,BWFPDivider], 21, [1,1,14], 2>; 291defm : BWWriteResPair<WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM). 292defm : BWWriteResPair<WriteFSqrt64Y, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM). 293defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 294defm : BWWriteResPair<WriteFSqrt80, [BWPort0,BWFPDivider], 23, [1,9]>; // Floating point long double square root. 295 296defm : BWWriteResPair<WriteFRcp, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate. 297defm : BWWriteResPair<WriteFRcpX, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate (XMM). 298defm : BWWriteResPair<WriteFRcpY, [BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal estimate (YMM/ZMM). 299defm : X86WriteResPairUnsupported<WriteFRcpZ>; 300 301defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate. 302defm : BWWriteResPair<WriteFRsqrtX,[BWPort0], 5, [1], 1, 5>; // Floating point reciprocal square root estimate (XMM). 303defm : BWWriteResPair<WriteFRsqrtY,[BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal square root estimate (YMM/ZMM). 304defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 305 306defm : BWWriteResPair<WriteFMA, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add. 307defm : BWWriteResPair<WriteFMAX, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM). 308defm : BWWriteResPair<WriteFMAY, [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM). 309defm : X86WriteResPairUnsupported<WriteFMAZ>; 310defm : BWWriteResPair<WriteDPPD, [BWPort0,BWPort1,BWPort5], 9, [1,1,1], 3, 5>; // Floating point double dot product. 311defm : BWWriteResPair<WriteDPPS, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 5>; // Floating point single dot product. 312defm : BWWriteResPair<WriteDPPSY, [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 6>; // Floating point single dot product (YMM). 313defm : X86WriteResPairUnsupported<WriteDPPSZ>; 314defm : BWWriteResPair<WriteFSign, [BWPort5], 1>; // Floating point fabs/fchs. 315defm : X86WriteRes<WriteFRnd, [BWPort23], 6, [1], 1>; // Floating point rounding. 316defm : X86WriteRes<WriteFRndY, [BWPort23], 6, [1], 1>; // Floating point rounding (YMM/ZMM). 317defm : X86WriteResPairUnsupported<WriteFRndZ>; 318defm : X86WriteRes<WriteFRndLd, [BWPort1,BWPort23], 11, [2,1], 3>; 319defm : X86WriteRes<WriteFRndYLd, [BWPort1,BWPort23], 12, [2,1], 3>; 320defm : BWWriteResPair<WriteFLogic, [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals. 321defm : BWWriteResPair<WriteFLogicY, [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM). 322defm : X86WriteResPairUnsupported<WriteFLogicZ>; 323defm : BWWriteResPair<WriteFTest, [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions. 324defm : BWWriteResPair<WriteFTestY, [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM). 325defm : X86WriteResPairUnsupported<WriteFTestZ>; 326defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles. 327defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM). 328defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 329defm : BWWriteResPair<WriteFVarShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles. 330defm : BWWriteResPair<WriteFVarShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles. 331defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 332defm : BWWriteResPair<WriteFBlend, [BWPort015], 1, [1], 1, 5>; // Floating point vector blends. 333defm : BWWriteResPair<WriteFBlendY, [BWPort015], 1, [1], 1, 6>; // Floating point vector blends. 334defm : X86WriteResPairUnsupported<WriteFBlendZ>; 335defm : BWWriteResPair<WriteFVarBlend, [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends. 336defm : BWWriteResPair<WriteFVarBlendY, [BWPort5], 2, [2], 2, 6>; // Fp vector variable blends. 337defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 338 339// FMA Scheduling helper class. 340// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 341 342// Vector integer operations. 343defm : X86WriteRes<WriteVecLoad, [BWPort23], 5, [1], 1>; 344defm : X86WriteRes<WriteVecLoadX, [BWPort23], 5, [1], 1>; 345defm : X86WriteRes<WriteVecLoadY, [BWPort23], 6, [1], 1>; 346defm : X86WriteRes<WriteVecLoadNT, [BWPort23], 5, [1], 1>; 347defm : X86WriteRes<WriteVecLoadNTY, [BWPort23], 6, [1], 1>; 348defm : X86WriteRes<WriteVecMaskedLoad, [BWPort23,BWPort5], 7, [1,2], 3>; 349defm : X86WriteRes<WriteVecMaskedLoadY, [BWPort23,BWPort5], 8, [1,2], 3>; 350defm : X86WriteRes<WriteVecStore, [BWPort237,BWPort4], 1, [1,1], 2>; 351defm : X86WriteRes<WriteVecStoreX, [BWPort237,BWPort4], 1, [1,1], 2>; 352defm : X86WriteRes<WriteVecStoreY, [BWPort237,BWPort4], 1, [1,1], 2>; 353defm : X86WriteRes<WriteVecStoreNT, [BWPort237,BWPort4], 1, [1,1], 2>; 354defm : X86WriteRes<WriteVecStoreNTY, [BWPort237,BWPort4], 1, [1,1], 2>; 355defm : X86WriteRes<WriteVecMaskedStore32, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 356defm : X86WriteRes<WriteVecMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 357defm : X86WriteRes<WriteVecMaskedStore64, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 358defm : X86WriteRes<WriteVecMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>; 359defm : X86WriteRes<WriteVecMove, [BWPort015], 1, [1], 1>; 360defm : X86WriteRes<WriteVecMoveX, [BWPort015], 1, [1], 1>; 361defm : X86WriteRes<WriteVecMoveY, [BWPort015], 1, [1], 1>; 362defm : X86WriteRes<WriteVecMoveToGpr, [BWPort0], 1, [1], 1>; 363defm : X86WriteRes<WriteVecMoveFromGpr, [BWPort5], 1, [1], 1>; 364 365defm : X86WriteRes<WriteEMMS, [BWPort01,BWPort15,BWPort015,BWPort0156], 31, [8,1,21,1], 31>; 366 367defm : BWWriteResPair<WriteVecALU, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 368defm : BWWriteResPair<WriteVecALUX, [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 369defm : BWWriteResPair<WriteVecALUY, [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM). 370defm : X86WriteResPairUnsupported<WriteVecALUZ>; 371defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor. 372defm : BWWriteResPair<WriteVecLogicX,[BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor. 373defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM). 374defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 375defm : BWWriteResPair<WriteVecTest, [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions. 376defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM). 377defm : X86WriteResPairUnsupported<WriteVecTestZ>; 378defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply. 379defm : BWWriteResPair<WriteVecIMulX, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply. 380defm : BWWriteResPair<WriteVecIMulY, [BWPort0], 5, [1], 1, 6>; // Vector integer multiply. 381defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 382defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // Vector PMULLD. 383defm : BWWriteResPair<WritePMULLDY, [BWPort0], 10, [2], 2, 6>; // Vector PMULLD (YMM/ZMM). 384defm : X86WriteResPairUnsupported<WritePMULLDZ>; 385defm : BWWriteResPair<WriteShuffle, [BWPort5], 1, [1], 1, 5>; // Vector shuffles. 386defm : BWWriteResPair<WriteShuffleX, [BWPort5], 1, [1], 1, 5>; // Vector shuffles. 387defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM). 388defm : X86WriteResPairUnsupported<WriteShuffleZ>; 389defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles. 390defm : BWWriteResPair<WriteVarShuffleX,[BWPort5], 1, [1], 1, 5>; // Vector variable shuffles. 391defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM). 392defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 393defm : BWWriteResPair<WriteBlend, [BWPort5], 1, [1], 1, 5>; // Vector blends. 394defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM). 395defm : X86WriteResPairUnsupported<WriteBlendZ>; 396defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2], 2, 5>; // Vector variable blends. 397defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM). 398defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 399defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD. 400defm : BWWriteResPair<WriteMPSADY, [BWPort0, BWPort5], 7, [1, 2], 3, 6>; // Vector MPSAD. 401defm : X86WriteResPairUnsupported<WriteMPSADZ>; 402defm : BWWriteResPair<WritePSADBW, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW. 403defm : BWWriteResPair<WritePSADBWX, [BWPort0], 5, [1], 1, 5>; // Vector PSADBW. 404defm : BWWriteResPair<WritePSADBWY, [BWPort0], 5, [1], 1, 6>; // Vector PSADBW (YMM/ZMM). 405defm : X86WriteResPairUnsupported<WritePSADBWZ>; 406defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS. 407 408// Vector integer shifts. 409defm : BWWriteResPair<WriteVecShift, [BWPort0], 1, [1], 1, 5>; 410defm : BWWriteResPair<WriteVecShiftX, [BWPort0,BWPort5], 2, [1,1], 2, 5>; 411defm : X86WriteRes<WriteVecShiftY, [BWPort0,BWPort5], 4, [1,1], 2>; 412defm : X86WriteRes<WriteVecShiftYLd, [BWPort0,BWPort23], 7, [1,1], 2>; 413defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 414 415defm : BWWriteResPair<WriteVecShiftImm, [BWPort0], 1, [1], 1, 5>; 416defm : BWWriteResPair<WriteVecShiftImmX, [BWPort0], 1, [1], 1, 5>; // Vector integer immediate shifts (XMM). 417defm : BWWriteResPair<WriteVecShiftImmY, [BWPort0], 1, [1], 1, 6>; // Vector integer immediate shifts (YMM/ZMM). 418defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 419defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts. 420defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM). 421defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 422 423// Vector insert/extract operations. 424def : WriteRes<WriteVecInsert, [BWPort5]> { 425 let Latency = 2; 426 let NumMicroOps = 2; 427 let ResourceCycles = [2]; 428} 429def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> { 430 let Latency = 6; 431 let NumMicroOps = 2; 432} 433 434def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> { 435 let Latency = 2; 436 let NumMicroOps = 2; 437} 438def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> { 439 let Latency = 2; 440 let NumMicroOps = 3; 441} 442 443// Conversion between integer and float. 444defm : BWWriteResPair<WriteCvtSS2I, [BWPort1], 3>; 445defm : BWWriteResPair<WriteCvtPS2I, [BWPort1], 3>; 446defm : BWWriteResPair<WriteCvtPS2IY, [BWPort1], 3>; 447defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 448defm : BWWriteResPair<WriteCvtSD2I, [BWPort1], 3>; 449defm : BWWriteResPair<WriteCvtPD2I, [BWPort1], 3>; 450defm : BWWriteResPair<WriteCvtPD2IY, [BWPort1], 3>; 451defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 452 453defm : BWWriteResPair<WriteCvtI2SS, [BWPort1], 4>; 454defm : BWWriteResPair<WriteCvtI2PS, [BWPort1], 4>; 455defm : BWWriteResPair<WriteCvtI2PSY, [BWPort1], 4>; 456defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 457defm : BWWriteResPair<WriteCvtI2SD, [BWPort1], 4>; 458defm : BWWriteResPair<WriteCvtI2PD, [BWPort1], 4>; 459defm : BWWriteResPair<WriteCvtI2PDY, [BWPort1], 4>; 460defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 461 462defm : BWWriteResPair<WriteCvtSS2SD, [BWPort1], 3>; 463defm : BWWriteResPair<WriteCvtPS2PD, [BWPort1], 3>; 464defm : BWWriteResPair<WriteCvtPS2PDY, [BWPort1], 3>; 465defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 466defm : BWWriteResPair<WriteCvtSD2SS, [BWPort1], 3>; 467defm : BWWriteResPair<WriteCvtPD2PS, [BWPort1], 3>; 468defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1], 3>; 469defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 470 471defm : X86WriteRes<WriteCvtPH2PS, [BWPort0,BWPort5], 2, [1,1], 2>; 472defm : X86WriteRes<WriteCvtPH2PSY, [BWPort0,BWPort5], 2, [1,1], 2>; 473defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 474defm : X86WriteRes<WriteCvtPH2PSLd, [BWPort0,BWPort23], 6, [1,1], 2>; 475defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort0,BWPort23], 6, [1,1], 2>; 476defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 477 478defm : X86WriteRes<WriteCvtPS2PH, [BWPort1,BWPort5], 4, [1,1], 2>; 479defm : X86WriteRes<WriteCvtPS2PHY, [BWPort1,BWPort5], 6, [1,1], 2>; 480defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 481defm : X86WriteRes<WriteCvtPS2PHSt, [BWPort1,BWPort4,BWPort237], 5, [1,1,1], 3>; 482defm : X86WriteRes<WriteCvtPS2PHYSt, [BWPort1,BWPort4,BWPort237], 7, [1,1,1], 3>; 483defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 484 485// Strings instructions. 486 487// Packed Compare Implicit Length Strings, Return Mask 488def : WriteRes<WritePCmpIStrM, [BWPort0]> { 489 let Latency = 11; 490 let NumMicroOps = 3; 491 let ResourceCycles = [3]; 492} 493def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> { 494 let Latency = 16; 495 let NumMicroOps = 4; 496 let ResourceCycles = [3,1]; 497} 498 499// Packed Compare Explicit Length Strings, Return Mask 500def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> { 501 let Latency = 19; 502 let NumMicroOps = 9; 503 let ResourceCycles = [4,3,1,1]; 504} 505def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> { 506 let Latency = 24; 507 let NumMicroOps = 10; 508 let ResourceCycles = [4,3,1,1,1]; 509} 510 511// Packed Compare Implicit Length Strings, Return Index 512def : WriteRes<WritePCmpIStrI, [BWPort0]> { 513 let Latency = 11; 514 let NumMicroOps = 3; 515 let ResourceCycles = [3]; 516} 517def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> { 518 let Latency = 16; 519 let NumMicroOps = 4; 520 let ResourceCycles = [3,1]; 521} 522 523// Packed Compare Explicit Length Strings, Return Index 524def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> { 525 let Latency = 18; 526 let NumMicroOps = 8; 527 let ResourceCycles = [4,3,1]; 528} 529def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> { 530 let Latency = 23; 531 let NumMicroOps = 9; 532 let ResourceCycles = [4,3,1,1]; 533} 534 535// MOVMSK Instructions. 536def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; } 537def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; } 538def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; } 539def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; } 540 541// AES instructions. 542def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption. 543 let Latency = 7; 544 let NumMicroOps = 1; 545 let ResourceCycles = [1]; 546} 547def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> { 548 let Latency = 12; 549 let NumMicroOps = 2; 550 let ResourceCycles = [1,1]; 551} 552 553def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn. 554 let Latency = 14; 555 let NumMicroOps = 2; 556 let ResourceCycles = [2]; 557} 558def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> { 559 let Latency = 19; 560 let NumMicroOps = 3; 561 let ResourceCycles = [2,1]; 562} 563 564def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation. 565 let Latency = 29; 566 let NumMicroOps = 11; 567 let ResourceCycles = [2,7,2]; 568} 569def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> { 570 let Latency = 33; 571 let NumMicroOps = 11; 572 let ResourceCycles = [2,7,1,1]; 573} 574 575// Carry-less multiplication instructions. 576defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>; 577 578// Catch-all for expensive system instructions. 579def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 580 581// AVX2. 582defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles. 583defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles. 584defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector shuffles. 585defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>; // 256-bit width vector variable shuffles. 586 587// Old microcoded instructions that nobody use. 588def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 589 590// Fence instructions. 591def : WriteRes<WriteFence, [BWPort23, BWPort4]>; 592 593// Load/store MXCSR. 594def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 595def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 596 597// Nop, not very useful expect it provides a model for nops! 598def : WriteRes<WriteNop, []>; 599 600//////////////////////////////////////////////////////////////////////////////// 601// Horizontal add/sub instructions. 602//////////////////////////////////////////////////////////////////////////////// 603 604defm : BWWriteResPair<WriteFHAdd, [BWPort1,BWPort5], 5, [1,2], 3, 5>; 605defm : BWWriteResPair<WriteFHAddY, [BWPort1,BWPort5], 5, [1,2], 3, 6>; 606defm : BWWriteResPair<WritePHAdd, [BWPort5,BWPort15], 3, [2,1], 3, 5>; 607defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>; 608defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>; 609 610// Remaining instrs. 611 612def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> { 613 let Latency = 1; 614 let NumMicroOps = 1; 615 let ResourceCycles = [1]; 616} 617def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr", 618 "VPSRLVQ(Y?)rr")>; 619 620def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> { 621 let Latency = 1; 622 let NumMicroOps = 1; 623 let ResourceCycles = [1]; 624} 625def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r", 626 "UCOM_F(P?)r")>; 627 628def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> { 629 let Latency = 1; 630 let NumMicroOps = 1; 631 let ResourceCycles = [1]; 632} 633def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>; 634 635def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> { 636 let Latency = 1; 637 let NumMicroOps = 1; 638 let ResourceCycles = [1]; 639} 640def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>; 641 642def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> { 643 let Latency = 1; 644 let NumMicroOps = 1; 645 let ResourceCycles = [1]; 646} 647def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>; 648 649def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> { 650 let Latency = 1; 651 let NumMicroOps = 1; 652 let ResourceCycles = [1]; 653} 654def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>; 655 656def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> { 657 let Latency = 1; 658 let NumMicroOps = 1; 659 let ResourceCycles = [1]; 660} 661def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>; 662 663def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> { 664 let Latency = 1; 665 let NumMicroOps = 1; 666 let ResourceCycles = [1]; 667} 668def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>; 669 670def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> { 671 let Latency = 1; 672 let NumMicroOps = 1; 673 let ResourceCycles = [1]; 674} 675def: InstRW<[BWWriteResGroup9], (instrs SGDT64m, 676 SIDT64m, 677 SMSW16m, 678 STRm, 679 SYSCALL)>; 680 681def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> { 682 let Latency = 1; 683 let NumMicroOps = 2; 684 let ResourceCycles = [1,1]; 685} 686def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>; 687def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>; 688 689def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> { 690 let Latency = 2; 691 let NumMicroOps = 2; 692 let ResourceCycles = [2]; 693} 694def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>; 695 696def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> { 697 let Latency = 2; 698 let NumMicroOps = 2; 699 let ResourceCycles = [2]; 700} 701def: InstRW<[BWWriteResGroup14], (instrs LFENCE, 702 MFENCE, 703 WAIT, 704 XGETBV)>; 705 706def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> { 707 let Latency = 2; 708 let NumMicroOps = 2; 709 let ResourceCycles = [1,1]; 710} 711def: InstRW<[BWWriteResGroup15], (instregex "(V?)CVTPS2PDrr", 712 "(V?)CVTSS2SDrr")>; 713 714def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> { 715 let Latency = 2; 716 let NumMicroOps = 2; 717 let ResourceCycles = [1,1]; 718} 719def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>; 720 721def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> { 722 let Latency = 2; 723 let NumMicroOps = 2; 724 let ResourceCycles = [1,1]; 725} 726def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>; 727 728def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> { 729 let Latency = 2; 730 let NumMicroOps = 2; 731 let ResourceCycles = [1,1]; 732} 733def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>; 734 735def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> { 736 let Latency = 2; 737 let NumMicroOps = 2; 738 let ResourceCycles = [1,1]; 739} 740def: InstRW<[BWWriteResGroup20], (instrs CWD, 741 JCXZ, JECXZ, JRCXZ, 742 ADC8i8, SBB8i8, 743 ADC16i16, SBB16i16, 744 ADC32i32, SBB32i32, 745 ADC64i32, SBB64i32)>; 746 747def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> { 748 let Latency = 2; 749 let NumMicroOps = 3; 750 let ResourceCycles = [1,1,1]; 751} 752def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>; 753 754def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> { 755 let Latency = 2; 756 let NumMicroOps = 3; 757 let ResourceCycles = [1,1,1]; 758} 759def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>; 760 761def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { 762 let Latency = 2; 763 let NumMicroOps = 3; 764 let ResourceCycles = [1,1,1]; 765} 766def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 767 STOSB, STOSL, STOSQ, STOSW)>; 768def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>; 769 770def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> { 771 let Latency = 3; 772 let NumMicroOps = 1; 773 let ResourceCycles = [1]; 774} 775def: InstRW<[BWWriteResGroup27], (instrs MMX_CVTPI2PSirr)>; 776def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr", 777 "(V?)CVTDQ2PS(Y?)rr")>; 778 779def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> { 780 let Latency = 3; 781 let NumMicroOps = 1; 782 let ResourceCycles = [1]; 783} 784def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr, 785 VPBROADCASTWrr)>; 786 787def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> { 788 let Latency = 3; 789 let NumMicroOps = 3; 790 let ResourceCycles = [2,1]; 791} 792def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWirr, 793 MMX_PACKSSWBirr, 794 MMX_PACKUSWBirr)>; 795 796def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> { 797 let Latency = 3; 798 let NumMicroOps = 3; 799 let ResourceCycles = [1,2]; 800} 801def: InstRW<[BWWriteResGroup34], (instregex "CLD")>; 802 803def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> { 804 let Latency = 3; 805 let NumMicroOps = 3; 806 let ResourceCycles = [1,2]; 807} 808def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r(1|i)", 809 "RCR(8|16|32|64)r(1|i)")>; 810 811def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> { 812 let Latency = 3; 813 let NumMicroOps = 4; 814 let ResourceCycles = [1,1,1,1]; 815} 816def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>; 817 818def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { 819 let Latency = 3; 820 let NumMicroOps = 4; 821 let ResourceCycles = [1,1,1,1]; 822} 823def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>; 824 825def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> { 826 let Latency = 4; 827 let NumMicroOps = 2; 828 let ResourceCycles = [1,1]; 829} 830def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr", 831 "(V?)CVT(T?)SD2SIrr", 832 "(V?)CVT(T?)SS2SI64rr", 833 "(V?)CVT(T?)SS2SIrr")>; 834 835def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> { 836 let Latency = 4; 837 let NumMicroOps = 2; 838 let ResourceCycles = [1,1]; 839} 840def: InstRW<[BWWriteResGroup40], (instrs VCVTPS2PDYrr)>; 841 842def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> { 843 let Latency = 4; 844 let NumMicroOps = 2; 845 let ResourceCycles = [1,1]; 846} 847def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>; 848 849def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> { 850 let Latency = 4; 851 let NumMicroOps = 2; 852 let ResourceCycles = [1,1]; 853} 854def: InstRW<[BWWriteResGroup42], (instrs MMX_CVTPI2PDirr)>; 855def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PD2PIirr", 856 "MMX_CVT(T?)PS2PIirr", 857 "(V?)CVTDQ2PDrr", 858 "(V?)CVTPD2PSrr", 859 "(V?)CVTSD2SSrr", 860 "(V?)CVTSI642SDrr", 861 "(V?)CVTSI2SDrr", 862 "(V?)CVTSI2SSrr", 863 "(V?)CVT(T?)PD2DQrr")>; 864 865def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> { 866 let Latency = 4; 867 let NumMicroOps = 3; 868 let ResourceCycles = [1,1,1]; 869} 870def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>; 871 872def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> { 873 let Latency = 4; 874 let NumMicroOps = 3; 875 let ResourceCycles = [1,1,1]; 876} 877def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m", 878 "IST_F(16|32)m")>; 879 880def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> { 881 let Latency = 4; 882 let NumMicroOps = 4; 883 let ResourceCycles = [4]; 884} 885def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>; 886 887def BWWriteResGroup46 : SchedWriteRes<[]> { 888 let Latency = 0; 889 let NumMicroOps = 4; 890 let ResourceCycles = []; 891} 892def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>; 893 894def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> { 895 let Latency = 5; 896 let NumMicroOps = 1; 897 let ResourceCycles = [1]; 898} 899def: InstRW<[BWWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 900 901def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> { 902 let Latency = 5; 903 let NumMicroOps = 1; 904 let ResourceCycles = [1]; 905} 906def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm(8|16|32)", 907 "MOVZX(16|32|64)rm(8|16)")>; 908def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm, 909 VMOVDDUPrm, MOVDDUPrm, 910 VMOVSHDUPrm, MOVSHDUPrm, 911 VMOVSLDUPrm, MOVSLDUPrm, 912 VPBROADCASTDrm, 913 VPBROADCASTQrm)>; 914 915def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> { 916 let Latency = 5; 917 let NumMicroOps = 3; 918 let ResourceCycles = [1,2]; 919} 920def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>; 921 922def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> { 923 let Latency = 5; 924 let NumMicroOps = 3; 925 let ResourceCycles = [1,1,1]; 926} 927def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>; 928 929def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> { 930 let Latency = 5; 931 let NumMicroOps = 5; 932 let ResourceCycles = [1,4]; 933} 934def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>; 935 936def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> { 937 let Latency = 5; 938 let NumMicroOps = 5; 939 let ResourceCycles = [1,4]; 940} 941def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>; 942 943def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { 944 let Latency = 5; 945 let NumMicroOps = 6; 946 let ResourceCycles = [1,1,4]; 947} 948def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>; 949 950def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> { 951 let Latency = 6; 952 let NumMicroOps = 1; 953 let ResourceCycles = [1]; 954} 955def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>; 956def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128, 957 VBROADCASTI128, 958 VBROADCASTSDYrm, 959 VBROADCASTSSYrm, 960 VMOVDDUPYrm, 961 VMOVSHDUPYrm, 962 VMOVSLDUPYrm, 963 VPBROADCASTDYrm, 964 VPBROADCASTQYrm)>; 965 966def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> { 967 let Latency = 6; 968 let NumMicroOps = 2; 969 let ResourceCycles = [1,1]; 970} 971def: InstRW<[BWWriteResGroup59], (instrs CVTPS2PDrm, VCVTPS2PDrm, 972 CVTSS2SDrm, VCVTSS2SDrm, 973 CVTSS2SDrm_Int, VCVTSS2SDrm_Int, 974 VPSLLVQrm, 975 VPSRLVQrm)>; 976 977def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> { 978 let Latency = 6; 979 let NumMicroOps = 2; 980 let ResourceCycles = [1,1]; 981} 982def: InstRW<[BWWriteResGroup60], (instrs VCVTDQ2PDYrr, 983 VCVTPD2PSYrr, 984 VCVTPD2DQYrr, 985 VCVTTPD2DQYrr)>; 986 987def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> { 988 let Latency = 6; 989 let NumMicroOps = 2; 990 let ResourceCycles = [1,1]; 991} 992def: InstRW<[BWWriteResGroup62], (instrs FARJMP64m)>; 993def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>; 994 995def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> { 996 let Latency = 6; 997 let NumMicroOps = 2; 998 let ResourceCycles = [1,1]; 999} 1000def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm", 1001 "MOVBE(16|32|64)rm")>; 1002 1003def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> { 1004 let Latency = 6; 1005 let NumMicroOps = 2; 1006 let ResourceCycles = [1,1]; 1007} 1008def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm, 1009 VINSERTI128rm, 1010 VPBLENDDrmi)>; 1011 1012def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> { 1013 let Latency = 6; 1014 let NumMicroOps = 2; 1015 let ResourceCycles = [1,1]; 1016} 1017def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>; 1018def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>; 1019 1020def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> { 1021 let Latency = 6; 1022 let NumMicroOps = 4; 1023 let ResourceCycles = [1,1,1,1]; 1024} 1025def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>; 1026 1027def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { 1028 let Latency = 6; 1029 let NumMicroOps = 4; 1030 let ResourceCycles = [1,1,1,1]; 1031} 1032def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)", 1033 "SHL(8|16|32|64)m(1|i)", 1034 "SHR(8|16|32|64)m(1|i)")>; 1035 1036def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1037 let Latency = 6; 1038 let NumMicroOps = 4; 1039 let ResourceCycles = [1,1,1,1]; 1040} 1041def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm", 1042 "PUSH(16|32|64)rmm")>; 1043 1044def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> { 1045 let Latency = 6; 1046 let NumMicroOps = 6; 1047 let ResourceCycles = [1,5]; 1048} 1049def: InstRW<[BWWriteResGroup71], (instrs STD)>; 1050 1051def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> { 1052 let Latency = 7; 1053 let NumMicroOps = 2; 1054 let ResourceCycles = [1,1]; 1055} 1056def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm, 1057 VPSRLVQYrm)>; 1058 1059def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> { 1060 let Latency = 7; 1061 let NumMicroOps = 2; 1062 let ResourceCycles = [1,1]; 1063} 1064def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>; 1065 1066def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> { 1067 let Latency = 7; 1068 let NumMicroOps = 2; 1069 let ResourceCycles = [1,1]; 1070} 1071def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>; 1072 1073def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> { 1074 let Latency = 7; 1075 let NumMicroOps = 3; 1076 let ResourceCycles = [2,1]; 1077} 1078def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWirm, 1079 MMX_PACKSSWBirm, 1080 MMX_PACKUSWBirm)>; 1081 1082def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> { 1083 let Latency = 7; 1084 let NumMicroOps = 3; 1085 let ResourceCycles = [1,2]; 1086} 1087def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64, 1088 SCASB, SCASL, SCASQ, SCASW)>; 1089 1090def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> { 1091 let Latency = 7; 1092 let NumMicroOps = 3; 1093 let ResourceCycles = [1,1,1]; 1094} 1095def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>; 1096 1097def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1098 let Latency = 7; 1099 let NumMicroOps = 3; 1100 let ResourceCycles = [1,1,1]; 1101} 1102def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>; 1103 1104def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { 1105 let Latency = 7; 1106 let NumMicroOps = 5; 1107 let ResourceCycles = [1,1,1,2]; 1108} 1109def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)", 1110 "ROR(8|16|32|64)m(1|i)")>; 1111 1112def BWWriteResGroup87_1 : SchedWriteRes<[BWPort06]> { 1113 let Latency = 2; 1114 let NumMicroOps = 2; 1115 let ResourceCycles = [2]; 1116} 1117def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1118 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1119 1120def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1121 let Latency = 7; 1122 let NumMicroOps = 5; 1123 let ResourceCycles = [1,1,1,2]; 1124} 1125def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>; 1126 1127def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1128 let Latency = 7; 1129 let NumMicroOps = 5; 1130 let ResourceCycles = [1,1,1,1,1]; 1131} 1132def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>; 1133def: InstRW<[BWWriteResGroup89], (instrs FARCALL64m)>; 1134 1135def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> { 1136 let Latency = 7; 1137 let NumMicroOps = 7; 1138 let ResourceCycles = [2,2,1,2]; 1139} 1140def: InstRW<[BWWriteResGroup90], (instrs LOOP)>; 1141 1142def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> { 1143 let Latency = 8; 1144 let NumMicroOps = 2; 1145 let ResourceCycles = [1,1]; 1146} 1147def: InstRW<[BWWriteResGroup91], (instrs MMX_CVTPI2PSirm, 1148 CVTDQ2PSrm, 1149 VCVTDQ2PSrm)>; 1150def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>; 1151 1152def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> { 1153 let Latency = 8; 1154 let NumMicroOps = 2; 1155 let ResourceCycles = [1,1]; 1156} 1157def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm, 1158 VPMOVSXBQYrm, 1159 VPMOVSXBWYrm, 1160 VPMOVSXDQYrm, 1161 VPMOVSXWDYrm, 1162 VPMOVSXWQYrm, 1163 VPMOVZXWDYrm)>; 1164 1165def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> { 1166 let Latency = 8; 1167 let NumMicroOps = 5; 1168 let ResourceCycles = [1,1,1,2]; 1169} 1170def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)", 1171 "RCR(8|16|32|64)m(1|i)")>; 1172 1173def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> { 1174 let Latency = 8; 1175 let NumMicroOps = 6; 1176 let ResourceCycles = [1,1,1,3]; 1177} 1178def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>; 1179 1180def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1181 let Latency = 8; 1182 let NumMicroOps = 6; 1183 let ResourceCycles = [1,1,1,2,1]; 1184} 1185def : SchedAlias<WriteADCRMW, BWWriteResGroup100>; 1186def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL", 1187 "ROR(8|16|32|64)mCL", 1188 "SAR(8|16|32|64)mCL", 1189 "SHL(8|16|32|64)mCL", 1190 "SHR(8|16|32|64)mCL")>; 1191 1192def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> { 1193 let Latency = 9; 1194 let NumMicroOps = 2; 1195 let ResourceCycles = [1,1]; 1196} 1197def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1198 "ILD_F(16|32|64)m")>; 1199def: InstRW<[BWWriteResGroup101], (instrs VCVTPS2DQYrm, 1200 VCVTTPS2DQYrm)>; 1201 1202def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1203 let Latency = 9; 1204 let NumMicroOps = 3; 1205 let ResourceCycles = [1,1,1]; 1206} 1207def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm", 1208 "(V?)CVT(T?)SD2SI64rm", 1209 "(V?)CVT(T?)SD2SIrm", 1210 "VCVTTSS2SI64rm", 1211 "(V?)CVTTSS2SIrm")>; 1212 1213def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> { 1214 let Latency = 9; 1215 let NumMicroOps = 3; 1216 let ResourceCycles = [1,1,1]; 1217} 1218def: InstRW<[BWWriteResGroup106], (instrs VCVTPS2PDYrm)>; 1219 1220def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { 1221 let Latency = 9; 1222 let NumMicroOps = 3; 1223 let ResourceCycles = [1,1,1]; 1224} 1225def: InstRW<[BWWriteResGroup107], (instrs CVTPD2PSrm, 1226 CVTPD2DQrm, 1227 CVTTPD2DQrm, 1228 MMX_CVTPI2PDirm)>; 1229def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVT(T?)PD2PIirm", 1230 "(V?)CVTDQ2PDrm", 1231 "(V?)CVTSD2SSrm")>; 1232 1233def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> { 1234 let Latency = 9; 1235 let NumMicroOps = 3; 1236 let ResourceCycles = [1,1,1]; 1237} 1238def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm", 1239 "VPBROADCASTW(Y?)rm")>; 1240 1241def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { 1242 let Latency = 9; 1243 let NumMicroOps = 5; 1244 let ResourceCycles = [1,1,3]; 1245} 1246def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; 1247 1248def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { 1249 let Latency = 9; 1250 let NumMicroOps = 5; 1251 let ResourceCycles = [1,2,1,1]; 1252} 1253def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm", 1254 "LSL(16|32|64)rm")>; 1255 1256def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> { 1257 let Latency = 10; 1258 let NumMicroOps = 2; 1259 let ResourceCycles = [1,1]; 1260} 1261def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>; 1262 1263def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> { 1264 let Latency = 10; 1265 let NumMicroOps = 3; 1266 let ResourceCycles = [2,1]; 1267} 1268def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>; 1269 1270def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> { 1271 let Latency = 10; 1272 let NumMicroOps = 4; 1273 let ResourceCycles = [1,1,1,1]; 1274} 1275def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>; 1276 1277def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { 1278 let Latency = 11; 1279 let NumMicroOps = 1; 1280 let ResourceCycles = [1,3]; // Really 2.5 cycle throughput 1281} 1282def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair 1283 1284def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> { 1285 let Latency = 11; 1286 let NumMicroOps = 2; 1287 let ResourceCycles = [1,1]; 1288} 1289def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>; 1290def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>; 1291 1292def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { 1293 let Latency = 11; 1294 let NumMicroOps = 3; 1295 let ResourceCycles = [1,1,1]; 1296} 1297def: InstRW<[BWWriteResGroup128], (instrs VCVTDQ2PDYrm)>; 1298 1299def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { 1300 let Latency = 11; 1301 let NumMicroOps = 7; 1302 let ResourceCycles = [2,2,3]; 1303} 1304def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL", 1305 "RCR(16|32|64)rCL")>; 1306 1307def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { 1308 let Latency = 11; 1309 let NumMicroOps = 9; 1310 let ResourceCycles = [1,4,1,3]; 1311} 1312def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>; 1313 1314def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> { 1315 let Latency = 11; 1316 let NumMicroOps = 11; 1317 let ResourceCycles = [2,9]; 1318} 1319def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>; 1320def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>; 1321 1322def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> { 1323 let Latency = 12; 1324 let NumMicroOps = 3; 1325 let ResourceCycles = [2,1]; 1326} 1327def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1328 1329def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> { 1330 let Latency = 14; 1331 let NumMicroOps = 1; 1332 let ResourceCycles = [1,4]; 1333} 1334def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair 1335 1336def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1337 let Latency = 14; 1338 let NumMicroOps = 3; 1339 let ResourceCycles = [1,1,1]; 1340} 1341def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>; 1342 1343def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { 1344 let Latency = 14; 1345 let NumMicroOps = 8; 1346 let ResourceCycles = [2,2,1,3]; 1347} 1348def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>; 1349 1350def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> { 1351 let Latency = 14; 1352 let NumMicroOps = 10; 1353 let ResourceCycles = [2,3,1,4]; 1354} 1355def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>; 1356 1357def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> { 1358 let Latency = 14; 1359 let NumMicroOps = 12; 1360 let ResourceCycles = [2,1,4,5]; 1361} 1362def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>; 1363 1364def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> { 1365 let Latency = 15; 1366 let NumMicroOps = 1; 1367 let ResourceCycles = [1]; 1368} 1369def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1370 1371def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1372 let Latency = 15; 1373 let NumMicroOps = 10; 1374 let ResourceCycles = [1,1,1,4,1,2]; 1375} 1376def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>; 1377 1378def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { 1379 let Latency = 16; 1380 let NumMicroOps = 2; 1381 let ResourceCycles = [1,1,5]; 1382} 1383def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair 1384 1385def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1386 let Latency = 16; 1387 let NumMicroOps = 14; 1388 let ResourceCycles = [1,1,1,4,2,5]; 1389} 1390def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>; 1391 1392def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> { 1393 let Latency = 8; 1394 let NumMicroOps = 20; 1395 let ResourceCycles = [1,1]; 1396} 1397def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>; 1398 1399def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> { 1400 let Latency = 18; 1401 let NumMicroOps = 8; 1402 let ResourceCycles = [1,1,1,5]; 1403} 1404def: InstRW<[BWWriteResGroup159], (instrs CPUID)>; 1405def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>; 1406 1407def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> { 1408 let Latency = 18; 1409 let NumMicroOps = 11; 1410 let ResourceCycles = [2,1,1,3,1,3]; 1411} 1412def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>; 1413 1414def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> { 1415 let Latency = 19; 1416 let NumMicroOps = 2; 1417 let ResourceCycles = [1,1,8]; 1418} 1419def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair 1420 1421def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> { 1422 let Latency = 20; 1423 let NumMicroOps = 1; 1424 let ResourceCycles = [1]; 1425} 1426def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1427 1428def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1429 let Latency = 20; 1430 let NumMicroOps = 8; 1431 let ResourceCycles = [1,1,1,1,1,1,2]; 1432} 1433def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>; 1434 1435def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> { 1436 let Latency = 21; 1437 let NumMicroOps = 2; 1438 let ResourceCycles = [1,1]; 1439} 1440def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>; 1441 1442def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1443 let Latency = 21; 1444 let NumMicroOps = 19; 1445 let ResourceCycles = [2,1,4,1,1,4,6]; 1446} 1447def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>; 1448 1449def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1450 let Latency = 22; 1451 let NumMicroOps = 18; 1452 let ResourceCycles = [1,1,16]; 1453} 1454def: InstRW<[BWWriteResGroup172], (instrs POPF64)>; 1455 1456def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { 1457 let Latency = 23; 1458 let NumMicroOps = 19; 1459 let ResourceCycles = [3,1,15]; 1460} 1461def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>; 1462 1463def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1464 let Latency = 24; 1465 let NumMicroOps = 3; 1466 let ResourceCycles = [1,1,1]; 1467} 1468def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>; 1469 1470def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> { 1471 let Latency = 26; 1472 let NumMicroOps = 2; 1473 let ResourceCycles = [1,1]; 1474} 1475def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>; 1476 1477def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { 1478 let Latency = 29; 1479 let NumMicroOps = 3; 1480 let ResourceCycles = [1,1,1]; 1481} 1482def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>; 1483 1484def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1485 let Latency = 17; 1486 let NumMicroOps = 7; 1487 let ResourceCycles = [1,3,2,1]; 1488} 1489def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERDPDrm, VPGATHERDQrm, 1490 VGATHERQPDrm, VPGATHERQQrm)>; 1491 1492def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1493 let Latency = 18; 1494 let NumMicroOps = 9; 1495 let ResourceCycles = [1,3,4,1]; 1496} 1497def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 1498 VGATHERQPDYrm, VPGATHERQQYrm)>; 1499 1500def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1501 let Latency = 19; 1502 let NumMicroOps = 9; 1503 let ResourceCycles = [1,5,2,1]; 1504} 1505def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSrm, VPGATHERQDrm)>; 1506 1507def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1508 let Latency = 19; 1509 let NumMicroOps = 10; 1510 let ResourceCycles = [1,4,4,1]; 1511} 1512def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPSrm, VPGATHERDDrm, 1513 VGATHERQPSYrm, VPGATHERQDYrm)>; 1514 1515def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { 1516 let Latency = 21; 1517 let NumMicroOps = 14; 1518 let ResourceCycles = [1,4,8,1]; 1519} 1520def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 1521 1522def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1523 let Latency = 29; 1524 let NumMicroOps = 27; 1525 let ResourceCycles = [1,5,1,1,19]; 1526} 1527def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>; 1528 1529def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> { 1530 let Latency = 30; 1531 let NumMicroOps = 28; 1532 let ResourceCycles = [1,6,1,1,19]; 1533} 1534def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>; 1535def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 1536 1537def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> { 1538 let Latency = 34; 1539 let NumMicroOps = 23; 1540 let ResourceCycles = [1,5,3,4,10]; 1541} 1542def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri", 1543 "IN(8|16|32)rr")>; 1544 1545def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> { 1546 let Latency = 35; 1547 let NumMicroOps = 23; 1548 let ResourceCycles = [1,5,2,1,4,10]; 1549} 1550def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir", 1551 "OUT(8|16|32)rr")>; 1552 1553def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> { 1554 let Latency = 42; 1555 let NumMicroOps = 22; 1556 let ResourceCycles = [2,20]; 1557} 1558def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>; 1559 1560def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> { 1561 let Latency = 60; 1562 let NumMicroOps = 64; 1563 let ResourceCycles = [2,2,8,1,10,2,39]; 1564} 1565def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>; 1566 1567def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { 1568 let Latency = 63; 1569 let NumMicroOps = 88; 1570 let ResourceCycles = [4,4,31,1,2,1,45]; 1571} 1572def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>; 1573 1574def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { 1575 let Latency = 63; 1576 let NumMicroOps = 90; 1577 let ResourceCycles = [4,2,33,1,2,1,47]; 1578} 1579def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>; 1580 1581def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> { 1582 let Latency = 75; 1583 let NumMicroOps = 15; 1584 let ResourceCycles = [6,3,6]; 1585} 1586def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>; 1587 1588def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> { 1589 let Latency = 115; 1590 let NumMicroOps = 100; 1591 let ResourceCycles = [9,9,11,8,1,11,21,30]; 1592} 1593def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>; 1594 1595def: InstRW<[WriteZero], (instrs CLC)>; 1596 1597 1598// Instruction variants handled by the renamer. These might not need execution 1599// ports in certain conditions. 1600// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1601// section "Haswell and Broadwell Pipeline" > "Register allocation and 1602// renaming". 1603// These can be investigated with llvm-exegesis, e.g. 1604// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1605// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1606 1607def BWWriteZeroLatency : SchedWriteRes<[]> { 1608 let Latency = 0; 1609} 1610 1611def BWWriteZeroIdiom : SchedWriteVariant<[ 1612 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1613 SchedVar<NoSchedPred, [WriteALU]> 1614]>; 1615def : InstRW<[BWWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1616 XOR32rr, XOR64rr)>; 1617 1618def BWWriteFZeroIdiom : SchedWriteVariant<[ 1619 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1620 SchedVar<NoSchedPred, [WriteFLogic]> 1621]>; 1622def : InstRW<[BWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1623 VXORPDrr)>; 1624 1625def BWWriteFZeroIdiomY : SchedWriteVariant<[ 1626 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1627 SchedVar<NoSchedPred, [WriteFLogicY]> 1628]>; 1629def : InstRW<[BWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1630 1631def BWWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1632 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1633 SchedVar<NoSchedPred, [WriteVecLogicX]> 1634]>; 1635def : InstRW<[BWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1636 1637def BWWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1638 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1639 SchedVar<NoSchedPred, [WriteVecLogicY]> 1640]>; 1641def : InstRW<[BWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1642 1643def BWWriteVZeroIdiomALUX : SchedWriteVariant<[ 1644 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1645 SchedVar<NoSchedPred, [WriteVecALUX]> 1646]>; 1647def : InstRW<[BWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1648 PSUBDrr, VPSUBDrr, 1649 PSUBQrr, VPSUBQrr, 1650 PSUBWrr, VPSUBWrr, 1651 PCMPGTBrr, VPCMPGTBrr, 1652 PCMPGTDrr, VPCMPGTDrr, 1653 PCMPGTWrr, VPCMPGTWrr)>; 1654 1655def BWWriteVZeroIdiomALUY : SchedWriteVariant<[ 1656 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1657 SchedVar<NoSchedPred, [WriteVecALUY]> 1658]>; 1659def : InstRW<[BWWriteVZeroIdiomALUY], (instrs VPSUBBYrr, 1660 VPSUBDYrr, 1661 VPSUBQYrr, 1662 VPSUBWYrr, 1663 VPCMPGTBYrr, 1664 VPCMPGTDYrr, 1665 VPCMPGTWYrr)>; 1666 1667def BWWritePCMPGTQ : SchedWriteRes<[BWPort0]> { 1668 let Latency = 5; 1669 let NumMicroOps = 1; 1670 let ResourceCycles = [1]; 1671} 1672 1673def BWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1674 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>, 1675 SchedVar<NoSchedPred, [BWWritePCMPGTQ]> 1676]>; 1677def : InstRW<[BWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1678 VPCMPGTQYrr)>; 1679 1680 1681// CMOVs that use both Z and C flag require an extra uop. 1682def BWWriteCMOVA_CMOVBErr : SchedWriteRes<[BWPort06,BWPort0156]> { 1683 let Latency = 2; 1684 let ResourceCycles = [1,1]; 1685 let NumMicroOps = 2; 1686} 1687 1688def BWWriteCMOVA_CMOVBErm : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { 1689 let Latency = 7; 1690 let ResourceCycles = [1,1,1]; 1691 let NumMicroOps = 3; 1692} 1693 1694def BWCMOVA_CMOVBErr : SchedWriteVariant<[ 1695 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [BWWriteCMOVA_CMOVBErr]>, 1696 SchedVar<NoSchedPred, [WriteCMOV]> 1697]>; 1698 1699def BWCMOVA_CMOVBErm : SchedWriteVariant<[ 1700 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [BWWriteCMOVA_CMOVBErm]>, 1701 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1702]>; 1703 1704def : InstRW<[BWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1705def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1706 1707// SETCCs that use both Z and C flag require an extra uop. 1708def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> { 1709 let Latency = 2; 1710 let ResourceCycles = [1,1]; 1711 let NumMicroOps = 2; 1712} 1713 1714def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> { 1715 let Latency = 3; 1716 let ResourceCycles = [1,1,1,1]; 1717 let NumMicroOps = 4; 1718} 1719 1720def BWSETA_SETBErr : SchedWriteVariant<[ 1721 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [BWWriteSETA_SETBEr]>, 1722 SchedVar<NoSchedPred, [WriteSETCC]> 1723]>; 1724 1725def BWSETA_SETBErm : SchedWriteVariant<[ 1726 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [BWWriteSETA_SETBEm]>, 1727 SchedVar<NoSchedPred, [WriteSETCCStore]> 1728]>; 1729 1730def : InstRW<[BWSETA_SETBErr], (instrs SETCCr)>; 1731def : InstRW<[BWSETA_SETBErm], (instrs SETCCm)>; 1732 1733} // SchedModel 1734