1//===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the available hardware counters for various subtargets. 10// 11//===----------------------------------------------------------------------===// 12 13def UnhaltedCoreCyclesPfmCounter : PfmCounter<"unhalted_core_cycles">; 14def UopsIssuedPfmCounter : PfmCounter<"uops_issued:any">; 15 16// No default counters on X86. 17def DefaultPfmCounters : ProcPfmCounters {} 18def : PfmCountersDefaultBinding<DefaultPfmCounters>; 19 20// Intel X86 Counters. 21def PentiumPfmCounters : ProcPfmCounters { 22 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 23 let UopsCounter = PfmCounter<"uops_retired">; 24} 25def : PfmCountersBinding<"pentiumpro", PentiumPfmCounters>; 26def : PfmCountersBinding<"pentium2", PentiumPfmCounters>; 27def : PfmCountersBinding<"pentium3", PentiumPfmCounters>; 28def : PfmCountersBinding<"pentium3m", PentiumPfmCounters>; 29def : PfmCountersBinding<"pentium-m", PentiumPfmCounters>; 30 31def CorePfmCounters : ProcPfmCounters { 32 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 33 let UopsCounter = PfmCounter<"uops_retired:any">; 34} 35def : PfmCountersBinding<"yonah", CorePfmCounters>; 36def : PfmCountersBinding<"prescott", CorePfmCounters>; 37def : PfmCountersBinding<"core2", CorePfmCounters>; 38def : PfmCountersBinding<"penryn", CorePfmCounters>; 39def : PfmCountersBinding<"nehalem", CorePfmCounters>; 40def : PfmCountersBinding<"corei7", CorePfmCounters>; 41def : PfmCountersBinding<"westmere", CorePfmCounters>; 42 43def AtomPfmCounters : ProcPfmCounters { 44 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 45 let UopsCounter = PfmCounter<"uops_retired:any">; 46} 47def : PfmCountersBinding<"bonnell", AtomPfmCounters>; 48def : PfmCountersBinding<"atom", AtomPfmCounters>; 49 50def SLMPfmCounters : ProcPfmCounters { 51 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 52 let UopsCounter = PfmCounter<"uops_retired:any">; 53} 54def : PfmCountersBinding<"silvermont", SLMPfmCounters>; 55def : PfmCountersBinding<"goldmont", SLMPfmCounters>; 56def : PfmCountersBinding<"goldmont-plus", SLMPfmCounters>; 57def : PfmCountersBinding<"tremont", SLMPfmCounters>; 58 59def KnightPfmCounters : ProcPfmCounters { 60 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 61 let UopsCounter = PfmCounter<"uops_retired:all">; 62} 63def : PfmCountersBinding<"knl", KnightPfmCounters>; 64def : PfmCountersBinding<"knm", KnightPfmCounters>; 65 66def SandyBridgePfmCounters : ProcPfmCounters { 67 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 68 let UopsCounter = UopsIssuedPfmCounter; 69 let IssueCounters = [ 70 PfmIssueCounter<"SBPort0", "uops_dispatched_port:port_0">, 71 PfmIssueCounter<"SBPort1", "uops_dispatched_port:port_1">, 72 PfmIssueCounter<"SBPort23", "uops_dispatched_port:port_2 + uops_dispatched_port:port_3">, 73 PfmIssueCounter<"SBPort4", "uops_dispatched_port:port_4">, 74 PfmIssueCounter<"SBPort5", "uops_dispatched_port:port_5"> 75 ]; 76} 77def : PfmCountersBinding<"sandybridge", SandyBridgePfmCounters>; 78def : PfmCountersBinding<"ivybridge", SandyBridgePfmCounters>; 79 80def HaswellPfmCounters : ProcPfmCounters { 81 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 82 let UopsCounter = UopsIssuedPfmCounter; 83 let IssueCounters = [ 84 PfmIssueCounter<"HWPort0", "uops_executed_port:port_0">, 85 PfmIssueCounter<"HWPort1", "uops_executed_port:port_1">, 86 PfmIssueCounter<"HWPort2", "uops_executed_port:port_2">, 87 PfmIssueCounter<"HWPort3", "uops_executed_port:port_3">, 88 PfmIssueCounter<"HWPort4", "uops_executed_port:port_4">, 89 PfmIssueCounter<"HWPort5", "uops_executed_port:port_5">, 90 PfmIssueCounter<"HWPort6", "uops_executed_port:port_6">, 91 PfmIssueCounter<"HWPort7", "uops_executed_port:port_7"> 92 ]; 93} 94def : PfmCountersBinding<"haswell", HaswellPfmCounters>; 95 96def BroadwellPfmCounters : ProcPfmCounters { 97 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 98 let UopsCounter = UopsIssuedPfmCounter; 99 let IssueCounters = [ 100 PfmIssueCounter<"BWPort0", "uops_executed_port:port_0">, 101 PfmIssueCounter<"BWPort1", "uops_executed_port:port_1">, 102 PfmIssueCounter<"BWPort2", "uops_executed_port:port_2">, 103 PfmIssueCounter<"BWPort3", "uops_executed_port:port_3">, 104 PfmIssueCounter<"BWPort4", "uops_executed_port:port_4">, 105 PfmIssueCounter<"BWPort5", "uops_executed_port:port_5">, 106 PfmIssueCounter<"BWPort6", "uops_executed_port:port_6">, 107 PfmIssueCounter<"BWPort7", "uops_executed_port:port_7"> 108 ]; 109} 110def : PfmCountersBinding<"broadwell", BroadwellPfmCounters>; 111 112def SkylakeClientPfmCounters : ProcPfmCounters { 113 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 114 let UopsCounter = UopsIssuedPfmCounter; 115 let IssueCounters = [ 116 PfmIssueCounter<"SKLPort0", "uops_dispatched_port:port_0">, 117 PfmIssueCounter<"SKLPort1", "uops_dispatched_port:port_1">, 118 PfmIssueCounter<"SKLPort2", "uops_dispatched_port:port_2">, 119 PfmIssueCounter<"SKLPort3", "uops_dispatched_port:port_3">, 120 PfmIssueCounter<"SKLPort4", "uops_dispatched_port:port_4">, 121 PfmIssueCounter<"SKLPort5", "uops_dispatched_port:port_5">, 122 PfmIssueCounter<"SKLPort6", "uops_dispatched_port:port_6">, 123 PfmIssueCounter<"SKLPort7", "uops_dispatched_port:port_7"> 124 ]; 125} 126def : PfmCountersBinding<"skylake", SkylakeClientPfmCounters>; 127 128def SkylakeServerPfmCounters : ProcPfmCounters { 129 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 130 let UopsCounter = UopsIssuedPfmCounter; 131 let IssueCounters = [ 132 PfmIssueCounter<"SKXPort0", "uops_dispatched_port:port_0">, 133 PfmIssueCounter<"SKXPort1", "uops_dispatched_port:port_1">, 134 PfmIssueCounter<"SKXPort2", "uops_dispatched_port:port_2">, 135 PfmIssueCounter<"SKXPort3", "uops_dispatched_port:port_3">, 136 PfmIssueCounter<"SKXPort4", "uops_dispatched_port:port_4">, 137 PfmIssueCounter<"SKXPort5", "uops_dispatched_port:port_5">, 138 PfmIssueCounter<"SKXPort6", "uops_dispatched_port:port_6">, 139 PfmIssueCounter<"SKXPort7", "uops_dispatched_port:port_7"> 140 ]; 141} 142def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>; 143def : PfmCountersBinding<"cascadelake", SkylakeServerPfmCounters>; 144def : PfmCountersBinding<"cannonlake", SkylakeServerPfmCounters>; 145 146def IceLakePfmCounters : ProcPfmCounters { 147 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 148 let UopsCounter = UopsIssuedPfmCounter; 149 let IssueCounters = [ 150 PfmIssueCounter<"ICXPort0", "uops_dispatched_port:port_0">, 151 PfmIssueCounter<"ICXPort1", "uops_dispatched_port:port_1">, 152 PfmIssueCounter<"ICXPort23", "uops_dispatched_port:port_2_3">, 153 PfmIssueCounter<"ICXPort49", "uops_dispatched_port:port_4_9">, 154 PfmIssueCounter<"ICXPort5", "uops_dispatched_port:port_5">, 155 PfmIssueCounter<"ICXPort6", "uops_dispatched_port:port_6">, 156 PfmIssueCounter<"ICXPort78", "uops_dispatched_port:port_7_8"> 157 ]; 158} 159def : PfmCountersBinding<"icelake-client", IceLakePfmCounters>; 160def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>; 161def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>; 162def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>; 163 164// AMD X86 Counters. 165// Set basic counters for AMD cpus that we know libpfm4 supports. 166def DefaultAMDPfmCounters : ProcPfmCounters { 167 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 168 let UopsCounter = PfmCounter<"retired_uops">; 169} 170def : PfmCountersBinding<"athlon", DefaultAMDPfmCounters>; 171def : PfmCountersBinding<"athlon-tbird", DefaultAMDPfmCounters>; 172def : PfmCountersBinding<"athlon-4", DefaultAMDPfmCounters>; 173def : PfmCountersBinding<"athlon-xp", DefaultAMDPfmCounters>; 174def : PfmCountersBinding<"athlon-mp", DefaultAMDPfmCounters>; 175def : PfmCountersBinding<"k8", DefaultAMDPfmCounters>; 176def : PfmCountersBinding<"opteron", DefaultAMDPfmCounters>; 177def : PfmCountersBinding<"athlon64", DefaultAMDPfmCounters>; 178def : PfmCountersBinding<"athlon-fx", DefaultAMDPfmCounters>; 179def : PfmCountersBinding<"k8-sse3", DefaultAMDPfmCounters>; 180def : PfmCountersBinding<"opteron-sse3", DefaultAMDPfmCounters>; 181def : PfmCountersBinding<"athlon64-sse3", DefaultAMDPfmCounters>; 182def : PfmCountersBinding<"amdfam10", DefaultAMDPfmCounters>; 183def : PfmCountersBinding<"barcelona", DefaultAMDPfmCounters>; 184 185def BdVer2PfmCounters : ProcPfmCounters { 186 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 187 let UopsCounter = PfmCounter<"retired_uops">; 188 let IssueCounters = [ 189 PfmIssueCounter<"PdFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">, 190 PfmIssueCounter<"PdFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">, 191 PfmIssueCounter<"PdFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">, 192 PfmIssueCounter<"PdFPU3", "dispatched_fpu_ops:ops_pipe3 + dispatched_fpu_ops:ops_dual_pipe3"> 193 ]; 194} 195def : PfmCountersBinding<"bdver1", BdVer2PfmCounters>; 196def : PfmCountersBinding<"bdver2", BdVer2PfmCounters>; 197 198def BdVer3PfmCounters : ProcPfmCounters { 199 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 200 let UopsCounter = PfmCounter<"retired_uops">; 201 let IssueCounters = [ 202 PfmIssueCounter<"SrFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">, 203 PfmIssueCounter<"SrFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">, 204 PfmIssueCounter<"SrFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2"> 205 ]; 206} 207def : PfmCountersBinding<"bdver3", BdVer3PfmCounters>; 208def : PfmCountersBinding<"bdver4", BdVer3PfmCounters>; 209 210def BtVer1PfmCounters : ProcPfmCounters { 211 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 212 let UopsCounter = PfmCounter<"retired_uops">; 213 let IssueCounters = [ 214 PfmIssueCounter<"BtFPU0", "dispatched_fpu:pipe0">, 215 PfmIssueCounter<"BtFPU1", "dispatched_fpu:pipe1"> 216 ]; 217} 218def : PfmCountersBinding<"btver1", BtVer1PfmCounters>; 219 220def BtVer2PfmCounters : ProcPfmCounters { 221 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 222 let UopsCounter = PfmCounter<"retired_uops">; 223 let IssueCounters = [ 224 PfmIssueCounter<"JFPU0", "dispatched_fpu:pipe0">, 225 PfmIssueCounter<"JFPU1", "dispatched_fpu:pipe1"> 226 ]; 227} 228def : PfmCountersBinding<"btver2", BtVer2PfmCounters>; 229 230def ZnVer1PfmCounters : ProcPfmCounters { 231 let CycleCounter = PfmCounter<"cycles_not_in_halt">; 232 let UopsCounter = PfmCounter<"retired_uops">; 233 let IssueCounters = [ 234 PfmIssueCounter<"ZnFPU0", "fpu_pipe_assignment:total0">, 235 PfmIssueCounter<"ZnFPU1", "fpu_pipe_assignment:total1">, 236 PfmIssueCounter<"ZnFPU2", "fpu_pipe_assignment:total2">, 237 PfmIssueCounter<"ZnFPU3", "fpu_pipe_assignment:total3">, 238 PfmIssueCounter<"ZnDivider", "div_op_count"> 239 ]; 240} 241def : PfmCountersBinding<"znver1", ZnVer1PfmCounters>; 242 243def ZnVer2PfmCounters : ProcPfmCounters { 244 let CycleCounter = PfmCounter<"cycles_not_in_halt">; 245 let UopsCounter = PfmCounter<"retired_uops">; 246 let IssueCounters = [ 247 PfmIssueCounter<"Zn2AGU", "ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">, 248 PfmIssueCounter<"Zn2Divider", "div_op_count"> 249 ]; 250} 251def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>; 252 253def ZnVer3PfmCounters : ProcPfmCounters { 254 let CycleCounter = PfmCounter<"cycles_not_in_halt">; 255 let UopsCounter = PfmCounter<"retired_ops">; 256 let IssueCounters = [ 257 PfmIssueCounter<"Zn3Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">, 258 PfmIssueCounter<"Zn3FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">, 259 PfmIssueCounter<"Zn3Load", "ls_dispatch:ld_dispatch">, 260 PfmIssueCounter<"Zn3Store", "ls_dispatch:store_dispatch">, 261 PfmIssueCounter<"Zn3Divider", "div_op_count"> 262 ]; 263} 264def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>; 265