1//===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the available hardware counters for various subtargets. 10// 11//===----------------------------------------------------------------------===// 12 13def UnhaltedCoreCyclesPfmCounter : PfmCounter<"unhalted_core_cycles">; 14def UopsIssuedPfmCounter : PfmCounter<"uops_issued:any">; 15 16// No default counters on X86. 17def DefaultPfmCounters : ProcPfmCounters {} 18def : PfmCountersDefaultBinding<DefaultPfmCounters>; 19 20// Intel X86 Counters. 21defvar DefaultIntelPfmValidationCounters = [ 22 PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">, 23 PfmValidationCounter<L1DCacheLoadMiss, "MEM_LOAD_UOPS_RETIRED:L1_MISS">, 24 PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">, 25 PfmValidationCounter<DataTLBLoadMiss, "DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK">, 26 PfmValidationCounter<DataTLBStoreMiss, "DTLB_STORE_MISSES:MISS_CAUSES_A_WALK">, 27 PfmValidationCounter<InstructionTLBLoadMiss, "ITLB_MISSES:MISS_CAUSES_A_WALK">, 28 PfmValidationCounter<BranchPredictionMiss, "BRANCH-MISSES"> 29]; 30 31def PentiumPfmCounters : ProcPfmCounters { 32 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 33 let UopsCounter = PfmCounter<"uops_retired">; 34} 35def : PfmCountersBinding<"pentiumpro", PentiumPfmCounters>; 36def : PfmCountersBinding<"pentium2", PentiumPfmCounters>; 37def : PfmCountersBinding<"pentium3", PentiumPfmCounters>; 38def : PfmCountersBinding<"pentium3m", PentiumPfmCounters>; 39def : PfmCountersBinding<"pentium-m", PentiumPfmCounters>; 40 41def CorePfmCounters : ProcPfmCounters { 42 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 43 let UopsCounter = PfmCounter<"uops_retired:any">; 44} 45def : PfmCountersBinding<"yonah", CorePfmCounters>; 46def : PfmCountersBinding<"prescott", CorePfmCounters>; 47 48def AtomPfmCounters : ProcPfmCounters { 49 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 50 let UopsCounter = PfmCounter<"uops_retired:any">; 51} 52def : PfmCountersBinding<"bonnell", AtomPfmCounters>; 53def : PfmCountersBinding<"atom", AtomPfmCounters>; 54 55def SLMPfmCounters : ProcPfmCounters { 56 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 57 let UopsCounter = PfmCounter<"uops_retired:any">; 58 let IssueCounters = [ 59 PfmIssueCounter<"SLM_MEC_RSV", "mem_uop_retired:any_ld + mem_uop_retired:any_st"> 60 ]; 61} 62def : PfmCountersBinding<"silvermont", SLMPfmCounters>; 63def : PfmCountersBinding<"goldmont", SLMPfmCounters>; 64def : PfmCountersBinding<"goldmont-plus", SLMPfmCounters>; 65def : PfmCountersBinding<"tremont", SLMPfmCounters>; 66 67def KnightPfmCounters : ProcPfmCounters { 68 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 69 let UopsCounter = PfmCounter<"uops_retired:all">; 70} 71def : PfmCountersBinding<"knl", KnightPfmCounters>; 72def : PfmCountersBinding<"knm", KnightPfmCounters>; 73 74def Core2PfmCounters : ProcPfmCounters { 75 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 76 let UopsCounter = PfmCounter<"uops_retired:any">; 77 let IssueCounters = [ 78 PfmIssueCounter<"SBPort0", "rs_uops_dispatched_cycles:port_0">, 79 PfmIssueCounter<"SBPort1", "rs_uops_dispatched_cycles:port_1">, 80 PfmIssueCounter<"SBPort23", "rs_uops_dispatched_cycles:port_2 + rs_uops_dispatched_cycles:port_3">, 81 PfmIssueCounter<"SBPort4", "rs_uops_dispatched_cycles:port_4">, 82 PfmIssueCounter<"SBPort5", "rs_uops_dispatched_cycles:port_5"> 83 ]; 84} 85def : PfmCountersBinding<"core2", Core2PfmCounters>; 86def : PfmCountersBinding<"penryn", Core2PfmCounters>; 87 88def NehalemPfmCounters : ProcPfmCounters { 89 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 90 let UopsCounter = PfmCounter<"uops_retired:any">; 91 let IssueCounters = [ 92 PfmIssueCounter<"SBPort0", "uops_executed:port0">, 93 PfmIssueCounter<"SBPort1", "uops_executed:port1">, 94 PfmIssueCounter<"SBPort23", "uops_executed:port2_core + uops_executed:port3_core">, 95 PfmIssueCounter<"SBPort4", "uops_executed:port4_core">, 96 PfmIssueCounter<"SBPort5", "uops_executed:port5"> 97 ]; 98} 99def : PfmCountersBinding<"nehalem", NehalemPfmCounters>; 100def : PfmCountersBinding<"corei7", NehalemPfmCounters>; 101def : PfmCountersBinding<"westmere", NehalemPfmCounters>; 102 103def SandyBridgePfmCounters : ProcPfmCounters { 104 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 105 let UopsCounter = UopsIssuedPfmCounter; 106 let IssueCounters = [ 107 PfmIssueCounter<"SBPort0", "uops_dispatched_port:port_0">, 108 PfmIssueCounter<"SBPort1", "uops_dispatched_port:port_1">, 109 PfmIssueCounter<"SBPort23", "uops_dispatched_port:port_2 + uops_dispatched_port:port_3">, 110 PfmIssueCounter<"SBPort4", "uops_dispatched_port:port_4">, 111 PfmIssueCounter<"SBPort5", "uops_dispatched_port:port_5"> 112 ]; 113 let ValidationCounters = DefaultIntelPfmValidationCounters; 114} 115def : PfmCountersBinding<"sandybridge", SandyBridgePfmCounters>; 116def : PfmCountersBinding<"ivybridge", SandyBridgePfmCounters>; 117 118def HaswellPfmCounters : ProcPfmCounters { 119 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 120 let UopsCounter = UopsIssuedPfmCounter; 121 let IssueCounters = [ 122 PfmIssueCounter<"HWPort0", "uops_executed_port:port_0">, 123 PfmIssueCounter<"HWPort1", "uops_executed_port:port_1">, 124 PfmIssueCounter<"HWPort2", "uops_executed_port:port_2">, 125 PfmIssueCounter<"HWPort3", "uops_executed_port:port_3">, 126 PfmIssueCounter<"HWPort4", "uops_executed_port:port_4">, 127 PfmIssueCounter<"HWPort5", "uops_executed_port:port_5">, 128 PfmIssueCounter<"HWPort6", "uops_executed_port:port_6">, 129 PfmIssueCounter<"HWPort7", "uops_executed_port:port_7"> 130 ]; 131 let ValidationCounters = DefaultIntelPfmValidationCounters; 132} 133def : PfmCountersBinding<"haswell", HaswellPfmCounters>; 134 135def BroadwellPfmCounters : ProcPfmCounters { 136 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 137 let UopsCounter = UopsIssuedPfmCounter; 138 let IssueCounters = [ 139 PfmIssueCounter<"BWPort0", "uops_executed_port:port_0">, 140 PfmIssueCounter<"BWPort1", "uops_executed_port:port_1">, 141 PfmIssueCounter<"BWPort2", "uops_executed_port:port_2">, 142 PfmIssueCounter<"BWPort3", "uops_executed_port:port_3">, 143 PfmIssueCounter<"BWPort4", "uops_executed_port:port_4">, 144 PfmIssueCounter<"BWPort5", "uops_executed_port:port_5">, 145 PfmIssueCounter<"BWPort6", "uops_executed_port:port_6">, 146 PfmIssueCounter<"BWPort7", "uops_executed_port:port_7"> 147 ]; 148 let ValidationCounters = DefaultIntelPfmValidationCounters; 149} 150def : PfmCountersBinding<"broadwell", BroadwellPfmCounters>; 151 152def SkylakeClientPfmCounters : ProcPfmCounters { 153 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 154 let UopsCounter = UopsIssuedPfmCounter; 155 let IssueCounters = [ 156 PfmIssueCounter<"SKLPort0", "uops_dispatched_port:port_0">, 157 PfmIssueCounter<"SKLPort1", "uops_dispatched_port:port_1">, 158 PfmIssueCounter<"SKLPort2", "uops_dispatched_port:port_2">, 159 PfmIssueCounter<"SKLPort3", "uops_dispatched_port:port_3">, 160 PfmIssueCounter<"SKLPort4", "uops_dispatched_port:port_4">, 161 PfmIssueCounter<"SKLPort5", "uops_dispatched_port:port_5">, 162 PfmIssueCounter<"SKLPort6", "uops_dispatched_port:port_6">, 163 PfmIssueCounter<"SKLPort7", "uops_dispatched_port:port_7"> 164 ]; 165 let ValidationCounters = DefaultIntelPfmValidationCounters; 166} 167def : PfmCountersBinding<"skylake", SkylakeClientPfmCounters>; 168 169def SkylakeServerPfmCounters : ProcPfmCounters { 170 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 171 let UopsCounter = UopsIssuedPfmCounter; 172 let IssueCounters = [ 173 PfmIssueCounter<"SKXPort0", "uops_dispatched_port:port_0">, 174 PfmIssueCounter<"SKXPort1", "uops_dispatched_port:port_1">, 175 PfmIssueCounter<"SKXPort2", "uops_dispatched_port:port_2">, 176 PfmIssueCounter<"SKXPort3", "uops_dispatched_port:port_3">, 177 PfmIssueCounter<"SKXPort4", "uops_dispatched_port:port_4">, 178 PfmIssueCounter<"SKXPort5", "uops_dispatched_port:port_5">, 179 PfmIssueCounter<"SKXPort6", "uops_dispatched_port:port_6">, 180 PfmIssueCounter<"SKXPort7", "uops_dispatched_port:port_7"> 181 ]; 182 let ValidationCounters = DefaultIntelPfmValidationCounters; 183} 184def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>; 185def : PfmCountersBinding<"cascadelake", SkylakeServerPfmCounters>; 186def : PfmCountersBinding<"cannonlake", SkylakeServerPfmCounters>; 187 188def IceLakePfmCounters : ProcPfmCounters { 189 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 190 let UopsCounter = UopsIssuedPfmCounter; 191 let IssueCounters = [ 192 PfmIssueCounter<"ICXPort0", "uops_dispatched_port:port_0">, 193 PfmIssueCounter<"ICXPort1", "uops_dispatched_port:port_1">, 194 PfmIssueCounter<"ICXPort23", "uops_dispatched_port:port_2_3">, 195 PfmIssueCounter<"ICXPort49", "uops_dispatched_port:port_4_9">, 196 PfmIssueCounter<"ICXPort5", "uops_dispatched_port:port_5">, 197 PfmIssueCounter<"ICXPort6", "uops_dispatched_port:port_6">, 198 PfmIssueCounter<"ICXPort78", "uops_dispatched_port:port_7_8"> 199 ]; 200 let ValidationCounters = DefaultIntelPfmValidationCounters; 201} 202def : PfmCountersBinding<"icelake-client", IceLakePfmCounters>; 203def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>; 204def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>; 205def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>; 206 207def AlderLakePfmCounters : ProcPfmCounters { 208 let CycleCounter = UnhaltedCoreCyclesPfmCounter; 209 let UopsCounter = UopsIssuedPfmCounter; 210 let IssueCounters = [ 211 PfmIssueCounter<"ADLPPort00", "uops_dispatched_port:port_0">, 212 PfmIssueCounter<"ADLPPort01", "uops_dispatched_port:port_1">, 213 PfmIssueCounter<"ADLPPort02_03_10", "uops_dispatched_port:port_2_3_10">, 214 PfmIssueCounter<"ADLPPort04_09", "uops_dispatched_port:port_4_9">, 215 PfmIssueCounter<"ADLPPort05_11", "uops_dispatched_port:port_5_11">, 216 PfmIssueCounter<"ADLPPort06", "uops_dispatched_port:port_6">, 217 PfmIssueCounter<"ADLPPort07_08", "uops_dispatched_port:port_7_8"> 218 ]; 219 let ValidationCounters = DefaultIntelPfmValidationCounters; 220} 221def : PfmCountersBinding<"alderlake", AlderLakePfmCounters>; 222 223// AMD X86 Counters. 224defvar DefaultAMDPfmValidationCounters = [ 225 PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">, 226 PfmValidationCounter<L1DCacheLoadMiss, "L1-DCACHE-LOAD-MISSES">, 227 PfmValidationCounter<L1DCacheStoreMiss, "L1-DCACHE-STORE-MISSES">, 228 PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">, 229 PfmValidationCounter<DataTLBLoadMiss, "DTLB-LOAD-MISSES">, 230 PfmValidationCounter<InstructionTLBLoadMiss, "ITLB-LOAD-MISSES">, 231 PfmValidationCounter<BranchPredictionMiss, "BRANCH-MISSES"> 232]; 233 234// Set basic counters for AMD cpus that we know libpfm4 supports. 235def DefaultAMDPfmCounters : ProcPfmCounters { 236 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 237 let UopsCounter = PfmCounter<"retired_uops">; 238} 239def : PfmCountersBinding<"athlon", DefaultAMDPfmCounters>; 240def : PfmCountersBinding<"athlon-tbird", DefaultAMDPfmCounters>; 241def : PfmCountersBinding<"athlon-4", DefaultAMDPfmCounters>; 242def : PfmCountersBinding<"athlon-xp", DefaultAMDPfmCounters>; 243def : PfmCountersBinding<"athlon-mp", DefaultAMDPfmCounters>; 244def : PfmCountersBinding<"k8", DefaultAMDPfmCounters>; 245def : PfmCountersBinding<"opteron", DefaultAMDPfmCounters>; 246def : PfmCountersBinding<"athlon64", DefaultAMDPfmCounters>; 247def : PfmCountersBinding<"athlon-fx", DefaultAMDPfmCounters>; 248def : PfmCountersBinding<"k8-sse3", DefaultAMDPfmCounters>; 249def : PfmCountersBinding<"opteron-sse3", DefaultAMDPfmCounters>; 250def : PfmCountersBinding<"athlon64-sse3", DefaultAMDPfmCounters>; 251def : PfmCountersBinding<"amdfam10", DefaultAMDPfmCounters>; 252def : PfmCountersBinding<"barcelona", DefaultAMDPfmCounters>; 253 254def BdVer2PfmCounters : ProcPfmCounters { 255 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 256 let UopsCounter = PfmCounter<"retired_uops">; 257 let IssueCounters = [ 258 PfmIssueCounter<"PdFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">, 259 PfmIssueCounter<"PdFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">, 260 PfmIssueCounter<"PdFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">, 261 PfmIssueCounter<"PdFPU3", "dispatched_fpu_ops:ops_pipe3 + dispatched_fpu_ops:ops_dual_pipe3"> 262 ]; 263} 264def : PfmCountersBinding<"bdver1", BdVer2PfmCounters>; 265def : PfmCountersBinding<"bdver2", BdVer2PfmCounters>; 266 267def BdVer3PfmCounters : ProcPfmCounters { 268 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 269 let UopsCounter = PfmCounter<"retired_uops">; 270 let IssueCounters = [ 271 PfmIssueCounter<"SrFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">, 272 PfmIssueCounter<"SrFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">, 273 PfmIssueCounter<"SrFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2"> 274 ]; 275} 276def : PfmCountersBinding<"bdver3", BdVer3PfmCounters>; 277def : PfmCountersBinding<"bdver4", BdVer3PfmCounters>; 278 279def BtVer1PfmCounters : ProcPfmCounters { 280 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 281 let UopsCounter = PfmCounter<"retired_uops">; 282 let IssueCounters = [ 283 PfmIssueCounter<"BtFPU0", "dispatched_fpu:pipe0">, 284 PfmIssueCounter<"BtFPU1", "dispatched_fpu:pipe1"> 285 ]; 286} 287def : PfmCountersBinding<"btver1", BtVer1PfmCounters>; 288 289def BtVer2PfmCounters : ProcPfmCounters { 290 let CycleCounter = PfmCounter<"cpu_clk_unhalted">; 291 let UopsCounter = PfmCounter<"retired_uops">; 292 let IssueCounters = [ 293 PfmIssueCounter<"JFPU0", "dispatched_fpu:pipe0">, 294 PfmIssueCounter<"JFPU1", "dispatched_fpu:pipe1"> 295 ]; 296} 297def : PfmCountersBinding<"btver2", BtVer2PfmCounters>; 298 299def ZnVer1PfmCounters : ProcPfmCounters { 300 let CycleCounter = PfmCounter<"cycles_not_in_halt">; 301 let UopsCounter = PfmCounter<"retired_uops">; 302 let IssueCounters = [ 303 PfmIssueCounter<"ZnFPU0", "fpu_pipe_assignment:total0">, 304 PfmIssueCounter<"ZnFPU1", "fpu_pipe_assignment:total1">, 305 PfmIssueCounter<"ZnFPU2", "fpu_pipe_assignment:total2">, 306 PfmIssueCounter<"ZnFPU3", "fpu_pipe_assignment:total3">, 307 PfmIssueCounter<"ZnAGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">, 308 PfmIssueCounter<"ZnDivider", "div_op_count"> 309 ]; 310 let ValidationCounters = DefaultAMDPfmValidationCounters; 311} 312def : PfmCountersBinding<"znver1", ZnVer1PfmCounters>; 313 314def ZnVer2PfmCounters : ProcPfmCounters { 315 let CycleCounter = PfmCounter<"cycles_not_in_halt">; 316 let UopsCounter = PfmCounter<"retired_uops">; 317 let IssueCounters = [ 318 PfmIssueCounter<"Zn2AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">, 319 PfmIssueCounter<"Zn2Divider", "div_op_count"> 320 ]; 321 let ValidationCounters = DefaultAMDPfmValidationCounters; 322} 323def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>; 324 325def ZnVer3PfmCounters : ProcPfmCounters { 326 let CycleCounter = PfmCounter<"cycles_not_in_halt">; 327 let UopsCounter = PfmCounter<"retired_ops">; 328 let IssueCounters = [ 329 PfmIssueCounter<"Zn3Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">, 330 PfmIssueCounter<"Zn3FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">, 331 PfmIssueCounter<"Zn3Load", "ls_dispatch:ld_dispatch">, 332 PfmIssueCounter<"Zn3Store", "ls_dispatch:store_dispatch">, 333 PfmIssueCounter<"Zn3Divider", "div_op_count"> 334 ]; 335 let ValidationCounters = DefaultAMDPfmValidationCounters; 336} 337def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>; 338 339def ZnVer4PfmCounters : ProcPfmCounters { 340 let CycleCounter = PfmCounter<"cycles_not_in_halt">; 341 let UopsCounter = PfmCounter<"retired_ops">; 342 let IssueCounters = [ 343 PfmIssueCounter<"Zn4Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">, 344 PfmIssueCounter<"Zn4FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">, 345 PfmIssueCounter<"Zn4Load", "ls_dispatch:ld_dispatch">, 346 PfmIssueCounter<"Zn4Store", "ls_dispatch:store_dispatch">, 347 PfmIssueCounter<"Zn4Divider", "div_op_count">, 348 PfmIssueCounter<"Zn4AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch"> 349 ]; 350 let ValidationCounters = DefaultAMDPfmValidationCounters; 351} 352def : PfmCountersBinding<"znver4", ZnVer4PfmCounters>; 353def : PfmCountersBinding<"znver5", ZnVer4PfmCounters>; 354