1//===- X86InstrVecCompiler.td - Vector Compiler Patterns ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the various vector pseudo instructions used by the 10// compiler, as well as Pat patterns used during instruction selection. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Non-instruction patterns 16//===----------------------------------------------------------------------===// 17 18let Predicates = [NoAVX512] in { 19 // A vector extract of the first f32/f64 position is a subregister copy 20 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))), 21 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>; 22 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))), 23 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>; 24} 25 26let Predicates = [HasAVX512] in { 27 // A vector extract of the first f32/f64 position is a subregister copy 28 def : Pat<(f16 (extractelt (v8f16 VR128X:$src), (iPTR 0))), 29 (COPY_TO_REGCLASS (v8f16 VR128X:$src), FR16X)>; 30 def : Pat<(f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))), 31 (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X)>; 32 def : Pat<(f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))), 33 (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X)>; 34} 35 36let Predicates = [NoVLX] in { 37 def : Pat<(v8f16 (scalar_to_vector FR16X:$src)), 38 (COPY_TO_REGCLASS FR16X:$src, VR128)>; 39 // Implicitly promote a 32-bit scalar to a vector. 40 def : Pat<(v4f32 (scalar_to_vector FR32:$src)), 41 (COPY_TO_REGCLASS FR32:$src, VR128)>; 42 // Implicitly promote a 64-bit scalar to a vector. 43 def : Pat<(v2f64 (scalar_to_vector FR64:$src)), 44 (COPY_TO_REGCLASS FR64:$src, VR128)>; 45} 46 47let Predicates = [HasVLX] in { 48 def : Pat<(v8f16 (scalar_to_vector FR16X:$src)), 49 (COPY_TO_REGCLASS FR16X:$src, VR128X)>; 50 // Implicitly promote a 32-bit scalar to a vector. 51 def : Pat<(v4f32 (scalar_to_vector FR32X:$src)), 52 (COPY_TO_REGCLASS FR32X:$src, VR128X)>; 53 // Implicitly promote a 64-bit scalar to a vector. 54 def : Pat<(v2f64 (scalar_to_vector FR64X:$src)), 55 (COPY_TO_REGCLASS FR64X:$src, VR128X)>; 56} 57 58//===----------------------------------------------------------------------===// 59// Subvector tricks 60//===----------------------------------------------------------------------===// 61 62// Patterns for insert_subvector/extract_subvector to/from index=0 63multiclass subvector_subreg_lowering<RegisterClass subRC, ValueType subVT, 64 RegisterClass RC, ValueType VT, 65 SubRegIndex subIdx> { 66 def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))), 67 (subVT (EXTRACT_SUBREG RC:$src, subIdx))>; 68 69 def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))), 70 (VT (INSERT_SUBREG (IMPLICIT_DEF), subRC:$src, subIdx))>; 71} 72 73// A 128-bit subvector extract from the first 256-bit vector position is a 74// subregister copy that needs no instruction. Likewise, a 128-bit subvector 75// insert to the first 256-bit vector position is a subregister copy that needs 76// no instruction. 77defm : subvector_subreg_lowering<VR128, v4i32, VR256, v8i32, sub_xmm>; 78defm : subvector_subreg_lowering<VR128, v4f32, VR256, v8f32, sub_xmm>; 79defm : subvector_subreg_lowering<VR128, v2i64, VR256, v4i64, sub_xmm>; 80defm : subvector_subreg_lowering<VR128, v2f64, VR256, v4f64, sub_xmm>; 81defm : subvector_subreg_lowering<VR128, v8i16, VR256, v16i16, sub_xmm>; 82defm : subvector_subreg_lowering<VR128, v16i8, VR256, v32i8, sub_xmm>; 83defm : subvector_subreg_lowering<VR128, v8f16, VR256, v16f16, sub_xmm>; 84 85// A 128-bit subvector extract from the first 512-bit vector position is a 86// subregister copy that needs no instruction. Likewise, a 128-bit subvector 87// insert to the first 512-bit vector position is a subregister copy that needs 88// no instruction. 89defm : subvector_subreg_lowering<VR128, v4i32, VR512, v16i32, sub_xmm>; 90defm : subvector_subreg_lowering<VR128, v4f32, VR512, v16f32, sub_xmm>; 91defm : subvector_subreg_lowering<VR128, v2i64, VR512, v8i64, sub_xmm>; 92defm : subvector_subreg_lowering<VR128, v2f64, VR512, v8f64, sub_xmm>; 93defm : subvector_subreg_lowering<VR128, v8i16, VR512, v32i16, sub_xmm>; 94defm : subvector_subreg_lowering<VR128, v16i8, VR512, v64i8, sub_xmm>; 95defm : subvector_subreg_lowering<VR128, v8f16, VR512, v32f16, sub_xmm>; 96 97// A 128-bit subvector extract from the first 512-bit vector position is a 98// subregister copy that needs no instruction. Likewise, a 128-bit subvector 99// insert to the first 512-bit vector position is a subregister copy that needs 100// no instruction. 101defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>; 102defm : subvector_subreg_lowering<VR256, v8f32, VR512, v16f32, sub_ymm>; 103defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>; 104defm : subvector_subreg_lowering<VR256, v4f64, VR512, v8f64, sub_ymm>; 105defm : subvector_subreg_lowering<VR256, v16i16, VR512, v32i16, sub_ymm>; 106defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>; 107defm : subvector_subreg_lowering<VR256, v16f16, VR512, v32f16, sub_ymm>; 108 109 110// If we're inserting into an all zeros vector, just use a plain move which 111// will zero the upper bits. A post-isel hook will take care of removing 112// any moves that we can prove are unnecessary. 113multiclass subvec_zero_lowering<string MoveStr, 114 RegisterClass RC, ValueType DstTy, 115 ValueType SrcTy, SubRegIndex SubIdx> { 116 def : Pat<(DstTy (insert_subvector immAllZerosV, 117 (SrcTy RC:$src), (iPTR 0))), 118 (SUBREG_TO_REG (i64 0), 119 (SrcTy (!cast<Instruction>("VMOV"#MoveStr#"rr") RC:$src)), SubIdx)>; 120} 121 122let Predicates = [HasAVX, NoVLX] in { 123 defm : subvec_zero_lowering<"APD", VR128, v4f64, v2f64, sub_xmm>; 124 defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, sub_xmm>; 125 defm : subvec_zero_lowering<"DQA", VR128, v4i64, v2i64, sub_xmm>; 126 defm : subvec_zero_lowering<"DQA", VR128, v8i32, v4i32, sub_xmm>; 127 defm : subvec_zero_lowering<"DQA", VR128, v16i16, v8i16, sub_xmm>; 128 defm : subvec_zero_lowering<"DQA", VR128, v32i8, v16i8, sub_xmm>; 129} 130 131let Predicates = [HasVLX] in { 132 defm : subvec_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, sub_xmm>; 133 defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, sub_xmm>; 134 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v4i64, v2i64, sub_xmm>; 135 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i32, v4i32, sub_xmm>; 136 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i16, v8i16, sub_xmm>; 137 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i8, v16i8, sub_xmm>; 138 139 defm : subvec_zero_lowering<"APDZ128", VR128X, v8f64, v2f64, sub_xmm>; 140 defm : subvec_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, sub_xmm>; 141 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, sub_xmm>; 142 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i32, v4i32, sub_xmm>; 143 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, sub_xmm>; 144 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, sub_xmm>; 145 146 defm : subvec_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, sub_ymm>; 147 defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, sub_ymm>; 148 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, sub_ymm>; 149 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v16i32, v8i32, sub_ymm>; 150 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v32i16, v16i16, sub_ymm>; 151 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, sub_ymm>; 152} 153 154let Predicates = [HasAVX512, NoVLX] in { 155 defm : subvec_zero_lowering<"APD", VR128, v8f64, v2f64, sub_xmm>; 156 defm : subvec_zero_lowering<"APS", VR128, v16f32, v4f32, sub_xmm>; 157 defm : subvec_zero_lowering<"DQA", VR128, v8i64, v2i64, sub_xmm>; 158 defm : subvec_zero_lowering<"DQA", VR128, v16i32, v4i32, sub_xmm>; 159 defm : subvec_zero_lowering<"DQA", VR128, v32i16, v8i16, sub_xmm>; 160 defm : subvec_zero_lowering<"DQA", VR128, v64i8, v16i8, sub_xmm>; 161 162 defm : subvec_zero_lowering<"APDY", VR256, v8f64, v4f64, sub_ymm>; 163 defm : subvec_zero_lowering<"APSY", VR256, v16f32, v8f32, sub_ymm>; 164 defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, sub_ymm>; 165 defm : subvec_zero_lowering<"DQAY", VR256, v16i32, v8i32, sub_ymm>; 166 defm : subvec_zero_lowering<"DQAY", VR256, v32i16, v16i16, sub_ymm>; 167 defm : subvec_zero_lowering<"DQAY", VR256, v64i8, v32i8, sub_ymm>; 168} 169 170let Predicates = [HasFP16, HasVLX] in { 171 defm : subvec_zero_lowering<"APSZ128", VR128X, v16f16, v8f16, sub_xmm>; 172 defm : subvec_zero_lowering<"APSZ128", VR128X, v32f16, v8f16, sub_xmm>; 173 defm : subvec_zero_lowering<"APSZ256", VR256X, v32f16, v16f16, sub_ymm>; 174} 175 176class maskzeroupper<ValueType vt, RegisterClass RC> : 177 PatLeaf<(vt RC:$src), [{ 178 return isMaskZeroExtended(N); 179 }]>; 180 181def maskzeroupperv1i1 : maskzeroupper<v1i1, VK1>; 182def maskzeroupperv2i1 : maskzeroupper<v2i1, VK2>; 183def maskzeroupperv4i1 : maskzeroupper<v4i1, VK4>; 184def maskzeroupperv8i1 : maskzeroupper<v8i1, VK8>; 185def maskzeroupperv16i1 : maskzeroupper<v16i1, VK16>; 186def maskzeroupperv32i1 : maskzeroupper<v32i1, VK32>; 187 188// The patterns determine if we can depend on the upper bits of a mask register 189// being zeroed by the previous operation so that we can skip explicit 190// zeroing. 191let Predicates = [HasBWI] in { 192 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 193 maskzeroupperv1i1:$src, (iPTR 0))), 194 (COPY_TO_REGCLASS VK1:$src, VK32)>; 195 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 196 maskzeroupperv8i1:$src, (iPTR 0))), 197 (COPY_TO_REGCLASS VK8:$src, VK32)>; 198 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 199 maskzeroupperv16i1:$src, (iPTR 0))), 200 (COPY_TO_REGCLASS VK16:$src, VK32)>; 201 202 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 203 maskzeroupperv1i1:$src, (iPTR 0))), 204 (COPY_TO_REGCLASS VK1:$src, VK64)>; 205 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 206 maskzeroupperv8i1:$src, (iPTR 0))), 207 (COPY_TO_REGCLASS VK8:$src, VK64)>; 208 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 209 maskzeroupperv16i1:$src, (iPTR 0))), 210 (COPY_TO_REGCLASS VK16:$src, VK64)>; 211 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 212 maskzeroupperv32i1:$src, (iPTR 0))), 213 (COPY_TO_REGCLASS VK32:$src, VK64)>; 214} 215 216let Predicates = [HasAVX512] in { 217 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 218 maskzeroupperv1i1:$src, (iPTR 0))), 219 (COPY_TO_REGCLASS VK1:$src, VK16)>; 220 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 221 maskzeroupperv8i1:$src, (iPTR 0))), 222 (COPY_TO_REGCLASS VK8:$src, VK16)>; 223} 224 225let Predicates = [HasDQI] in { 226 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 227 maskzeroupperv1i1:$src, (iPTR 0))), 228 (COPY_TO_REGCLASS VK1:$src, VK8)>; 229} 230 231let Predicates = [HasVLX, HasDQI] in { 232 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 233 maskzeroupperv2i1:$src, (iPTR 0))), 234 (COPY_TO_REGCLASS VK2:$src, VK8)>; 235 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 236 maskzeroupperv4i1:$src, (iPTR 0))), 237 (COPY_TO_REGCLASS VK4:$src, VK8)>; 238} 239 240let Predicates = [HasVLX] in { 241 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 242 maskzeroupperv2i1:$src, (iPTR 0))), 243 (COPY_TO_REGCLASS VK2:$src, VK16)>; 244 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 245 maskzeroupperv4i1:$src, (iPTR 0))), 246 (COPY_TO_REGCLASS VK4:$src, VK16)>; 247} 248 249let Predicates = [HasBWI, HasVLX] in { 250 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 251 maskzeroupperv2i1:$src, (iPTR 0))), 252 (COPY_TO_REGCLASS VK2:$src, VK32)>; 253 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 254 maskzeroupperv4i1:$src, (iPTR 0))), 255 (COPY_TO_REGCLASS VK4:$src, VK32)>; 256 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 257 maskzeroupperv2i1:$src, (iPTR 0))), 258 (COPY_TO_REGCLASS VK2:$src, VK64)>; 259 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 260 maskzeroupperv4i1:$src, (iPTR 0))), 261 (COPY_TO_REGCLASS VK4:$src, VK64)>; 262} 263 264// If the bits are not zero we have to fall back to explicitly zeroing by 265// using shifts. 266let Predicates = [HasAVX512] in { 267 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 268 (v1i1 VK1:$mask), (iPTR 0))), 269 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK1:$mask, VK16), 270 (i8 15)), (i8 15))>; 271 272 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 273 (v2i1 VK2:$mask), (iPTR 0))), 274 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK2:$mask, VK16), 275 (i8 14)), (i8 14))>; 276 277 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 278 (v4i1 VK4:$mask), (iPTR 0))), 279 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK4:$mask, VK16), 280 (i8 12)), (i8 12))>; 281} 282 283let Predicates = [HasAVX512, NoDQI] in { 284 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 285 (v8i1 VK8:$mask), (iPTR 0))), 286 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK8:$mask, VK16), 287 (i8 8)), (i8 8))>; 288} 289 290let Predicates = [HasDQI] in { 291 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 292 (v8i1 VK8:$mask), (iPTR 0))), 293 (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK16)>; 294 295 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 296 (v1i1 VK1:$mask), (iPTR 0))), 297 (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK1:$mask, VK8), 298 (i8 7)), (i8 7))>; 299 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 300 (v2i1 VK2:$mask), (iPTR 0))), 301 (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK2:$mask, VK8), 302 (i8 6)), (i8 6))>; 303 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 304 (v4i1 VK4:$mask), (iPTR 0))), 305 (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK4:$mask, VK8), 306 (i8 4)), (i8 4))>; 307} 308 309let Predicates = [HasBWI] in { 310 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 311 (v16i1 VK16:$mask), (iPTR 0))), 312 (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK32)>; 313 314 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 315 (v16i1 VK16:$mask), (iPTR 0))), 316 (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK64)>; 317 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 318 (v32i1 VK32:$mask), (iPTR 0))), 319 (COPY_TO_REGCLASS (KMOVDkk VK32:$mask), VK64)>; 320} 321 322let Predicates = [HasBWI, NoDQI] in { 323 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 324 (v8i1 VK8:$mask), (iPTR 0))), 325 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK8:$mask, VK32), 326 (i8 24)), (i8 24))>; 327 328 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 329 (v8i1 VK8:$mask), (iPTR 0))), 330 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK8:$mask, VK64), 331 (i8 56)), (i8 56))>; 332} 333 334let Predicates = [HasBWI, HasDQI] in { 335 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 336 (v8i1 VK8:$mask), (iPTR 0))), 337 (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK32)>; 338 339 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 340 (v8i1 VK8:$mask), (iPTR 0))), 341 (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK64)>; 342} 343 344let Predicates = [HasBWI] in { 345 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 346 (v1i1 VK1:$mask), (iPTR 0))), 347 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK1:$mask, VK32), 348 (i8 31)), (i8 31))>; 349 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 350 (v2i1 VK2:$mask), (iPTR 0))), 351 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK2:$mask, VK32), 352 (i8 30)), (i8 30))>; 353 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 354 (v4i1 VK4:$mask), (iPTR 0))), 355 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK4:$mask, VK32), 356 (i8 28)), (i8 28))>; 357 358 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 359 (v1i1 VK1:$mask), (iPTR 0))), 360 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK1:$mask, VK64), 361 (i8 63)), (i8 63))>; 362 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 363 (v2i1 VK2:$mask), (iPTR 0))), 364 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK2:$mask, VK64), 365 (i8 62)), (i8 62))>; 366 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 367 (v4i1 VK4:$mask), (iPTR 0))), 368 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK4:$mask, VK64), 369 (i8 60)), (i8 60))>; 370} 371 372//===----------------------------------------------------------------------===// 373// Extra selection patterns for f128, f128mem 374 375// movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2. 376let Predicates = [NoAVX] in { 377def : Pat<(alignedstore (f128 VR128:$src), addr:$dst), 378 (MOVAPSmr addr:$dst, VR128:$src)>; 379def : Pat<(store (f128 VR128:$src), addr:$dst), 380 (MOVUPSmr addr:$dst, VR128:$src)>; 381 382def : Pat<(alignedloadf128 addr:$src), 383 (MOVAPSrm addr:$src)>; 384def : Pat<(loadf128 addr:$src), 385 (MOVUPSrm addr:$src)>; 386} 387 388let Predicates = [HasAVX, NoVLX] in { 389def : Pat<(alignedstore (f128 VR128:$src), addr:$dst), 390 (VMOVAPSmr addr:$dst, VR128:$src)>; 391def : Pat<(store (f128 VR128:$src), addr:$dst), 392 (VMOVUPSmr addr:$dst, VR128:$src)>; 393 394def : Pat<(alignedloadf128 addr:$src), 395 (VMOVAPSrm addr:$src)>; 396def : Pat<(loadf128 addr:$src), 397 (VMOVUPSrm addr:$src)>; 398} 399 400let Predicates = [HasVLX] in { 401def : Pat<(alignedstore (f128 VR128X:$src), addr:$dst), 402 (VMOVAPSZ128mr addr:$dst, VR128X:$src)>; 403def : Pat<(store (f128 VR128X:$src), addr:$dst), 404 (VMOVUPSZ128mr addr:$dst, VR128X:$src)>; 405 406def : Pat<(alignedloadf128 addr:$src), 407 (VMOVAPSZ128rm addr:$src)>; 408def : Pat<(loadf128 addr:$src), 409 (VMOVUPSZ128rm addr:$src)>; 410} 411 412let Predicates = [UseSSE1] in { 413// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2 414def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))), 415 (ANDPSrm VR128:$src1, f128mem:$src2)>; 416 417def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)), 418 (ANDPSrr VR128:$src1, VR128:$src2)>; 419 420def : Pat<(f128 (X86for VR128:$src1, (memopf128 addr:$src2))), 421 (ORPSrm VR128:$src1, f128mem:$src2)>; 422 423def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)), 424 (ORPSrr VR128:$src1, VR128:$src2)>; 425 426def : Pat<(f128 (X86fxor VR128:$src1, (memopf128 addr:$src2))), 427 (XORPSrm VR128:$src1, f128mem:$src2)>; 428 429def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)), 430 (XORPSrr VR128:$src1, VR128:$src2)>; 431} 432 433let Predicates = [HasAVX, NoVLX] in { 434// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2 435def : Pat<(f128 (X86fand VR128:$src1, (loadf128 addr:$src2))), 436 (VANDPSrm VR128:$src1, f128mem:$src2)>; 437 438def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)), 439 (VANDPSrr VR128:$src1, VR128:$src2)>; 440 441def : Pat<(f128 (X86for VR128:$src1, (loadf128 addr:$src2))), 442 (VORPSrm VR128:$src1, f128mem:$src2)>; 443 444def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)), 445 (VORPSrr VR128:$src1, VR128:$src2)>; 446 447def : Pat<(f128 (X86fxor VR128:$src1, (loadf128 addr:$src2))), 448 (VXORPSrm VR128:$src1, f128mem:$src2)>; 449 450def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)), 451 (VXORPSrr VR128:$src1, VR128:$src2)>; 452} 453 454let Predicates = [HasVLX] in { 455// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2 456def : Pat<(f128 (X86fand VR128X:$src1, (loadf128 addr:$src2))), 457 (VANDPSZ128rm VR128X:$src1, f128mem:$src2)>; 458 459def : Pat<(f128 (X86fand VR128X:$src1, VR128X:$src2)), 460 (VANDPSZ128rr VR128X:$src1, VR128X:$src2)>; 461 462def : Pat<(f128 (X86for VR128X:$src1, (loadf128 addr:$src2))), 463 (VORPSZ128rm VR128X:$src1, f128mem:$src2)>; 464 465def : Pat<(f128 (X86for VR128X:$src1, VR128X:$src2)), 466 (VORPSZ128rr VR128X:$src1, VR128X:$src2)>; 467 468def : Pat<(f128 (X86fxor VR128X:$src1, (loadf128 addr:$src2))), 469 (VXORPSZ128rm VR128X:$src1, f128mem:$src2)>; 470 471def : Pat<(f128 (X86fxor VR128X:$src1, VR128X:$src2)), 472 (VXORPSZ128rr VR128X:$src1, VR128X:$src2)>; 473} 474