1//===- X86InstrVecCompiler.td - Vector Compiler Patterns ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the various vector pseudo instructions used by the 10// compiler, as well as Pat patterns used during instruction selection. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Non-instruction patterns 16//===----------------------------------------------------------------------===// 17 18let Predicates = [NoAVX512] in { 19 // A vector extract of the first f32/f64 position is a subregister copy 20 def : Pat<(f16 (extractelt (v8f16 VR128:$src), (iPTR 0))), 21 (COPY_TO_REGCLASS (v8f16 VR128:$src), FR16)>; 22 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))), 23 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>; 24 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))), 25 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>; 26} 27 28let Predicates = [HasAVX512] in { 29 // A vector extract of the first f32/f64 position is a subregister copy 30 def : Pat<(f16 (extractelt (v8f16 VR128X:$src), (iPTR 0))), 31 (COPY_TO_REGCLASS (v8f16 VR128X:$src), FR16X)>; 32 def : Pat<(f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))), 33 (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X)>; 34 def : Pat<(f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))), 35 (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X)>; 36} 37 38let Predicates = [NoVLX] in { 39 def : Pat<(v8f16 (scalar_to_vector FR16:$src)), 40 (COPY_TO_REGCLASS FR16:$src, VR128)>; 41 // Implicitly promote a 32-bit scalar to a vector. 42 def : Pat<(v4f32 (scalar_to_vector FR32:$src)), 43 (COPY_TO_REGCLASS FR32:$src, VR128)>; 44 // Implicitly promote a 64-bit scalar to a vector. 45 def : Pat<(v2f64 (scalar_to_vector FR64:$src)), 46 (COPY_TO_REGCLASS FR64:$src, VR128)>; 47} 48 49let Predicates = [HasVLX] in { 50 def : Pat<(v8f16 (scalar_to_vector FR16X:$src)), 51 (COPY_TO_REGCLASS FR16X:$src, VR128X)>; 52 // Implicitly promote a 32-bit scalar to a vector. 53 def : Pat<(v4f32 (scalar_to_vector FR32X:$src)), 54 (COPY_TO_REGCLASS FR32X:$src, VR128X)>; 55 // Implicitly promote a 64-bit scalar to a vector. 56 def : Pat<(v2f64 (scalar_to_vector FR64X:$src)), 57 (COPY_TO_REGCLASS FR64X:$src, VR128X)>; 58} 59 60//===----------------------------------------------------------------------===// 61// Subvector tricks 62//===----------------------------------------------------------------------===// 63 64// Patterns for insert_subvector/extract_subvector to/from index=0 65multiclass subvector_subreg_lowering<RegisterClass subRC, ValueType subVT, 66 RegisterClass RC, ValueType VT, 67 SubRegIndex subIdx> { 68 def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))), 69 (subVT (EXTRACT_SUBREG RC:$src, subIdx))>; 70 71 def : Pat<(VT (insert_subvector undef_or_freeze_undef, subRC:$src, (iPTR 0))), 72 (VT (INSERT_SUBREG (IMPLICIT_DEF), subRC:$src, subIdx))>; 73} 74 75// A 128-bit subvector extract from the first 256-bit vector position is a 76// subregister copy that needs no instruction. Likewise, a 128-bit subvector 77// insert to the first 256-bit vector position is a subregister copy that needs 78// no instruction. 79defm : subvector_subreg_lowering<VR128, v4i32, VR256, v8i32, sub_xmm>; 80defm : subvector_subreg_lowering<VR128, v4f32, VR256, v8f32, sub_xmm>; 81defm : subvector_subreg_lowering<VR128, v2i64, VR256, v4i64, sub_xmm>; 82defm : subvector_subreg_lowering<VR128, v2f64, VR256, v4f64, sub_xmm>; 83defm : subvector_subreg_lowering<VR128, v8i16, VR256, v16i16, sub_xmm>; 84defm : subvector_subreg_lowering<VR128, v16i8, VR256, v32i8, sub_xmm>; 85defm : subvector_subreg_lowering<VR128, v8f16, VR256, v16f16, sub_xmm>; 86 87// A 128-bit subvector extract from the first 512-bit vector position is a 88// subregister copy that needs no instruction. Likewise, a 128-bit subvector 89// insert to the first 512-bit vector position is a subregister copy that needs 90// no instruction. 91defm : subvector_subreg_lowering<VR128, v4i32, VR512, v16i32, sub_xmm>; 92defm : subvector_subreg_lowering<VR128, v4f32, VR512, v16f32, sub_xmm>; 93defm : subvector_subreg_lowering<VR128, v2i64, VR512, v8i64, sub_xmm>; 94defm : subvector_subreg_lowering<VR128, v2f64, VR512, v8f64, sub_xmm>; 95defm : subvector_subreg_lowering<VR128, v8i16, VR512, v32i16, sub_xmm>; 96defm : subvector_subreg_lowering<VR128, v16i8, VR512, v64i8, sub_xmm>; 97defm : subvector_subreg_lowering<VR128, v8f16, VR512, v32f16, sub_xmm>; 98 99// A 128-bit subvector extract from the first 512-bit vector position is a 100// subregister copy that needs no instruction. Likewise, a 128-bit subvector 101// insert to the first 512-bit vector position is a subregister copy that needs 102// no instruction. 103defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>; 104defm : subvector_subreg_lowering<VR256, v8f32, VR512, v16f32, sub_ymm>; 105defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>; 106defm : subvector_subreg_lowering<VR256, v4f64, VR512, v8f64, sub_ymm>; 107defm : subvector_subreg_lowering<VR256, v16i16, VR512, v32i16, sub_ymm>; 108defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>; 109defm : subvector_subreg_lowering<VR256, v16f16, VR512, v32f16, sub_ymm>; 110 111 112// If we're inserting into an all zeros vector, just use a plain move which 113// will zero the upper bits. A post-isel hook will take care of removing 114// any moves that we can prove are unnecessary. 115multiclass subvec_zero_lowering<string MoveStr, 116 RegisterClass RC, ValueType DstTy, 117 ValueType SrcTy, SubRegIndex SubIdx> { 118 def : Pat<(DstTy (insert_subvector immAllZerosV, 119 (SrcTy RC:$src), (iPTR 0))), 120 (SUBREG_TO_REG (i64 0), 121 (SrcTy (!cast<Instruction>("VMOV"#MoveStr#"rr") RC:$src)), SubIdx)>; 122} 123 124let Predicates = [HasAVX, NoVLX] in { 125 defm : subvec_zero_lowering<"APD", VR128, v4f64, v2f64, sub_xmm>; 126 defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, sub_xmm>; 127 defm : subvec_zero_lowering<"DQA", VR128, v4i64, v2i64, sub_xmm>; 128 defm : subvec_zero_lowering<"DQA", VR128, v8i32, v4i32, sub_xmm>; 129 defm : subvec_zero_lowering<"DQA", VR128, v16i16, v8i16, sub_xmm>; 130 defm : subvec_zero_lowering<"DQA", VR128, v32i8, v16i8, sub_xmm>; 131} 132 133let Predicates = [HasVLX] in { 134 defm : subvec_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, sub_xmm>; 135 defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, sub_xmm>; 136 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v4i64, v2i64, sub_xmm>; 137 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i32, v4i32, sub_xmm>; 138 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i16, v8i16, sub_xmm>; 139 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i8, v16i8, sub_xmm>; 140 141 defm : subvec_zero_lowering<"APDZ128", VR128X, v8f64, v2f64, sub_xmm>; 142 defm : subvec_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, sub_xmm>; 143 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, sub_xmm>; 144 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i32, v4i32, sub_xmm>; 145 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, sub_xmm>; 146 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, sub_xmm>; 147 148 defm : subvec_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, sub_ymm>; 149 defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, sub_ymm>; 150 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, sub_ymm>; 151 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v16i32, v8i32, sub_ymm>; 152 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v32i16, v16i16, sub_ymm>; 153 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, sub_ymm>; 154} 155 156let Predicates = [HasAVX512, NoVLX] in { 157 defm : subvec_zero_lowering<"APD", VR128, v8f64, v2f64, sub_xmm>; 158 defm : subvec_zero_lowering<"APS", VR128, v16f32, v4f32, sub_xmm>; 159 defm : subvec_zero_lowering<"DQA", VR128, v8i64, v2i64, sub_xmm>; 160 defm : subvec_zero_lowering<"DQA", VR128, v16i32, v4i32, sub_xmm>; 161 defm : subvec_zero_lowering<"DQA", VR128, v32i16, v8i16, sub_xmm>; 162 defm : subvec_zero_lowering<"DQA", VR128, v64i8, v16i8, sub_xmm>; 163 164 defm : subvec_zero_lowering<"APDY", VR256, v8f64, v4f64, sub_ymm>; 165 defm : subvec_zero_lowering<"APSY", VR256, v16f32, v8f32, sub_ymm>; 166 defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, sub_ymm>; 167 defm : subvec_zero_lowering<"DQAY", VR256, v16i32, v8i32, sub_ymm>; 168 defm : subvec_zero_lowering<"DQAY", VR256, v32i16, v16i16, sub_ymm>; 169 defm : subvec_zero_lowering<"DQAY", VR256, v64i8, v32i8, sub_ymm>; 170} 171 172let Predicates = [HasFP16, HasVLX] in { 173 defm : subvec_zero_lowering<"APSZ128", VR128X, v16f16, v8f16, sub_xmm>; 174 defm : subvec_zero_lowering<"APSZ128", VR128X, v32f16, v8f16, sub_xmm>; 175 defm : subvec_zero_lowering<"APSZ256", VR256X, v32f16, v16f16, sub_ymm>; 176} 177 178class maskzeroupper<ValueType vt, RegisterClass RC> : 179 PatLeaf<(vt RC:$src), [{ 180 return isMaskZeroExtended(N); 181 }]>; 182 183def maskzeroupperv1i1 : maskzeroupper<v1i1, VK1>; 184def maskzeroupperv2i1 : maskzeroupper<v2i1, VK2>; 185def maskzeroupperv4i1 : maskzeroupper<v4i1, VK4>; 186def maskzeroupperv8i1 : maskzeroupper<v8i1, VK8>; 187def maskzeroupperv16i1 : maskzeroupper<v16i1, VK16>; 188def maskzeroupperv32i1 : maskzeroupper<v32i1, VK32>; 189 190// The patterns determine if we can depend on the upper bits of a mask register 191// being zeroed by the previous operation so that we can skip explicit 192// zeroing. 193let Predicates = [HasBWI] in { 194 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 195 maskzeroupperv1i1:$src, (iPTR 0))), 196 (COPY_TO_REGCLASS VK1:$src, VK32)>; 197 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 198 maskzeroupperv8i1:$src, (iPTR 0))), 199 (COPY_TO_REGCLASS VK8:$src, VK32)>; 200 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 201 maskzeroupperv16i1:$src, (iPTR 0))), 202 (COPY_TO_REGCLASS VK16:$src, VK32)>; 203 204 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 205 maskzeroupperv1i1:$src, (iPTR 0))), 206 (COPY_TO_REGCLASS VK1:$src, VK64)>; 207 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 208 maskzeroupperv8i1:$src, (iPTR 0))), 209 (COPY_TO_REGCLASS VK8:$src, VK64)>; 210 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 211 maskzeroupperv16i1:$src, (iPTR 0))), 212 (COPY_TO_REGCLASS VK16:$src, VK64)>; 213 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 214 maskzeroupperv32i1:$src, (iPTR 0))), 215 (COPY_TO_REGCLASS VK32:$src, VK64)>; 216} 217 218let Predicates = [HasAVX512] in { 219 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 220 maskzeroupperv1i1:$src, (iPTR 0))), 221 (COPY_TO_REGCLASS VK1:$src, VK16)>; 222 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 223 maskzeroupperv8i1:$src, (iPTR 0))), 224 (COPY_TO_REGCLASS VK8:$src, VK16)>; 225} 226 227let Predicates = [HasDQI] in { 228 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 229 maskzeroupperv1i1:$src, (iPTR 0))), 230 (COPY_TO_REGCLASS VK1:$src, VK8)>; 231} 232 233let Predicates = [HasVLX, HasDQI] in { 234 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 235 maskzeroupperv2i1:$src, (iPTR 0))), 236 (COPY_TO_REGCLASS VK2:$src, VK8)>; 237 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 238 maskzeroupperv4i1:$src, (iPTR 0))), 239 (COPY_TO_REGCLASS VK4:$src, VK8)>; 240} 241 242let Predicates = [HasVLX] in { 243 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 244 maskzeroupperv2i1:$src, (iPTR 0))), 245 (COPY_TO_REGCLASS VK2:$src, VK16)>; 246 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 247 maskzeroupperv4i1:$src, (iPTR 0))), 248 (COPY_TO_REGCLASS VK4:$src, VK16)>; 249} 250 251let Predicates = [HasBWI, HasVLX] in { 252 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 253 maskzeroupperv2i1:$src, (iPTR 0))), 254 (COPY_TO_REGCLASS VK2:$src, VK32)>; 255 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 256 maskzeroupperv4i1:$src, (iPTR 0))), 257 (COPY_TO_REGCLASS VK4:$src, VK32)>; 258 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 259 maskzeroupperv2i1:$src, (iPTR 0))), 260 (COPY_TO_REGCLASS VK2:$src, VK64)>; 261 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 262 maskzeroupperv4i1:$src, (iPTR 0))), 263 (COPY_TO_REGCLASS VK4:$src, VK64)>; 264} 265 266// If the bits are not zero we have to fall back to explicitly zeroing by 267// using shifts. 268let Predicates = [HasAVX512] in { 269 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 270 (v1i1 VK1:$mask), (iPTR 0))), 271 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK1:$mask, VK16), 272 (i8 15)), (i8 15))>; 273 274 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 275 (v2i1 VK2:$mask), (iPTR 0))), 276 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK2:$mask, VK16), 277 (i8 14)), (i8 14))>; 278 279 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 280 (v4i1 VK4:$mask), (iPTR 0))), 281 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK4:$mask, VK16), 282 (i8 12)), (i8 12))>; 283} 284 285let Predicates = [HasAVX512, NoDQI] in { 286 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 287 (v8i1 VK8:$mask), (iPTR 0))), 288 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK8:$mask, VK16), 289 (i8 8)), (i8 8))>; 290} 291 292let Predicates = [HasDQI] in { 293 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), 294 (v8i1 VK8:$mask), (iPTR 0))), 295 (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK16)>; 296 297 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 298 (v1i1 VK1:$mask), (iPTR 0))), 299 (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK1:$mask, VK8), 300 (i8 7)), (i8 7))>; 301 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 302 (v2i1 VK2:$mask), (iPTR 0))), 303 (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK2:$mask, VK8), 304 (i8 6)), (i8 6))>; 305 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), 306 (v4i1 VK4:$mask), (iPTR 0))), 307 (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK4:$mask, VK8), 308 (i8 4)), (i8 4))>; 309} 310 311let Predicates = [HasBWI] in { 312 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 313 (v16i1 VK16:$mask), (iPTR 0))), 314 (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK32)>; 315 316 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 317 (v16i1 VK16:$mask), (iPTR 0))), 318 (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK64)>; 319 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 320 (v32i1 VK32:$mask), (iPTR 0))), 321 (COPY_TO_REGCLASS (KMOVDkk VK32:$mask), VK64)>; 322} 323 324let Predicates = [HasBWI, NoDQI] in { 325 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 326 (v8i1 VK8:$mask), (iPTR 0))), 327 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK8:$mask, VK32), 328 (i8 24)), (i8 24))>; 329 330 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 331 (v8i1 VK8:$mask), (iPTR 0))), 332 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK8:$mask, VK64), 333 (i8 56)), (i8 56))>; 334} 335 336let Predicates = [HasBWI, HasDQI] in { 337 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 338 (v8i1 VK8:$mask), (iPTR 0))), 339 (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK32)>; 340 341 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 342 (v8i1 VK8:$mask), (iPTR 0))), 343 (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK64)>; 344} 345 346let Predicates = [HasBWI] in { 347 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 348 (v1i1 VK1:$mask), (iPTR 0))), 349 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK1:$mask, VK32), 350 (i8 31)), (i8 31))>; 351 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 352 (v2i1 VK2:$mask), (iPTR 0))), 353 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK2:$mask, VK32), 354 (i8 30)), (i8 30))>; 355 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), 356 (v4i1 VK4:$mask), (iPTR 0))), 357 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK4:$mask, VK32), 358 (i8 28)), (i8 28))>; 359 360 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 361 (v1i1 VK1:$mask), (iPTR 0))), 362 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK1:$mask, VK64), 363 (i8 63)), (i8 63))>; 364 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 365 (v2i1 VK2:$mask), (iPTR 0))), 366 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK2:$mask, VK64), 367 (i8 62)), (i8 62))>; 368 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), 369 (v4i1 VK4:$mask), (iPTR 0))), 370 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK4:$mask, VK64), 371 (i8 60)), (i8 60))>; 372} 373 374//===----------------------------------------------------------------------===// 375// Extra selection patterns for f128, f128mem 376 377// movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2. 378let Predicates = [NoAVX] in { 379def : Pat<(alignedstore (f128 VR128:$src), addr:$dst), 380 (MOVAPSmr addr:$dst, VR128:$src)>; 381def : Pat<(store (f128 VR128:$src), addr:$dst), 382 (MOVUPSmr addr:$dst, VR128:$src)>; 383 384def : Pat<(alignedloadf128 addr:$src), 385 (MOVAPSrm addr:$src)>; 386def : Pat<(loadf128 addr:$src), 387 (MOVUPSrm addr:$src)>; 388} 389 390let Predicates = [HasAVX, NoVLX] in { 391def : Pat<(alignedstore (f128 VR128:$src), addr:$dst), 392 (VMOVAPSmr addr:$dst, VR128:$src)>; 393def : Pat<(store (f128 VR128:$src), addr:$dst), 394 (VMOVUPSmr addr:$dst, VR128:$src)>; 395 396def : Pat<(alignedloadf128 addr:$src), 397 (VMOVAPSrm addr:$src)>; 398def : Pat<(loadf128 addr:$src), 399 (VMOVUPSrm addr:$src)>; 400} 401 402let Predicates = [HasVLX] in { 403def : Pat<(alignedstore (f128 VR128X:$src), addr:$dst), 404 (VMOVAPSZ128mr addr:$dst, VR128X:$src)>; 405def : Pat<(store (f128 VR128X:$src), addr:$dst), 406 (VMOVUPSZ128mr addr:$dst, VR128X:$src)>; 407 408def : Pat<(alignedloadf128 addr:$src), 409 (VMOVAPSZ128rm addr:$src)>; 410def : Pat<(loadf128 addr:$src), 411 (VMOVUPSZ128rm addr:$src)>; 412} 413 414let Predicates = [UseSSE1] in { 415// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2 416def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))), 417 (ANDPSrm VR128:$src1, f128mem:$src2)>; 418 419def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)), 420 (ANDPSrr VR128:$src1, VR128:$src2)>; 421 422def : Pat<(f128 (X86for VR128:$src1, (memopf128 addr:$src2))), 423 (ORPSrm VR128:$src1, f128mem:$src2)>; 424 425def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)), 426 (ORPSrr VR128:$src1, VR128:$src2)>; 427 428def : Pat<(f128 (X86fxor VR128:$src1, (memopf128 addr:$src2))), 429 (XORPSrm VR128:$src1, f128mem:$src2)>; 430 431def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)), 432 (XORPSrr VR128:$src1, VR128:$src2)>; 433} 434 435let Predicates = [HasAVX, NoVLX] in { 436// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2 437def : Pat<(f128 (X86fand VR128:$src1, (loadf128 addr:$src2))), 438 (VANDPSrm VR128:$src1, f128mem:$src2)>; 439 440def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)), 441 (VANDPSrr VR128:$src1, VR128:$src2)>; 442 443def : Pat<(f128 (X86for VR128:$src1, (loadf128 addr:$src2))), 444 (VORPSrm VR128:$src1, f128mem:$src2)>; 445 446def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)), 447 (VORPSrr VR128:$src1, VR128:$src2)>; 448 449def : Pat<(f128 (X86fxor VR128:$src1, (loadf128 addr:$src2))), 450 (VXORPSrm VR128:$src1, f128mem:$src2)>; 451 452def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)), 453 (VXORPSrr VR128:$src1, VR128:$src2)>; 454} 455 456let Predicates = [HasVLX] in { 457// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2 458def : Pat<(f128 (X86fand VR128X:$src1, (loadf128 addr:$src2))), 459 (VANDPSZ128rm VR128X:$src1, f128mem:$src2)>; 460 461def : Pat<(f128 (X86fand VR128X:$src1, VR128X:$src2)), 462 (VANDPSZ128rr VR128X:$src1, VR128X:$src2)>; 463 464def : Pat<(f128 (X86for VR128X:$src1, (loadf128 addr:$src2))), 465 (VORPSZ128rm VR128X:$src1, f128mem:$src2)>; 466 467def : Pat<(f128 (X86for VR128X:$src1, VR128X:$src2)), 468 (VORPSZ128rr VR128X:$src1, VR128X:$src2)>; 469 470def : Pat<(f128 (X86fxor VR128X:$src1, (loadf128 addr:$src2))), 471 (VXORPSZ128rm VR128X:$src1, f128mem:$src2)>; 472 473def : Pat<(f128 (X86fxor VR128X:$src1, VR128X:$src2)), 474 (VXORPSZ128rr VR128X:$src1, VR128X:$src2)>; 475} 476