1//===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the instructions that make up the Intel VMX instruction 10// set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// VMX instructions 16 17let SchedRW = [WriteSystem] in { 18// 66 0F 38 80 19def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), 20 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD, 21 Requires<[Not64BitMode]>; 22def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 23 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD, 24 Requires<[In64BitMode]>; 25 26// 66 0F 38 81 27def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), 28 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD, 29 Requires<[Not64BitMode]>; 30def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 31 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD, 32 Requires<[In64BitMode]>; 33 34// 0F 01 C1 35def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB; 36def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), 37 "vmclear\t$vmcs", []>, PD; 38 39// OF 01 D4 40def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, PS; 41 42// 0F 01 C2 43def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB; 44 45// 0F 01 C3 46def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB; 47def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), 48 "vmptrld\t$vmcs", []>, PS; 49def VMPTRSTm : I<0xC7, MRM7m, (outs), (ins i64mem:$vmcs), 50 "vmptrst\t$vmcs", []>, PS; 51def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 52 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>; 53def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 54 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>; 55 56let mayStore = 1 in { 57def VMREAD64mr : I<0x78, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 58 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>; 59def VMREAD32mr : I<0x78, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 60 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>; 61} // mayStore 62 63def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 64 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>; 65def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 66 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>; 67 68let mayLoad = 1 in { 69def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 70 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>; 71def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 72 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>; 73} // mayLoad 74 75// 0F 01 C4 76def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB; 77def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon), 78 "vmxon\t$vmxon", []>, XS; 79} // SchedRW 80