1//===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the instructions that make up the Intel VMX instruction 10// set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// VMX instructions 16 17let SchedRW = [WriteSystem] in { 18// 66 0F 38 80 19def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), 20 "invept\t{$src2, $src1|$src1, $src2}", []>, T8, PD, 21 Requires<[Not64BitMode]>; 22def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 23 "invept\t{$src2, $src1|$src1, $src2}", []>, T8, PD, 24 Requires<[In64BitMode]>; 25def INVEPT64_EVEX : I<0xF0, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 26 "invept\t{$src2, $src1|$src1, $src2}", []>, 27 EVEX, NoCD8, T_MAP4, XS, Requires<[In64BitMode]>; 28 29// 66 0F 38 81 30def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), 31 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8, PD, 32 Requires<[Not64BitMode]>; 33def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 34 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8, PD, 35 Requires<[In64BitMode]>; 36def INVVPID64_EVEX : I<0xF1, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 37 "invvpid\t{$src2, $src1|$src1, $src2}", []>, 38 EVEX, NoCD8, T_MAP4, XS, Requires<[In64BitMode]>; 39 40// 0F 01 C1 41def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB; 42def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), 43 "vmclear\t$vmcs", []>, TB, PD; 44 45// OF 01 D4 46def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB; 47 48// 0F 01 C2 49def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB; 50 51// 0F 01 C3 52def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB; 53def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), 54 "vmptrld\t$vmcs", []>, TB; 55def VMPTRSTm : I<0xC7, MRM7m, (outs), (ins i64mem:$vmcs), 56 "vmptrst\t$vmcs", []>, TB; 57def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 58 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>; 59def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 60 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[Not64BitMode]>; 61 62let mayStore = 1 in { 63def VMREAD64mr : I<0x78, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 64 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>; 65def VMREAD32mr : I<0x78, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 66 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[Not64BitMode]>; 67} // mayStore 68 69def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 70 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>; 71def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 72 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[Not64BitMode]>; 73 74let mayLoad = 1 in { 75def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 76 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>; 77def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 78 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[Not64BitMode]>; 79} // mayLoad 80 81// 0F 01 C4 82def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB; 83def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon), 84 "vmxon\t$vmxon", []>, TB, XS; 85} // SchedRW 86