1//===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the instructions that make up the Intel TSX instruction 10// set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// TSX instructions 16 17def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>, 18 [SDNPHasChain, SDNPSideEffect]>; 19 20let SchedRW = [WriteSystem] in { 21 22let usesCustomInserter = 1 in 23def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins), 24 "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>, 25 Requires<[HasRTM]>; 26 27let isBranch = 1, isTerminator = 1, Defs = [EAX] in { 28def XBEGIN_2 : Ii16PCRel<0xc7, MRM_F8, (outs), (ins brtarget16:$dst), 29 "xbegin\t$dst", []>, OpSize16; 30def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst), 31 "xbegin\t$dst", []>, OpSize32; 32} 33 34// Pseudo instruction to fake the definition of EAX on the fallback code path. 35let isPseudo = 1, Defs = [EAX] in { 36def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>; 37} 38 39def XEND : I<0x01, MRM_D5, (outs), (ins), 40 "xend", [(int_x86_xend)]>, PS, Requires<[HasRTM]>; 41 42let Defs = [EFLAGS] in 43def XTEST : I<0x01, MRM_D6, (outs), (ins), 44 "xtest", [(set EFLAGS, (X86xtest))]>, PS, Requires<[HasRTM]>; 45 46def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm), 47 "xabort\t$imm", 48 [(int_x86_xabort timm:$imm)]>, Requires<[HasRTM]>; 49} // SchedRW 50 51// HLE prefixes 52let SchedRW = [WriteSystem] in { 53 54let isAsmParserOnly = 1 in { 55def XACQUIRE_PREFIX : I<0xF2, PrefixByte, (outs), (ins), "xacquire", []>; 56def XRELEASE_PREFIX : I<0xF3, PrefixByte, (outs), (ins), "xrelease", []>; 57} 58 59} // SchedRW 60