xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86InstrSystem.td (revision da759cfa320d5076b075d15ff3f00ab3ba5634fd) 
1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 instructions that are generally used in
10// privileged modes.  These are not typically used by the compiler, but are
11// supported for the assembler and disassembler.
12//
13//===----------------------------------------------------------------------===//
14
15let SchedRW = [WriteSystem] in {
16let Defs = [RAX, RDX] in
17def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
18
19let Defs = [RAX, RCX, RDX] in
20def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
21
22// CPU flow control instructions
23
24let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
25  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
27}
28
29def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
30def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
31
32// Interrupt and SysCall Instructions.
33let Uses = [EFLAGS] in
34  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
35
36def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
37} // SchedRW
38
39// The long form of "int $3" turns into int3 as a size optimization.
40// FIXME: This doesn't work because InstAlias can't match immediate constants.
41//def : InstAlias<"int\t$3", (INT3)>;
42
43let SchedRW = [WriteSystem] in {
44
45def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
46              [(int_x86_int timm:$trap)]>;
47
48
49def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
50def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB;
51def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
52               Requires<[In64BitMode]>;
53
54def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
55
56def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
57def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
58                  Requires<[In64BitMode]>;
59} // SchedRW
60
61def : Pat<(debugtrap),
62          (INT3)>, Requires<[NotPS4]>;
63def : Pat<(debugtrap),
64          (INT (i8 0x41))>, Requires<[IsPS4]>;
65
66//===----------------------------------------------------------------------===//
67//  Input/Output Instructions.
68//
69let SchedRW = [WriteSystem] in {
70let Defs = [AL], Uses = [DX] in
71def IN8rr  : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>;
72let Defs = [AX], Uses = [DX] in
73def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>,
74               OpSize16;
75let Defs = [EAX], Uses = [DX] in
76def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>,
77               OpSize32;
78
79let Defs = [AL] in
80def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
81                 "in{b}\t{$port, %al|al, $port}", []>;
82let Defs = [AX] in
83def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
84                 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
85let Defs = [EAX] in
86def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
87                 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
88
89let Uses = [DX, AL] in
90def OUT8rr  : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>;
91let Uses = [DX, AX] in
92def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>,
93                OpSize16;
94let Uses = [DX, EAX] in
95def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>,
96                OpSize32;
97
98let Uses = [AL] in
99def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
100                   "out{b}\t{%al, $port|$port, al}", []>;
101let Uses = [AX] in
102def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
103                   "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
104let Uses = [EAX] in
105def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
106                  "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
107
108} // SchedRW
109
110//===----------------------------------------------------------------------===//
111// Moves to and from debug registers
112
113let SchedRW = [WriteSystem] in {
114def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
115                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
116                Requires<[Not64BitMode]>;
117def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
118                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
119                Requires<[In64BitMode]>;
120
121def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
122                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
123                Requires<[Not64BitMode]>;
124def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
125                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
126                Requires<[In64BitMode]>;
127} // SchedRW
128
129//===----------------------------------------------------------------------===//
130// Moves to and from control registers
131
132let SchedRW = [WriteSystem] in {
133def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
134                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
135                Requires<[Not64BitMode]>;
136def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
137                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
138                Requires<[In64BitMode]>;
139
140def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
141                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
142                Requires<[Not64BitMode]>;
143def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
144                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
145                Requires<[In64BitMode]>;
146} // SchedRW
147
148//===----------------------------------------------------------------------===//
149// Segment override instruction prefixes
150
151let SchedRW = [WriteNop] in {
152def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
153def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
154def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
155def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
156def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
157def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
158} // SchedRW
159
160//===----------------------------------------------------------------------===//
161// Moves to and from segment registers.
162//
163
164let SchedRW = [WriteMove] in {
165def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
166                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
167def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
168                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
169def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
170                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
171let mayStore = 1 in {
172def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
173                "mov{w}\t{$src, $dst|$dst, $src}", []>;
174}
175def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
176                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
177def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
178                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
179def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
180                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
181let mayLoad = 1 in {
182def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
183                "mov{w}\t{$src, $dst|$dst, $src}", []>;
184}
185} // SchedRW
186
187//===----------------------------------------------------------------------===//
188// Segmentation support instructions.
189
190let SchedRW = [WriteSystem] in {
191def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
192
193let mayLoad = 1 in
194def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
195                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
196                OpSize16, NotMemoryFoldable;
197def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
198                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
199                OpSize16, NotMemoryFoldable;
200
201// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
202let mayLoad = 1 in
203def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
204                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
205                OpSize32, NotMemoryFoldable;
206def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
207                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
208                OpSize32, NotMemoryFoldable;
209// i16mem operand in LAR64rm and GR32 operand in LAR64rr is not a typo.
210let mayLoad = 1 in
211def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
212                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
213def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
214                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
215
216// i16mem operand in LSL32rm and GR32 operand in LSL32rr is not a typo.
217let mayLoad = 1 in
218def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
219                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
220                OpSize16, NotMemoryFoldable;
221def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
222                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
223                OpSize16, NotMemoryFoldable;
224// i16mem operand in LSL64rm and GR32 operand in LSL64rr is not a typo.
225let mayLoad = 1 in
226def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
227                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
228                OpSize32, NotMemoryFoldable;
229def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
230                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
231                OpSize32, NotMemoryFoldable;
232let mayLoad = 1 in
233def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
234                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
235def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
236                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
237
238def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
239
240def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
241               "str{w}\t$dst", []>, TB, OpSize16;
242def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
243               "str{l}\t$dst", []>, TB, OpSize32;
244def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
245                "str{q}\t$dst", []>, TB;
246let mayStore = 1 in
247def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB;
248
249def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
250let mayLoad = 1 in
251def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
252
253def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>,
254                 OpSize16, Requires<[Not64BitMode]>;
255def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>,
256                 OpSize32, Requires<[Not64BitMode]>;
257def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>,
258                 OpSize16, Requires<[Not64BitMode]>;
259def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>,
260                 OpSize32, Requires<[Not64BitMode]>;
261def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>,
262                 OpSize16, Requires<[Not64BitMode]>;
263def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>,
264                 OpSize32, Requires<[Not64BitMode]>;
265def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>,
266                 OpSize16, Requires<[Not64BitMode]>;
267def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>,
268                 OpSize32, Requires<[Not64BitMode]>;
269def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>,
270                 OpSize16, TB;
271def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB,
272                 OpSize32, Requires<[Not64BitMode]>;
273def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>,
274                 OpSize16, TB;
275def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB,
276                 OpSize32, Requires<[Not64BitMode]>;
277def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB,
278                 OpSize32, Requires<[In64BitMode]>;
279def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB,
280                 OpSize32, Requires<[In64BitMode]>;
281
282// No "pop cs" instruction.
283def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>,
284              OpSize16, Requires<[Not64BitMode]>;
285def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>,
286              OpSize32, Requires<[Not64BitMode]>;
287
288def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>,
289              OpSize16, Requires<[Not64BitMode]>;
290def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>,
291              OpSize32, Requires<[Not64BitMode]>;
292
293def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>,
294              OpSize16, Requires<[Not64BitMode]>;
295def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>,
296              OpSize32, Requires<[Not64BitMode]>;
297
298def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>,
299                OpSize16, TB;
300def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB,
301                OpSize32, Requires<[Not64BitMode]>;
302def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB,
303                OpSize32, Requires<[In64BitMode]>;
304
305def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>,
306                OpSize16, TB;
307def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB,
308                OpSize32, Requires<[Not64BitMode]>;
309def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB,
310                OpSize32, Requires<[In64BitMode]>;
311
312def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
313                "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
314                Requires<[Not64BitMode]>;
315def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
316                "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
317                Requires<[Not64BitMode]>;
318
319def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
320                "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
321def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
322                "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
323def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
324                 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
325
326def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
327                "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
328                Requires<[Not64BitMode]>;
329def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
330                "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
331                Requires<[Not64BitMode]>;
332
333def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
334                "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
335def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
336                "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
337def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
338                 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
339
340def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
341                "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
342def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
343                "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
344
345def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
346                 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
347
348def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
349def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
350let mayLoad = 1 in {
351def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
352def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
353}
354} // SchedRW
355
356//===----------------------------------------------------------------------===//
357// Descriptor-table support instructions
358
359let SchedRW = [WriteSystem] in {
360def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
361                "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
362def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
363                "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
364def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
365                "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
366def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
367                "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
368def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
369                "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
370def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
371                "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
372def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
373                "sldt{w}\t$dst", []>, TB, OpSize16;
374let mayStore = 1 in
375def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
376                "sldt{w}\t$dst", []>, TB;
377def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
378                "sldt{l}\t$dst", []>, OpSize32, TB;
379
380// LLDT is not interpreted specially in 64-bit mode because there is no sign
381//   extension.
382def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
383                 "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
384
385def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
386                "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
387def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
388                "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
389def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
390                "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
391def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
392                "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
393def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
394                "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
395def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
396                "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
397def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
398                "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
399let mayLoad = 1 in
400def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
401                "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
402} // SchedRW
403
404//===----------------------------------------------------------------------===//
405// Specialized register support
406let SchedRW = [WriteSystem] in {
407let Uses = [EAX, ECX, EDX] in
408def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
409let Defs = [EAX, EDX], Uses = [ECX] in
410def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
411
412let Defs = [RAX, RDX], Uses = [ECX] in
413def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
414
415def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
416                "smsw{w}\t$dst", []>, OpSize16, TB;
417def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
418                "smsw{l}\t$dst", []>, OpSize32, TB;
419// no m form encodable; use SMSW16m
420def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
421                 "smsw{q}\t$dst", []>, TB;
422
423// For memory operands, there is only a 16-bit form
424def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
425                "smsw{w}\t$dst", []>, TB;
426
427def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
428                "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
429let mayLoad = 1 in
430def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
431                "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
432
433let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
434  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
435} // SchedRW
436
437//===----------------------------------------------------------------------===//
438// Cache instructions
439let SchedRW = [WriteSystem] in {
440def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
441def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, TB;
442
443// wbnoinvd is like wbinvd, except without invalidation
444// encoding: like wbinvd + an 0xF3 prefix
445def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd",
446                 [(int_x86_wbnoinvd)]>, XS,
447                 Requires<[HasWBNOINVD]>;
448} // SchedRW
449
450//===----------------------------------------------------------------------===//
451// CET instructions
452// Use with caution, availability is not predicated on features.
453let SchedRW = [WriteSystem] in {
454  let Uses = [SSP] in {
455    let Defs = [SSP] in {
456      def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
457                       [(int_x86_incsspd GR32:$src)]>, XS;
458      def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
459                       [(int_x86_incsspq GR64:$src)]>, XS;
460    } // Defs SSP
461
462    let Constraints = "$src = $dst" in {
463      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
464                     "rdsspd\t$dst",
465                     [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
466      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
467                     "rdsspq\t$dst",
468                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS;
469    }
470
471    let Defs = [SSP] in {
472      def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
473                       [(int_x86_saveprevssp)]>, XS;
474      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
475                       "rstorssp\t$src",
476                       [(int_x86_rstorssp addr:$src)]>, XS;
477    } // Defs SSP
478  } // Uses SSP
479
480  def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
481                "wrssd\t{$src, $dst|$dst, $src}",
482                [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS;
483  def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
484                 "wrssq\t{$src, $dst|$dst, $src}",
485                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS;
486  def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
487                 "wrussd\t{$src, $dst|$dst, $src}",
488                 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
489  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
490                  "wrussq\t{$src, $dst|$dst, $src}",
491                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD;
492
493  let Defs = [SSP] in {
494    let Uses = [SSP] in {
495        def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
496                         [(int_x86_setssbsy)]>, XS;
497    } // Uses SSP
498
499    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
500                     "clrssbsy\t$src",
501                     [(int_x86_clrssbsy addr:$src)]>, XS;
502  } // Defs SSP
503} // SchedRW
504
505let SchedRW = [WriteSystem] in {
506    def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
507    def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
508} // SchedRW
509
510//===----------------------------------------------------------------------===//
511// XSAVE instructions
512let SchedRW = [WriteSystem] in {
513let Predicates = [HasXSAVE] in {
514let Defs = [EDX, EAX], Uses = [ECX] in
515  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
516
517let Uses = [EDX, EAX, ECX] in
518  def XSETBV : I<0x01, MRM_D1, (outs), (ins),
519                "xsetbv",
520                [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
521
522} // HasXSAVE
523
524let Uses = [EDX, EAX] in {
525def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
526              "xsave\t$dst",
527              [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
528def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
529                 "xsave64\t$dst",
530                 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
531def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
532               "xrstor\t$dst",
533               [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
534def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
535                  "xrstor64\t$dst",
536                  [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
537def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
538                 "xsaveopt\t$dst",
539                 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>;
540def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
541                    "xsaveopt64\t$dst",
542                    [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>;
543def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
544               "xsavec\t$dst",
545               [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>;
546def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
547                 "xsavec64\t$dst",
548                 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>;
549def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
550               "xsaves\t$dst",
551               [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
552def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
553                  "xsaves64\t$dst",
554                  [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
555def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
556                "xrstors\t$dst",
557                [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
558def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
559                   "xrstors64\t$dst",
560                   [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>;
561} // Uses
562} // SchedRW
563
564//===----------------------------------------------------------------------===//
565// VIA PadLock crypto instructions
566let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
567  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
568
569def : InstAlias<"xstorerng", (XSTORE)>;
570
571let SchedRW = [WriteSystem] in {
572let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
573  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
574  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
575  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
576  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
577  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
578}
579
580let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
581  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
582  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
583}
584let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
585  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
586} // SchedRW
587
588//==-----------------------------------------------------------------------===//
589// PKU  - enable protection key
590let SchedRW = [WriteSystem] in {
591let Defs = [EAX, EDX], Uses = [ECX] in
592  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru",
593                  [(set EAX, (X86rdpkru ECX)), (implicit EDX)]>, TB;
594let Uses = [EAX, ECX, EDX] in
595  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru",
596                  [(X86wrpkru EAX, EDX, ECX)]>, TB;
597} // SchedRW
598
599//===----------------------------------------------------------------------===//
600// FS/GS Base Instructions
601let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
602  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
603                   "rdfsbase{l}\t$dst",
604                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
605  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
606                     "rdfsbase{q}\t$dst",
607                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
608  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
609                   "rdgsbase{l}\t$dst",
610                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
611  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
612                     "rdgsbase{q}\t$dst",
613                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
614  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
615                   "wrfsbase{l}\t$src",
616                   [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
617  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
618                      "wrfsbase{q}\t$src",
619                      [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
620  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
621                   "wrgsbase{l}\t$src",
622                   [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
623  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
624                      "wrgsbase{q}\t$src",
625                      [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
626}
627
628//===----------------------------------------------------------------------===//
629// INVPCID Instruction
630let SchedRW = [WriteSystem] in {
631def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
632                  "invpcid\t{$src2, $src1|$src1, $src2}",
633                  [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD,
634                  Requires<[Not64BitMode, HasINVPCID]>;
635def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
636                  "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
637                  Requires<[In64BitMode, HasINVPCID]>;
638} // SchedRW
639
640let Predicates = [In64BitMode, HasINVPCID] in {
641  // The instruction can only use a 64 bit register as the register argument
642  // in 64 bit mode, while the intrinsic only accepts a 32 bit argument
643  // corresponding to it.
644  // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID
645  // type),/ so it doesn't hurt us that one can't supply a 64 bit value here.
646  def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
647            (INVPCID64
648              (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit),
649              addr:$src2)>;
650}
651
652
653//===----------------------------------------------------------------------===//
654// SMAP Instruction
655let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
656  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
657  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
658}
659
660//===----------------------------------------------------------------------===//
661// SMX Instruction
662let SchedRW = [WriteSystem] in {
663let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
664  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
665} // Uses, Defs
666} // SchedRW
667
668//===----------------------------------------------------------------------===//
669// TS flag control instruction.
670let SchedRW = [WriteSystem] in {
671def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
672}
673
674//===----------------------------------------------------------------------===//
675// IF (inside EFLAGS) management instructions.
676let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
677def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
678def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
679}
680
681//===----------------------------------------------------------------------===//
682// RDPID Instruction
683let SchedRW = [WriteSystem] in {
684def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
685                "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS,
686                Requires<[Not64BitMode, HasRDPID]>;
687def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS,
688                Requires<[In64BitMode, HasRDPID]>;
689} // SchedRW
690
691let Predicates = [In64BitMode, HasRDPID] in {
692  // Due to silly instruction definition, we have to compensate for the
693  // instruction outputing a 64-bit register.
694  def : Pat<(int_x86_rdpid),
695            (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
696}
697
698
699//===----------------------------------------------------------------------===//
700// PTWRITE Instruction - Write Data to a Processor Trace Packet
701let SchedRW = [WriteSystem] in {
702def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
703                "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS,
704                Requires<[HasPTWRITE]>;
705def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
706                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS,
707                    Requires<[In64BitMode, HasPTWRITE]>;
708
709def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
710                 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS,
711                    Requires<[HasPTWRITE]>;
712def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
713                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS,
714                    Requires<[In64BitMode, HasPTWRITE]>;
715} // SchedRW
716
717//===----------------------------------------------------------------------===//
718// Platform Configuration instruction
719
720// From ISA docs:
721//  "This instruction is used to execute functions for configuring platform
722//   features.
723//   EAX: Leaf function to be invoked.
724//   RBX/RCX/RDX: Leaf-specific purpose."
725//  "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
726//   AF, OF, and SF are cleared. In case of failure, the failure reason is
727//   indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
728// Thus all these mentioned registers are considered clobbered.
729
730let SchedRW = [WriteSystem] in {
731let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
732    def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB,
733                  Requires<[HasPCONFIG]>;
734} // SchedRW
735