xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86InstrSystem.td (revision bc5304a006238115291e7568583632889dffbab9) 
1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 instructions that are generally used in
10// privileged modes.  These are not typically used by the compiler, but are
11// supported for the assembler and disassembler.
12//
13//===----------------------------------------------------------------------===//
14
15let SchedRW = [WriteSystem] in {
16let Defs = [RAX, RDX] in
17def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
18
19let Defs = [RAX, RCX, RDX] in
20def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
21
22// CPU flow control instructions
23
24let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
25  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26
27  def UD1Wm   : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
28                  "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
29  def UD1Lm   : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
30                  "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
31  def UD1Qm   : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
32                   "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
33
34  def UD1Wr   : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
35                  "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
36  def UD1Lr   : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
37                  "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
38  def UD1Qr   : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
39                   "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
40}
41
42def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
43def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
44
45// Interrupt and SysCall Instructions.
46let Uses = [EFLAGS] in
47  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
48
49def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
50} // SchedRW
51
52def UBSAN_UD1 : PseudoI<(outs), (ins i32imm:$kind), [(ubsantrap (i32 timm:$kind))]>;
53// The long form of "int $3" turns into int3 as a size optimization.
54// FIXME: This doesn't work because InstAlias can't match immediate constants.
55//def : InstAlias<"int\t$3", (INT3)>;
56
57let SchedRW = [WriteSystem] in {
58
59def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
60              [(int_x86_int timm:$trap)]>;
61
62
63def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
64def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB;
65def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
66               Requires<[In64BitMode]>;
67
68def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
69
70def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
71def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
72                  Requires<[In64BitMode]>;
73} // SchedRW
74
75def : Pat<(debugtrap),
76          (INT3)>, Requires<[NotPS4]>;
77def : Pat<(debugtrap),
78          (INT (i8 0x41))>, Requires<[IsPS4]>;
79
80//===----------------------------------------------------------------------===//
81//  Input/Output Instructions.
82//
83let SchedRW = [WriteSystem] in {
84let Defs = [AL], Uses = [DX] in
85def IN8rr  : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>;
86let Defs = [AX], Uses = [DX] in
87def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>,
88               OpSize16;
89let Defs = [EAX], Uses = [DX] in
90def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>,
91               OpSize32;
92
93let Defs = [AL] in
94def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
95                 "in{b}\t{$port, %al|al, $port}", []>;
96let Defs = [AX] in
97def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
98                 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
99let Defs = [EAX] in
100def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
101                 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
102
103let Uses = [DX, AL] in
104def OUT8rr  : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>;
105let Uses = [DX, AX] in
106def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>,
107                OpSize16;
108let Uses = [DX, EAX] in
109def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>,
110                OpSize32;
111
112let Uses = [AL] in
113def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
114                   "out{b}\t{%al, $port|$port, al}", []>;
115let Uses = [AX] in
116def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
117                   "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
118let Uses = [EAX] in
119def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
120                  "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
121
122} // SchedRW
123
124//===----------------------------------------------------------------------===//
125// Moves to and from debug registers
126
127let SchedRW = [WriteSystem] in {
128def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
129                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
130                Requires<[Not64BitMode]>;
131def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
132                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
133                Requires<[In64BitMode]>;
134
135def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
136                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
137                Requires<[Not64BitMode]>;
138def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
139                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
140                Requires<[In64BitMode]>;
141} // SchedRW
142
143//===----------------------------------------------------------------------===//
144// Moves to and from control registers
145
146let SchedRW = [WriteSystem] in {
147def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
148                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
149                Requires<[Not64BitMode]>;
150def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
151                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
152                Requires<[In64BitMode]>;
153
154def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
155                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
156                Requires<[Not64BitMode]>;
157def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
158                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
159                Requires<[In64BitMode]>;
160} // SchedRW
161
162//===----------------------------------------------------------------------===//
163// Segment override instruction prefixes
164
165let SchedRW = [WriteNop] in {
166def CS_PREFIX : I<0x2E, PrefixByte, (outs), (ins), "cs", []>;
167def SS_PREFIX : I<0x36, PrefixByte, (outs), (ins), "ss", []>;
168def DS_PREFIX : I<0x3E, PrefixByte, (outs), (ins), "ds", []>;
169def ES_PREFIX : I<0x26, PrefixByte, (outs), (ins), "es", []>;
170def FS_PREFIX : I<0x64, PrefixByte, (outs), (ins), "fs", []>;
171def GS_PREFIX : I<0x65, PrefixByte, (outs), (ins), "gs", []>;
172} // SchedRW
173
174//===----------------------------------------------------------------------===//
175// Address-size override prefixes.
176//
177
178let SchedRW = [WriteNop] in {
179def ADDR16_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr16", []>,
180                      Requires<[In32BitMode]>;
181def ADDR32_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr32", []>,
182                      Requires<[In64BitMode]>;
183} // SchedRW
184
185//===----------------------------------------------------------------------===//
186// Moves to and from segment registers.
187//
188
189let SchedRW = [WriteMove] in {
190def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
191                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
192def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
193                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
194def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
195                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
196let mayStore = 1 in {
197def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
198                "mov{w}\t{$src, $dst|$dst, $src}", []>;
199}
200def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
201                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
202def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
203                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
204def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
205                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
206let mayLoad = 1 in {
207def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
208                "mov{w}\t{$src, $dst|$dst, $src}", []>;
209}
210} // SchedRW
211
212//===----------------------------------------------------------------------===//
213// Segmentation support instructions.
214
215let SchedRW = [WriteSystem] in {
216def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
217
218let mayLoad = 1 in
219def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
220                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
221                OpSize16, NotMemoryFoldable;
222def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src),
223                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
224                OpSize16, NotMemoryFoldable;
225
226let mayLoad = 1 in
227def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
228                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
229                OpSize32, NotMemoryFoldable;
230def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src),
231                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
232                OpSize32, NotMemoryFoldable;
233let mayLoad = 1 in
234def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
235                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
236def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src),
237                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
238
239let mayLoad = 1 in
240def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
241                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
242                OpSize16, NotMemoryFoldable;
243def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src),
244                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
245                OpSize16, NotMemoryFoldable;
246let mayLoad = 1 in
247def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
248                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
249                OpSize32, NotMemoryFoldable;
250def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src),
251                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
252                OpSize32, NotMemoryFoldable;
253let mayLoad = 1 in
254def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
255                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
256def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src),
257                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
258
259def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
260
261def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
262               "str{w}\t$dst", []>, TB, OpSize16;
263def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
264               "str{l}\t$dst", []>, TB, OpSize32;
265def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
266                "str{q}\t$dst", []>, TB;
267let mayStore = 1 in
268def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB;
269
270def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
271let mayLoad = 1 in
272def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
273
274def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>,
275                 OpSize16, Requires<[Not64BitMode]>;
276def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>,
277                 OpSize32, Requires<[Not64BitMode]>;
278def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>,
279                 OpSize16, Requires<[Not64BitMode]>;
280def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>,
281                 OpSize32, Requires<[Not64BitMode]>;
282def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>,
283                 OpSize16, Requires<[Not64BitMode]>;
284def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>,
285                 OpSize32, Requires<[Not64BitMode]>;
286def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>,
287                 OpSize16, Requires<[Not64BitMode]>;
288def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>,
289                 OpSize32, Requires<[Not64BitMode]>;
290def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>,
291                 OpSize16, TB;
292def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB,
293                 OpSize32, Requires<[Not64BitMode]>;
294def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>,
295                 OpSize16, TB;
296def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB,
297                 OpSize32, Requires<[Not64BitMode]>;
298def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB,
299                 OpSize32, Requires<[In64BitMode]>;
300def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB,
301                 OpSize32, Requires<[In64BitMode]>;
302
303// No "pop cs" instruction.
304def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>,
305              OpSize16, Requires<[Not64BitMode]>;
306def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>,
307              OpSize32, Requires<[Not64BitMode]>;
308
309def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>,
310              OpSize16, Requires<[Not64BitMode]>;
311def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>,
312              OpSize32, Requires<[Not64BitMode]>;
313
314def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>,
315              OpSize16, Requires<[Not64BitMode]>;
316def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>,
317              OpSize32, Requires<[Not64BitMode]>;
318
319def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>,
320                OpSize16, TB;
321def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB,
322                OpSize32, Requires<[Not64BitMode]>;
323def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB,
324                OpSize32, Requires<[In64BitMode]>;
325
326def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>,
327                OpSize16, TB;
328def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB,
329                OpSize32, Requires<[Not64BitMode]>;
330def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB,
331                OpSize32, Requires<[In64BitMode]>;
332
333def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
334                "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
335                Requires<[Not64BitMode]>;
336def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
337                "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
338                Requires<[Not64BitMode]>;
339
340def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
341                "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
342def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
343                "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
344def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
345                 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
346
347def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
348                "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
349                Requires<[Not64BitMode]>;
350def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
351                "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
352                Requires<[Not64BitMode]>;
353
354def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
355                "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
356def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
357                "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
358def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
359                 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
360
361def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
362                "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
363def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
364                "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
365
366def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
367                 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
368
369def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
370def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
371let mayLoad = 1 in {
372def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
373def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
374}
375} // SchedRW
376
377//===----------------------------------------------------------------------===//
378// Descriptor-table support instructions
379
380let SchedRW = [WriteSystem] in {
381def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
382                "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
383def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
384                "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
385def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
386                "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
387def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
388                "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
389def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
390                "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
391def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
392                "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
393def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
394                "sldt{w}\t$dst", []>, TB, OpSize16;
395let mayStore = 1 in
396def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
397                "sldt{w}\t$dst", []>, TB;
398def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
399                "sldt{l}\t$dst", []>, OpSize32, TB;
400
401// LLDT is not interpreted specially in 64-bit mode because there is no sign
402//   extension.
403def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
404                 "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
405
406def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
407                "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
408def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
409                "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
410def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
411                "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
412def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
413                "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
414def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
415                "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
416def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
417                "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
418def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
419                "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
420let mayLoad = 1 in
421def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
422                "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
423} // SchedRW
424
425//===----------------------------------------------------------------------===//
426// Specialized register support
427let SchedRW = [WriteSystem] in {
428let Uses = [EAX, ECX, EDX] in
429def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
430let Defs = [EAX, EDX], Uses = [ECX] in
431def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
432
433let Defs = [RAX, RDX], Uses = [ECX] in
434def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
435
436def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
437                "smsw{w}\t$dst", []>, OpSize16, TB;
438def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
439                "smsw{l}\t$dst", []>, OpSize32, TB;
440// no m form encodable; use SMSW16m
441def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
442                 "smsw{q}\t$dst", []>, TB;
443
444// For memory operands, there is only a 16-bit form
445def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
446                "smsw{w}\t$dst", []>, TB;
447
448def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
449                "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
450let mayLoad = 1 in
451def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
452                "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
453
454let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
455  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
456} // SchedRW
457
458//===----------------------------------------------------------------------===//
459// Cache instructions
460let SchedRW = [WriteSystem] in {
461def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
462def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, PS;
463
464// wbnoinvd is like wbinvd, except without invalidation
465// encoding: like wbinvd + an 0xF3 prefix
466def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd",
467                 [(int_x86_wbnoinvd)]>, XS,
468                 Requires<[HasWBNOINVD]>;
469} // SchedRW
470
471//===----------------------------------------------------------------------===//
472// CET instructions
473// Use with caution, availability is not predicated on features.
474let SchedRW = [WriteSystem] in {
475  let Uses = [SSP] in {
476    let Defs = [SSP] in {
477      def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
478                       [(int_x86_incsspd GR32:$src)]>, XS;
479      def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
480                       [(int_x86_incsspq GR64:$src)]>, XS;
481    } // Defs SSP
482
483    let Constraints = "$src = $dst" in {
484      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
485                     "rdsspd\t$dst",
486                     [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
487      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
488                     "rdsspq\t$dst",
489                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS;
490    }
491
492    let Defs = [SSP] in {
493      def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
494                       [(int_x86_saveprevssp)]>, XS;
495      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
496                       "rstorssp\t$src",
497                       [(int_x86_rstorssp addr:$src)]>, XS;
498    } // Defs SSP
499  } // Uses SSP
500
501  def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
502                "wrssd\t{$src, $dst|$dst, $src}",
503                [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS;
504  def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
505                 "wrssq\t{$src, $dst|$dst, $src}",
506                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS;
507  def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
508                 "wrussd\t{$src, $dst|$dst, $src}",
509                 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
510  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
511                  "wrussq\t{$src, $dst|$dst, $src}",
512                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD;
513
514  let Defs = [SSP] in {
515    let Uses = [SSP] in {
516        def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
517                         [(int_x86_setssbsy)]>, XS;
518    } // Uses SSP
519
520    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
521                     "clrssbsy\t$src",
522                     [(int_x86_clrssbsy addr:$src)]>, XS;
523  } // Defs SSP
524} // SchedRW
525
526let SchedRW = [WriteSystem] in {
527    def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
528    def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
529} // SchedRW
530
531//===----------------------------------------------------------------------===//
532// XSAVE instructions
533let SchedRW = [WriteSystem] in {
534let Predicates = [HasXSAVE] in {
535let Defs = [EDX, EAX], Uses = [ECX] in
536  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, PS;
537
538let Uses = [EDX, EAX, ECX] in
539  def XSETBV : I<0x01, MRM_D1, (outs), (ins),
540                "xsetbv",
541                [(int_x86_xsetbv ECX, EDX, EAX)]>, PS;
542
543} // HasXSAVE
544
545let Uses = [EDX, EAX] in {
546def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
547              "xsave\t$dst",
548              [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
549def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
550                 "xsave64\t$dst",
551                 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
552def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
553               "xrstor\t$dst",
554               [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
555def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
556                  "xrstor64\t$dst",
557                  [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
558def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
559                 "xsaveopt\t$dst",
560                 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>;
561def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
562                    "xsaveopt64\t$dst",
563                    [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>;
564def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
565               "xsavec\t$dst",
566               [(int_x86_xsavec addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEC]>;
567def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
568                 "xsavec64\t$dst",
569                 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEC, In64BitMode]>;
570def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
571               "xsaves\t$dst",
572               [(int_x86_xsaves addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES]>;
573def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
574                  "xsaves64\t$dst",
575                  [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
576def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
577                "xrstors\t$dst",
578                [(int_x86_xrstors addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES]>;
579def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
580                   "xrstors64\t$dst",
581                   [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES, In64BitMode]>;
582} // Uses
583} // SchedRW
584
585//===----------------------------------------------------------------------===//
586// VIA PadLock crypto instructions
587let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
588  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB, REP;
589
590def : InstAlias<"xstorerng", (XSTORE)>;
591
592let SchedRW = [WriteSystem] in {
593let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
594  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB, REP;
595  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB, REP;
596  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB, REP;
597  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB, REP;
598  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB, REP;
599}
600
601let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
602  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB, REP;
603  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB, REP;
604}
605let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
606  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB, REP;
607} // SchedRW
608
609//==-----------------------------------------------------------------------===//
610// PKU  - enable protection key
611let SchedRW = [WriteSystem] in {
612let Defs = [EAX, EDX], Uses = [ECX] in
613  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru",
614                  [(set EAX, (X86rdpkru ECX)), (implicit EDX)]>, PS;
615let Uses = [EAX, ECX, EDX] in
616  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru",
617                  [(X86wrpkru EAX, EDX, ECX)]>, PS;
618} // SchedRW
619
620//===----------------------------------------------------------------------===//
621// FS/GS Base Instructions
622let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
623  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
624                   "rdfsbase{l}\t$dst",
625                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
626  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
627                     "rdfsbase{q}\t$dst",
628                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
629  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
630                   "rdgsbase{l}\t$dst",
631                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
632  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
633                     "rdgsbase{q}\t$dst",
634                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
635  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
636                   "wrfsbase{l}\t$src",
637                   [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
638  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
639                      "wrfsbase{q}\t$src",
640                      [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
641  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
642                   "wrgsbase{l}\t$src",
643                   [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
644  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
645                      "wrgsbase{q}\t$src",
646                      [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
647}
648
649//===----------------------------------------------------------------------===//
650// INVPCID Instruction
651let SchedRW = [WriteSystem] in {
652def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
653                  "invpcid\t{$src2, $src1|$src1, $src2}",
654                  [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD,
655                  Requires<[Not64BitMode, HasINVPCID]>;
656def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
657                  "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
658                  Requires<[In64BitMode, HasINVPCID]>;
659} // SchedRW
660
661let Predicates = [In64BitMode, HasINVPCID] in {
662  // The instruction can only use a 64 bit register as the register argument
663  // in 64 bit mode, while the intrinsic only accepts a 32 bit argument
664  // corresponding to it.
665  // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID
666  // type),/ so it doesn't hurt us that one can't supply a 64 bit value here.
667  def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
668            (INVPCID64
669              (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit),
670              addr:$src2)>;
671}
672
673
674//===----------------------------------------------------------------------===//
675// SMAP Instruction
676let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
677  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, PS;
678  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, PS;
679}
680
681//===----------------------------------------------------------------------===//
682// SMX Instruction
683let SchedRW = [WriteSystem] in {
684let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
685  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, PS;
686} // Uses, Defs
687} // SchedRW
688
689//===----------------------------------------------------------------------===//
690// TS flag control instruction.
691let SchedRW = [WriteSystem] in {
692def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
693}
694
695//===----------------------------------------------------------------------===//
696// IF (inside EFLAGS) management instructions.
697let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
698def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
699def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
700}
701
702//===----------------------------------------------------------------------===//
703// RDPID Instruction
704let SchedRW = [WriteSystem] in {
705def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
706                "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS,
707                Requires<[Not64BitMode, HasRDPID]>;
708def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS,
709                Requires<[In64BitMode, HasRDPID]>;
710} // SchedRW
711
712let Predicates = [In64BitMode, HasRDPID] in {
713  // Due to silly instruction definition, we have to compensate for the
714  // instruction outputing a 64-bit register.
715  def : Pat<(int_x86_rdpid),
716            (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
717}
718
719
720//===----------------------------------------------------------------------===//
721// PTWRITE Instruction - Write Data to a Processor Trace Packet
722let SchedRW = [WriteSystem] in {
723def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
724                "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS,
725                Requires<[HasPTWRITE]>;
726def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
727                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS,
728                    Requires<[In64BitMode, HasPTWRITE]>;
729
730def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
731                 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS,
732                    Requires<[HasPTWRITE]>;
733def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
734                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS,
735                    Requires<[In64BitMode, HasPTWRITE]>;
736} // SchedRW
737
738//===----------------------------------------------------------------------===//
739// Platform Configuration instruction
740
741// From ISA docs:
742//  "This instruction is used to execute functions for configuring platform
743//   features.
744//   EAX: Leaf function to be invoked.
745//   RBX/RCX/RDX: Leaf-specific purpose."
746//  "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
747//   AF, OF, and SF are cleared. In case of failure, the failure reason is
748//   indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
749// Thus all these mentioned registers are considered clobbered.
750
751let SchedRW = [WriteSystem] in {
752let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
753    def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, PS,
754                  Requires<[HasPCONFIG]>;
755} // SchedRW
756