1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 instructions that are generally used in 10// privileged modes. These are not typically used by the compiler, but are 11// supported for the assembler and disassembler. 12// 13//===----------------------------------------------------------------------===// 14 15let SchedRW = [WriteSystem] in { 16let Defs = [RAX, RDX] in 17def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB; 18 19let Defs = [RAX, RCX, RDX] in 20def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB; 21 22// CPU flow control instructions 23 24let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in { 25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; 26 27 def UD1Wm : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2), 28 "ud1{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16; 29 def UD1Lm : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2), 30 "ud1{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32; 31 def UD1Qm : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2), 32 "ud1{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 33 34 def UD1Wr : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2), 35 "ud1{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16; 36 def UD1Lr : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2), 37 "ud1{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32; 38 def UD1Qr : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2), 39 "ud1{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 40} 41 42let isTerminator = 1 in 43 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>; 44def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB; 45 46// Interrupt and SysCall Instructions. 47let Uses = [EFLAGS] in 48 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>; 49 50def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>; 51 52def UBSAN_UD1 : PseudoI<(outs), (ins i32imm:$kind), [(ubsantrap (i32 timm:$kind))]>; 53// The long form of "int $3" turns into int3 as a size optimization. 54// FIXME: This doesn't work because InstAlias can't match immediate constants. 55//def : InstAlias<"int\t$3", (INT3)>; 56 57def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap", 58 [(int_x86_int timm:$trap)]>; 59 60 61def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB; 62def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB; 63def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB, 64 Requires<[In64BitMode]>; 65 66def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB; 67 68def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB; 69def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB, 70 Requires<[In64BitMode]>; 71} // SchedRW 72 73def : Pat<(debugtrap), 74 (INT3)>, Requires<[NotPS]>; 75def : Pat<(debugtrap), 76 (INT (i8 0x41))>, Requires<[IsPS]>; 77 78//===----------------------------------------------------------------------===// 79// Input/Output Instructions. 80// 81let SchedRW = [WriteSystem] in { 82let Defs = [AL], Uses = [DX] in 83def IN8rr : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>; 84let Defs = [AX], Uses = [DX] in 85def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>, 86 OpSize16; 87let Defs = [EAX], Uses = [DX] in 88def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>, 89 OpSize32; 90 91let Defs = [AL] in 92def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port), 93 "in{b}\t{$port, %al|al, $port}", []>; 94let Defs = [AX] in 95def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), 96 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16; 97let Defs = [EAX] in 98def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), 99 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32; 100 101let Uses = [DX, AL] in 102def OUT8rr : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>; 103let Uses = [DX, AX] in 104def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>, 105 OpSize16; 106let Uses = [DX, EAX] in 107def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>, 108 OpSize32; 109 110let Uses = [AL] in 111def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port), 112 "out{b}\t{%al, $port|$port, al}", []>; 113let Uses = [AX] in 114def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), 115 "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16; 116let Uses = [EAX] in 117def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), 118 "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32; 119 120} // SchedRW 121 122//===----------------------------------------------------------------------===// 123// Moves to and from debug registers 124 125let SchedRW = [WriteSystem] in { 126def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src), 127 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 128 Requires<[Not64BitMode]>; 129def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src), 130 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 131 Requires<[In64BitMode]>; 132 133def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src), 134 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 135 Requires<[Not64BitMode]>; 136def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src), 137 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 138 Requires<[In64BitMode]>; 139} // SchedRW 140 141//===----------------------------------------------------------------------===// 142// Moves to and from control registers 143 144let SchedRW = [WriteSystem] in { 145def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src), 146 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 147 Requires<[Not64BitMode]>; 148def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src), 149 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 150 Requires<[In64BitMode]>; 151 152def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src), 153 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 154 Requires<[Not64BitMode]>; 155def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src), 156 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 157 Requires<[In64BitMode]>; 158} // SchedRW 159 160//===----------------------------------------------------------------------===// 161// Segment override instruction prefixes 162 163let SchedRW = [WriteNop] in { 164def CS_PREFIX : I<0x2E, PrefixByte, (outs), (ins), "cs", []>; 165def SS_PREFIX : I<0x36, PrefixByte, (outs), (ins), "ss", []>; 166def DS_PREFIX : I<0x3E, PrefixByte, (outs), (ins), "ds", []>; 167def ES_PREFIX : I<0x26, PrefixByte, (outs), (ins), "es", []>; 168def FS_PREFIX : I<0x64, PrefixByte, (outs), (ins), "fs", []>; 169def GS_PREFIX : I<0x65, PrefixByte, (outs), (ins), "gs", []>; 170} // SchedRW 171 172//===----------------------------------------------------------------------===// 173// Address-size override prefixes. 174// 175 176let SchedRW = [WriteNop] in { 177def ADDR16_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr16", []>, 178 Requires<[In32BitMode]>; 179def ADDR32_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr32", []>, 180 Requires<[In64BitMode]>; 181} // SchedRW 182 183//===----------------------------------------------------------------------===// 184// Moves to and from segment registers. 185// 186 187let SchedRW = [WriteMove] in { 188def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src), 189 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 190def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src), 191 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 192def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src), 193 "mov{q}\t{$src, $dst|$dst, $src}", []>; 194let mayStore = 1 in { 195def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src), 196 "mov{w}\t{$src, $dst|$dst, $src}", []>; 197} 198def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), 199 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 200def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src), 201 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 202def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src), 203 "mov{q}\t{$src, $dst|$dst, $src}", []>; 204let mayLoad = 1 in { 205def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src), 206 "mov{w}\t{$src, $dst|$dst, $src}", []>; 207} 208} // SchedRW 209 210//===----------------------------------------------------------------------===// 211// Segmentation support instructions. 212 213let SchedRW = [WriteSystem] in { 214def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB; 215 216let mayLoad = 1 in 217def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 218 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, 219 OpSize16, NotMemoryFoldable; 220def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src), 221 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, 222 OpSize16, NotMemoryFoldable; 223 224let mayLoad = 1 in 225def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 226 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB, 227 OpSize32, NotMemoryFoldable; 228def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src), 229 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB, 230 OpSize32, NotMemoryFoldable; 231let mayLoad = 1 in 232def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 233 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 234def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src), 235 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 236 237let mayLoad = 1 in 238def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 239 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, 240 OpSize16, NotMemoryFoldable; 241def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src), 242 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, 243 OpSize16, NotMemoryFoldable; 244let mayLoad = 1 in 245def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 246 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB, 247 OpSize32, NotMemoryFoldable; 248def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src), 249 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB, 250 OpSize32, NotMemoryFoldable; 251let mayLoad = 1 in 252def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 253 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 254def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src), 255 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 256 257def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB; 258 259def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), 260 "str{w}\t$dst", []>, TB, OpSize16; 261def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), 262 "str{l}\t$dst", []>, TB, OpSize32; 263def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), 264 "str{q}\t$dst", []>, TB; 265let mayStore = 1 in 266def STRm : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB; 267 268def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable; 269let mayLoad = 1 in 270def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable; 271 272def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>, 273 OpSize16, Requires<[Not64BitMode]>; 274def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>, 275 OpSize32, Requires<[Not64BitMode]>; 276def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>, 277 OpSize16, Requires<[Not64BitMode]>; 278def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>, 279 OpSize32, Requires<[Not64BitMode]>; 280def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>, 281 OpSize16, Requires<[Not64BitMode]>; 282def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>, 283 OpSize32, Requires<[Not64BitMode]>; 284def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>, 285 OpSize16, Requires<[Not64BitMode]>; 286def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>, 287 OpSize32, Requires<[Not64BitMode]>; 288def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>, 289 OpSize16, TB; 290def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB, 291 OpSize32, Requires<[Not64BitMode]>; 292def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>, 293 OpSize16, TB; 294def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB, 295 OpSize32, Requires<[Not64BitMode]>; 296def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB, 297 OpSize32, Requires<[In64BitMode]>; 298def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB, 299 OpSize32, Requires<[In64BitMode]>; 300 301// No "pop cs" instruction. 302def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>, 303 OpSize16, Requires<[Not64BitMode]>; 304def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>, 305 OpSize32, Requires<[Not64BitMode]>; 306 307def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>, 308 OpSize16, Requires<[Not64BitMode]>; 309def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>, 310 OpSize32, Requires<[Not64BitMode]>; 311 312def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>, 313 OpSize16, Requires<[Not64BitMode]>; 314def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>, 315 OpSize32, Requires<[Not64BitMode]>; 316 317def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>, 318 OpSize16, TB; 319def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB, 320 OpSize32, Requires<[Not64BitMode]>; 321def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB, 322 OpSize32, Requires<[In64BitMode]>; 323 324def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>, 325 OpSize16, TB; 326def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB, 327 OpSize32, Requires<[Not64BitMode]>; 328def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB, 329 OpSize32, Requires<[In64BitMode]>; 330 331def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 332 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 333 Requires<[Not64BitMode]>; 334def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 335 "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 336 Requires<[Not64BitMode]>; 337 338def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 339 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; 340def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 341 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; 342def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), 343 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB; 344 345def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 346 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 347 Requires<[Not64BitMode]>; 348def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 349 "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 350 Requires<[Not64BitMode]>; 351 352def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 353 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; 354def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 355 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; 356def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), 357 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB; 358 359def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 360 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; 361def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 362 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; 363 364def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), 365 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB; 366 367def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable; 368def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable; 369let mayLoad = 1 in { 370def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable; 371def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable; 372} 373} // SchedRW 374 375//===----------------------------------------------------------------------===// 376// Descriptor-table support instructions 377 378let SchedRW = [WriteSystem] in { 379def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), 380 "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; 381def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), 382 "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; 383def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), 384 "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; 385def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), 386 "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; 387def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), 388 "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; 389def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), 390 "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; 391def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins), 392 "sldt{w}\t$dst", []>, TB, OpSize16; 393let mayStore = 1 in 394def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst), 395 "sldt{w}\t$dst", []>, TB; 396def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins), 397 "sldt{l}\t$dst", []>, OpSize32, TB; 398 399// LLDT is not interpreted specially in 64-bit mode because there is no sign 400// extension. 401def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins), 402 "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>; 403 404def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), 405 "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; 406def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), 407 "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; 408def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), 409 "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>; 410def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), 411 "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; 412def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), 413 "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; 414def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), 415 "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>; 416def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src), 417 "lldt{w}\t$src", []>, TB, NotMemoryFoldable; 418let mayLoad = 1 in 419def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src), 420 "lldt{w}\t$src", []>, TB, NotMemoryFoldable; 421} // SchedRW 422 423//===----------------------------------------------------------------------===// 424// Specialized register support 425let SchedRW = [WriteSystem] in { 426let Uses = [EAX, ECX, EDX] in 427def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB; 428let Uses = [EAX, ECX, EDX] in 429def WRMSRNS : I<0x01, MRM_C6, (outs), (ins), "wrmsrns", []>, PS; 430let Defs = [EAX, EDX], Uses = [ECX] in 431def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB; 432 433let Uses = [RSI, RDI, RCX], Predicates = [In64BitMode] in { 434def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, XS; 435def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, XD; 436} 437 438let Defs = [RAX, RDX], Uses = [ECX] in 439def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB; 440 441def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins), 442 "smsw{w}\t$dst", []>, OpSize16, TB; 443def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins), 444 "smsw{l}\t$dst", []>, OpSize32, TB; 445// no m form encodable; use SMSW16m 446def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins), 447 "smsw{q}\t$dst", []>, TB; 448 449// For memory operands, there is only a 16-bit form 450def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst), 451 "smsw{w}\t$dst", []>, TB; 452 453def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src), 454 "lmsw{w}\t$src", []>, TB, NotMemoryFoldable; 455let mayLoad = 1 in 456def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src), 457 "lmsw{w}\t$src", []>, TB, NotMemoryFoldable; 458 459let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in 460 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB; 461} // SchedRW 462 463//===----------------------------------------------------------------------===// 464// Cache instructions 465let SchedRW = [WriteSystem] in { 466def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB; 467def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, PS; 468 469// wbnoinvd is like wbinvd, except without invalidation 470// encoding: like wbinvd + an 0xF3 prefix 471def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd", 472 [(int_x86_wbnoinvd)]>, XS, 473 Requires<[HasWBNOINVD]>; 474} // SchedRW 475 476//===----------------------------------------------------------------------===// 477// CET instructions 478// Use with caution, availability is not predicated on features. 479let SchedRW = [WriteSystem] in { 480 let Uses = [SSP] in { 481 let Defs = [SSP] in { 482 def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src", 483 [(int_x86_incsspd GR32:$src)]>, XS; 484 def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src", 485 [(int_x86_incsspq GR64:$src)]>, XS; 486 } // Defs SSP 487 488 let Constraints = "$src = $dst" in { 489 def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src), 490 "rdsspd\t$dst", 491 [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS; 492 def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src), 493 "rdsspq\t$dst", 494 [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS; 495 } 496 497 let Defs = [SSP] in { 498 def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp", 499 [(int_x86_saveprevssp)]>, XS; 500 def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src), 501 "rstorssp\t$src", 502 [(int_x86_rstorssp addr:$src)]>, XS; 503 } // Defs SSP 504 } // Uses SSP 505 506 def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 507 "wrssd\t{$src, $dst|$dst, $src}", 508 [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS; 509 def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 510 "wrssq\t{$src, $dst|$dst, $src}", 511 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS; 512 def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 513 "wrussd\t{$src, $dst|$dst, $src}", 514 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD; 515 def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 516 "wrussq\t{$src, $dst|$dst, $src}", 517 [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD; 518 519 let Defs = [SSP] in { 520 let Uses = [SSP] in { 521 def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy", 522 [(int_x86_setssbsy)]>, XS; 523 } // Uses SSP 524 525 def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src), 526 "clrssbsy\t$src", 527 [(int_x86_clrssbsy addr:$src)]>, XS; 528 } // Defs SSP 529} // SchedRW 530 531let SchedRW = [WriteSystem] in { 532 def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS; 533 def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS; 534} // SchedRW 535 536//===----------------------------------------------------------------------===// 537// XSAVE instructions 538let SchedRW = [WriteSystem] in { 539// NOTE: No HasXSAVE predicate so that these can be used with _xgetbv/_xsetbv 540// on Windows without needing to enable the xsave feature to be compatible with 541// MSVC. 542let Defs = [EDX, EAX], Uses = [ECX] in 543def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, PS; 544 545let Uses = [EDX, EAX, ECX] in 546def XSETBV : I<0x01, MRM_D1, (outs), (ins), 547 "xsetbv", 548 [(int_x86_xsetbv ECX, EDX, EAX)]>, PS; 549 550 551let Uses = [EDX, EAX] in { 552def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst), 553 "xsave\t$dst", 554 [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; 555def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst), 556 "xsave64\t$dst", 557 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; 558def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst), 559 "xrstor\t$dst", 560 [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; 561def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst), 562 "xrstor64\t$dst", 563 [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; 564def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst), 565 "xsaveopt\t$dst", 566 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>; 567def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst), 568 "xsaveopt64\t$dst", 569 [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>; 570def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst), 571 "xsavec\t$dst", 572 [(int_x86_xsavec addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEC]>; 573def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst), 574 "xsavec64\t$dst", 575 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEC, In64BitMode]>; 576def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst), 577 "xsaves\t$dst", 578 [(int_x86_xsaves addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES]>; 579def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst), 580 "xsaves64\t$dst", 581 [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; 582def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst), 583 "xrstors\t$dst", 584 [(int_x86_xrstors addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES]>; 585def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst), 586 "xrstors64\t$dst", 587 [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES, In64BitMode]>; 588} // Uses 589} // SchedRW 590 591//===----------------------------------------------------------------------===// 592// VIA PadLock crypto instructions 593let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in 594 def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB; 595 596def : InstAlias<"xstorerng", (XSTORE)>; 597 598let SchedRW = [WriteSystem] in { 599let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in { 600 def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB, REP; 601 def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB, REP; 602 def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB, REP; 603 def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB, REP; 604 def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB, REP; 605} 606 607let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in { 608 def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB, REP; 609 def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB, REP; 610} 611let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in 612 def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB, REP; 613} // SchedRW 614 615//==-----------------------------------------------------------------------===// 616// PKU - enable protection key 617let SchedRW = [WriteSystem] in { 618let Defs = [EAX, EDX], Uses = [ECX] in 619 def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", 620 [(set EAX, (X86rdpkru ECX)), (implicit EDX)]>, PS; 621let Uses = [EAX, ECX, EDX] in 622 def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", 623 [(X86wrpkru EAX, EDX, ECX)]>, PS; 624} // SchedRW 625 626//===----------------------------------------------------------------------===// 627// FS/GS Base Instructions 628let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in { 629 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins), 630 "rdfsbase{l}\t$dst", 631 [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS; 632 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins), 633 "rdfsbase{q}\t$dst", 634 [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS; 635 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), 636 "rdgsbase{l}\t$dst", 637 [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS; 638 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins), 639 "rdgsbase{q}\t$dst", 640 [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS; 641 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src), 642 "wrfsbase{l}\t$src", 643 [(int_x86_wrfsbase_32 GR32:$src)]>, XS; 644 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src), 645 "wrfsbase{q}\t$src", 646 [(int_x86_wrfsbase_64 GR64:$src)]>, XS; 647 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src), 648 "wrgsbase{l}\t$src", 649 [(int_x86_wrgsbase_32 GR32:$src)]>, XS; 650 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src), 651 "wrgsbase{q}\t$src", 652 [(int_x86_wrgsbase_64 GR64:$src)]>, XS; 653} 654 655//===----------------------------------------------------------------------===// 656// INVPCID Instruction 657let SchedRW = [WriteSystem] in { 658def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), 659 "invpcid\t{$src2, $src1|$src1, $src2}", 660 [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD, 661 Requires<[Not64BitMode, HasINVPCID]>; 662def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 663 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD, 664 Requires<[In64BitMode, HasINVPCID]>; 665} // SchedRW 666 667let Predicates = [In64BitMode, HasINVPCID] in { 668 // The instruction can only use a 64 bit register as the register argument 669 // in 64 bit mode, while the intrinsic only accepts a 32 bit argument 670 // corresponding to it. 671 // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID 672 // type),/ so it doesn't hurt us that one can't supply a 64 bit value here. 673 def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2), 674 (INVPCID64 675 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit), 676 addr:$src2)>; 677} 678 679 680//===----------------------------------------------------------------------===// 681// SMAP Instruction 682let Defs = [EFLAGS], SchedRW = [WriteSystem] in { 683 def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, PS; 684 def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, PS; 685} 686 687//===----------------------------------------------------------------------===// 688// SMX Instruction 689let SchedRW = [WriteSystem] in { 690let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in { 691 def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, PS; 692} // Uses, Defs 693} // SchedRW 694 695//===----------------------------------------------------------------------===// 696// TS flag control instruction. 697let SchedRW = [WriteSystem] in { 698def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB; 699} 700 701//===----------------------------------------------------------------------===// 702// IF (inside EFLAGS) management instructions. 703let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in { 704def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>; 705def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>; 706} 707 708//===----------------------------------------------------------------------===// 709// RDPID Instruction 710let SchedRW = [WriteSystem] in { 711def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins), 712 "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS, 713 Requires<[Not64BitMode, HasRDPID]>; 714def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS, 715 Requires<[In64BitMode, HasRDPID]>; 716} // SchedRW 717 718let Predicates = [In64BitMode, HasRDPID] in { 719 // Due to silly instruction definition, we have to compensate for the 720 // instruction outputing a 64-bit register. 721 def : Pat<(int_x86_rdpid), 722 (EXTRACT_SUBREG (RDPID64), sub_32bit)>; 723} 724 725 726//===----------------------------------------------------------------------===// 727// PTWRITE Instruction - Write Data to a Processor Trace Packet 728let SchedRW = [WriteSystem] in { 729def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst), 730 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS, 731 Requires<[HasPTWRITE]>; 732def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst), 733 "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS, 734 Requires<[In64BitMode, HasPTWRITE]>; 735 736def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst), 737 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS, 738 Requires<[HasPTWRITE]>; 739def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst), 740 "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS, 741 Requires<[In64BitMode, HasPTWRITE]>; 742} // SchedRW 743 744//===----------------------------------------------------------------------===// 745// RDPRU - Read Processor Register instruction. 746 747let SchedRW = [WriteSystem] in { 748let Uses = [ECX], Defs = [EAX, EDX] in 749 def RDPRU : I<0x01, MRM_FD, (outs), (ins), "rdpru", []>, PS, 750 Requires<[HasRDPRU]>; 751} 752 753//===----------------------------------------------------------------------===// 754// Platform Configuration instruction 755 756// From ISA docs: 757// "This instruction is used to execute functions for configuring platform 758// features. 759// EAX: Leaf function to be invoked. 760// RBX/RCX/RDX: Leaf-specific purpose." 761// "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF, 762// AF, OF, and SF are cleared. In case of failure, the failure reason is 763// indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared." 764// Thus all these mentioned registers are considered clobbered. 765 766let SchedRW = [WriteSystem] in { 767let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in 768 def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, PS, 769 Requires<[HasPCONFIG]>; 770} // SchedRW 771