xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86InstrSystem.td (revision 7a6dacaca14b62ca4b74406814becb87a3fefac0) 
1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 instructions that are generally used in
10// privileged modes.  These are not typically used by the compiler, but are
11// supported for the assembler and disassembler.
12//
13//===----------------------------------------------------------------------===//
14
15let SchedRW = [WriteSystem] in {
16let Defs = [RAX, RDX] in
17def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
18
19let Defs = [RAX, RCX, RDX] in
20def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
21
22// CPU flow control instructions
23
24let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
25  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26
27  def UD1Wm   : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
28                  "ud1{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
29  def UD1Lm   : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
30                  "ud1{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
31  def UD1Qm   : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
32                   "ud1{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
33
34  def UD1Wr   : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
35                  "ud1{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
36  def UD1Lr   : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
37                  "ud1{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
38  def UD1Qr   : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
39                   "ud1{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
40}
41
42let isTerminator = 1 in
43  def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
44def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
45
46// Interrupt and SysCall Instructions.
47let Uses = [EFLAGS] in
48  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
49
50def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
51
52def UBSAN_UD1 : PseudoI<(outs), (ins i32imm:$kind), [(ubsantrap (i32 timm:$kind))]>;
53// The long form of "int $3" turns into int3 as a size optimization.
54// FIXME: This doesn't work because InstAlias can't match immediate constants.
55//def : InstAlias<"int\t$3", (INT3)>;
56
57def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
58              [(int_x86_int timm:$trap)]>;
59
60
61def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
62def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB;
63def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
64               Requires<[In64BitMode]>;
65
66def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
67
68def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
69def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
70                  Requires<[In64BitMode]>;
71} // SchedRW
72
73def : Pat<(debugtrap),
74          (INT3)>, Requires<[NotPS]>;
75def : Pat<(debugtrap),
76          (INT (i8 0x41))>, Requires<[IsPS]>;
77
78//===----------------------------------------------------------------------===//
79//  Input/Output Instructions.
80//
81let SchedRW = [WriteSystem] in {
82let Defs = [AL], Uses = [DX] in
83def IN8rr  : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>;
84let Defs = [AX], Uses = [DX] in
85def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>,
86               OpSize16;
87let Defs = [EAX], Uses = [DX] in
88def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>,
89               OpSize32;
90
91let Defs = [AL] in
92def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
93                 "in{b}\t{$port, %al|al, $port}", []>;
94let Defs = [AX] in
95def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
96                 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
97let Defs = [EAX] in
98def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
99                 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
100
101let Uses = [DX, AL] in
102def OUT8rr  : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>;
103let Uses = [DX, AX] in
104def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>,
105                OpSize16;
106let Uses = [DX, EAX] in
107def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>,
108                OpSize32;
109
110let Uses = [AL] in
111def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
112                   "out{b}\t{%al, $port|$port, al}", []>;
113let Uses = [AX] in
114def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
115                   "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
116let Uses = [EAX] in
117def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
118                  "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
119
120} // SchedRW
121
122//===----------------------------------------------------------------------===//
123// Moves to and from debug registers
124
125let SchedRW = [WriteSystem] in {
126def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
127                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
128                Requires<[Not64BitMode]>;
129def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
130                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
131                Requires<[In64BitMode]>;
132
133def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
134                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
135                Requires<[Not64BitMode]>;
136def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
137                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
138                Requires<[In64BitMode]>;
139} // SchedRW
140
141//===----------------------------------------------------------------------===//
142// Moves to and from control registers
143
144let SchedRW = [WriteSystem] in {
145def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
146                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
147                Requires<[Not64BitMode]>;
148def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
149                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
150                Requires<[In64BitMode]>;
151
152def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
153                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
154                Requires<[Not64BitMode]>;
155def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
156                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
157                Requires<[In64BitMode]>;
158} // SchedRW
159
160//===----------------------------------------------------------------------===//
161// Segment override instruction prefixes
162
163let SchedRW = [WriteNop] in {
164def CS_PREFIX : I<0x2E, PrefixByte, (outs), (ins), "cs", []>;
165def SS_PREFIX : I<0x36, PrefixByte, (outs), (ins), "ss", []>;
166def DS_PREFIX : I<0x3E, PrefixByte, (outs), (ins), "ds", []>;
167def ES_PREFIX : I<0x26, PrefixByte, (outs), (ins), "es", []>;
168def FS_PREFIX : I<0x64, PrefixByte, (outs), (ins), "fs", []>;
169def GS_PREFIX : I<0x65, PrefixByte, (outs), (ins), "gs", []>;
170} // SchedRW
171
172//===----------------------------------------------------------------------===//
173// Address-size override prefixes.
174//
175
176let SchedRW = [WriteNop] in {
177def ADDR16_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr16", []>,
178                      Requires<[In32BitMode]>;
179def ADDR32_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr32", []>,
180                      Requires<[In64BitMode]>;
181} // SchedRW
182
183//===----------------------------------------------------------------------===//
184// Moves to and from segment registers.
185//
186
187let SchedRW = [WriteMove] in {
188def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
189                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
190def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
191                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
192def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
193                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
194let mayStore = 1 in {
195def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
196                "mov{w}\t{$src, $dst|$dst, $src}", []>;
197}
198def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
199                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
200def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
201                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
202def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
203                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
204let mayLoad = 1 in {
205def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
206                "mov{w}\t{$src, $dst|$dst, $src}", []>;
207}
208} // SchedRW
209
210//===----------------------------------------------------------------------===//
211// Segmentation support instructions.
212
213let SchedRW = [WriteSystem] in {
214def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
215
216let mayLoad = 1 in
217def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
218                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
219                OpSize16;
220def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src),
221                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
222                OpSize16;
223
224let mayLoad = 1 in
225def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
226                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
227                OpSize32;
228def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src),
229                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
230                OpSize32;
231let mayLoad = 1 in
232def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
233                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
234def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src),
235                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
236
237let mayLoad = 1 in
238def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
239                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
240                OpSize16;
241def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src),
242                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
243                OpSize16;
244let mayLoad = 1 in
245def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
246                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
247                OpSize32;
248def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src),
249                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
250                OpSize32;
251let mayLoad = 1 in
252def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
253                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
254def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src),
255                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
256
257def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
258
259def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
260               "str{w}\t$dst", []>, TB, OpSize16;
261def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
262               "str{l}\t$dst", []>, TB, OpSize32;
263def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
264                "str{q}\t$dst", []>, TB;
265let mayStore = 1 in
266def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB;
267
268def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB;
269let mayLoad = 1 in
270def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB;
271
272def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>,
273                 OpSize16, Requires<[Not64BitMode]>;
274def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>,
275                 OpSize32, Requires<[Not64BitMode]>;
276def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>,
277                 OpSize16, Requires<[Not64BitMode]>;
278def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>,
279                 OpSize32, Requires<[Not64BitMode]>;
280def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>,
281                 OpSize16, Requires<[Not64BitMode]>;
282def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>,
283                 OpSize32, Requires<[Not64BitMode]>;
284def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>,
285                 OpSize16, Requires<[Not64BitMode]>;
286def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>,
287                 OpSize32, Requires<[Not64BitMode]>;
288def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>,
289                 OpSize16, TB;
290def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB,
291                 OpSize32, Requires<[Not64BitMode]>;
292def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>,
293                 OpSize16, TB;
294def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB,
295                 OpSize32, Requires<[Not64BitMode]>;
296def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB,
297                 OpSize32, Requires<[In64BitMode]>;
298def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB,
299                 OpSize32, Requires<[In64BitMode]>;
300
301// No "pop cs" instruction.
302def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>,
303              OpSize16, Requires<[Not64BitMode]>;
304def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>,
305              OpSize32, Requires<[Not64BitMode]>;
306
307def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>,
308              OpSize16, Requires<[Not64BitMode]>;
309def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>,
310              OpSize32, Requires<[Not64BitMode]>;
311
312def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>,
313              OpSize16, Requires<[Not64BitMode]>;
314def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>,
315              OpSize32, Requires<[Not64BitMode]>;
316
317def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>,
318                OpSize16, TB;
319def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB,
320                OpSize32, Requires<[Not64BitMode]>;
321def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB,
322                OpSize32, Requires<[In64BitMode]>;
323
324def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>,
325                OpSize16, TB;
326def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB,
327                OpSize32, Requires<[Not64BitMode]>;
328def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB,
329                OpSize32, Requires<[In64BitMode]>;
330
331def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
332                "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
333                Requires<[Not64BitMode]>;
334def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
335                "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
336                Requires<[Not64BitMode]>;
337
338def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
339                "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
340def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
341                "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
342def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
343                 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
344
345def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
346                "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
347                Requires<[Not64BitMode]>;
348def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
349                "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
350                Requires<[Not64BitMode]>;
351
352def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
353                "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
354def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
355                "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
356def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
357                 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
358
359def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
360                "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
361def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
362                "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
363
364def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
365                 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
366
367def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB;
368def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB;
369let mayLoad = 1 in {
370def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB;
371def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB;
372}
373} // SchedRW
374
375//===----------------------------------------------------------------------===//
376// Descriptor-table support instructions
377
378let SchedRW = [WriteSystem] in {
379def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
380                "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
381def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
382                "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
383def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
384                "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
385def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
386                "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
387def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
388                "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
389def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
390                "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
391def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
392                "sldt{w}\t$dst", []>, TB, OpSize16;
393let mayStore = 1 in
394def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
395                "sldt{w}\t$dst", []>, TB;
396def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
397                "sldt{l}\t$dst", []>, OpSize32, TB;
398
399// LLDT is not interpreted specially in 64-bit mode because there is no sign
400//   extension.
401def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
402                 "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
403
404def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
405                "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
406def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
407                "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
408def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
409                "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
410def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
411                "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
412def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
413                "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
414def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
415                "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
416def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
417                "lldt{w}\t$src", []>, TB;
418let mayLoad = 1 in
419def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
420                "lldt{w}\t$src", []>, TB;
421} // SchedRW
422
423//===----------------------------------------------------------------------===//
424// Specialized register support
425let SchedRW = [WriteSystem] in {
426let Uses = [EAX, ECX, EDX] in
427def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
428let Uses = [EAX, ECX, EDX] in
429def WRMSRNS : I<0x01, MRM_C6, (outs), (ins), "wrmsrns", []>, TB;
430let Defs = [EAX, EDX], Uses = [ECX] in
431def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
432let Defs = [RAX, EFLAGS], Uses = [RBX, RCX], Predicates = [In64BitMode] in
433def PBNDKB : I<0x01, MRM_C7, (outs), (ins), "pbndkb", []>, TB;
434let Uses = [RSI, RDI, RCX], Predicates = [In64BitMode] in {
435def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
436def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
437}
438
439let Predicates = [HasUSERMSR], mayLoad = 1 in {
440  def URDMSRrr : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
441                "urdmsr\t{$src, $dst|$dst, $src}",
442                [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T8, XD;
443  def URDMSRri : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
444                "urdmsr\t{$imm, $dst|$dst, $imm}",
445                [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, VEX;
446}
447let Predicates = [HasUSERMSR], mayStore = 1 in {
448  def UWRMSRrr : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
449                "uwrmsr\t{$src2, $src1|$src1, $src2}",
450                [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T8, XS;
451  def UWRMSRir : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
452                "uwrmsr\t{$src, $imm|$imm, $src}",
453                [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, VEX;
454}
455let Defs = [RAX, RDX], Uses = [ECX] in
456def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
457
458def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
459                "smsw{w}\t$dst", []>, OpSize16, TB;
460def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
461                "smsw{l}\t$dst", []>, OpSize32, TB;
462// no m form encodable; use SMSW16m
463def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
464                 "smsw{q}\t$dst", []>, TB;
465
466// For memory operands, there is only a 16-bit form
467def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
468                "smsw{w}\t$dst", []>, TB;
469
470def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
471                "lmsw{w}\t$src", []>, TB;
472let mayLoad = 1 in
473def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
474                "lmsw{w}\t$src", []>, TB;
475
476let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
477  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
478} // SchedRW
479
480//===----------------------------------------------------------------------===//
481// Cache instructions
482let SchedRW = [WriteSystem] in {
483def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
484def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, TB, PS;
485
486// wbnoinvd is like wbinvd, except without invalidation
487// encoding: like wbinvd + an 0xF3 prefix
488def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd",
489                 [(int_x86_wbnoinvd)]>, TB, XS,
490                 Requires<[HasWBNOINVD]>;
491} // SchedRW
492
493//===----------------------------------------------------------------------===//
494// CET instructions
495// Use with caution, availability is not predicated on features.
496let SchedRW = [WriteSystem] in {
497  let Uses = [SSP] in {
498    let Defs = [SSP] in {
499      def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
500                       [(int_x86_incsspd GR32:$src)]>, TB, XS;
501      def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
502                       [(int_x86_incsspq GR64:$src)]>, TB, XS;
503    } // Defs SSP
504
505    let Constraints = "$src = $dst" in {
506      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
507                     "rdsspd\t$dst",
508                     [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, TB, XS;
509      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
510                     "rdsspq\t$dst",
511                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, TB, XS;
512    }
513
514    let Defs = [SSP] in {
515      def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
516                       [(int_x86_saveprevssp)]>, TB, XS;
517      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
518                       "rstorssp\t$src",
519                       [(int_x86_rstorssp addr:$src)]>, TB, XS;
520    } // Defs SSP
521  } // Uses SSP
522
523let Predicates = [NoEGPR] in {
524  def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
525                "wrssd\t{$src, $dst|$dst, $src}",
526                [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8;
527  def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
528                 "wrssq\t{$src, $dst|$dst, $src}",
529                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8;
530  def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
531                 "wrussd\t{$src, $dst|$dst, $src}",
532                 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8, PD;
533  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
534                  "wrussq\t{$src, $dst|$dst, $src}",
535                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8, PD;
536}
537
538let Predicates = [HasEGPR, In64BitMode] in {
539  def WRSSD_EVEX : I<0x66, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
540                     "wrssd\t{$src, $dst|$dst, $src}",
541                     [(int_x86_wrssd GR32:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4;
542  def WRSSQ_EVEX : RI<0x66, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
543                      "wrssq\t{$src, $dst|$dst, $src}",
544                      [(int_x86_wrssq GR64:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4;
545  def WRUSSD_EVEX : I<0x65, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
546                      "wrussd\t{$src, $dst|$dst, $src}",
547                      [(int_x86_wrussd GR32:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4, PD;
548  def WRUSSQ_EVEX : RI<0x65, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
549                       "wrussq\t{$src, $dst|$dst, $src}",
550                       [(int_x86_wrussq GR64:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4, PD;
551}
552
553  let Defs = [SSP] in {
554    let Uses = [SSP] in {
555        def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
556                         [(int_x86_setssbsy)]>, TB, XS;
557    } // Uses SSP
558
559    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
560                     "clrssbsy\t$src",
561                     [(int_x86_clrssbsy addr:$src)]>, TB, XS;
562  } // Defs SSP
563} // SchedRW
564
565let SchedRW = [WriteSystem] in {
566    def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, TB, XS;
567    def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, TB, XS;
568} // SchedRW
569
570//===----------------------------------------------------------------------===//
571// XSAVE instructions
572let SchedRW = [WriteSystem] in {
573// NOTE: No HasXSAVE predicate so that these can be used with _xgetbv/_xsetbv
574// on Windows without needing to enable the xsave feature to be compatible with
575// MSVC.
576let Defs = [EDX, EAX], Uses = [ECX] in
577def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
578
579let Uses = [EDX, EAX, ECX] in
580def XSETBV : I<0x01, MRM_D1, (outs), (ins),
581              "xsetbv",
582              [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
583
584
585let Uses = [EDX, EAX] in {
586def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
587              "xsave\t$dst",
588              [(int_x86_xsave addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE]>;
589def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
590                 "xsave64\t$dst",
591                 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
592def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
593               "xrstor\t$dst",
594               [(int_x86_xrstor addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE]>;
595def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
596                  "xrstor64\t$dst",
597                  [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
598def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
599                 "xsaveopt\t$dst",
600                 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEOPT]>;
601def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
602                    "xsaveopt64\t$dst",
603                    [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEOPT, In64BitMode]>;
604def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
605               "xsavec\t$dst",
606               [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>;
607def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
608                 "xsavec64\t$dst",
609                 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>;
610def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
611               "xsaves\t$dst",
612               [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
613def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
614                  "xsaves64\t$dst",
615                  [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
616def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
617                "xrstors\t$dst",
618                [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
619def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
620                   "xrstors64\t$dst",
621                   [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>;
622} // Uses
623} // SchedRW
624
625//===----------------------------------------------------------------------===//
626// VIA PadLock crypto instructions
627let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
628  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
629
630def : InstAlias<"xstorerng", (XSTORE)>;
631
632let SchedRW = [WriteSystem] in {
633let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
634  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB, REP;
635  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB, REP;
636  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB, REP;
637  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB, REP;
638  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB, REP;
639}
640
641let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
642  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB, REP;
643  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB, REP;
644}
645let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
646  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB, REP;
647} // SchedRW
648
649//==-----------------------------------------------------------------------===//
650// PKU  - enable protection key
651let SchedRW = [WriteSystem] in {
652let Defs = [EAX, EDX], Uses = [ECX] in
653  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru",
654                  [(set EAX, (X86rdpkru ECX)), (implicit EDX)]>, TB;
655let Uses = [EAX, ECX, EDX] in
656  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru",
657                  [(X86wrpkru EAX, EDX, ECX)]>, TB;
658} // SchedRW
659
660//===----------------------------------------------------------------------===//
661// FS/GS Base Instructions
662let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
663  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
664                   "rdfsbase{l}\t$dst",
665                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS;
666  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
667                     "rdfsbase{q}\t$dst",
668                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS;
669  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
670                   "rdgsbase{l}\t$dst",
671                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS;
672  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
673                     "rdgsbase{q}\t$dst",
674                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS;
675  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
676                   "wrfsbase{l}\t$src",
677                   [(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS;
678  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
679                      "wrfsbase{q}\t$src",
680                      [(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS;
681  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
682                   "wrgsbase{l}\t$src",
683                   [(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS;
684  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
685                      "wrgsbase{q}\t$src",
686                      [(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS;
687}
688
689//===----------------------------------------------------------------------===//
690// INVPCID Instruction
691let SchedRW = [WriteSystem] in {
692def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
693                  "invpcid\t{$src2, $src1|$src1, $src2}",
694                  [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8, PD,
695                  Requires<[Not64BitMode, HasINVPCID]>;
696def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
697                  "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8, PD,
698                  Requires<[In64BitMode]>;
699
700def INVPCID64_EVEX : I<0xF2, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
701                       "invpcid\t{$src2, $src1|$src1, $src2}", []>,
702                     EVEX, NoCD8, T_MAP4, XS, Requires<[In64BitMode]>;
703} // SchedRW
704
705let Predicates = [HasINVPCID, NoEGPR] in {
706  // The instruction can only use a 64 bit register as the register argument
707  // in 64 bit mode, while the intrinsic only accepts a 32 bit argument
708  // corresponding to it.
709  // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID
710  // type),/ so it doesn't hurt us that one can't supply a 64 bit value here.
711  def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
712            (INVPCID64
713              (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit),
714              addr:$src2)>;
715}
716
717let Predicates = [HasINVPCID, HasEGPR] in {
718  def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
719            (INVPCID64_EVEX
720              (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit),
721              addr:$src2)>;
722}
723
724
725//===----------------------------------------------------------------------===//
726// SMAP Instruction
727let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
728  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
729  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
730}
731
732//===----------------------------------------------------------------------===//
733// SMX Instruction
734let SchedRW = [WriteSystem] in {
735let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
736  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
737} // Uses, Defs
738} // SchedRW
739
740//===----------------------------------------------------------------------===//
741// TS flag control instruction.
742let SchedRW = [WriteSystem] in {
743def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
744}
745
746//===----------------------------------------------------------------------===//
747// IF (inside EFLAGS) management instructions.
748let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
749def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
750def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
751}
752
753//===----------------------------------------------------------------------===//
754// RDPID Instruction
755let SchedRW = [WriteSystem] in {
756def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
757                "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, TB, XS,
758                Requires<[Not64BitMode, HasRDPID]>;
759def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, TB, XS,
760                Requires<[In64BitMode, HasRDPID]>;
761} // SchedRW
762
763let Predicates = [In64BitMode, HasRDPID] in {
764  // Due to silly instruction definition, we have to compensate for the
765  // instruction outputing a 64-bit register.
766  def : Pat<(int_x86_rdpid),
767            (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
768}
769
770
771//===----------------------------------------------------------------------===//
772// PTWRITE Instruction - Write Data to a Processor Trace Packet
773let SchedRW = [WriteSystem] in {
774def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
775                "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, TB, XS,
776                Requires<[HasPTWRITE]>;
777def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
778                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, TB, XS,
779                    Requires<[In64BitMode, HasPTWRITE]>;
780
781def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
782                 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, TB, XS,
783                    Requires<[HasPTWRITE]>;
784def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
785                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, TB, XS,
786                    Requires<[In64BitMode, HasPTWRITE]>;
787} // SchedRW
788
789//===----------------------------------------------------------------------===//
790// RDPRU - Read Processor Register instruction.
791
792let SchedRW = [WriteSystem] in {
793let Uses = [ECX], Defs = [EAX, EDX] in
794   def RDPRU : I<0x01, MRM_FD, (outs), (ins), "rdpru", []>, TB,
795               Requires<[HasRDPRU]>;
796}
797
798//===----------------------------------------------------------------------===//
799// Platform Configuration instruction
800
801// From ISA docs:
802//  "This instruction is used to execute functions for configuring platform
803//   features.
804//   EAX: Leaf function to be invoked.
805//   RBX/RCX/RDX: Leaf-specific purpose."
806//  "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
807//   AF, OF, and SF are cleared. In case of failure, the failure reason is
808//   indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
809// Thus all these mentioned registers are considered clobbered.
810
811let SchedRW = [WriteSystem] in {
812let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
813    def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB,
814                  Requires<[HasPCONFIG]>;
815} // SchedRW
816