xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86InstrSystem.td (revision 59948e95d8deadafca3acd659b6dfc78b708f117) 
1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 instructions that are generally used in
10// privileged modes.  These are not typically used by the compiler, but are
11// supported for the assembler and disassembler.
12//
13//===----------------------------------------------------------------------===//
14
15let SchedRW = [WriteSystem] in {
16let Defs = [RAX, RDX] in
17def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
18
19let Defs = [RAX, RCX, RDX] in
20def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
21
22// CPU flow control instructions
23
24let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
25  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26
27  def UD1Wm   : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
28                  "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
29  def UD1Lm   : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
30                  "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
31  def UD1Qm   : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
32                   "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
33
34  def UD1Wr   : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
35                  "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
36  def UD1Lr   : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
37                  "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
38  def UD1Qr   : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
39                   "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
40}
41
42def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
43def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
44
45// Interrupt and SysCall Instructions.
46let Uses = [EFLAGS] in
47  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
48
49def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
50} // SchedRW
51
52// The long form of "int $3" turns into int3 as a size optimization.
53// FIXME: This doesn't work because InstAlias can't match immediate constants.
54//def : InstAlias<"int\t$3", (INT3)>;
55
56let SchedRW = [WriteSystem] in {
57
58def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
59              [(int_x86_int timm:$trap)]>;
60
61
62def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
63def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB;
64def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
65               Requires<[In64BitMode]>;
66
67def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
68
69def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
70def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
71                  Requires<[In64BitMode]>;
72} // SchedRW
73
74def : Pat<(debugtrap),
75          (INT3)>, Requires<[NotPS4]>;
76def : Pat<(debugtrap),
77          (INT (i8 0x41))>, Requires<[IsPS4]>;
78
79//===----------------------------------------------------------------------===//
80//  Input/Output Instructions.
81//
82let SchedRW = [WriteSystem] in {
83let Defs = [AL], Uses = [DX] in
84def IN8rr  : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>;
85let Defs = [AX], Uses = [DX] in
86def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>,
87               OpSize16;
88let Defs = [EAX], Uses = [DX] in
89def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>,
90               OpSize32;
91
92let Defs = [AL] in
93def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
94                 "in{b}\t{$port, %al|al, $port}", []>;
95let Defs = [AX] in
96def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
97                 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
98let Defs = [EAX] in
99def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
100                 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
101
102let Uses = [DX, AL] in
103def OUT8rr  : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>;
104let Uses = [DX, AX] in
105def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>,
106                OpSize16;
107let Uses = [DX, EAX] in
108def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>,
109                OpSize32;
110
111let Uses = [AL] in
112def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
113                   "out{b}\t{%al, $port|$port, al}", []>;
114let Uses = [AX] in
115def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
116                   "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
117let Uses = [EAX] in
118def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
119                  "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
120
121} // SchedRW
122
123//===----------------------------------------------------------------------===//
124// Moves to and from debug registers
125
126let SchedRW = [WriteSystem] in {
127def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
128                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
129                Requires<[Not64BitMode]>;
130def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
131                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
132                Requires<[In64BitMode]>;
133
134def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
135                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
136                Requires<[Not64BitMode]>;
137def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
138                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
139                Requires<[In64BitMode]>;
140} // SchedRW
141
142//===----------------------------------------------------------------------===//
143// Moves to and from control registers
144
145let SchedRW = [WriteSystem] in {
146def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
147                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
148                Requires<[Not64BitMode]>;
149def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
150                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
151                Requires<[In64BitMode]>;
152
153def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
154                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
155                Requires<[Not64BitMode]>;
156def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
157                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
158                Requires<[In64BitMode]>;
159} // SchedRW
160
161//===----------------------------------------------------------------------===//
162// Segment override instruction prefixes
163
164let SchedRW = [WriteNop] in {
165def CS_PREFIX : I<0x2E, PrefixByte, (outs), (ins), "cs", []>;
166def SS_PREFIX : I<0x36, PrefixByte, (outs), (ins), "ss", []>;
167def DS_PREFIX : I<0x3E, PrefixByte, (outs), (ins), "ds", []>;
168def ES_PREFIX : I<0x26, PrefixByte, (outs), (ins), "es", []>;
169def FS_PREFIX : I<0x64, PrefixByte, (outs), (ins), "fs", []>;
170def GS_PREFIX : I<0x65, PrefixByte, (outs), (ins), "gs", []>;
171} // SchedRW
172
173//===----------------------------------------------------------------------===//
174// Moves to and from segment registers.
175//
176
177let SchedRW = [WriteMove] in {
178def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
179                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
180def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
181                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
182def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
183                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
184let mayStore = 1 in {
185def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
186                "mov{w}\t{$src, $dst|$dst, $src}", []>;
187}
188def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
189                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
190def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
191                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
192def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
193                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
194let mayLoad = 1 in {
195def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
196                "mov{w}\t{$src, $dst|$dst, $src}", []>;
197}
198} // SchedRW
199
200//===----------------------------------------------------------------------===//
201// Segmentation support instructions.
202
203let SchedRW = [WriteSystem] in {
204def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
205
206let mayLoad = 1 in
207def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
208                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
209                OpSize16, NotMemoryFoldable;
210def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src),
211                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
212                OpSize16, NotMemoryFoldable;
213
214let mayLoad = 1 in
215def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
216                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
217                OpSize32, NotMemoryFoldable;
218def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src),
219                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
220                OpSize32, NotMemoryFoldable;
221let mayLoad = 1 in
222def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
223                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
224def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src),
225                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
226
227let mayLoad = 1 in
228def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
229                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
230                OpSize16, NotMemoryFoldable;
231def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src),
232                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
233                OpSize16, NotMemoryFoldable;
234let mayLoad = 1 in
235def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
236                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
237                OpSize32, NotMemoryFoldable;
238def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src),
239                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
240                OpSize32, NotMemoryFoldable;
241let mayLoad = 1 in
242def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
243                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
244def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src),
245                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable;
246
247def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
248
249def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
250               "str{w}\t$dst", []>, TB, OpSize16;
251def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
252               "str{l}\t$dst", []>, TB, OpSize32;
253def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
254                "str{q}\t$dst", []>, TB;
255let mayStore = 1 in
256def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB;
257
258def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
259let mayLoad = 1 in
260def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable;
261
262def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>,
263                 OpSize16, Requires<[Not64BitMode]>;
264def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>,
265                 OpSize32, Requires<[Not64BitMode]>;
266def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>,
267                 OpSize16, Requires<[Not64BitMode]>;
268def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>,
269                 OpSize32, Requires<[Not64BitMode]>;
270def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>,
271                 OpSize16, Requires<[Not64BitMode]>;
272def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>,
273                 OpSize32, Requires<[Not64BitMode]>;
274def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>,
275                 OpSize16, Requires<[Not64BitMode]>;
276def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>,
277                 OpSize32, Requires<[Not64BitMode]>;
278def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>,
279                 OpSize16, TB;
280def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB,
281                 OpSize32, Requires<[Not64BitMode]>;
282def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>,
283                 OpSize16, TB;
284def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB,
285                 OpSize32, Requires<[Not64BitMode]>;
286def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB,
287                 OpSize32, Requires<[In64BitMode]>;
288def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB,
289                 OpSize32, Requires<[In64BitMode]>;
290
291// No "pop cs" instruction.
292def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>,
293              OpSize16, Requires<[Not64BitMode]>;
294def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>,
295              OpSize32, Requires<[Not64BitMode]>;
296
297def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>,
298              OpSize16, Requires<[Not64BitMode]>;
299def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>,
300              OpSize32, Requires<[Not64BitMode]>;
301
302def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>,
303              OpSize16, Requires<[Not64BitMode]>;
304def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>,
305              OpSize32, Requires<[Not64BitMode]>;
306
307def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>,
308                OpSize16, TB;
309def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB,
310                OpSize32, Requires<[Not64BitMode]>;
311def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB,
312                OpSize32, Requires<[In64BitMode]>;
313
314def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>,
315                OpSize16, TB;
316def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB,
317                OpSize32, Requires<[Not64BitMode]>;
318def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB,
319                OpSize32, Requires<[In64BitMode]>;
320
321def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
322                "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
323                Requires<[Not64BitMode]>;
324def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
325                "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
326                Requires<[Not64BitMode]>;
327
328def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
329                "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
330def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
331                "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
332def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
333                 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
334
335def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
336                "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
337                Requires<[Not64BitMode]>;
338def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
339                "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
340                Requires<[Not64BitMode]>;
341
342def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
343                "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
344def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
345                "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
346def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
347                 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
348
349def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
350                "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
351def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
352                "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
353
354def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
355                 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
356
357def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
358def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
359let mayLoad = 1 in {
360def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable;
361def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
362}
363} // SchedRW
364
365//===----------------------------------------------------------------------===//
366// Descriptor-table support instructions
367
368let SchedRW = [WriteSystem] in {
369def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
370                "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
371def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
372                "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
373def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
374                "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
375def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
376                "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
377def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
378                "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
379def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
380                "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
381def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
382                "sldt{w}\t$dst", []>, TB, OpSize16;
383let mayStore = 1 in
384def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
385                "sldt{w}\t$dst", []>, TB;
386def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
387                "sldt{l}\t$dst", []>, OpSize32, TB;
388
389// LLDT is not interpreted specially in 64-bit mode because there is no sign
390//   extension.
391def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
392                 "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
393
394def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
395                "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
396def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
397                "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
398def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
399                "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
400def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
401                "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
402def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
403                "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
404def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
405                "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
406def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
407                "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
408let mayLoad = 1 in
409def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
410                "lldt{w}\t$src", []>, TB, NotMemoryFoldable;
411} // SchedRW
412
413//===----------------------------------------------------------------------===//
414// Specialized register support
415let SchedRW = [WriteSystem] in {
416let Uses = [EAX, ECX, EDX] in
417def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
418let Defs = [EAX, EDX], Uses = [ECX] in
419def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
420
421let Defs = [RAX, RDX], Uses = [ECX] in
422def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
423
424def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
425                "smsw{w}\t$dst", []>, OpSize16, TB;
426def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
427                "smsw{l}\t$dst", []>, OpSize32, TB;
428// no m form encodable; use SMSW16m
429def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
430                 "smsw{q}\t$dst", []>, TB;
431
432// For memory operands, there is only a 16-bit form
433def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
434                "smsw{w}\t$dst", []>, TB;
435
436def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
437                "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
438let mayLoad = 1 in
439def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
440                "lmsw{w}\t$src", []>, TB, NotMemoryFoldable;
441
442let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
443  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
444} // SchedRW
445
446//===----------------------------------------------------------------------===//
447// Cache instructions
448let SchedRW = [WriteSystem] in {
449def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
450def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, TB;
451
452// wbnoinvd is like wbinvd, except without invalidation
453// encoding: like wbinvd + an 0xF3 prefix
454def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd",
455                 [(int_x86_wbnoinvd)]>, XS,
456                 Requires<[HasWBNOINVD]>;
457} // SchedRW
458
459//===----------------------------------------------------------------------===//
460// CET instructions
461// Use with caution, availability is not predicated on features.
462let SchedRW = [WriteSystem] in {
463  let Uses = [SSP] in {
464    let Defs = [SSP] in {
465      def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
466                       [(int_x86_incsspd GR32:$src)]>, XS;
467      def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
468                       [(int_x86_incsspq GR64:$src)]>, XS;
469    } // Defs SSP
470
471    let Constraints = "$src = $dst" in {
472      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
473                     "rdsspd\t$dst",
474                     [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS;
475      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
476                     "rdsspq\t$dst",
477                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS;
478    }
479
480    let Defs = [SSP] in {
481      def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
482                       [(int_x86_saveprevssp)]>, XS;
483      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
484                       "rstorssp\t$src",
485                       [(int_x86_rstorssp addr:$src)]>, XS;
486    } // Defs SSP
487  } // Uses SSP
488
489  def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
490                "wrssd\t{$src, $dst|$dst, $src}",
491                [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS;
492  def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
493                 "wrssq\t{$src, $dst|$dst, $src}",
494                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS;
495  def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
496                 "wrussd\t{$src, $dst|$dst, $src}",
497                 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD;
498  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
499                  "wrussq\t{$src, $dst|$dst, $src}",
500                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD;
501
502  let Defs = [SSP] in {
503    let Uses = [SSP] in {
504        def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
505                         [(int_x86_setssbsy)]>, XS;
506    } // Uses SSP
507
508    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
509                     "clrssbsy\t$src",
510                     [(int_x86_clrssbsy addr:$src)]>, XS;
511  } // Defs SSP
512} // SchedRW
513
514let SchedRW = [WriteSystem] in {
515    def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
516    def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
517} // SchedRW
518
519//===----------------------------------------------------------------------===//
520// XSAVE instructions
521let SchedRW = [WriteSystem] in {
522let Predicates = [HasXSAVE] in {
523let Defs = [EDX, EAX], Uses = [ECX] in
524  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, PS;
525
526let Uses = [EDX, EAX, ECX] in
527  def XSETBV : I<0x01, MRM_D1, (outs), (ins),
528                "xsetbv",
529                [(int_x86_xsetbv ECX, EDX, EAX)]>, PS;
530
531} // HasXSAVE
532
533let Uses = [EDX, EAX] in {
534def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
535              "xsave\t$dst",
536              [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
537def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
538                 "xsave64\t$dst",
539                 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
540def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
541               "xrstor\t$dst",
542               [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>;
543def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
544                  "xrstor64\t$dst",
545                  [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
546def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
547                 "xsaveopt\t$dst",
548                 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>;
549def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
550                    "xsaveopt64\t$dst",
551                    [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>;
552def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
553               "xsavec\t$dst",
554               [(int_x86_xsavec addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEC]>;
555def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
556                 "xsavec64\t$dst",
557                 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEC, In64BitMode]>;
558def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
559               "xsaves\t$dst",
560               [(int_x86_xsaves addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES]>;
561def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
562                  "xsaves64\t$dst",
563                  [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>;
564def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
565                "xrstors\t$dst",
566                [(int_x86_xrstors addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES]>;
567def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
568                   "xrstors64\t$dst",
569                   [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVES, In64BitMode]>;
570} // Uses
571} // SchedRW
572
573//===----------------------------------------------------------------------===//
574// VIA PadLock crypto instructions
575let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
576  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB, REP;
577
578def : InstAlias<"xstorerng", (XSTORE)>;
579
580let SchedRW = [WriteSystem] in {
581let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
582  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB, REP;
583  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB, REP;
584  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB, REP;
585  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB, REP;
586  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB, REP;
587}
588
589let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
590  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB, REP;
591  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB, REP;
592}
593let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
594  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB, REP;
595} // SchedRW
596
597//==-----------------------------------------------------------------------===//
598// PKU  - enable protection key
599let SchedRW = [WriteSystem] in {
600let Defs = [EAX, EDX], Uses = [ECX] in
601  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru",
602                  [(set EAX, (X86rdpkru ECX)), (implicit EDX)]>, PS;
603let Uses = [EAX, ECX, EDX] in
604  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru",
605                  [(X86wrpkru EAX, EDX, ECX)]>, PS;
606} // SchedRW
607
608//===----------------------------------------------------------------------===//
609// FS/GS Base Instructions
610let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
611  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
612                   "rdfsbase{l}\t$dst",
613                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
614  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
615                     "rdfsbase{q}\t$dst",
616                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
617  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
618                   "rdgsbase{l}\t$dst",
619                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
620  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
621                     "rdgsbase{q}\t$dst",
622                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
623  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
624                   "wrfsbase{l}\t$src",
625                   [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
626  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
627                      "wrfsbase{q}\t$src",
628                      [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
629  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
630                   "wrgsbase{l}\t$src",
631                   [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
632  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
633                      "wrgsbase{q}\t$src",
634                      [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
635}
636
637//===----------------------------------------------------------------------===//
638// INVPCID Instruction
639let SchedRW = [WriteSystem] in {
640def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
641                  "invpcid\t{$src2, $src1|$src1, $src2}",
642                  [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD,
643                  Requires<[Not64BitMode, HasINVPCID]>;
644def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
645                  "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
646                  Requires<[In64BitMode, HasINVPCID]>;
647} // SchedRW
648
649let Predicates = [In64BitMode, HasINVPCID] in {
650  // The instruction can only use a 64 bit register as the register argument
651  // in 64 bit mode, while the intrinsic only accepts a 32 bit argument
652  // corresponding to it.
653  // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID
654  // type),/ so it doesn't hurt us that one can't supply a 64 bit value here.
655  def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
656            (INVPCID64
657              (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit),
658              addr:$src2)>;
659}
660
661
662//===----------------------------------------------------------------------===//
663// SMAP Instruction
664let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
665  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, PS;
666  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, PS;
667}
668
669//===----------------------------------------------------------------------===//
670// SMX Instruction
671let SchedRW = [WriteSystem] in {
672let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
673  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, PS;
674} // Uses, Defs
675} // SchedRW
676
677//===----------------------------------------------------------------------===//
678// TS flag control instruction.
679let SchedRW = [WriteSystem] in {
680def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
681}
682
683//===----------------------------------------------------------------------===//
684// IF (inside EFLAGS) management instructions.
685let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
686def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
687def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
688}
689
690//===----------------------------------------------------------------------===//
691// RDPID Instruction
692let SchedRW = [WriteSystem] in {
693def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
694                "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS,
695                Requires<[Not64BitMode, HasRDPID]>;
696def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS,
697                Requires<[In64BitMode, HasRDPID]>;
698} // SchedRW
699
700let Predicates = [In64BitMode, HasRDPID] in {
701  // Due to silly instruction definition, we have to compensate for the
702  // instruction outputing a 64-bit register.
703  def : Pat<(int_x86_rdpid),
704            (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
705}
706
707
708//===----------------------------------------------------------------------===//
709// PTWRITE Instruction - Write Data to a Processor Trace Packet
710let SchedRW = [WriteSystem] in {
711def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
712                "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS,
713                Requires<[HasPTWRITE]>;
714def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
715                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS,
716                    Requires<[In64BitMode, HasPTWRITE]>;
717
718def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
719                 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS,
720                    Requires<[HasPTWRITE]>;
721def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
722                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS,
723                    Requires<[In64BitMode, HasPTWRITE]>;
724} // SchedRW
725
726//===----------------------------------------------------------------------===//
727// Platform Configuration instruction
728
729// From ISA docs:
730//  "This instruction is used to execute functions for configuring platform
731//   features.
732//   EAX: Leaf function to be invoked.
733//   RBX/RCX/RDX: Leaf-specific purpose."
734//  "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
735//   AF, OF, and SF are cleared. In case of failure, the failure reason is
736//   indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
737// Thus all these mentioned registers are considered clobbered.
738
739let SchedRW = [WriteSystem] in {
740let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
741    def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, PS,
742                  Requires<[HasPCONFIG]>;
743} // SchedRW
744