1//===-- X86InstrSVM.td - SVM Instruction Set Extension -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the instructions that make up the AMD SVM instruction 10// set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// SVM instructions 16 17let SchedRW = [WriteSystem] in { 18// 0F 01 D9 19def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB; 20 21// 0F 01 DC 22def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB; 23 24// 0F 01 DD 25def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB; 26 27// 0F 01 DE 28let Uses = [EAX] in 29def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB; 30 31// 0F 01 D8 32let Uses = [EAX] in 33def VMRUN32 : I<0x01, MRM_D8, (outs), (ins), "vmrun\t{%eax|eax}", []>, TB, 34 Requires<[Not64BitMode]>; 35let Uses = [RAX] in 36def VMRUN64 : I<0x01, MRM_D8, (outs), (ins), "vmrun\t{%rax|rax}", []>, TB, 37 Requires<[In64BitMode]>; 38 39// 0F 01 DA 40let Uses = [EAX] in 41def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins), "vmload\t{%eax|eax}", []>, TB, 42 Requires<[Not64BitMode]>; 43let Uses = [RAX] in 44def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins), "vmload\t{%rax|rax}", []>, TB, 45 Requires<[In64BitMode]>; 46 47// 0F 01 DB 48let Uses = [EAX] in 49def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins), "vmsave\t{%eax|eax}", []>, TB, 50 Requires<[Not64BitMode]>; 51let Uses = [RAX] in 52def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins), "vmsave\t{%rax|rax}", []>, TB, 53 Requires<[In64BitMode]>; 54 55// 0F 01 DF 56let Uses = [EAX, ECX] in 57def INVLPGA32 : I<0x01, MRM_DF, (outs), (ins), 58 "invlpga\t{%eax, %ecx|eax, ecx}", []>, TB, Requires<[Not64BitMode]>; 59let Uses = [RAX, ECX] in 60def INVLPGA64 : I<0x01, MRM_DF, (outs), (ins), 61 "invlpga\t{%rax, %ecx|rax, ecx}", []>, TB, Requires<[In64BitMode]>; 62} // SchedRW 63