1//===---- X86InstrRAOINT.td -------------------------------*- tablegen -*--===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the instructions that make up the Intel RAO-INT 10// instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RAO-INT instructions 16 17def SDTRAOBinaryArith : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 18 19def X86rao_add : SDNode<"X86ISD::AADD", SDTRAOBinaryArith, 20 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 21def X86rao_or : SDNode<"X86ISD::AOR", SDTRAOBinaryArith, 22 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 23def X86rao_xor : SDNode<"X86ISD::AXOR", SDTRAOBinaryArith, 24 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 25def X86rao_and : SDNode<"X86ISD::AAND", SDTRAOBinaryArith, 26 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 27 28multiclass RaoInt<string m, string suffix = ""> { 29 let Pattern = [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR32:$src2)] in 30 def 32mr#suffix : BinOpMR_M<0xfc, "a" # m, Xi32>; 31 let Pattern = [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR64:$src2)] in 32 def 64mr#suffix : BinOpMR_M<0xfc, "a" # m, Xi64>; 33} 34 35let Predicates = [HasRAOINT, NoEGPR] in { 36 defm AADD : RaoInt<"add">, T8; 37 defm AAND : RaoInt<"and">, T8, PD; 38 defm AOR : RaoInt<"or" >, T8, XD; 39 defm AXOR : RaoInt<"xor">, T8, XS; 40} 41 42let Predicates = [HasRAOINT, HasEGPR, In64BitMode] in { 43 defm AADD : RaoInt<"add", "_EVEX">, EVEX, T_MAP4; 44 defm AAND : RaoInt<"and", "_EVEX">, EVEX, T_MAP4, PD; 45 defm AOR : RaoInt<"or", "_EVEX">, EVEX, T_MAP4, XD; 46 defm AXOR : RaoInt<"xor", "_EVEX">, EVEX, T_MAP4, XS; 47} 48