1//===---- X86InstrRAOINT.td -------------------------------*- tablegen -*--===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the instructions that make up the Intel RAO-INT 10// instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RAO-INT instructions 16 17def SDTRAOBinaryArith : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 18 19def X86rao_add : SDNode<"X86ISD::AADD", SDTRAOBinaryArith, 20 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 21def X86rao_or : SDNode<"X86ISD::AOR", SDTRAOBinaryArith, 22 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 23def X86rao_xor : SDNode<"X86ISD::AXOR", SDTRAOBinaryArith, 24 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 25def X86rao_and : SDNode<"X86ISD::AAND", SDTRAOBinaryArith, 26 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 27 28multiclass RAOINT_BASE<string OpcodeStr> { 29 let Predicates = [HasRAOINT] in 30 def 32mr : I<0xfc, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 31 !strconcat("a", OpcodeStr, "{l}\t{$src, $dst|$dst, $src}"), 32 [(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR32:$src)]>, 33 Sched<[WriteALURMW]>; 34 35 let Predicates = [HasRAOINT, In64BitMode] in 36 def 64mr : I<0xfc, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 37 !strconcat("a", OpcodeStr, "{q}\t{$src, $dst|$dst, $src}"), 38 [(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR64:$src)]>, 39 Sched<[WriteALURMW]>, REX_W; 40} 41 42defm AADD : RAOINT_BASE<"add">, T8; 43defm AAND : RAOINT_BASE<"and">, T8, PD; 44defm AOR : RAOINT_BASE<"or" >, T8, XD; 45defm AXOR : RAOINT_BASE<"xor">, T8, XS; 46