xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86InstrMMX.td (revision 4b50c451720d8b427757a6da1dd2bb4c52cd9e35) 
1//===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 MMX instruction set, defining the instructions,
10// and properties of the instructions which are needed for code generation,
11// machine code emission, and analysis.
12//
13// All instructions that use MMX should be in this file, even if they also use
14// SSE.
15//
16//===----------------------------------------------------------------------===//
17
18//===----------------------------------------------------------------------===//
19// MMX Multiclasses
20//===----------------------------------------------------------------------===//
21
22// Alias instruction that maps zero vector to pxor mmx.
23// This is expanded by ExpandPostRAPseudos to an pxor.
24// We set canFoldAsLoad because this can be converted to a constant-pool
25// load of an all-zeros value if folding it would be beneficial.
26let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
27    isPseudo = 1, SchedRW = [WriteZero] in {
28def MMX_SET0 : I<0, Pseudo, (outs VR64:$dst), (ins), "", []>;
29}
30
31let Constraints = "$src1 = $dst" in {
32  // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
33  // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
34  multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
35                               X86FoldableSchedWrite sched, bit Commutable = 0,
36                               X86MemOperand OType = i64mem> {
37    def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
38                 (ins VR64:$src1, VR64:$src2),
39                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
40                 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
41              Sched<[sched]> {
42      let isCommutable = Commutable;
43    }
44    def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
45                 (ins VR64:$src1, OType:$src2),
46                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
47                 [(set VR64:$dst, (IntId VR64:$src1,
48                                   (bitconvert (load_mmx addr:$src2))))]>,
49                 Sched<[sched.Folded, sched.ReadAfterFold]>;
50  }
51
52  multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
53                                string OpcodeStr, Intrinsic IntId,
54                                Intrinsic IntId2, X86FoldableSchedWrite sched,
55                                X86FoldableSchedWrite schedImm> {
56    def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
57                                  (ins VR64:$src1, VR64:$src2),
58                  !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
59                  [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
60             Sched<[sched]>;
61    def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
62                                  (ins VR64:$src1, i64mem:$src2),
63                  !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
64                  [(set VR64:$dst, (IntId VR64:$src1,
65                                    (bitconvert (load_mmx addr:$src2))))]>,
66                  Sched<[sched.Folded, sched.ReadAfterFold]>;
67    def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
68                                   (ins VR64:$src1, i32u8imm:$src2),
69                    !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
70           [(set VR64:$dst, (IntId2 VR64:$src1, imm:$src2))]>,
71           Sched<[schedImm]>;
72  }
73}
74
75/// Unary MMX instructions requiring SSSE3.
76multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
77                               Intrinsic IntId64, X86FoldableSchedWrite sched> {
78  def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
79                 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
80                 [(set VR64:$dst, (IntId64 VR64:$src))]>,
81           Sched<[sched]>;
82
83  def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
84                 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
85                 [(set VR64:$dst,
86                   (IntId64 (bitconvert (load_mmx addr:$src))))]>,
87                 Sched<[sched.Folded]>;
88}
89
90/// Binary MMX instructions requiring SSSE3.
91let ImmT = NoImm, Constraints = "$src1 = $dst" in {
92multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
93                             Intrinsic IntId64, X86FoldableSchedWrite sched,
94                             bit Commutable = 0> {
95  let isCommutable = Commutable in
96  def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
97       (ins VR64:$src1, VR64:$src2),
98        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
99       [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>,
100      Sched<[sched]>;
101  def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),
102       (ins VR64:$src1, i64mem:$src2),
103        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
104       [(set VR64:$dst,
105         (IntId64 VR64:$src1,
106          (bitconvert (load_mmx addr:$src2))))]>,
107      Sched<[sched.Folded, sched.ReadAfterFold]>;
108}
109}
110
111/// PALIGN MMX instructions (require SSSE3).
112multiclass ssse3_palign_mm<string asm, Intrinsic IntId,
113                           X86FoldableSchedWrite sched> {
114  def rri  : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
115      (ins VR64:$src1, VR64:$src2, u8imm:$src3),
116      !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
117      [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>,
118      Sched<[sched]>;
119  def rmi  : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
120      (ins VR64:$src1, i64mem:$src2, u8imm:$src3),
121      !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
122      [(set VR64:$dst, (IntId VR64:$src1,
123                       (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>,
124      Sched<[sched.Folded, sched.ReadAfterFold]>;
125}
126
127multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
128                         Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
129                         string asm, X86FoldableSchedWrite sched, Domain d> {
130  def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
131                  [(set DstRC:$dst, (Int SrcRC:$src))], d>,
132            Sched<[sched]>;
133  def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
134                  [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,
135            Sched<[sched.Folded]>;
136}
137
138multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
139                    RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
140                    PatFrag ld_frag, string asm, Domain d> {
141  def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
142                  (ins DstRC:$src1, SrcRC:$src2), asm,
143                  [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
144                  Sched<[WriteCvtI2PS]>;
145  def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
146                  (ins DstRC:$src1, x86memop:$src2), asm,
147                  [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>,
148                  Sched<[WriteCvtI2PS.Folded]>;
149}
150
151//===----------------------------------------------------------------------===//
152// MMX EMMS Instruction
153//===----------------------------------------------------------------------===//
154
155let SchedRW = [WriteEMMS],
156    Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
157            ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
158def MMX_EMMS  : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
159
160//===----------------------------------------------------------------------===//
161// MMX Scalar Instructions
162//===----------------------------------------------------------------------===//
163
164// Data Transfer Instructions
165def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
166                        "movd\t{$src, $dst|$dst, $src}",
167                        [(set VR64:$dst,
168                         (x86mmx (scalar_to_vector GR32:$src)))]>,
169                        Sched<[WriteVecMoveFromGpr]>;
170def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
171                        "movd\t{$src, $dst|$dst, $src}",
172                        [(set VR64:$dst,
173                        (x86mmx (scalar_to_vector (loadi32 addr:$src))))]>,
174                        Sched<[WriteVecLoad]>;
175
176let Predicates = [HasMMX] in {
177  def : Pat<(x86mmx (MMX_X86movw2d GR32:$src)),
178            (MMX_MOVD64rr GR32:$src)>;
179  def : Pat<(x86mmx (MMX_X86movw2d (i32 0))),
180            (MMX_SET0)>;
181  def : Pat<(x86mmx (MMX_X86movw2d (loadi32 addr:$src))),
182            (MMX_MOVD64rm addr:$src)>;
183}
184
185let mayStore = 1 in
186def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
187                        "movd\t{$src, $dst|$dst, $src}", []>,
188                   Sched<[WriteVecStore]>;
189
190def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
191                         "movd\t{$src, $dst|$dst, $src}",
192                         [(set GR32:$dst,
193                          (MMX_X86movd2w (x86mmx VR64:$src)))]>,
194                         Sched<[WriteVecMoveToGpr]>, FoldGenData<"MMX_MOVD64rr">;
195
196let isBitcast = 1 in
197def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
198                             "movq\t{$src, $dst|$dst, $src}",
199                             [(set VR64:$dst, (bitconvert GR64:$src))]>,
200                             Sched<[WriteVecMoveFromGpr]>;
201
202let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
203def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst),
204                             (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}",
205                             []>, Sched<[SchedWriteVecMoveLS.MMX.RM]>;
206
207let isBitcast = 1 in {
208def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
209                               (outs GR64:$dst), (ins VR64:$src),
210                               "movq\t{$src, $dst|$dst, $src}",
211                               [(set GR64:$dst, (bitconvert VR64:$src))]>,
212                               Sched<[WriteVecMoveToGpr]>;
213let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in {
214def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
215                        "movq\t{$src, $dst|$dst, $src}", []>;
216let isCodeGenOnly = 1, ForceDisassemble = 1 in
217def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
218                            "movq\t{$src, $dst|$dst, $src}", []>,
219                            FoldGenData<"MMX_MOVQ64rr">;
220} // SchedRW, hasSideEffects, isMoveReg
221} // isBitcast
222
223def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
224                (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>;
225
226let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
227def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem,
228                               (outs), (ins i64mem:$dst, VR64:$src),
229                               "movq\t{$src, $dst|$dst, $src}", []>,
230                               Sched<[SchedWriteVecMoveLS.MMX.MR]>;
231
232let SchedRW = [SchedWriteVecMoveLS.MMX.RM] in {
233let canFoldAsLoad = 1 in
234def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
235                        "movq\t{$src, $dst|$dst, $src}",
236                        [(set VR64:$dst, (load_mmx addr:$src))]>;
237} // SchedRW
238
239let SchedRW = [SchedWriteVecMoveLS.MMX.MR] in
240def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
241                        "movq\t{$src, $dst|$dst, $src}",
242                        [(store (x86mmx VR64:$src), addr:$dst)]>;
243
244let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in {
245def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
246                             (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",
247                             [(set VR64:$dst,
248                               (x86mmx (bitconvert
249                               (i64 (extractelt (v2i64 VR128:$src),
250                                     (iPTR 0))))))]>;
251
252def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
253                              (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
254                              [(set VR128:$dst,
255                                (v2i64
256                                  (scalar_to_vector
257                                    (i64 (bitconvert (x86mmx VR64:$src))))))]>;
258
259let isCodeGenOnly = 1, hasSideEffects = 1 in {
260def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst),
261                               (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
262                               []>;
263
264def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
265                              (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}",
266                              []>;
267}
268} // SchedRW
269
270let Predicates = [HasMMX, HasSSE1] in
271def MMX_MOVNTQmr  : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
272                         "movntq\t{$src, $dst|$dst, $src}",
273                         [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>,
274                         Sched<[SchedWriteVecMoveLSNT.MMX.MR]>;
275
276let Predicates = [HasMMX] in {
277  // movd to MMX register zero-extends
278  def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))),
279            (MMX_MOVD64rr GR32:$src)>;
280  def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector (loadi32 addr:$src))))),
281            (MMX_MOVD64rm addr:$src)>;
282}
283
284// Arithmetic Instructions
285defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b,
286                                     SchedWriteVecALU.MMX>;
287defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w,
288                                     SchedWriteVecALU.MMX>;
289defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d,
290                                     SchedWriteVecALU.MMX>;
291// -- Addition
292defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b,
293                                   SchedWriteVecALU.MMX, 1>;
294defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w,
295                                   SchedWriteVecALU.MMX, 1>;
296defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d,
297                                   SchedWriteVecALU.MMX, 1>;
298let Predicates = [HasMMX, HasSSE2] in
299defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q,
300                                   SchedWriteVecALU.MMX, 1>;
301defm MMX_PADDSB  : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b,
302                                     SchedWriteVecALU.MMX, 1>;
303defm MMX_PADDSW  : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w,
304                                     SchedWriteVecALU.MMX, 1>;
305
306defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b,
307                                   SchedWriteVecALU.MMX, 1>;
308defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w,
309                                   SchedWriteVecALU.MMX, 1>;
310
311defm MMX_PHADDW  : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,
312                                        SchedWritePHAdd.MMX>;
313defm MMX_PHADDD  : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
314                                        SchedWritePHAdd.MMX>;
315defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,
316                                        SchedWritePHAdd.MMX>;
317
318// -- Subtraction
319defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b,
320                                   SchedWriteVecALU.MMX>;
321defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w,
322                                   SchedWriteVecALU.MMX>;
323defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d,
324                                   SchedWriteVecALU.MMX>;
325let Predicates = [HasMMX, HasSSE2] in
326defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q,
327                                   SchedWriteVecALU.MMX>;
328
329defm MMX_PSUBSB  : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b,
330                                   SchedWriteVecALU.MMX>;
331defm MMX_PSUBSW  : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w,
332                                   SchedWriteVecALU.MMX>;
333
334defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b,
335                                   SchedWriteVecALU.MMX>;
336defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w,
337                                   SchedWriteVecALU.MMX>;
338
339defm MMX_PHSUBW  : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w,
340                                        SchedWritePHAdd.MMX>;
341defm MMX_PHSUBD  : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d,
342                                        SchedWritePHAdd.MMX>;
343defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw,
344                                        SchedWritePHAdd.MMX>;
345
346// -- Multiplication
347defm MMX_PMULLW  : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w,
348                                     SchedWriteVecIMul.MMX, 1>;
349
350defm MMX_PMULHW  : MMXI_binop_rm_int<0xE5, "pmulhw",  int_x86_mmx_pmulh_w,
351                                     SchedWriteVecIMul.MMX, 1>;
352let Predicates = [HasMMX, HasSSE1] in
353defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w,
354                                     SchedWriteVecIMul.MMX, 1>;
355let Predicates = [HasMMX, HasSSE2] in
356defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq,
357                                     SchedWriteVecIMul.MMX, 1>;
358defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
359                                     int_x86_ssse3_pmul_hr_sw,
360                                     SchedWriteVecIMul.MMX, 1>;
361
362// -- Miscellanea
363defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd,
364                                     SchedWriteVecIMul.MMX, 1>;
365
366defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
367                                          int_x86_ssse3_pmadd_ub_sw,
368                                          SchedWriteVecIMul.MMX>;
369let Predicates = [HasMMX, HasSSE1] in {
370defm MMX_PAVGB   : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b,
371                                     SchedWriteVecALU.MMX, 1>;
372defm MMX_PAVGW   : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w,
373                                     SchedWriteVecALU.MMX, 1>;
374
375defm MMX_PMINUB  : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b,
376                                     SchedWriteVecALU.MMX, 1>;
377defm MMX_PMINSW  : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w,
378                                     SchedWriteVecALU.MMX, 1>;
379
380defm MMX_PMAXUB  : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b,
381                                     SchedWriteVecALU.MMX, 1>;
382defm MMX_PMAXSW  : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w,
383                                     SchedWriteVecALU.MMX, 1>;
384
385defm MMX_PSADBW  : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw,
386                                     SchedWritePSADBW.MMX, 1>;
387}
388
389defm MMX_PSIGNB :  SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b,
390                                        SchedWriteVecALU.MMX>;
391defm MMX_PSIGNW :  SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w,
392                                        SchedWriteVecALU.MMX>;
393defm MMX_PSIGND :  SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d,
394                                        SchedWriteVecALU.MMX>;
395let Constraints = "$src1 = $dst" in
396  defm MMX_PALIGNR : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b,
397                                     SchedWriteShuffle.MMX>;
398
399// Logical Instructions
400defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,
401                                  SchedWriteVecLogic.MMX, 1>;
402defm MMX_POR  : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por,
403                                  SchedWriteVecLogic.MMX, 1>;
404defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor,
405                                  SchedWriteVecLogic.MMX, 1>;
406defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn,
407                                   SchedWriteVecLogic.MMX>;
408
409// Shift Instructions
410defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
411                                    int_x86_mmx_psrl_w, int_x86_mmx_psrli_w,
412                                    SchedWriteVecShift.MMX,
413                                    SchedWriteVecShiftImm.MMX>;
414defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
415                                    int_x86_mmx_psrl_d, int_x86_mmx_psrli_d,
416                                    SchedWriteVecShift.MMX,
417                                    SchedWriteVecShiftImm.MMX>;
418defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
419                                    int_x86_mmx_psrl_q, int_x86_mmx_psrli_q,
420                                    SchedWriteVecShift.MMX,
421                                    SchedWriteVecShiftImm.MMX>;
422
423defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
424                                    int_x86_mmx_psll_w, int_x86_mmx_pslli_w,
425                                    SchedWriteVecShift.MMX,
426                                    SchedWriteVecShiftImm.MMX>;
427defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
428                                    int_x86_mmx_psll_d, int_x86_mmx_pslli_d,
429                                    SchedWriteVecShift.MMX,
430                                    SchedWriteVecShiftImm.MMX>;
431defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
432                                    int_x86_mmx_psll_q, int_x86_mmx_pslli_q,
433                                    SchedWriteVecShift.MMX,
434                                    SchedWriteVecShiftImm.MMX>;
435
436defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
437                                    int_x86_mmx_psra_w, int_x86_mmx_psrai_w,
438                                    SchedWriteVecShift.MMX,
439                                    SchedWriteVecShiftImm.MMX>;
440defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
441                                    int_x86_mmx_psra_d, int_x86_mmx_psrai_d,
442                                    SchedWriteVecShift.MMX,
443                                    SchedWriteVecShiftImm.MMX>;
444
445// Comparison Instructions
446defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b,
447                                     SchedWriteVecALU.MMX>;
448defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w,
449                                     SchedWriteVecALU.MMX>;
450defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d,
451                                     SchedWriteVecALU.MMX>;
452
453defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b,
454                                     SchedWriteVecALU.MMX>;
455defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w,
456                                     SchedWriteVecALU.MMX>;
457defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d,
458                                     SchedWriteVecALU.MMX>;
459
460// -- Unpack Instructions
461defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
462                                       int_x86_mmx_punpckhbw,
463                                       SchedWriteShuffle.MMX>;
464defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
465                                       int_x86_mmx_punpckhwd,
466                                       SchedWriteShuffle.MMX>;
467defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
468                                       int_x86_mmx_punpckhdq,
469                                       SchedWriteShuffle.MMX>;
470defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
471                                       int_x86_mmx_punpcklbw,
472                                       SchedWriteShuffle.MMX,
473                                       0, i32mem>;
474defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
475                                       int_x86_mmx_punpcklwd,
476                                       SchedWriteShuffle.MMX,
477                                       0, i32mem>;
478defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
479                                       int_x86_mmx_punpckldq,
480                                       SchedWriteShuffle.MMX,
481                                       0, i32mem>;
482
483// -- Pack Instructions
484defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb,
485                                      SchedWriteShuffle.MMX>;
486defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw,
487                                      SchedWriteShuffle.MMX>;
488defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb,
489                                      SchedWriteShuffle.MMX>;
490
491// -- Shuffle Instructions
492defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b,
493                                       SchedWriteVarShuffle.MMX>;
494
495def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
496                          (outs VR64:$dst), (ins VR64:$src1, u8imm:$src2),
497                          "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
498                          [(set VR64:$dst,
499                             (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))]>,
500                          Sched<[SchedWriteShuffle.MMX]>;
501def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
502                          (outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2),
503                          "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
504                          [(set VR64:$dst,
505                             (int_x86_sse_pshuf_w (load_mmx addr:$src1),
506                                                   imm:$src2))]>,
507                          Sched<[SchedWriteShuffle.MMX.Folded]>;
508
509// -- Conversion Instructions
510defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
511                      f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
512                      WriteCvtPS2I, SSEPackedSingle>, PS;
513defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
514                      f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
515                      WriteCvtPD2I, SSEPackedDouble>, PD;
516defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
517                       f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
518                       WriteCvtPS2I, SSEPackedSingle>, PS;
519defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
520                       f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
521                       WriteCvtPD2I, SSEPackedDouble>, PD;
522defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
523                         i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
524                         WriteCvtI2PD, SSEPackedDouble>, PD;
525let Constraints = "$src1 = $dst" in {
526  defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
527                         int_x86_sse_cvtpi2ps,
528                         i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
529                         SSEPackedSingle>, PS;
530}
531
532// Extract / Insert
533let Predicates = [HasMMX, HasSSE1] in
534def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg,
535                     (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2),
536                     "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
537                     [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1,
538                                             imm:$src2))]>,
539                     Sched<[WriteVecExtract]>;
540let Constraints = "$src1 = $dst" in {
541let Predicates = [HasMMX, HasSSE1] in {
542  def MMX_PINSRWrr : MMXIi8<0xC4, MRMSrcReg,
543                    (outs VR64:$dst),
544                    (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
545                    "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
546                    [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
547                                      GR32orGR64:$src2, imm:$src3))]>,
548                    Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>;
549
550  def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem,
551                   (outs VR64:$dst),
552                   (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
553                   "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
554                   [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
555                                       (i32 (anyext (loadi16 addr:$src2))),
556                                     imm:$src3))]>,
557                   Sched<[WriteVecInsert.Folded, WriteVecInsert.ReadAfterFold]>;
558}
559}
560
561// Mask creation
562let Predicates = [HasMMX, HasSSE1] in
563def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
564                          (ins VR64:$src),
565                          "pmovmskb\t{$src, $dst|$dst, $src}",
566                          [(set GR32orGR64:$dst,
567                                (int_x86_mmx_pmovmskb VR64:$src))]>,
568                          Sched<[WriteMMXMOVMSK]>;
569
570// Low word of XMM to MMX.
571def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,
572                            [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
573
574def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)),
575          (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>;
576
577def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))),
578          (x86mmx (MMX_MOVQ64rm addr:$src))>;
579
580// Misc.
581let SchedRW = [SchedWriteShuffle.MMX] in {
582let Uses = [EDI], Predicates = [HasMMX, HasSSE1,Not64BitMode] in
583def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
584                          "maskmovq\t{$mask, $src|$src, $mask}",
585                          [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
586let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in
587def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
588                           "maskmovq\t{$mask, $src|$src, $mask}",
589                           [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
590}
591
592// 64-bit bit convert.
593let Predicates = [HasMMX, HasSSE2] in {
594def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
595          (MMX_MOVQ2FR64rr VR64:$src)>;
596def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
597          (MMX_MOVFR642Qrr FR64:$src)>;
598def : Pat<(x86mmx (MMX_X86movdq2q
599                   (bc_v2i64 (v4i32 (X86cvtp2Int (v4f32 VR128:$src)))))),
600          (MMX_CVTPS2PIirr VR128:$src)>;
601def : Pat<(x86mmx (MMX_X86movdq2q
602                   (bc_v2i64 (v4i32 (X86cvttp2si (v4f32 VR128:$src)))))),
603          (MMX_CVTTPS2PIirr VR128:$src)>;
604def : Pat<(x86mmx (MMX_X86movdq2q
605                   (bc_v2i64 (v4i32 (fp_to_sint (v4f32 VR128:$src)))))),
606          (MMX_CVTTPS2PIirr VR128:$src)>;
607def : Pat<(x86mmx (MMX_X86movdq2q
608                   (bc_v2i64 (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))),
609          (MMX_CVTPD2PIirr VR128:$src)>;
610def : Pat<(x86mmx (MMX_X86movdq2q
611                   (bc_v2i64 (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))),
612          (MMX_CVTTPD2PIirr VR128:$src)>;
613}
614