1//===---------------------------*-tablegen-*-------------------------------===// 2//===------------- X86InstrKL.td - KL Instruction Set Extension -----------===// 3// 4// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 5// See https://llvm.org/LICENSE.txt for license information. 6// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the instructions that make up the Intel key locker 11// instruction set. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Key Locker instructions 17 18let SchedRW = [WriteSystem], Predicates = [HasKL] in { 19 let Uses = [XMM0, EAX], Defs = [EFLAGS] in { 20 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), 21 "loadiwkey\t{$src2, $src1|$src1, $src2}", 22 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8, XS; 23 } 24 25 let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in { 26 def ENCODEKEY128 : I<0xFA, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 27 "encodekey128\t{$src, $dst|$dst, $src}", []>, T8, XS; 28 } 29 30 let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in { 31 def ENCODEKEY256 : I<0xFB, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 32 "encodekey256\t{$src, $dst|$dst, $src}", []>, T8, XS; 33 } 34 35 let Constraints = "$src1 = $dst", 36 Defs = [EFLAGS] in { 37 def AESENC128KL : I<0xDC, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2), 38 "aesenc128kl\t{$src2, $src1|$src1, $src2}", 39 [(set VR128:$dst, EFLAGS, 40 (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8, XS; 41 42 def AESDEC128KL : I<0xDD, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2), 43 "aesdec128kl\t{$src2, $src1|$src1, $src2}", 44 [(set VR128:$dst, EFLAGS, 45 (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8, XS; 46 47 def AESENC256KL : I<0xDE, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2), 48 "aesenc256kl\t{$src2, $src1|$src1, $src2}", 49 [(set VR128:$dst, EFLAGS, 50 (X86aesenc256kl VR128:$src1, addr:$src2))]>, T8, XS; 51 52 def AESDEC256KL : I<0xDF, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2), 53 "aesdec256kl\t{$src2, $src1|$src1, $src2}", 54 [(set VR128:$dst, EFLAGS, 55 (X86aesdec256kl VR128:$src1, addr:$src2))]>, T8, XS; 56 } 57 58} // SchedRW, Predicates 59 60let SchedRW = [WriteSystem], Predicates = [HasWIDEKL] in { 61 let Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], 62 Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], 63 mayLoad = 1 in { 64 def AESENCWIDE128KL : I<0xD8, MRM0m, (outs), (ins opaquemem:$src), 65 "aesencwide128kl\t$src", []>, T8, XS; 66 def AESDECWIDE128KL : I<0xD8, MRM1m, (outs), (ins opaquemem:$src), 67 "aesdecwide128kl\t$src", []>, T8, XS; 68 def AESENCWIDE256KL : I<0xD8, MRM2m, (outs), (ins opaquemem:$src), 69 "aesencwide256kl\t$src", []>, T8, XS; 70 def AESDECWIDE256KL : I<0xD8, MRM3m, (outs), (ins opaquemem:$src), 71 "aesdecwide256kl\t$src", []>, T8, XS; 72 } 73 74} // SchedRW, Predicates 75