1//===---------------------------*-tablegen-*-------------------------------===// 2//===------------- X86InstrKL.td - KL Instruction Set Extension -----------===// 3// 4// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 5// See https://llvm.org/LICENSE.txt for license information. 6// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the instructions that make up the Intel key locker 11// instruction set. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Key Locker instructions 17class Encodekey<bits<8> opcode, string m> 18 : I<opcode, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), m#"\t{$src, $dst|$dst, $src}", []>, 19 NoCD8, XS; 20 21multiclass Aesencdec<string suffix> { 22 def AESENC128KL#suffix : I<0xDC, MRMSrcMem, (outs VR128:$dst), 23 (ins VR128:$src1, opaquemem:$src2), 24 "aesenc128kl\t{$src2, $src1|$src1, $src2}", 25 [(set VR128:$dst, EFLAGS, (X86aesenc128kl VR128:$src1, addr:$src2))]>, 26 NoCD8, XS; 27 def AESDEC128KL#suffix : I<0xDD, MRMSrcMem, (outs VR128:$dst), 28 (ins VR128:$src1, opaquemem:$src2), 29 "aesdec128kl\t{$src2, $src1|$src1, $src2}", 30 [(set VR128:$dst, EFLAGS, (X86aesdec128kl VR128:$src1, addr:$src2))]>, 31 NoCD8, XS; 32 def AESENC256KL#suffix : I<0xDE, MRMSrcMem, (outs VR128:$dst), 33 (ins VR128:$src1, opaquemem:$src2), 34 "aesenc256kl\t{$src2, $src1|$src1, $src2}", 35 [(set VR128:$dst, EFLAGS, (X86aesenc256kl VR128:$src1, addr:$src2))]>, 36 NoCD8, XS; 37 def AESDEC256KL#suffix : I<0xDF, MRMSrcMem, (outs VR128:$dst), 38 (ins VR128:$src1, opaquemem:$src2), 39 "aesdec256kl\t{$src2, $src1|$src1, $src2}", 40 [(set VR128:$dst, EFLAGS, (X86aesdec256kl VR128:$src1, addr:$src2))]>, 41 NoCD8, XS; 42} 43 44let SchedRW = [WriteSystem] in { 45 let Uses = [XMM0, EAX], Defs = [EFLAGS], Predicates = [HasKL] in { 46 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), 47 "loadiwkey\t{$src2, $src1|$src1, $src2}", 48 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8, XS; 49 } 50 51 let Predicates = [HasKL] in { 52 let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in 53 def ENCODEKEY128 : Encodekey<0xFA, "encodekey128">, T8; 54 55 let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in 56 def ENCODEKEY256 : Encodekey<0xFB, "encodekey256">, T8; 57 58 let Constraints = "$src1 = $dst", Defs = [EFLAGS] in 59 defm "" : Aesencdec<"">, T8; 60 } 61} // SchedRW 62 63multiclass Aesencdecwide<string suffix> { 64 def AESENCWIDE128KL#suffix : I<0xD8, MRM0m, (outs), (ins opaquemem:$src), "aesencwide128kl\t$src", []>, NoCD8, XS; 65 def AESDECWIDE128KL#suffix : I<0xD8, MRM1m, (outs), (ins opaquemem:$src), "aesdecwide128kl\t$src", []>, NoCD8, XS; 66 def AESENCWIDE256KL#suffix : I<0xD8, MRM2m, (outs), (ins opaquemem:$src), "aesencwide256kl\t$src", []>, NoCD8, XS; 67 def AESDECWIDE256KL#suffix : I<0xD8, MRM3m, (outs), (ins opaquemem:$src), "aesdecwide256kl\t$src", []>, NoCD8, XS; 68} 69 70let SchedRW = [WriteSystem], Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], 71 Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], mayLoad = 1 in { 72 let Predicates = [HasWIDEKL] in 73 defm "" : Aesencdecwide<"">, T8; 74} // SchedRW 75