1//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 instruction set, defining the instructions, and 10// properties of the instructions which are needed for code generation, machine 11// code emission, and analysis. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// X86 specific DAG Nodes. 17// 18 19def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, 20 SDTCisSameAs<1, 2>]>; 21def SDTX86FCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisFP<1>, 22 SDTCisSameAs<1, 2>]>; 23 24def SDTX86Cmov : SDTypeProfile<1, 4, 25 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 26 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 27 28// Unary and binary operator instructions that set EFLAGS as a side-effect. 29def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 30 [SDTCisSameAs<0, 2>, 31 SDTCisInt<0>, SDTCisVT<1, i32>]>; 32 33def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 34 [SDTCisSameAs<0, 2>, 35 SDTCisSameAs<0, 3>, 36 SDTCisInt<0>, SDTCisVT<1, i32>]>; 37 38// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 39def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 40 [SDTCisSameAs<0, 2>, 41 SDTCisSameAs<0, 3>, 42 SDTCisInt<0>, 43 SDTCisVT<1, i32>, 44 SDTCisVT<4, i32>]>; 45// RES1, RES2, FLAGS = op LHS, RHS 46def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 47 [SDTCisSameAs<0, 1>, 48 SDTCisSameAs<0, 2>, 49 SDTCisSameAs<0, 3>, 50 SDTCisInt<0>, SDTCisVT<1, i32>]>; 51def SDTX86BrCond : SDTypeProfile<0, 3, 52 [SDTCisVT<0, OtherVT>, 53 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 54 55def SDTX86SetCC : SDTypeProfile<1, 2, 56 [SDTCisVT<0, i8>, 57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 58def SDTX86SetCC_C : SDTypeProfile<1, 2, 59 [SDTCisInt<0>, 60 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 61 62def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 63 64def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 65 66def SDTX86rdpkru : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 67def SDTX86wrpkru : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 68 SDTCisVT<2, i32>]>; 69 70def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 71 SDTCisVT<2, i8>]>; 72def SDTX86cas8pair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 73def SDTX86cas16pair : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i64>]>; 74 75def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 76 SDTCisPtrTy<1>, 77 SDTCisInt<2>]>; 78 79def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, 80 SDTCisPtrTy<1>]>; 81 82def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 83 84def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, 85 SDTCisVT<1, i32>]>; 86def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 87 SDTCisVT<1, i32>]>; 88 89def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 90 91def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 92 93def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 94 SDTCisPtrTy<1>]>; 95 96def SDT_X86VAARG : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 97 SDTCisPtrTy<1>, 98 SDTCisVT<2, i32>, 99 SDTCisVT<3, i8>, 100 SDTCisVT<4, i32>]>; 101 102def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 103 104def SDTX86Void : SDTypeProfile<0, 0, []>; 105 106def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 107 108def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 109 110def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 111 112def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 113 114def SDT_X86DYN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 115 116def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 117 118def SDT_X86PROBED_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 119 120def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 121 122def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 123 124def SDT_X86ENQCMD : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 125 SDTCisPtrTy<1>, SDTCisSameAs<1, 2>]>; 126 127def SDT_X86AESENCDECKL : SDTypeProfile<2, 2, [SDTCisVT<0, v2i64>, 128 SDTCisVT<1, i32>, 129 SDTCisVT<2, v2i64>, 130 SDTCisPtrTy<3>]>; 131 132def SDTX86Cmpccxadd : SDTypeProfile<1, 4, [SDTCisSameAs<0, 2>, 133 SDTCisPtrTy<1>, SDTCisSameAs<2, 3>, 134 SDTCisVT<4, i8>]>; 135 136def X86MFence : SDNode<"X86ISD::MFENCE", SDTNone, [SDNPHasChain]>; 137 138 139def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 140def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 141def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>; 142def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>; 143 144def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 145def X86fcmp : SDNode<"X86ISD::FCMP", SDTX86FCmp>; 146def X86strict_fcmp : SDNode<"X86ISD::STRICT_FCMP", SDTX86FCmp, [SDNPHasChain]>; 147def X86strict_fcmps : SDNode<"X86ISD::STRICT_FCMPS", SDTX86FCmp, [SDNPHasChain]>; 148def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 149 150def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 151def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 152 [SDNPHasChain]>; 153def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 154def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 155 156def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 157 [SDNPHasChain, SDNPSideEffect]>; 158 159def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 160 [SDNPHasChain, SDNPSideEffect]>; 161 162def X86rdpkru : SDNode<"X86ISD::RDPKRU", SDTX86rdpkru, 163 [SDNPHasChain, SDNPSideEffect]>; 164def X86wrpkru : SDNode<"X86ISD::WRPKRU", SDTX86wrpkru, 165 [SDNPHasChain, SDNPSideEffect]>; 166 167def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 168 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 169 SDNPMayLoad, SDNPMemOperand]>; 170def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8pair, 171 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 172 SDNPMayLoad, SDNPMemOperand]>; 173def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86cas16pair, 174 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 175 SDNPMayLoad, SDNPMemOperand]>; 176 177def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 178 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 179def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, 180 [SDNPHasChain, SDNPOptInGlue]>; 181 182def X86vastart_save_xmm_regs : 183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 184 SDT_X86VASTART_SAVE_XMM_REGS, 185 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPVariadic]>; 186def X86vaarg64 : 187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG, 188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 189 SDNPMemOperand]>; 190def X86vaargx32 : 191 SDNode<"X86ISD::VAARG_X32", SDT_X86VAARG, 192 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 193 SDNPMemOperand]>; 194def X86callseq_start : 195 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 196 [SDNPHasChain, SDNPOutGlue]>; 197def X86callseq_end : 198 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 199 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 200 201def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 202 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 203 SDNPVariadic]>; 204 205def X86call_rvmarker : SDNode<"X86ISD::CALL_RVMARKER", SDT_X86Call, 206 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 207 SDNPVariadic]>; 208 209 210def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call, 211 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 212 SDNPVariadic]>; 213def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind, 214 [SDNPHasChain]>; 215 216def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 217 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 218def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 219 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 220 SDNPMayLoad]>; 221 222def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 223def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 224 225def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", 226 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 227 SDTCisInt<1>]>>; 228 229def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 230 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 231 232def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 233 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 234 235def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 236 [SDNPHasChain]>; 237 238def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 239 SDTypeProfile<1, 1, [SDTCisInt<0>, 240 SDTCisPtrTy<1>]>, 241 [SDNPHasChain, SDNPSideEffect]>; 242def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 243 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 244 [SDNPHasChain, SDNPSideEffect]>; 245def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH", 246 SDTypeProfile<0, 0, []>, 247 [SDNPHasChain, SDNPSideEffect]>; 248 249def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 250 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 251 252def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 253 [SDNPCommutative]>; 254def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 255def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 256 [SDNPCommutative]>; 257def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 258 [SDNPCommutative]>; 259def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 260def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 261 262def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 263 [SDNPCommutative]>; 264def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 265 [SDNPCommutative]>; 266def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 267 [SDNPCommutative]>; 268 269def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags, 270 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 271 SDNPMemOperand]>; 272def X86lock_sub : SDNode<"X86ISD::LSUB", SDTLockBinaryArithWithFlags, 273 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 274 SDNPMemOperand]>; 275def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, 276 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 277 SDNPMemOperand]>; 278def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, 279 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 280 SDNPMemOperand]>; 281def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, 282 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 283 SDNPMemOperand]>; 284 285def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; 286def X86bextri : SDNode<"X86ISD::BEXTRI", SDTIntBinOp>; 287 288def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntBinOp>; 289 290def X86pdep : SDNode<"X86ISD::PDEP", SDTIntBinOp>; 291def X86pext : SDNode<"X86ISD::PEXT", SDTIntBinOp>; 292 293def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 294 295def X86DynAlloca : SDNode<"X86ISD::DYN_ALLOCA", SDT_X86DYN_ALLOCA, 296 [SDNPHasChain, SDNPOutGlue]>; 297 298def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 299 [SDNPHasChain]>; 300 301def X86ProbedAlloca : SDNode<"X86ISD::PROBED_ALLOCA", SDT_X86PROBED_ALLOCA, 302 [SDNPHasChain]>; 303 304def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 305 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 306 307def X86lwpins : SDNode<"X86ISD::LWPINS", 308 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 309 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 310 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; 311 312def X86umwait : SDNode<"X86ISD::UMWAIT", 313 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 314 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 315 [SDNPHasChain, SDNPSideEffect]>; 316 317def X86tpause : SDNode<"X86ISD::TPAUSE", 318 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 319 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 320 [SDNPHasChain, SDNPSideEffect]>; 321 322def X86enqcmd : SDNode<"X86ISD::ENQCMD", SDT_X86ENQCMD, 323 [SDNPHasChain, SDNPSideEffect]>; 324def X86enqcmds : SDNode<"X86ISD::ENQCMDS", SDT_X86ENQCMD, 325 [SDNPHasChain, SDNPSideEffect]>; 326def X86testui : SDNode<"X86ISD::TESTUI", 327 SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>, 328 [SDNPHasChain, SDNPSideEffect]>; 329 330def X86aesenc128kl : SDNode<"X86ISD::AESENC128KL", SDT_X86AESENCDECKL, 331 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 332 SDNPMemOperand]>; 333def X86aesdec128kl : SDNode<"X86ISD::AESDEC128KL", SDT_X86AESENCDECKL, 334 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 335 SDNPMemOperand]>; 336def X86aesenc256kl : SDNode<"X86ISD::AESENC256KL", SDT_X86AESENCDECKL, 337 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 338 SDNPMemOperand]>; 339def X86aesdec256kl : SDNode<"X86ISD::AESDEC256KL", SDT_X86AESENCDECKL, 340 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 341 SDNPMemOperand]>; 342 343def X86cmpccxadd : SDNode<"X86ISD::CMPCCXADD", SDTX86Cmpccxadd, 344 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 345 SDNPMemOperand]>; 346 347//===----------------------------------------------------------------------===// 348// X86 Operand Definitions. 349// 350 351// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 352// the index operand of an address, to conform to x86 encoding restrictions. 353def ptr_rc_nosp : PointerLikeRegClass<1>; 354 355// *mem - Operand definitions for the funky X86 addressing mode operands. 356// 357def X86MemAsmOperand : AsmOperandClass { 358 let Name = "Mem"; 359} 360let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { 361 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } 362 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } 363 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } 364 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } 365 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } 366 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } 367 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } 368 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } 369 // Gather mem operands 370 def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } 371 def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; } 372 def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; } 373 def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; } 374 def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; } 375 376 def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } 377 def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; } 378 def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; } 379 def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; } 380 def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; } 381 def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } 382 def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } 383 def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } 384 385 def X86SibMemOperand : AsmOperandClass { let Name = "SibMem"; } 386} 387 388def X86AbsMemAsmOperand : AsmOperandClass { 389 let Name = "AbsMem"; 390 let SuperClasses = [X86MemAsmOperand]; 391} 392 393class X86MemOperand<string printMethod, 394 AsmOperandClass parserMatchClass = X86MemAsmOperand, 395 int size = 0> : Operand<iPTR> { 396 let PrintMethod = printMethod; 397 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); 398 let ParserMatchClass = parserMatchClass; 399 let OperandType = "OPERAND_MEMORY"; 400 int Size = size; 401} 402 403// Gather mem operands 404class X86VMemOperand<RegisterClass RC, string printMethod, 405 AsmOperandClass parserMatchClass, int size = 0> 406 : X86MemOperand<printMethod, parserMatchClass, size> { 407 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); 408} 409 410def anymem : X86MemOperand<"printMemReference">; 411def X86any_fcmp : PatFrags<(ops node:$lhs, node:$rhs), 412 [(X86strict_fcmp node:$lhs, node:$rhs), 413 (X86fcmp node:$lhs, node:$rhs)]>; 414 415// FIXME: Right now we allow any size during parsing, but we might want to 416// restrict to only unsized memory. 417def opaquemem : X86MemOperand<"printMemReference">; 418 419def sibmem: X86MemOperand<"printMemReference", X86SibMemOperand>; 420 421def i8mem : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8>; 422def i16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>; 423def i32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>; 424def i64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>; 425def i128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>; 426def i256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>; 427def i512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>; 428def f16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>; 429def f32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>; 430def f64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>; 431def f80mem : X86MemOperand<"printtbytemem", X86Mem80AsmOperand, 80>; 432def f128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>; 433def f256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>; 434def f512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>; 435 436// Gather mem operands 437def vx64mem : X86VMemOperand<VR128, "printqwordmem", X86Mem64_RC128Operand, 64>; 438def vx128mem : X86VMemOperand<VR128, "printxmmwordmem", X86Mem128_RC128Operand, 128>; 439def vx256mem : X86VMemOperand<VR128, "printymmwordmem", X86Mem256_RC128Operand, 256>; 440def vy128mem : X86VMemOperand<VR256, "printxmmwordmem", X86Mem128_RC256Operand, 128>; 441def vy256mem : X86VMemOperand<VR256, "printymmwordmem", X86Mem256_RC256Operand, 256>; 442 443def vx64xmem : X86VMemOperand<VR128X, "printqwordmem", X86Mem64_RC128XOperand, 64>; 444def vx128xmem : X86VMemOperand<VR128X, "printxmmwordmem", X86Mem128_RC128XOperand, 128>; 445def vx256xmem : X86VMemOperand<VR128X, "printymmwordmem", X86Mem256_RC128XOperand, 256>; 446def vy128xmem : X86VMemOperand<VR256X, "printxmmwordmem", X86Mem128_RC256XOperand, 128>; 447def vy256xmem : X86VMemOperand<VR256X, "printymmwordmem", X86Mem256_RC256XOperand, 256>; 448def vy512xmem : X86VMemOperand<VR256X, "printzmmwordmem", X86Mem512_RC256XOperand, 512>; 449def vz256mem : X86VMemOperand<VR512, "printymmwordmem", X86Mem256_RC512Operand, 256>; 450def vz512mem : X86VMemOperand<VR512, "printzmmwordmem", X86Mem512_RC512Operand, 512>; 451 452// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead 453// of a plain GPR, so that it doesn't potentially require a REX prefix. 454def ptr_rc_norex : PointerLikeRegClass<2>; 455def ptr_rc_norex_nosp : PointerLikeRegClass<3>; 456 457def i8mem_NOREX : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8> { 458 let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, 459 SEGMENT_REG); 460} 461 462// GPRs available for tailcall. 463// It represents GR32_TC, GR64_TC or GR64_TCW64. 464def ptr_rc_tailcall : PointerLikeRegClass<4>; 465 466// Special i32mem for addresses of load folding tail calls. These are not 467// allowed to use callee-saved registers since they must be scheduled 468// after callee-saved register are popped. 469def i32mem_TC : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32> { 470 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 471 i32imm, SEGMENT_REG); 472} 473 474// Special i64mem for addresses of load folding tail calls. These are not 475// allowed to use callee-saved registers since they must be scheduled 476// after callee-saved register are popped. 477def i64mem_TC : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64> { 478 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 479 ptr_rc_tailcall, i32imm, SEGMENT_REG); 480} 481 482// Special parser to detect 16-bit mode to select 16-bit displacement. 483def X86AbsMem16AsmOperand : AsmOperandClass { 484 let Name = "AbsMem16"; 485 let RenderMethod = "addAbsMemOperands"; 486 let SuperClasses = [X86AbsMemAsmOperand]; 487} 488 489// Branch targets print as pc-relative values. 490class BranchTargetOperand<ValueType ty> : Operand<ty> { 491 let OperandType = "OPERAND_PCREL"; 492 let PrintMethod = "printPCRelImm"; 493 let ParserMatchClass = X86AbsMemAsmOperand; 494} 495 496def i32imm_brtarget : BranchTargetOperand<i32>; 497def i16imm_brtarget : BranchTargetOperand<i16>; 498 499// 64-bits but only 32 bits are significant, and those bits are treated as being 500// pc relative. 501def i64i32imm_brtarget : BranchTargetOperand<i64>; 502 503def brtarget : BranchTargetOperand<OtherVT>; 504def brtarget8 : BranchTargetOperand<OtherVT>; 505def brtarget16 : BranchTargetOperand<OtherVT> { 506 let ParserMatchClass = X86AbsMem16AsmOperand; 507} 508def brtarget32 : BranchTargetOperand<OtherVT>; 509 510let RenderMethod = "addSrcIdxOperands" in { 511 def X86SrcIdx8Operand : AsmOperandClass { 512 let Name = "SrcIdx8"; 513 let SuperClasses = [X86Mem8AsmOperand]; 514 } 515 def X86SrcIdx16Operand : AsmOperandClass { 516 let Name = "SrcIdx16"; 517 let SuperClasses = [X86Mem16AsmOperand]; 518 } 519 def X86SrcIdx32Operand : AsmOperandClass { 520 let Name = "SrcIdx32"; 521 let SuperClasses = [X86Mem32AsmOperand]; 522 } 523 def X86SrcIdx64Operand : AsmOperandClass { 524 let Name = "SrcIdx64"; 525 let SuperClasses = [X86Mem64AsmOperand]; 526 } 527} // RenderMethod = "addSrcIdxOperands" 528 529let RenderMethod = "addDstIdxOperands" in { 530 def X86DstIdx8Operand : AsmOperandClass { 531 let Name = "DstIdx8"; 532 let SuperClasses = [X86Mem8AsmOperand]; 533 } 534 def X86DstIdx16Operand : AsmOperandClass { 535 let Name = "DstIdx16"; 536 let SuperClasses = [X86Mem16AsmOperand]; 537 } 538 def X86DstIdx32Operand : AsmOperandClass { 539 let Name = "DstIdx32"; 540 let SuperClasses = [X86Mem32AsmOperand]; 541 } 542 def X86DstIdx64Operand : AsmOperandClass { 543 let Name = "DstIdx64"; 544 let SuperClasses = [X86Mem64AsmOperand]; 545 } 546} // RenderMethod = "addDstIdxOperands" 547 548let RenderMethod = "addMemOffsOperands" in { 549 def X86MemOffs16_8AsmOperand : AsmOperandClass { 550 let Name = "MemOffs16_8"; 551 let SuperClasses = [X86Mem8AsmOperand]; 552 } 553 def X86MemOffs16_16AsmOperand : AsmOperandClass { 554 let Name = "MemOffs16_16"; 555 let SuperClasses = [X86Mem16AsmOperand]; 556 } 557 def X86MemOffs16_32AsmOperand : AsmOperandClass { 558 let Name = "MemOffs16_32"; 559 let SuperClasses = [X86Mem32AsmOperand]; 560 } 561 def X86MemOffs32_8AsmOperand : AsmOperandClass { 562 let Name = "MemOffs32_8"; 563 let SuperClasses = [X86Mem8AsmOperand]; 564 } 565 def X86MemOffs32_16AsmOperand : AsmOperandClass { 566 let Name = "MemOffs32_16"; 567 let SuperClasses = [X86Mem16AsmOperand]; 568 } 569 def X86MemOffs32_32AsmOperand : AsmOperandClass { 570 let Name = "MemOffs32_32"; 571 let SuperClasses = [X86Mem32AsmOperand]; 572 } 573 def X86MemOffs32_64AsmOperand : AsmOperandClass { 574 let Name = "MemOffs32_64"; 575 let SuperClasses = [X86Mem64AsmOperand]; 576 } 577 def X86MemOffs64_8AsmOperand : AsmOperandClass { 578 let Name = "MemOffs64_8"; 579 let SuperClasses = [X86Mem8AsmOperand]; 580 } 581 def X86MemOffs64_16AsmOperand : AsmOperandClass { 582 let Name = "MemOffs64_16"; 583 let SuperClasses = [X86Mem16AsmOperand]; 584 } 585 def X86MemOffs64_32AsmOperand : AsmOperandClass { 586 let Name = "MemOffs64_32"; 587 let SuperClasses = [X86Mem32AsmOperand]; 588 } 589 def X86MemOffs64_64AsmOperand : AsmOperandClass { 590 let Name = "MemOffs64_64"; 591 let SuperClasses = [X86Mem64AsmOperand]; 592 } 593} // RenderMethod = "addMemOffsOperands" 594 595class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 596 : X86MemOperand<printMethod, parserMatchClass> { 597 let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); 598} 599 600class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 601 : X86MemOperand<printMethod, parserMatchClass> { 602 let MIOperandInfo = (ops ptr_rc); 603} 604 605def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; 606def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; 607def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; 608def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; 609def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; 610def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; 611def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; 612def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; 613 614class X86MemOffsOperand<Operand immOperand, string printMethod, 615 AsmOperandClass parserMatchClass> 616 : X86MemOperand<printMethod, parserMatchClass> { 617 let MIOperandInfo = (ops immOperand, SEGMENT_REG); 618} 619 620def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8", 621 X86MemOffs16_8AsmOperand>; 622def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16", 623 X86MemOffs16_16AsmOperand>; 624def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32", 625 X86MemOffs16_32AsmOperand>; 626def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8", 627 X86MemOffs32_8AsmOperand>; 628def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16", 629 X86MemOffs32_16AsmOperand>; 630def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32", 631 X86MemOffs32_32AsmOperand>; 632def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64", 633 X86MemOffs32_64AsmOperand>; 634def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8", 635 X86MemOffs64_8AsmOperand>; 636def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16", 637 X86MemOffs64_16AsmOperand>; 638def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32", 639 X86MemOffs64_32AsmOperand>; 640def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64", 641 X86MemOffs64_64AsmOperand>; 642 643def ccode : Operand<i8> { 644 let PrintMethod = "printCondCode"; 645 let OperandNamespace = "X86"; 646 let OperandType = "OPERAND_COND_CODE"; 647} 648 649class ImmSExtAsmOperandClass : AsmOperandClass { 650 let SuperClasses = [ImmAsmOperand]; 651 let RenderMethod = "addImmOperands"; 652} 653 654def X86GR32orGR64AsmOperand : AsmOperandClass { 655 let Name = "GR32orGR64"; 656} 657def GR32orGR64 : RegisterOperand<GR32> { 658 let ParserMatchClass = X86GR32orGR64AsmOperand; 659} 660 661def X86GR16orGR32orGR64AsmOperand : AsmOperandClass { 662 let Name = "GR16orGR32orGR64"; 663} 664def GR16orGR32orGR64 : RegisterOperand<GR16> { 665 let ParserMatchClass = X86GR16orGR32orGR64AsmOperand; 666} 667 668def AVX512RCOperand : AsmOperandClass { 669 let Name = "AVX512RC"; 670} 671def AVX512RC : Operand<i32> { 672 let PrintMethod = "printRoundingControl"; 673 let OperandNamespace = "X86"; 674 let OperandType = "OPERAND_ROUNDING_CONTROL"; 675 let ParserMatchClass = AVX512RCOperand; 676} 677 678// Sign-extended immediate classes. We don't need to define the full lattice 679// here because there is no instruction with an ambiguity between ImmSExti64i32 680// and ImmSExti32i8. 681// 682// The strange ranges come from the fact that the assembler always works with 683// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 684// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 685 686// [0, 0x7FFFFFFF] | 687// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 688def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 689 let Name = "ImmSExti64i32"; 690} 691 692// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 693// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 694def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 695 let Name = "ImmSExti16i8"; 696 let SuperClasses = [ImmSExti64i32AsmOperand]; 697} 698 699// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 700// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 701def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 702 let Name = "ImmSExti32i8"; 703} 704 705// [0, 0x0000007F] | 706// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 707def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 708 let Name = "ImmSExti64i8"; 709 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 710 ImmSExti64i32AsmOperand]; 711} 712 713// 4-bit immediate used by some XOP instructions 714// [0, 0xF] 715def ImmUnsignedi4AsmOperand : AsmOperandClass { 716 let Name = "ImmUnsignedi4"; 717 let RenderMethod = "addImmOperands"; 718 let DiagnosticType = "InvalidImmUnsignedi4"; 719} 720 721// Unsigned immediate used by SSE/AVX instructions 722// [0, 0xFF] 723// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 724def ImmUnsignedi8AsmOperand : AsmOperandClass { 725 let Name = "ImmUnsignedi8"; 726 let RenderMethod = "addImmOperands"; 727} 728 729// A couple of more descriptive operand definitions. 730// 16-bits but only 8 bits are significant. 731def i16i8imm : Operand<i16> { 732 let ParserMatchClass = ImmSExti16i8AsmOperand; 733 let OperandType = "OPERAND_IMMEDIATE"; 734} 735// 32-bits but only 8 bits are significant. 736def i32i8imm : Operand<i32> { 737 let ParserMatchClass = ImmSExti32i8AsmOperand; 738 let OperandType = "OPERAND_IMMEDIATE"; 739} 740 741// 64-bits but only 32 bits are significant. 742def i64i32imm : Operand<i64> { 743 let ParserMatchClass = ImmSExti64i32AsmOperand; 744 let OperandType = "OPERAND_IMMEDIATE"; 745} 746 747// 64-bits but only 8 bits are significant. 748def i64i8imm : Operand<i64> { 749 let ParserMatchClass = ImmSExti64i8AsmOperand; 750 let OperandType = "OPERAND_IMMEDIATE"; 751} 752 753// Unsigned 4-bit immediate used by some XOP instructions. 754def u4imm : Operand<i8> { 755 let PrintMethod = "printU8Imm"; 756 let ParserMatchClass = ImmUnsignedi4AsmOperand; 757 let OperandType = "OPERAND_IMMEDIATE"; 758} 759 760// Unsigned 8-bit immediate used by SSE/AVX instructions. 761def u8imm : Operand<i8> { 762 let PrintMethod = "printU8Imm"; 763 let ParserMatchClass = ImmUnsignedi8AsmOperand; 764 let OperandType = "OPERAND_IMMEDIATE"; 765} 766 767// 16-bit immediate but only 8-bits are significant and they are unsigned. 768// Used by BT instructions. 769def i16u8imm : Operand<i16> { 770 let PrintMethod = "printU8Imm"; 771 let ParserMatchClass = ImmUnsignedi8AsmOperand; 772 let OperandType = "OPERAND_IMMEDIATE"; 773} 774 775// 32-bit immediate but only 8-bits are significant and they are unsigned. 776// Used by some SSE/AVX instructions that use intrinsics. 777def i32u8imm : Operand<i32> { 778 let PrintMethod = "printU8Imm"; 779 let ParserMatchClass = ImmUnsignedi8AsmOperand; 780 let OperandType = "OPERAND_IMMEDIATE"; 781} 782 783// 64-bit immediate but only 8-bits are significant and they are unsigned. 784// Used by BT instructions. 785def i64u8imm : Operand<i64> { 786 let PrintMethod = "printU8Imm"; 787 let ParserMatchClass = ImmUnsignedi8AsmOperand; 788 let OperandType = "OPERAND_IMMEDIATE"; 789} 790 791def lea64_32mem : Operand<i32> { 792 let PrintMethod = "printMemReference"; 793 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 794 let ParserMatchClass = X86MemAsmOperand; 795} 796 797// Memory operands that use 64-bit pointers in both ILP32 and LP64. 798def lea64mem : Operand<i64> { 799 let PrintMethod = "printMemReference"; 800 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 801 let ParserMatchClass = X86MemAsmOperand; 802} 803 804let RenderMethod = "addMaskPairOperands" in { 805 def VK1PairAsmOperand : AsmOperandClass { let Name = "VK1Pair"; } 806 def VK2PairAsmOperand : AsmOperandClass { let Name = "VK2Pair"; } 807 def VK4PairAsmOperand : AsmOperandClass { let Name = "VK4Pair"; } 808 def VK8PairAsmOperand : AsmOperandClass { let Name = "VK8Pair"; } 809 def VK16PairAsmOperand : AsmOperandClass { let Name = "VK16Pair"; } 810} 811 812def VK1Pair : RegisterOperand<VK1PAIR, "printVKPair"> { 813 let ParserMatchClass = VK1PairAsmOperand; 814} 815 816def VK2Pair : RegisterOperand<VK2PAIR, "printVKPair"> { 817 let ParserMatchClass = VK2PairAsmOperand; 818} 819 820def VK4Pair : RegisterOperand<VK4PAIR, "printVKPair"> { 821 let ParserMatchClass = VK4PairAsmOperand; 822} 823 824def VK8Pair : RegisterOperand<VK8PAIR, "printVKPair"> { 825 let ParserMatchClass = VK8PairAsmOperand; 826} 827 828def VK16Pair : RegisterOperand<VK16PAIR, "printVKPair"> { 829 let ParserMatchClass = VK16PairAsmOperand; 830} 831 832//===----------------------------------------------------------------------===// 833// X86 Complex Pattern Definitions. 834// 835 836// Define X86-specific addressing mode. 837def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>; 838def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr", 839 [add, sub, mul, X86mul_imm, shl, or, xor, frameindex], 840 []>; 841// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 842def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr", 843 [add, sub, mul, X86mul_imm, shl, or, xor, 844 frameindex, X86WrapperRIP], 845 []>; 846 847def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 848 [tglobaltlsaddr], []>; 849 850def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 851 [tglobaltlsaddr], []>; 852 853def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr", 854 [add, sub, mul, X86mul_imm, shl, or, xor, frameindex, 855 X86WrapperRIP], []>; 856 857def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 858 [tglobaltlsaddr], []>; 859 860def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 861 [tglobaltlsaddr], []>; 862 863def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; 864 865// A relocatable immediate is an operand that can be relocated by the linker to 866// an immediate, such as a regular symbol in non-PIC code. 867def relocImm : ComplexPattern<iAny, 1, "selectRelocImm", 868 [X86Wrapper], [], 0>; 869 870//===----------------------------------------------------------------------===// 871// X86 Instruction Predicate Definitions. 872def TruePredicate : Predicate<"true">; 873 874def HasCMOV : Predicate<"Subtarget->canUseCMOV()">; 875def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">; 876 877def HasNOPL : Predicate<"Subtarget->hasNOPL()">; 878def HasMMX : Predicate<"Subtarget->hasMMX()">; 879def Has3DNow : Predicate<"Subtarget->hasThreeDNow()">; 880def Has3DNowA : Predicate<"Subtarget->hasThreeDNowA()">; 881def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 882def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; 883def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 884def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; 885def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 886def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; 887def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 888def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; 889def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 890def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; 891def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; 892def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 893def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; 894def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 895def NoAVX : Predicate<"!Subtarget->hasAVX()">; 896def HasAVX : Predicate<"Subtarget->hasAVX()">; 897def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 898def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; 899def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; 900def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; 901def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; 902def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; 903def HasCDI : Predicate<"Subtarget->hasCDI()">; 904def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">; 905def HasPFI : Predicate<"Subtarget->hasPFI()">; 906def HasERI : Predicate<"Subtarget->hasERI()">; 907def HasDQI : Predicate<"Subtarget->hasDQI()">; 908def NoDQI : Predicate<"!Subtarget->hasDQI()">; 909def HasBWI : Predicate<"Subtarget->hasBWI()">; 910def NoBWI : Predicate<"!Subtarget->hasBWI()">; 911def HasVLX : Predicate<"Subtarget->hasVLX()">; 912def NoVLX : Predicate<"!Subtarget->hasVLX()">; 913def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">; 914def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">; 915def HasPKU : Predicate<"Subtarget->hasPKU()">; 916def HasVNNI : Predicate<"Subtarget->hasVNNI()">; 917def HasVP2INTERSECT : Predicate<"Subtarget->hasVP2INTERSECT()">; 918def HasBF16 : Predicate<"Subtarget->hasBF16()">; 919def HasFP16 : Predicate<"Subtarget->hasFP16()">; 920def HasAVXVNNIINT8 : Predicate<"Subtarget->hasAVXVNNIINT8()">; 921def HasAVXVNNI : Predicate <"Subtarget->hasAVXVNNI()">; 922def NoVLX_Or_NoVNNI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVNNI()">; 923 924def HasBITALG : Predicate<"Subtarget->hasBITALG()">; 925def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 926def HasAES : Predicate<"Subtarget->hasAES()">; 927def HasVAES : Predicate<"Subtarget->hasVAES()">; 928def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">; 929def HasFXSR : Predicate<"Subtarget->hasFXSR()">; 930def HasX87 : Predicate<"Subtarget->hasX87()">; 931def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">; 932def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">; 933def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">; 934def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">; 935def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; 936def NoVLX_Or_NoVPCLMULQDQ : 937 Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">; 938def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">; 939def HasGFNI : Predicate<"Subtarget->hasGFNI()">; 940def HasFMA : Predicate<"Subtarget->hasFMA()">; 941def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 942def NoFMA4 : Predicate<"!Subtarget->hasFMA4()">; 943def HasXOP : Predicate<"Subtarget->hasXOP()">; 944def HasTBM : Predicate<"Subtarget->hasTBM()">; 945def NoTBM : Predicate<"!Subtarget->hasTBM()">; 946def HasLWP : Predicate<"Subtarget->hasLWP()">; 947def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 948def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 949def HasF16C : Predicate<"Subtarget->hasF16C()">; 950def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 951def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 952def HasBMI : Predicate<"Subtarget->hasBMI()">; 953def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 954def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">; 955def HasVBMI : Predicate<"Subtarget->hasVBMI()">; 956def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">; 957def HasIFMA : Predicate<"Subtarget->hasIFMA()">; 958def HasAVXIFMA : Predicate<"Subtarget->hasAVXIFMA()">; 959def NoVLX_Or_NoIFMA : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasIFMA()">; 960def HasRTM : Predicate<"Subtarget->hasRTM()">; 961def HasADX : Predicate<"Subtarget->hasADX()">; 962def HasSHA : Predicate<"Subtarget->hasSHA()">; 963def HasSGX : Predicate<"Subtarget->hasSGX()">; 964def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; 965def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; 966def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; 967def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; 968def HasPREFETCHI : Predicate<"Subtarget->hasPREFETCHI()">; 969def HasPrefetchW : Predicate<"Subtarget->hasPrefetchW()">; 970def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">; 971def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; 972def HasLAHFSAHF64 : Predicate<"Subtarget->hasLAHFSAHF64()">; 973def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">; 974def HasCLZERO : Predicate<"Subtarget->hasCLZERO()">; 975def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">; 976def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">; 977def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">; 978def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">; 979def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 980def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 981def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; 982def HasCLFLUSH : Predicate<"Subtarget->hasCLFLUSH()">; 983def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; 984def HasCLWB : Predicate<"Subtarget->hasCLWB()">; 985def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; 986def HasRDPID : Predicate<"Subtarget->hasRDPID()">; 987def HasRDPRU : Predicate<"Subtarget->hasRDPRU()">; 988def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">; 989def HasINVPCID : Predicate<"Subtarget->hasINVPCID()">; 990def HasCX8 : Predicate<"Subtarget->hasCX8()">; 991def HasCX16 : Predicate<"Subtarget->hasCX16()">; 992def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; 993def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">; 994def HasAMXFP16 : Predicate<"Subtarget->hasAMXFP16()">; 995def HasCMPCCXADD : Predicate<"Subtarget->hasCMPCCXADD()">; 996def HasAVXNECONVERT : Predicate<"Subtarget->hasAVXNECONVERT()">; 997def HasKL : Predicate<"Subtarget->hasKL()">; 998def HasRAOINT : Predicate<"Subtarget->hasRAOINT()">; 999def HasWIDEKL : Predicate<"Subtarget->hasWIDEKL()">; 1000def HasHRESET : Predicate<"Subtarget->hasHRESET()">; 1001def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">; 1002def HasTSXLDTRK : Predicate<"Subtarget->hasTSXLDTRK()">; 1003def HasAMXTILE : Predicate<"Subtarget->hasAMXTILE()">; 1004def HasAMXBF16 : Predicate<"Subtarget->hasAMXBF16()">; 1005def HasAMXINT8 : Predicate<"Subtarget->hasAMXINT8()">; 1006def HasUINTR : Predicate<"Subtarget->hasUINTR()">; 1007def HasCRC32 : Predicate<"Subtarget->hasCRC32()">; 1008 1009def HasX86_64 : Predicate<"Subtarget->hasX86_64()">; 1010def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, 1011 AssemblerPredicate<(all_of (not Is64Bit)), "Not 64-bit mode">; 1012def In64BitMode : Predicate<"Subtarget->is64Bit()">, 1013 AssemblerPredicate<(all_of Is64Bit), "64-bit mode">; 1014def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; 1015def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; 1016def In16BitMode : Predicate<"Subtarget->is16Bit()">, 1017 AssemblerPredicate<(all_of Is16Bit), "16-bit mode">; 1018def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, 1019 AssemblerPredicate<(all_of (not Is16Bit)), "Not 16-bit mode">; 1020def In32BitMode : Predicate<"Subtarget->is32Bit()">, 1021 AssemblerPredicate<(all_of Is32Bit), "32-bit mode">; 1022def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 1023def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; 1024def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" 1025 "Subtarget->getFrameLowering()->hasFP(*MF)"> { 1026 let RecomputePerFunction = 1; 1027} 1028def IsPS : Predicate<"Subtarget->isTargetPS()">; 1029def NotPS : Predicate<"!Subtarget->isTargetPS()">; 1030def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 1031def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 1032def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 1033def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 1034def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 1035 "TM.getCodeModel() == CodeModel::Kernel">; 1036def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; 1037 1038// We could compute these on a per-module basis but doing so requires accessing 1039// the Function object through the <Target>Subtarget and objections were raised 1040// to that (see post-commit review comments for r301750). 1041let RecomputePerFunction = 1 in { 1042 def OptForSize : Predicate<"shouldOptForSize(MF)">; 1043 def OptForMinSize : Predicate<"MF->getFunction().hasMinSize()">; 1044 def OptForSpeed : Predicate<"!shouldOptForSize(MF)">; 1045 def UseIncDec : Predicate<"!Subtarget->slowIncDec() || " 1046 "shouldOptForSize(MF)">; 1047 def NoSSE41_Or_OptForSize : Predicate<"shouldOptForSize(MF) || " 1048 "!Subtarget->hasSSE41()">; 1049} 1050 1051def CallImmAddr : Predicate<"Subtarget->isLegalToCallImmediateAddr()">; 1052def FavorMemIndirectCall : Predicate<"!Subtarget->slowTwoMemOps()">; 1053def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; 1054def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">; 1055def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">; 1056def HasERMSB : Predicate<"Subtarget->hasERMSB()">; 1057def HasFSRM : Predicate<"Subtarget->hasFSRM()">; 1058def HasMFence : Predicate<"Subtarget->hasMFence()">; 1059def UseIndirectThunkCalls : Predicate<"Subtarget->useIndirectThunkCalls()">; 1060def NotUseIndirectThunkCalls : Predicate<"!Subtarget->useIndirectThunkCalls()">; 1061 1062//===----------------------------------------------------------------------===// 1063// X86 Instruction Format Definitions. 1064// 1065 1066include "X86InstrFormats.td" 1067 1068//===----------------------------------------------------------------------===// 1069// Pattern fragments. 1070// 1071 1072// X86 specific condition code. These correspond to CondCode in 1073// X86InstrInfo.h. They must be kept in synch. 1074def X86_COND_O : PatLeaf<(i8 0)>; 1075def X86_COND_NO : PatLeaf<(i8 1)>; 1076def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 1077def X86_COND_AE : PatLeaf<(i8 3)>; // alt. COND_NC 1078def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 1079def X86_COND_NE : PatLeaf<(i8 5)>; // alt. COND_NZ 1080def X86_COND_BE : PatLeaf<(i8 6)>; // alt. COND_NA 1081def X86_COND_A : PatLeaf<(i8 7)>; // alt. COND_NBE 1082def X86_COND_S : PatLeaf<(i8 8)>; 1083def X86_COND_NS : PatLeaf<(i8 9)>; 1084def X86_COND_P : PatLeaf<(i8 10)>; // alt. COND_PE 1085def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 1086def X86_COND_L : PatLeaf<(i8 12)>; // alt. COND_NGE 1087def X86_COND_GE : PatLeaf<(i8 13)>; // alt. COND_NL 1088def X86_COND_LE : PatLeaf<(i8 14)>; // alt. COND_NG 1089def X86_COND_G : PatLeaf<(i8 15)>; // alt. COND_NLE 1090 1091def i16immSExt8 : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>; 1092def i32immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>; 1093def i64immSExt8 : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>; 1094def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>; 1095def i64timmSExt32 : TImmLeaf<i64, [{ return isInt<32>(Imm); }]>; 1096 1097def i16relocImmSExt8 : PatLeaf<(i16 relocImm), [{ 1098 return isSExtAbsoluteSymbolRef(8, N); 1099}]>; 1100def i32relocImmSExt8 : PatLeaf<(i32 relocImm), [{ 1101 return isSExtAbsoluteSymbolRef(8, N); 1102}]>; 1103def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{ 1104 return isSExtAbsoluteSymbolRef(8, N); 1105}]>; 1106def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{ 1107 return isSExtAbsoluteSymbolRef(32, N); 1108}]>; 1109 1110// If we have multiple users of an immediate, it's much smaller to reuse 1111// the register, rather than encode the immediate in every instruction. 1112// This has the risk of increasing register pressure from stretched live 1113// ranges, however, the immediates should be trivial to rematerialize by 1114// the RA in the event of high register pressure. 1115// TODO : This is currently enabled for stores and binary ops. There are more 1116// cases for which this can be enabled, though this catches the bulk of the 1117// issues. 1118// TODO2 : This should really also be enabled under O2, but there's currently 1119// an issue with RA where we don't pull the constants into their users 1120// when we rematerialize them. I'll follow-up on enabling O2 after we fix that 1121// issue. 1122// TODO3 : This is currently limited to single basic blocks (DAG creation 1123// pulls block immediates to the top and merges them if necessary). 1124// Eventually, it would be nice to allow ConstantHoisting to merge constants 1125// globally for potentially added savings. 1126// 1127def imm_su : PatLeaf<(imm), [{ 1128 return !shouldAvoidImmediateInstFormsForSize(N); 1129}]>; 1130def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ 1131 return !shouldAvoidImmediateInstFormsForSize(N); 1132}]>; 1133 1134def relocImm8_su : PatLeaf<(i8 relocImm), [{ 1135 return !shouldAvoidImmediateInstFormsForSize(N); 1136}]>; 1137def relocImm16_su : PatLeaf<(i16 relocImm), [{ 1138 return !shouldAvoidImmediateInstFormsForSize(N); 1139}]>; 1140def relocImm32_su : PatLeaf<(i32 relocImm), [{ 1141 return !shouldAvoidImmediateInstFormsForSize(N); 1142}]>; 1143 1144def i16relocImmSExt8_su : PatLeaf<(i16relocImmSExt8), [{ 1145 return !shouldAvoidImmediateInstFormsForSize(N); 1146}]>; 1147def i32relocImmSExt8_su : PatLeaf<(i32relocImmSExt8), [{ 1148 return !shouldAvoidImmediateInstFormsForSize(N); 1149}]>; 1150def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{ 1151 return !shouldAvoidImmediateInstFormsForSize(N); 1152}]>; 1153def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{ 1154 return !shouldAvoidImmediateInstFormsForSize(N); 1155}]>; 1156 1157def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ 1158 return !shouldAvoidImmediateInstFormsForSize(N); 1159}]>; 1160def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ 1161 return !shouldAvoidImmediateInstFormsForSize(N); 1162}]>; 1163def i64immSExt8_su : PatLeaf<(i64immSExt8), [{ 1164 return !shouldAvoidImmediateInstFormsForSize(N); 1165}]>; 1166 1167// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 1168// unsigned field. 1169def i64immZExt32 : ImmLeaf<i64, [{ return isUInt<32>(Imm); }]>; 1170 1171def i64immZExt32SExt8 : ImmLeaf<i64, [{ 1172 return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm)); 1173}]>; 1174 1175// Helper fragments for loads. 1176 1177// It's safe to fold a zextload/extload from i1 as a regular i8 load. The 1178// upper bits are guaranteed to be zero and we were going to emit a MOV8rm 1179// which might get folded during peephole anyway. 1180def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{ 1181 LoadSDNode *LD = cast<LoadSDNode>(N); 1182 ISD::LoadExtType ExtType = LD->getExtensionType(); 1183 return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD || 1184 ExtType == ISD::ZEXTLOAD; 1185}]>; 1186 1187// It's always safe to treat a anyext i16 load as a i32 load if the i16 is 1188// known to be 32-bit aligned or better. Ditto for i8 to i16. 1189def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 1190 LoadSDNode *LD = cast<LoadSDNode>(N); 1191 ISD::LoadExtType ExtType = LD->getExtensionType(); 1192 if (ExtType == ISD::NON_EXTLOAD) 1193 return true; 1194 if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad) 1195 return LD->getAlign() >= 2 && LD->isSimple(); 1196 return false; 1197}]>; 1198 1199def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 1200 LoadSDNode *LD = cast<LoadSDNode>(N); 1201 ISD::LoadExtType ExtType = LD->getExtensionType(); 1202 if (ExtType == ISD::NON_EXTLOAD) 1203 return true; 1204 if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad) 1205 return LD->getAlign() >= 4 && LD->isSimple(); 1206 return false; 1207}]>; 1208 1209def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 1210def loadf16 : PatFrag<(ops node:$ptr), (f16 (load node:$ptr))>; 1211def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 1212def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 1213def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 1214def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; 1215def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ 1216 LoadSDNode *Ld = cast<LoadSDNode>(N); 1217 return Ld->getAlign() >= Ld->getMemoryVT().getStoreSize(); 1218}]>; 1219def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ 1220 LoadSDNode *Ld = cast<LoadSDNode>(N); 1221 return Subtarget->hasSSEUnalignedMem() || 1222 Ld->getAlign() >= Ld->getMemoryVT().getStoreSize(); 1223}]>; 1224 1225def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 1226def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 1227def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 1228def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 1229def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 1230def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 1231 1232def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 1233def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 1234def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 1235def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 1236def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 1237def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 1238def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 1239def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 1240def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 1241def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 1242 1243def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 1244def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 1245def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 1246def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 1247def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 1248def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 1249def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 1250def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 1251def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 1252 1253// We can treat an i8/i16 extending load to i64 as a 32 bit load if its known 1254// to be 4 byte aligned or better. 1255def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (unindexedload node:$ptr)), [{ 1256 LoadSDNode *LD = cast<LoadSDNode>(N); 1257 ISD::LoadExtType ExtType = LD->getExtensionType(); 1258 if (ExtType != ISD::EXTLOAD) 1259 return false; 1260 if (LD->getMemoryVT() == MVT::i32) 1261 return true; 1262 1263 return LD->getAlign() >= 4 && LD->isSimple(); 1264}]>; 1265 1266 1267// An 'and' node with a single use. 1268def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 1269 return N->hasOneUse(); 1270}]>; 1271// An 'srl' node with a single use. 1272def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 1273 return N->hasOneUse(); 1274}]>; 1275// An 'trunc' node with a single use. 1276def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 1277 return N->hasOneUse(); 1278}]>; 1279 1280//===----------------------------------------------------------------------===// 1281// Instruction list. 1282// 1283 1284// Nop 1285let hasSideEffects = 0, SchedRW = [WriteNop] in { 1286 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; 1287 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), 1288 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; 1289 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), 1290 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; 1291 def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero), 1292 "nop{q}\t$zero", []>, TB, NotMemoryFoldable, 1293 Requires<[In64BitMode]>; 1294 // Also allow register so we can assemble/disassemble 1295 def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero), 1296 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; 1297 def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero), 1298 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; 1299 def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero), 1300 "nop{q}\t$zero", []>, TB, NotMemoryFoldable, 1301 Requires<[In64BitMode]>; 1302} 1303 1304 1305// Constructing a stack frame. 1306def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 1307 "enter\t$len, $lvl", []>, Sched<[WriteMicrocoded]>; 1308 1309let SchedRW = [WriteALU] in { 1310let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in 1311def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", []>, 1312 Requires<[Not64BitMode]>; 1313 1314let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in 1315def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", []>, 1316 Requires<[In64BitMode]>; 1317} // SchedRW 1318 1319//===----------------------------------------------------------------------===// 1320// Miscellaneous Instructions. 1321// 1322 1323let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1, 1324 SchedRW = [WriteSystem] in 1325 def Int_eh_sjlj_setup_dispatch 1326 : PseudoI<(outs), (ins), [(X86eh_sjlj_setup_dispatch)]>; 1327 1328let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { 1329let mayLoad = 1, SchedRW = [WriteLoad] in { 1330def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 1331 OpSize16; 1332def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, 1333 OpSize32, Requires<[Not64BitMode]>; 1334// Long form for the disassembler. 1335let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1336def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 1337 OpSize16, NotMemoryFoldable; 1338def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, 1339 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; 1340} // isCodeGenOnly = 1, ForceDisassemble = 1 1341} // mayLoad, SchedRW 1342let mayStore = 1, mayLoad = 1, SchedRW = [WriteCopy] in { 1343def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>, 1344 OpSize16; 1345def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>, 1346 OpSize32, Requires<[Not64BitMode]>; 1347} // mayStore, mayLoad, SchedRW 1348 1349let mayStore = 1, SchedRW = [WriteStore] in { 1350def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 1351 OpSize16; 1352def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, 1353 OpSize32, Requires<[Not64BitMode]>; 1354// Long form for the disassembler. 1355let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1356def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 1357 OpSize16, NotMemoryFoldable; 1358def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, 1359 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; 1360} // isCodeGenOnly = 1, ForceDisassemble = 1 1361 1362def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), 1363 "push{w}\t$imm", []>, OpSize16; 1364def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1365 "push{w}\t$imm", []>, OpSize16; 1366 1367def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 1368 "push{l}\t$imm", []>, OpSize32, 1369 Requires<[Not64BitMode]>; 1370def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 1371 "push{l}\t$imm", []>, OpSize32, 1372 Requires<[Not64BitMode]>; 1373} // mayStore, SchedRW 1374 1375let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in { 1376def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, 1377 OpSize16; 1378def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, 1379 OpSize32, Requires<[Not64BitMode]>; 1380} // mayLoad, mayStore, SchedRW 1381 1382} 1383 1384let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, 1385 SchedRW = [WriteRMW], Defs = [ESP] in { 1386 let Uses = [ESP] in 1387 def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins), 1388 [(set GR32:$dst, (int_x86_flags_read_u32))]>, 1389 Requires<[Not64BitMode]>; 1390 1391 let Uses = [RSP] in 1392 def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins), 1393 [(set GR64:$dst, (int_x86_flags_read_u64))]>, 1394 Requires<[In64BitMode]>; 1395} 1396 1397let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, 1398 SchedRW = [WriteRMW] in { 1399 let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in 1400 def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src), 1401 [(int_x86_flags_write_u32 GR32:$src)]>, 1402 Requires<[Not64BitMode]>; 1403 1404 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in 1405 def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src), 1406 [(int_x86_flags_write_u64 GR64:$src)]>, 1407 Requires<[In64BitMode]>; 1408} 1409 1410let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0, 1411 SchedRW = [WriteLoad] in { 1412def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize16; 1413def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, OpSize32, 1414 Requires<[Not64BitMode]>; 1415} 1416 1417let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0, 1418 SchedRW = [WriteStore] in { 1419def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize16; 1420def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, OpSize32, 1421 Requires<[Not64BitMode]>; 1422} 1423 1424let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { 1425let mayLoad = 1, SchedRW = [WriteLoad] in { 1426def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, 1427 OpSize32, Requires<[In64BitMode]>; 1428// Long form for the disassembler. 1429let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1430def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, 1431 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; 1432} // isCodeGenOnly = 1, ForceDisassemble = 1 1433} // mayLoad, SchedRW 1434let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in 1435def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>, 1436 OpSize32, Requires<[In64BitMode]>; 1437let mayStore = 1, SchedRW = [WriteStore] in { 1438def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, 1439 OpSize32, Requires<[In64BitMode]>; 1440// Long form for the disassembler. 1441let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1442def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, 1443 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; 1444} // isCodeGenOnly = 1, ForceDisassemble = 1 1445} // mayStore, SchedRW 1446let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in { 1447def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>, 1448 OpSize32, Requires<[In64BitMode]>; 1449} // mayLoad, mayStore, SchedRW 1450} 1451 1452let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, 1453 SchedRW = [WriteStore] in { 1454def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 1455 "push{q}\t$imm", []>, OpSize32, 1456 Requires<[In64BitMode]>; 1457def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 1458 "push{q}\t$imm", []>, OpSize32, 1459 Requires<[In64BitMode]>; 1460} 1461 1462let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in 1463def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, 1464 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; 1465let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in 1466def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, 1467 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; 1468 1469let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 1470 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { 1471def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", []>, 1472 OpSize32, Requires<[Not64BitMode]>; 1473def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", []>, 1474 OpSize16, Requires<[Not64BitMode]>; 1475} 1476let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 1477 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { 1478def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", []>, 1479 OpSize32, Requires<[Not64BitMode]>; 1480def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", []>, 1481 OpSize16, Requires<[Not64BitMode]>; 1482} 1483 1484let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in { 1485// This instruction is a consequence of BSWAP32r observing operand size. The 1486// encoding is valid, but the behavior is undefined. 1487let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in 1488def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 1489 "bswap{w}\t$dst", []>, OpSize16, TB; 1490// GR32 = bswap GR32 1491def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 1492 "bswap{l}\t$dst", 1493 [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB; 1494 1495let SchedRW = [WriteBSWAP64] in 1496def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 1497 "bswap{q}\t$dst", 1498 [(set GR64:$dst, (bswap GR64:$src))]>, TB; 1499} // Constraints = "$src = $dst", SchedRW 1500 1501// Bit scan instructions. 1502let Defs = [EFLAGS] in { 1503def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1504 "bsf{w}\t{$src, $dst|$dst, $src}", 1505 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, 1506 PS, OpSize16, Sched<[WriteBSF]>; 1507def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1508 "bsf{w}\t{$src, $dst|$dst, $src}", 1509 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, 1510 PS, OpSize16, Sched<[WriteBSFLd]>; 1511def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1512 "bsf{l}\t{$src, $dst|$dst, $src}", 1513 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, 1514 PS, OpSize32, Sched<[WriteBSF]>; 1515def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1516 "bsf{l}\t{$src, $dst|$dst, $src}", 1517 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, 1518 PS, OpSize32, Sched<[WriteBSFLd]>; 1519def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1520 "bsf{q}\t{$src, $dst|$dst, $src}", 1521 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, 1522 PS, Sched<[WriteBSF]>; 1523def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1524 "bsf{q}\t{$src, $dst|$dst, $src}", 1525 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, 1526 PS, Sched<[WriteBSFLd]>; 1527 1528def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1529 "bsr{w}\t{$src, $dst|$dst, $src}", 1530 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, 1531 PS, OpSize16, Sched<[WriteBSR]>; 1532def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1533 "bsr{w}\t{$src, $dst|$dst, $src}", 1534 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, 1535 PS, OpSize16, Sched<[WriteBSRLd]>; 1536def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1537 "bsr{l}\t{$src, $dst|$dst, $src}", 1538 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, 1539 PS, OpSize32, Sched<[WriteBSR]>; 1540def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1541 "bsr{l}\t{$src, $dst|$dst, $src}", 1542 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, 1543 PS, OpSize32, Sched<[WriteBSRLd]>; 1544def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1545 "bsr{q}\t{$src, $dst|$dst, $src}", 1546 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, 1547 PS, Sched<[WriteBSR]>; 1548def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1549 "bsr{q}\t{$src, $dst|$dst, $src}", 1550 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, 1551 PS, Sched<[WriteBSRLd]>; 1552} // Defs = [EFLAGS] 1553 1554let SchedRW = [WriteMicrocoded] in { 1555let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in { 1556def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1557 "movsb\t{$src, $dst|$dst, $src}", []>; 1558def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1559 "movsw\t{$src, $dst|$dst, $src}", []>, OpSize16; 1560def MOVSL : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1561 "movs{l|d}\t{$src, $dst|$dst, $src}", []>, OpSize32; 1562def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1563 "movsq\t{$src, $dst|$dst, $src}", []>, 1564 Requires<[In64BitMode]>; 1565} 1566 1567let Defs = [EDI], Uses = [AL,EDI,DF] in 1568def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst), 1569 "stosb\t{%al, $dst|$dst, al}", []>; 1570let Defs = [EDI], Uses = [AX,EDI,DF] in 1571def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst), 1572 "stosw\t{%ax, $dst|$dst, ax}", []>, OpSize16; 1573let Defs = [EDI], Uses = [EAX,EDI,DF] in 1574def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst), 1575 "stos{l|d}\t{%eax, $dst|$dst, eax}", []>, OpSize32; 1576let Defs = [RDI], Uses = [RAX,RDI,DF] in 1577def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst), 1578 "stosq\t{%rax, $dst|$dst, rax}", []>, 1579 Requires<[In64BitMode]>; 1580 1581let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in 1582def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), 1583 "scasb\t{$dst, %al|al, $dst}", []>; 1584let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in 1585def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), 1586 "scasw\t{$dst, %ax|ax, $dst}", []>, OpSize16; 1587let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in 1588def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), 1589 "scas{l|d}\t{$dst, %eax|eax, $dst}", []>, OpSize32; 1590let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in 1591def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), 1592 "scasq\t{$dst, %rax|rax, $dst}", []>, 1593 Requires<[In64BitMode]>; 1594 1595let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in { 1596def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1597 "cmpsb\t{$dst, $src|$src, $dst}", []>; 1598def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1599 "cmpsw\t{$dst, $src|$src, $dst}", []>, OpSize16; 1600def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1601 "cmps{l|d}\t{$dst, $src|$src, $dst}", []>, OpSize32; 1602def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1603 "cmpsq\t{$dst, $src|$src, $dst}", []>, 1604 Requires<[In64BitMode]>; 1605} 1606} // SchedRW 1607 1608//===----------------------------------------------------------------------===// 1609// Move Instructions. 1610// 1611let SchedRW = [WriteMove] in { 1612let hasSideEffects = 0, isMoveReg = 1 in { 1613def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 1614 "mov{b}\t{$src, $dst|$dst, $src}", []>; 1615def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1616 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 1617def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1618 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 1619def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1620 "mov{q}\t{$src, $dst|$dst, $src}", []>; 1621} 1622 1623let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 1624def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 1625 "mov{b}\t{$src, $dst|$dst, $src}", 1626 [(set GR8:$dst, imm:$src)]>; 1627def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 1628 "mov{w}\t{$src, $dst|$dst, $src}", 1629 [(set GR16:$dst, imm:$src)]>, OpSize16; 1630def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 1631 "mov{l}\t{$src, $dst|$dst, $src}", 1632 [(set GR32:$dst, imm:$src)]>, OpSize32; 1633def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 1634 "mov{q}\t{$src, $dst|$dst, $src}", 1635 [(set GR64:$dst, i64immSExt32:$src)]>; 1636} 1637let isReMaterializable = 1, isMoveImm = 1 in { 1638def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 1639 "movabs{q}\t{$src, $dst|$dst, $src}", 1640 [(set GR64:$dst, imm:$src)]>; 1641} 1642 1643// Longer forms that use a ModR/M byte. Needed for disassembler 1644let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 1645def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), 1646 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1647 FoldGenData<"MOV8ri">; 1648def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), 1649 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 1650 FoldGenData<"MOV16ri">; 1651def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), 1652 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 1653 FoldGenData<"MOV32ri">; 1654} 1655} // SchedRW 1656 1657let SchedRW = [WriteStore] in { 1658def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 1659 "mov{b}\t{$src, $dst|$dst, $src}", 1660 [(store (i8 imm_su:$src), addr:$dst)]>; 1661def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 1662 "mov{w}\t{$src, $dst|$dst, $src}", 1663 [(store (i16 imm_su:$src), addr:$dst)]>, OpSize16; 1664def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 1665 "mov{l}\t{$src, $dst|$dst, $src}", 1666 [(store (i32 imm_su:$src), addr:$dst)]>, OpSize32; 1667def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 1668 "mov{q}\t{$src, $dst|$dst, $src}", 1669 [(store i64immSExt32_su:$src, addr:$dst)]>, 1670 Requires<[In64BitMode]>; 1671} // SchedRW 1672 1673def : Pat<(i32 relocImm:$src), (MOV32ri relocImm:$src)>; 1674def : Pat<(i64 relocImm:$src), (MOV64ri relocImm:$src)>; 1675 1676def : Pat<(store (i8 relocImm8_su:$src), addr:$dst), 1677 (MOV8mi addr:$dst, relocImm8_su:$src)>; 1678def : Pat<(store (i16 relocImm16_su:$src), addr:$dst), 1679 (MOV16mi addr:$dst, relocImm16_su:$src)>; 1680def : Pat<(store (i32 relocImm32_su:$src), addr:$dst), 1681 (MOV32mi addr:$dst, relocImm32_su:$src)>; 1682def : Pat<(store (i64 i64relocImmSExt32_su:$src), addr:$dst), 1683 (MOV64mi32 addr:$dst, i64immSExt32_su:$src)>; 1684 1685let hasSideEffects = 0 in { 1686 1687/// Memory offset versions of moves. The immediate is an address mode sized 1688/// offset from the segment base. 1689let SchedRW = [WriteALU] in { 1690let mayLoad = 1 in { 1691let Defs = [AL] in 1692def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), 1693 "mov{b}\t{$src, %al|al, $src}", []>, 1694 AdSize32; 1695let Defs = [AX] in 1696def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), 1697 "mov{w}\t{$src, %ax|ax, $src}", []>, 1698 OpSize16, AdSize32; 1699let Defs = [EAX] in 1700def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), 1701 "mov{l}\t{$src, %eax|eax, $src}", []>, 1702 OpSize32, AdSize32; 1703let Defs = [RAX] in 1704def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), 1705 "mov{q}\t{$src, %rax|rax, $src}", []>, 1706 AdSize32; 1707 1708let Defs = [AL] in 1709def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), 1710 "mov{b}\t{$src, %al|al, $src}", []>, AdSize16; 1711let Defs = [AX] in 1712def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), 1713 "mov{w}\t{$src, %ax|ax, $src}", []>, 1714 OpSize16, AdSize16; 1715let Defs = [EAX] in 1716def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), 1717 "mov{l}\t{$src, %eax|eax, $src}", []>, 1718 AdSize16, OpSize32; 1719} // mayLoad 1720let mayStore = 1 in { 1721let Uses = [AL] in 1722def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst), 1723 "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32; 1724let Uses = [AX] in 1725def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst), 1726 "mov{w}\t{%ax, $dst|$dst, ax}", []>, 1727 OpSize16, AdSize32; 1728let Uses = [EAX] in 1729def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst), 1730 "mov{l}\t{%eax, $dst|$dst, eax}", []>, 1731 OpSize32, AdSize32; 1732let Uses = [RAX] in 1733def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst), 1734 "mov{q}\t{%rax, $dst|$dst, rax}", []>, 1735 AdSize32; 1736 1737let Uses = [AL] in 1738def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst), 1739 "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize16; 1740let Uses = [AX] in 1741def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst), 1742 "mov{w}\t{%ax, $dst|$dst, ax}", []>, 1743 OpSize16, AdSize16; 1744let Uses = [EAX] in 1745def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst), 1746 "mov{l}\t{%eax, $dst|$dst, eax}", []>, 1747 OpSize32, AdSize16; 1748} // mayStore 1749 1750// These forms all have full 64-bit absolute addresses in their instructions 1751// and use the movabs mnemonic to indicate this specific form. 1752let mayLoad = 1 in { 1753let Defs = [AL] in 1754def MOV8ao64 : Ii64<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), 1755 "movabs{b}\t{$src, %al|al, $src}", []>, 1756 AdSize64; 1757let Defs = [AX] in 1758def MOV16ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), 1759 "movabs{w}\t{$src, %ax|ax, $src}", []>, 1760 OpSize16, AdSize64; 1761let Defs = [EAX] in 1762def MOV32ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), 1763 "movabs{l}\t{$src, %eax|eax, $src}", []>, 1764 OpSize32, AdSize64; 1765let Defs = [RAX] in 1766def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), 1767 "movabs{q}\t{$src, %rax|rax, $src}", []>, 1768 AdSize64; 1769} // mayLoad 1770 1771let mayStore = 1 in { 1772let Uses = [AL] in 1773def MOV8o64a : Ii64<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst), 1774 "movabs{b}\t{%al, $dst|$dst, al}", []>, 1775 AdSize64; 1776let Uses = [AX] in 1777def MOV16o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst), 1778 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, 1779 OpSize16, AdSize64; 1780let Uses = [EAX] in 1781def MOV32o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst), 1782 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, 1783 OpSize32, AdSize64; 1784let Uses = [RAX] in 1785def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst), 1786 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, 1787 AdSize64; 1788} // mayStore 1789} // SchedRW 1790} // hasSideEffects = 0 1791 1792let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, 1793 SchedRW = [WriteMove], isMoveReg = 1 in { 1794def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 1795 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1796 FoldGenData<"MOV8rr">; 1797def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1798 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 1799 FoldGenData<"MOV16rr">; 1800def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1801 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 1802 FoldGenData<"MOV32rr">; 1803def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1804 "mov{q}\t{$src, $dst|$dst, $src}", []>, 1805 FoldGenData<"MOV64rr">; 1806} 1807 1808// Reversed version with ".s" suffix for GAS compatibility. 1809def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}", 1810 (MOV8rr_REV GR8:$dst, GR8:$src), 0>; 1811def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}", 1812 (MOV16rr_REV GR16:$dst, GR16:$src), 0>; 1813def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}", 1814 (MOV32rr_REV GR32:$dst, GR32:$src), 0>; 1815def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}", 1816 (MOV64rr_REV GR64:$dst, GR64:$src), 0>; 1817def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1818 (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">; 1819def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1820 (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">; 1821def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1822 (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">; 1823def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1824 (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">; 1825 1826let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 1827def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 1828 "mov{b}\t{$src, $dst|$dst, $src}", 1829 [(set GR8:$dst, (loadi8 addr:$src))]>; 1830def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1831 "mov{w}\t{$src, $dst|$dst, $src}", 1832 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize16; 1833def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1834 "mov{l}\t{$src, $dst|$dst, $src}", 1835 [(set GR32:$dst, (loadi32 addr:$src))]>, OpSize32; 1836def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1837 "mov{q}\t{$src, $dst|$dst, $src}", 1838 [(set GR64:$dst, (load addr:$src))]>; 1839} 1840 1841let SchedRW = [WriteStore] in { 1842def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 1843 "mov{b}\t{$src, $dst|$dst, $src}", 1844 [(store GR8:$src, addr:$dst)]>; 1845def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1846 "mov{w}\t{$src, $dst|$dst, $src}", 1847 [(store GR16:$src, addr:$dst)]>, OpSize16; 1848def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1849 "mov{l}\t{$src, $dst|$dst, $src}", 1850 [(store GR32:$src, addr:$dst)]>, OpSize32; 1851def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1852 "mov{q}\t{$src, $dst|$dst, $src}", 1853 [(store GR64:$src, addr:$dst)]>; 1854} // SchedRW 1855 1856// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 1857// that they can be used for copying and storing h registers, which can't be 1858// encoded when a REX prefix is present. 1859let isCodeGenOnly = 1 in { 1860let hasSideEffects = 0, isMoveReg = 1 in 1861def MOV8rr_NOREX : I<0x88, MRMDestReg, 1862 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1863 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1864 Sched<[WriteMove]>; 1865let mayStore = 1, hasSideEffects = 0 in 1866def MOV8mr_NOREX : I<0x88, MRMDestMem, 1867 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1868 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1869 Sched<[WriteStore]>; 1870let mayLoad = 1, hasSideEffects = 0, 1871 canFoldAsLoad = 1, isReMaterializable = 1 in 1872def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1873 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1874 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1875 Sched<[WriteLoad]>; 1876} 1877 1878 1879// Condition code ops, incl. set if equal/not equal/... 1880let SchedRW = [WriteLAHFSAHF] in { 1881let Defs = [EFLAGS], Uses = [AH], hasSideEffects = 0 in 1882def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>, // flags = AH 1883 Requires<[HasLAHFSAHF]>; 1884let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in 1885def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags 1886 Requires<[HasLAHFSAHF]>; 1887} // SchedRW 1888 1889//===----------------------------------------------------------------------===// 1890// Bit tests instructions: BT, BTS, BTR, BTC. 1891 1892let Defs = [EFLAGS] in { 1893let SchedRW = [WriteBitTest] in { 1894def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1895 "bt{w}\t{$src2, $src1|$src1, $src2}", 1896 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, 1897 OpSize16, TB, NotMemoryFoldable; 1898def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1899 "bt{l}\t{$src2, $src1|$src1, $src2}", 1900 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, 1901 OpSize32, TB, NotMemoryFoldable; 1902def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1903 "bt{q}\t{$src2, $src1|$src1, $src2}", 1904 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB, 1905 NotMemoryFoldable; 1906} // SchedRW 1907 1908// Unlike with the register+register form, the memory+register form of the 1909// bt instruction does not ignore the high bits of the index. From ISel's 1910// perspective, this is pretty bizarre. Make these instructions disassembly 1911// only for now. These instructions are also slow on modern CPUs so that's 1912// another reason to avoid generating them. 1913 1914let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteBitTestRegLd] in { 1915 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1916 "bt{w}\t{$src2, $src1|$src1, $src2}", 1917 []>, OpSize16, TB, NotMemoryFoldable; 1918 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1919 "bt{l}\t{$src2, $src1|$src1, $src2}", 1920 []>, OpSize32, TB, NotMemoryFoldable; 1921 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1922 "bt{q}\t{$src2, $src1|$src1, $src2}", 1923 []>, TB, NotMemoryFoldable; 1924} 1925 1926let SchedRW = [WriteBitTest] in { 1927def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16u8imm:$src2), 1928 "bt{w}\t{$src2, $src1|$src1, $src2}", 1929 [(set EFLAGS, (X86bt GR16:$src1, imm:$src2))]>, 1930 OpSize16, TB; 1931def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32u8imm:$src2), 1932 "bt{l}\t{$src2, $src1|$src1, $src2}", 1933 [(set EFLAGS, (X86bt GR32:$src1, imm:$src2))]>, 1934 OpSize32, TB; 1935def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64u8imm:$src2), 1936 "bt{q}\t{$src2, $src1|$src1, $src2}", 1937 [(set EFLAGS, (X86bt GR64:$src1, imm:$src2))]>, TB; 1938} // SchedRW 1939 1940// Note that these instructions aren't slow because that only applies when the 1941// other operand is in a register. When it's an immediate, bt is still fast. 1942let SchedRW = [WriteBitTestImmLd] in { 1943def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 1944 "bt{w}\t{$src2, $src1|$src1, $src2}", 1945 [(set EFLAGS, (X86bt (loadi16 addr:$src1), 1946 imm:$src2))]>, 1947 OpSize16, TB; 1948def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 1949 "bt{l}\t{$src2, $src1|$src1, $src2}", 1950 [(set EFLAGS, (X86bt (loadi32 addr:$src1), 1951 imm:$src2))]>, 1952 OpSize32, TB; 1953def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 1954 "bt{q}\t{$src2, $src1|$src1, $src2}", 1955 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1956 imm:$src2))]>, TB, 1957 Requires<[In64BitMode]>; 1958} // SchedRW 1959 1960let hasSideEffects = 0 in { 1961let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 1962def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1963 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, 1964 OpSize16, TB, NotMemoryFoldable; 1965def BTC32rr : I<0xBB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1966 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, 1967 OpSize32, TB, NotMemoryFoldable; 1968def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1969 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1970 NotMemoryFoldable; 1971} // SchedRW 1972 1973let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in { 1974def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1975 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, 1976 OpSize16, TB, NotMemoryFoldable; 1977def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1978 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, 1979 OpSize32, TB, NotMemoryFoldable; 1980def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1981 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1982 NotMemoryFoldable; 1983} 1984 1985let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 1986def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2), 1987 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 1988def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2), 1989 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 1990def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2), 1991 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1992} // SchedRW 1993 1994let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in { 1995def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 1996 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 1997def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 1998 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 1999def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 2000 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2001 Requires<[In64BitMode]>; 2002} 2003 2004let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 2005def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 2006 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 2007 OpSize16, TB, NotMemoryFoldable; 2008def BTR32rr : I<0xB3, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 2009 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 2010 OpSize32, TB, NotMemoryFoldable; 2011def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 2012 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2013 NotMemoryFoldable; 2014} // SchedRW 2015 2016let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in { 2017def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 2018 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 2019 OpSize16, TB, NotMemoryFoldable; 2020def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 2021 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 2022 OpSize32, TB, NotMemoryFoldable; 2023def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 2024 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2025 NotMemoryFoldable; 2026} 2027 2028let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 2029def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2), 2030 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 2031 OpSize16, TB; 2032def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2), 2033 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 2034 OpSize32, TB; 2035def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2), 2036 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 2037} // SchedRW 2038 2039let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in { 2040def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 2041 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 2042 OpSize16, TB; 2043def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 2044 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 2045 OpSize32, TB; 2046def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 2047 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2048 Requires<[In64BitMode]>; 2049} 2050 2051let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 2052def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 2053 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, 2054 OpSize16, TB, NotMemoryFoldable; 2055def BTS32rr : I<0xAB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 2056 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, 2057 OpSize32, TB, NotMemoryFoldable; 2058def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 2059 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2060 NotMemoryFoldable; 2061} // SchedRW 2062 2063let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in { 2064def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 2065 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, 2066 OpSize16, TB, NotMemoryFoldable; 2067def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 2068 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, 2069 OpSize32, TB, NotMemoryFoldable; 2070def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 2071 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2072 NotMemoryFoldable; 2073} 2074 2075let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 2076def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2), 2077 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 2078def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2), 2079 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 2080def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2), 2081 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 2082} // SchedRW 2083 2084let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in { 2085def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 2086 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 2087def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 2088 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 2089def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 2090 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2091 Requires<[In64BitMode]>; 2092} 2093} // hasSideEffects = 0 2094} // Defs = [EFLAGS] 2095 2096 2097//===----------------------------------------------------------------------===// 2098// Atomic support 2099// 2100 2101// Atomic swap. These are just normal xchg instructions. But since a memory 2102// operand is referenced, the atomicity is ensured. 2103multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag> { 2104 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 2105 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 2106 (ins GR8:$val, i8mem:$ptr), 2107 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 2108 [(set 2109 GR8:$dst, 2110 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>; 2111 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 2112 (ins GR16:$val, i16mem:$ptr), 2113 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 2114 [(set 2115 GR16:$dst, 2116 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, 2117 OpSize16; 2118 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 2119 (ins GR32:$val, i32mem:$ptr), 2120 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 2121 [(set 2122 GR32:$dst, 2123 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, 2124 OpSize32; 2125 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 2126 (ins GR64:$val, i64mem:$ptr), 2127 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 2128 [(set 2129 GR64:$dst, 2130 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; 2131 } 2132} 2133 2134defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">, NotMemoryFoldable; 2135 2136// Swap between registers. 2137let SchedRW = [WriteXCHG] in { 2138let Constraints = "$src1 = $dst1, $src2 = $dst2", hasSideEffects = 0 in { 2139def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2), 2140 (ins GR8:$src1, GR8:$src2), 2141 "xchg{b}\t{$src2, $src1|$src1, $src2}", []>, NotMemoryFoldable; 2142def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2), 2143 (ins GR16:$src1, GR16:$src2), 2144 "xchg{w}\t{$src2, $src1|$src1, $src2}", []>, 2145 OpSize16, NotMemoryFoldable; 2146def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2), 2147 (ins GR32:$src1, GR32:$src2), 2148 "xchg{l}\t{$src2, $src1|$src1, $src2}", []>, 2149 OpSize32, NotMemoryFoldable; 2150def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2), 2151 (ins GR64:$src1 ,GR64:$src2), 2152 "xchg{q}\t{$src2, $src1|$src1, $src2}", []>, NotMemoryFoldable; 2153} 2154 2155// Swap between EAX and other registers. 2156let Constraints = "$src = $dst", hasSideEffects = 0 in { 2157let Uses = [AX], Defs = [AX] in 2158def XCHG16ar : I<0x90, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 2159 "xchg{w}\t{$src, %ax|ax, $src}", []>, OpSize16; 2160let Uses = [EAX], Defs = [EAX] in 2161def XCHG32ar : I<0x90, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 2162 "xchg{l}\t{$src, %eax|eax, $src}", []>, OpSize32; 2163let Uses = [RAX], Defs = [RAX] in 2164def XCHG64ar : RI<0x90, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 2165 "xchg{q}\t{$src, %rax|rax, $src}", []>; 2166} 2167} // SchedRW 2168 2169let hasSideEffects = 0, Constraints = "$src1 = $dst1, $src2 = $dst2", 2170 Defs = [EFLAGS], SchedRW = [WriteXCHG] in { 2171def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst1, GR8:$dst2), 2172 (ins GR8:$src1, GR8:$src2), 2173 "xadd{b}\t{$src2, $src1|$src1, $src2}", []>, TB; 2174def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst1, GR16:$dst2), 2175 (ins GR16:$src1, GR16:$src2), 2176 "xadd{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16; 2177def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst1, GR32:$dst2), 2178 (ins GR32:$src1, GR32:$src2), 2179 "xadd{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32; 2180def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst1, GR64:$dst2), 2181 (ins GR64:$src1, GR64:$src2), 2182 "xadd{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 2183} // SchedRW 2184 2185let mayLoad = 1, mayStore = 1, hasSideEffects = 0, Constraints = "$val = $dst", 2186 Defs = [EFLAGS], SchedRW = [WriteALULd, WriteRMW] in { 2187def XADD8rm : I<0xC0, MRMSrcMem, (outs GR8:$dst), 2188 (ins GR8:$val, i8mem:$ptr), 2189 "xadd{b}\t{$val, $ptr|$ptr, $val}", []>, TB; 2190def XADD16rm : I<0xC1, MRMSrcMem, (outs GR16:$dst), 2191 (ins GR16:$val, i16mem:$ptr), 2192 "xadd{w}\t{$val, $ptr|$ptr, $val}", []>, TB, 2193 OpSize16; 2194def XADD32rm : I<0xC1, MRMSrcMem, (outs GR32:$dst), 2195 (ins GR32:$val, i32mem:$ptr), 2196 "xadd{l}\t{$val, $ptr|$ptr, $val}", []>, TB, 2197 OpSize32; 2198def XADD64rm : RI<0xC1, MRMSrcMem, (outs GR64:$dst), 2199 (ins GR64:$val, i64mem:$ptr), 2200 "xadd{q}\t{$val, $ptr|$ptr, $val}", []>, TB; 2201 2202} 2203 2204let SchedRW = [WriteCMPXCHG], hasSideEffects = 0 in { 2205let Defs = [AL, EFLAGS], Uses = [AL] in 2206def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 2207 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, 2208 NotMemoryFoldable; 2209let Defs = [AX, EFLAGS], Uses = [AX] in 2210def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 2211 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, 2212 NotMemoryFoldable; 2213let Defs = [EAX, EFLAGS], Uses = [EAX] in 2214def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 2215 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, 2216 NotMemoryFoldable; 2217let Defs = [RAX, EFLAGS], Uses = [RAX] in 2218def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 2219 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, 2220 NotMemoryFoldable; 2221} // SchedRW, hasSideEffects 2222 2223let SchedRW = [WriteCMPXCHGRMW], mayLoad = 1, mayStore = 1, 2224 hasSideEffects = 0 in { 2225let Defs = [AL, EFLAGS], Uses = [AL] in 2226def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 2227 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, 2228 NotMemoryFoldable; 2229let Defs = [AX, EFLAGS], Uses = [AX] in 2230def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2231 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, 2232 NotMemoryFoldable; 2233let Defs = [EAX, EFLAGS], Uses = [EAX] in 2234def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2235 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, 2236 NotMemoryFoldable; 2237let Defs = [RAX, EFLAGS], Uses = [RAX] in 2238def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2239 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, 2240 NotMemoryFoldable; 2241 2242let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 2243def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 2244 "cmpxchg8b\t$dst", []>, TB, Requires<[HasCX8]>; 2245 2246let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 2247// NOTE: In64BitMode check needed for the AssemblerPredicate. 2248def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 2249 "cmpxchg16b\t$dst", []>, 2250 TB, Requires<[HasCX16,In64BitMode]>; 2251} // SchedRW, mayLoad, mayStore, hasSideEffects 2252 2253 2254// Lock instruction prefix 2255let SchedRW = [WriteMicrocoded] in 2256def LOCK_PREFIX : I<0xF0, PrefixByte, (outs), (ins), "lock", []>; 2257 2258let SchedRW = [WriteNop] in { 2259 2260// Rex64 instruction prefix 2261def REX64_PREFIX : I<0x48, PrefixByte, (outs), (ins), "rex64", []>, 2262 Requires<[In64BitMode]>; 2263 2264// Data16 instruction prefix 2265def DATA16_PREFIX : I<0x66, PrefixByte, (outs), (ins), "data16", []>; 2266} // SchedRW 2267 2268// Repeat string operation instruction prefixes 2269let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in { 2270// Repeat (used with INS, OUTS, MOVS, LODS and STOS) 2271def REP_PREFIX : I<0xF3, PrefixByte, (outs), (ins), "rep", []>; 2272// Repeat while not equal (used with CMPS and SCAS) 2273def REPNE_PREFIX : I<0xF2, PrefixByte, (outs), (ins), "repne", []>; 2274} 2275 2276// String manipulation instructions 2277let SchedRW = [WriteMicrocoded] in { 2278let Defs = [AL,ESI], Uses = [ESI,DF] in 2279def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), 2280 "lodsb\t{$src, %al|al, $src}", []>; 2281let Defs = [AX,ESI], Uses = [ESI,DF] in 2282def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), 2283 "lodsw\t{$src, %ax|ax, $src}", []>, OpSize16; 2284let Defs = [EAX,ESI], Uses = [ESI,DF] in 2285def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), 2286 "lods{l|d}\t{$src, %eax|eax, $src}", []>, OpSize32; 2287let Defs = [RAX,ESI], Uses = [ESI,DF] in 2288def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), 2289 "lodsq\t{$src, %rax|rax, $src}", []>, 2290 Requires<[In64BitMode]>; 2291} 2292 2293let SchedRW = [WriteSystem] in { 2294let Defs = [ESI], Uses = [DX,ESI,DF] in { 2295def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), 2296 "outsb\t{$src, %dx|dx, $src}", []>; 2297def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), 2298 "outsw\t{$src, %dx|dx, $src}", []>, OpSize16; 2299def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), 2300 "outs{l|d}\t{$src, %dx|dx, $src}", []>, OpSize32; 2301} 2302 2303let Defs = [EDI], Uses = [DX,EDI,DF] in { 2304def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst), 2305 "insb\t{%dx, $dst|$dst, dx}", []>; 2306def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst), 2307 "insw\t{%dx, $dst|$dst, dx}", []>, OpSize16; 2308def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst), 2309 "ins{l|d}\t{%dx, $dst|$dst, dx}", []>, OpSize32; 2310} 2311} 2312 2313// EFLAGS management instructions. 2314let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { 2315def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; 2316def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; 2317def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; 2318} 2319 2320// DF management instructions. 2321let SchedRW = [WriteALU], Defs = [DF] in { 2322def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; 2323def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; 2324} 2325 2326// Table lookup instructions 2327let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in 2328def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>; 2329 2330let SchedRW = [WriteMicrocoded] in { 2331// ASCII Adjust After Addition 2332let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2333def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, 2334 Requires<[Not64BitMode]>; 2335 2336// ASCII Adjust AX Before Division 2337let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2338def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 2339 "aad\t$src", []>, Requires<[Not64BitMode]>; 2340 2341// ASCII Adjust AX After Multiply 2342let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2343def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 2344 "aam\t$src", []>, Requires<[Not64BitMode]>; 2345 2346// ASCII Adjust AL After Subtraction - sets 2347let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2348def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, 2349 Requires<[Not64BitMode]>; 2350 2351// Decimal Adjust AL after Addition 2352let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in 2353def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, 2354 Requires<[Not64BitMode]>; 2355 2356// Decimal Adjust AL after Subtraction 2357let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in 2358def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, 2359 Requires<[Not64BitMode]>; 2360} // SchedRW 2361 2362let SchedRW = [WriteSystem] in { 2363// Check Array Index Against Bounds 2364// Note: "bound" does not have reversed operands in at&t syntax. 2365def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2366 "bound\t$dst, $src", []>, OpSize16, 2367 Requires<[Not64BitMode]>; 2368def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2369 "bound\t$dst, $src", []>, OpSize32, 2370 Requires<[Not64BitMode]>; 2371 2372// Adjust RPL Field of Segment Selector 2373def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 2374 "arpl\t{$src, $dst|$dst, $src}", []>, 2375 Requires<[Not64BitMode]>, NotMemoryFoldable; 2376let mayStore = 1 in 2377def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2378 "arpl\t{$src, $dst|$dst, $src}", []>, 2379 Requires<[Not64BitMode]>, NotMemoryFoldable; 2380} // SchedRW 2381 2382//===----------------------------------------------------------------------===// 2383// MOVBE Instructions 2384// 2385let Predicates = [HasMOVBE] in { 2386 let SchedRW = [WriteALULd] in { 2387 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2388 "movbe{w}\t{$src, $dst|$dst, $src}", 2389 [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, 2390 OpSize16, T8PS; 2391 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2392 "movbe{l}\t{$src, $dst|$dst, $src}", 2393 [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, 2394 OpSize32, T8PS; 2395 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2396 "movbe{q}\t{$src, $dst|$dst, $src}", 2397 [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, 2398 T8PS; 2399 } 2400 let SchedRW = [WriteStore] in { 2401 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2402 "movbe{w}\t{$src, $dst|$dst, $src}", 2403 [(store (bswap GR16:$src), addr:$dst)]>, 2404 OpSize16, T8PS; 2405 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2406 "movbe{l}\t{$src, $dst|$dst, $src}", 2407 [(store (bswap GR32:$src), addr:$dst)]>, 2408 OpSize32, T8PS; 2409 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2410 "movbe{q}\t{$src, $dst|$dst, $src}", 2411 [(store (bswap GR64:$src), addr:$dst)]>, 2412 T8PS; 2413 } 2414} 2415 2416//===----------------------------------------------------------------------===// 2417// RDRAND Instruction 2418// 2419let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in { 2420 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 2421 "rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>, 2422 OpSize16, PS; 2423 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 2424 "rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>, 2425 OpSize32, PS; 2426 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 2427 "rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>, 2428 PS; 2429} 2430 2431//===----------------------------------------------------------------------===// 2432// RDSEED Instruction 2433// 2434let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { 2435 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst", 2436 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS; 2437 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst", 2438 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS; 2439 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst", 2440 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS; 2441} 2442 2443//===----------------------------------------------------------------------===// 2444// LZCNT Instruction 2445// 2446let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 2447 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2448 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2449 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, 2450 XS, OpSize16, Sched<[WriteLZCNT]>; 2451 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2452 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2453 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 2454 (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteLZCNTLd]>; 2455 2456 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2457 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2458 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, 2459 XS, OpSize32, Sched<[WriteLZCNT]>; 2460 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2461 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2462 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 2463 (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteLZCNTLd]>; 2464 2465 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2466 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2467 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 2468 XS, Sched<[WriteLZCNT]>; 2469 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2470 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2471 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 2472 (implicit EFLAGS)]>, XS, Sched<[WriteLZCNTLd]>; 2473} 2474 2475//===----------------------------------------------------------------------===// 2476// BMI Instructions 2477// 2478let Predicates = [HasBMI], Defs = [EFLAGS] in { 2479 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2480 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2481 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, 2482 XS, OpSize16, Sched<[WriteTZCNT]>; 2483 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2484 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2485 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 2486 (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteTZCNTLd]>; 2487 2488 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2489 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2490 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, 2491 XS, OpSize32, Sched<[WriteTZCNT]>; 2492 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2493 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2494 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 2495 (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteTZCNTLd]>; 2496 2497 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2498 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2499 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 2500 XS, Sched<[WriteTZCNT]>; 2501 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2502 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2503 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 2504 (implicit EFLAGS)]>, XS, Sched<[WriteTZCNTLd]>; 2505} 2506 2507multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 2508 RegisterClass RC, X86MemOperand x86memop, 2509 X86FoldableSchedWrite sched> { 2510let hasSideEffects = 0 in { 2511 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 2512 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, 2513 T8PS, VEX_4V, Sched<[sched]>; 2514 let mayLoad = 1 in 2515 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 2516 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, 2517 T8PS, VEX_4V, Sched<[sched.Folded]>; 2518} 2519} 2520 2521let Predicates = [HasBMI], Defs = [EFLAGS] in { 2522 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS>; 2523 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS>, VEX_W; 2524 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS>; 2525 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS>, VEX_W; 2526 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, WriteBLS>; 2527 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS>, VEX_W; 2528} 2529 2530//===----------------------------------------------------------------------===// 2531// Pattern fragments to auto generate BMI instructions. 2532//===----------------------------------------------------------------------===// 2533 2534def or_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 2535 (X86or_flag node:$lhs, node:$rhs), [{ 2536 return hasNoCarryFlagUses(SDValue(N, 1)); 2537}]>; 2538 2539def xor_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 2540 (X86xor_flag node:$lhs, node:$rhs), [{ 2541 return hasNoCarryFlagUses(SDValue(N, 1)); 2542}]>; 2543 2544def and_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 2545 (X86and_flag node:$lhs, node:$rhs), [{ 2546 return hasNoCarryFlagUses(SDValue(N, 1)); 2547}]>; 2548 2549let Predicates = [HasBMI] in { 2550 // FIXME: patterns for the load versions are not implemented 2551 def : Pat<(and GR32:$src, (add GR32:$src, -1)), 2552 (BLSR32rr GR32:$src)>; 2553 def : Pat<(and GR64:$src, (add GR64:$src, -1)), 2554 (BLSR64rr GR64:$src)>; 2555 2556 def : Pat<(xor GR32:$src, (add GR32:$src, -1)), 2557 (BLSMSK32rr GR32:$src)>; 2558 def : Pat<(xor GR64:$src, (add GR64:$src, -1)), 2559 (BLSMSK64rr GR64:$src)>; 2560 2561 def : Pat<(and GR32:$src, (ineg GR32:$src)), 2562 (BLSI32rr GR32:$src)>; 2563 def : Pat<(and GR64:$src, (ineg GR64:$src)), 2564 (BLSI64rr GR64:$src)>; 2565 2566 // Versions to match flag producing ops. 2567 def : Pat<(and_flag_nocf GR32:$src, (add GR32:$src, -1)), 2568 (BLSR32rr GR32:$src)>; 2569 def : Pat<(and_flag_nocf GR64:$src, (add GR64:$src, -1)), 2570 (BLSR64rr GR64:$src)>; 2571 2572 def : Pat<(xor_flag_nocf GR32:$src, (add GR32:$src, -1)), 2573 (BLSMSK32rr GR32:$src)>; 2574 def : Pat<(xor_flag_nocf GR64:$src, (add GR64:$src, -1)), 2575 (BLSMSK64rr GR64:$src)>; 2576 2577 def : Pat<(and_flag_nocf GR32:$src, (ineg GR32:$src)), 2578 (BLSI32rr GR32:$src)>; 2579 def : Pat<(and_flag_nocf GR64:$src, (ineg GR64:$src)), 2580 (BLSI64rr GR64:$src)>; 2581} 2582 2583multiclass bmi_bextr<bits<8> opc, string mnemonic, RegisterClass RC, 2584 X86MemOperand x86memop, SDNode OpNode, 2585 PatFrag ld_frag, X86FoldableSchedWrite Sched> { 2586 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2587 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2588 [(set RC:$dst, (OpNode RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2589 T8PS, VEX, Sched<[Sched]>; 2590 def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2591 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2592 [(set RC:$dst, (OpNode (ld_frag addr:$src1), RC:$src2)), 2593 (implicit EFLAGS)]>, T8PS, VEX, 2594 Sched<[Sched.Folded, 2595 // x86memop:$src1 2596 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 2597 ReadDefault, 2598 // RC:$src2 2599 Sched.ReadAfterFold]>; 2600} 2601 2602let Predicates = [HasBMI], Defs = [EFLAGS] in { 2603 defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem, 2604 X86bextr, loadi32, WriteBEXTR>; 2605 defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem, 2606 X86bextr, loadi64, WriteBEXTR>, VEX_W; 2607} 2608 2609multiclass bmi_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 2610 X86MemOperand x86memop, SDNode Int, 2611 PatFrag ld_frag, X86FoldableSchedWrite Sched> { 2612 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2613 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2614 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2615 T8PS, VEX, Sched<[Sched]>; 2616 def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2617 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2618 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 2619 (implicit EFLAGS)]>, T8PS, VEX, 2620 Sched<[Sched.Folded, 2621 // x86memop:$src1 2622 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 2623 ReadDefault, 2624 // RC:$src2 2625 Sched.ReadAfterFold]>; 2626} 2627 2628let Predicates = [HasBMI2], Defs = [EFLAGS] in { 2629 defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 2630 X86bzhi, loadi32, WriteBZHI>; 2631 defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 2632 X86bzhi, loadi64, WriteBZHI>, VEX_W; 2633} 2634 2635def CountTrailingOnes : SDNodeXForm<imm, [{ 2636 // Count the trailing ones in the immediate. 2637 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N)); 2638}]>; 2639 2640def BEXTRMaskXForm : SDNodeXForm<imm, [{ 2641 unsigned Length = countTrailingOnes(N->getZExtValue()); 2642 return getI32Imm(Length << 8, SDLoc(N)); 2643}]>; 2644 2645def AndMask64 : ImmLeaf<i64, [{ 2646 return isMask_64(Imm) && !isUInt<32>(Imm); 2647}]>; 2648 2649// Use BEXTR for 64-bit 'and' with large immediate 'mask'. 2650let Predicates = [HasBMI, NoBMI2, NoTBM] in { 2651 def : Pat<(and GR64:$src, AndMask64:$mask), 2652 (BEXTR64rr GR64:$src, 2653 (SUBREG_TO_REG (i64 0), 2654 (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; 2655 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2656 (BEXTR64rm addr:$src, 2657 (SUBREG_TO_REG (i64 0), 2658 (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; 2659} 2660 2661// Use BZHI for 64-bit 'and' with large immediate 'mask'. 2662let Predicates = [HasBMI2, NoTBM] in { 2663 def : Pat<(and GR64:$src, AndMask64:$mask), 2664 (BZHI64rr GR64:$src, 2665 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2666 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2667 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2668 (BZHI64rm addr:$src, 2669 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2670 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2671} 2672 2673multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 2674 X86MemOperand x86memop, SDNode OpNode, 2675 PatFrag ld_frag> { 2676 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2677 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2678 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>, 2679 VEX_4V, Sched<[WriteALU]>; 2680 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2681 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2682 [(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>, 2683 VEX_4V, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>; 2684} 2685 2686let Predicates = [HasBMI2] in { 2687 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 2688 X86pdep, loadi32>, T8XD; 2689 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 2690 X86pdep, loadi64>, T8XD, VEX_W; 2691 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 2692 X86pext, loadi32>, T8XS; 2693 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 2694 X86pext, loadi64>, T8XS, VEX_W; 2695} 2696 2697//===----------------------------------------------------------------------===// 2698// TBM Instructions 2699// 2700let Predicates = [HasTBM], Defs = [EFLAGS] in { 2701 2702multiclass tbm_bextri<bits<8> opc, RegisterClass RC, string OpcodeStr, 2703 X86MemOperand x86memop, PatFrag ld_frag, 2704 SDNode OpNode, Operand immtype, 2705 SDPatternOperator immoperator, 2706 X86FoldableSchedWrite Sched> { 2707 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2708 !strconcat(OpcodeStr, 2709 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2710 [(set RC:$dst, (OpNode RC:$src1, immoperator:$cntl))]>, 2711 XOP, XOPA, Sched<[Sched]>; 2712 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst), 2713 (ins x86memop:$src1, immtype:$cntl), 2714 !strconcat(OpcodeStr, 2715 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2716 [(set RC:$dst, (OpNode (ld_frag addr:$src1), immoperator:$cntl))]>, 2717 XOP, XOPA, Sched<[Sched.Folded]>; 2718} 2719 2720defm BEXTRI32 : tbm_bextri<0x10, GR32, "bextr{l}", i32mem, loadi32, 2721 X86bextri, i32imm, timm, WriteBEXTR>; 2722let ImmT = Imm32S in 2723defm BEXTRI64 : tbm_bextri<0x10, GR64, "bextr{q}", i64mem, loadi64, 2724 X86bextri, i64i32imm, 2725 i64timmSExt32, WriteBEXTR>, VEX_W; 2726 2727multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem, 2728 RegisterClass RC, string OpcodeStr, 2729 X86MemOperand x86memop, X86FoldableSchedWrite Sched> { 2730let hasSideEffects = 0 in { 2731 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src), 2732 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>, 2733 XOP_4V, XOP9, Sched<[Sched]>; 2734 let mayLoad = 1 in 2735 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src), 2736 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>, 2737 XOP_4V, XOP9, Sched<[Sched.Folded]>; 2738} 2739} 2740 2741multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr, 2742 X86FoldableSchedWrite Sched, 2743 Format FormReg, Format FormMem> { 2744 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr#"{l}", 2745 i32mem, Sched>; 2746 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr#"{q}", 2747 i64mem, Sched>, VEX_W; 2748} 2749 2750defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>; 2751defm BLCI : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>; 2752defm BLCIC : tbm_binary_intr<0x01, "blcic", WriteALU, MRM5r, MRM5m>; 2753defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>; 2754defm BLCS : tbm_binary_intr<0x01, "blcs", WriteALU, MRM3r, MRM3m>; 2755defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>; 2756defm BLSIC : tbm_binary_intr<0x01, "blsic", WriteALU, MRM6r, MRM6m>; 2757defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", WriteALU, MRM7r, MRM7m>; 2758defm TZMSK : tbm_binary_intr<0x01, "tzmsk", WriteALU, MRM4r, MRM4m>; 2759} // HasTBM, EFLAGS 2760 2761// Use BEXTRI for 64-bit 'and' with large immediate 'mask'. 2762let Predicates = [HasTBM] in { 2763 def : Pat<(and GR64:$src, AndMask64:$mask), 2764 (BEXTRI64ri GR64:$src, (BEXTRMaskXForm imm:$mask))>; 2765 2766 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2767 (BEXTRI64mi addr:$src, (BEXTRMaskXForm imm:$mask))>; 2768} 2769 2770//===----------------------------------------------------------------------===// 2771// Lightweight Profiling Instructions 2772 2773let Predicates = [HasLWP], SchedRW = [WriteSystem] in { 2774 2775def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", 2776 [(int_x86_llwpcb GR32:$src)]>, XOP, XOP9; 2777def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", 2778 [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9; 2779 2780def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", 2781 [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, VEX_W; 2782def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", 2783 [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, VEX_W; 2784 2785multiclass lwpins_intr<RegisterClass RC> { 2786 def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 2787 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2788 [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, timm:$cntl))]>, 2789 XOP_4V, XOPA; 2790 let mayLoad = 1 in 2791 def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), 2792 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2793 [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), timm:$cntl))]>, 2794 XOP_4V, XOPA; 2795} 2796 2797let Defs = [EFLAGS] in { 2798 defm LWPINS32 : lwpins_intr<GR32>; 2799 defm LWPINS64 : lwpins_intr<GR64>, VEX_W; 2800} // EFLAGS 2801 2802multiclass lwpval_intr<RegisterClass RC, Intrinsic Int> { 2803 def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 2804 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2805 [(Int RC:$src0, GR32:$src1, timm:$cntl)]>, XOP_4V, XOPA; 2806 let mayLoad = 1 in 2807 def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), 2808 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2809 [(Int RC:$src0, (loadi32 addr:$src1), timm:$cntl)]>, 2810 XOP_4V, XOPA; 2811} 2812 2813defm LWPVAL32 : lwpval_intr<GR32, int_x86_lwpval32>; 2814defm LWPVAL64 : lwpval_intr<GR64, int_x86_lwpval64>, VEX_W; 2815 2816} // HasLWP, SchedRW 2817 2818//===----------------------------------------------------------------------===// 2819// MONITORX/MWAITX Instructions 2820// 2821let SchedRW = [ WriteSystem ] in { 2822 let Uses = [ EAX, ECX, EDX ] in 2823 def MONITORX32rrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, 2824 TB, Requires<[ HasMWAITX, Not64BitMode ]>; 2825 let Uses = [ RAX, ECX, EDX ] in 2826 def MONITORX64rrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, 2827 TB, Requires<[ HasMWAITX, In64BitMode ]>; 2828 2829 let Uses = [ ECX, EAX, EBX ] in { 2830 def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", 2831 []>, TB, Requires<[ HasMWAITX ]>; 2832 } 2833} // SchedRW 2834 2835def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>, 2836 Requires<[ Not64BitMode ]>; 2837def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>, 2838 Requires<[ In64BitMode ]>; 2839 2840def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORX32rrr)>, 2841 Requires<[ Not64BitMode ]>; 2842def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORX64rrr)>, 2843 Requires<[ In64BitMode ]>; 2844 2845//===----------------------------------------------------------------------===// 2846// WAITPKG Instructions 2847// 2848let SchedRW = [WriteSystem] in { 2849 def UMONITOR16 : I<0xAE, MRM6r, (outs), (ins GR16:$src), 2850 "umonitor\t$src", [(int_x86_umonitor GR16:$src)]>, 2851 XS, AdSize16, Requires<[HasWAITPKG, Not64BitMode]>; 2852 def UMONITOR32 : I<0xAE, MRM6r, (outs), (ins GR32:$src), 2853 "umonitor\t$src", [(int_x86_umonitor GR32:$src)]>, 2854 XS, AdSize32, Requires<[HasWAITPKG]>; 2855 def UMONITOR64 : I<0xAE, MRM6r, (outs), (ins GR64:$src), 2856 "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>, 2857 XS, AdSize64, Requires<[HasWAITPKG, In64BitMode]>; 2858 let Uses = [EAX, EDX], Defs = [EFLAGS] in { 2859 def UMWAIT : I<0xAE, MRM6r, 2860 (outs), (ins GR32orGR64:$src), "umwait\t$src", 2861 [(set EFLAGS, (X86umwait GR32orGR64:$src, EDX, EAX))]>, 2862 XD, Requires<[HasWAITPKG]>; 2863 def TPAUSE : I<0xAE, MRM6r, 2864 (outs), (ins GR32orGR64:$src), "tpause\t$src", 2865 [(set EFLAGS, (X86tpause GR32orGR64:$src, EDX, EAX))]>, 2866 PD, Requires<[HasWAITPKG]>; 2867 } 2868} // SchedRW 2869 2870//===----------------------------------------------------------------------===// 2871// MOVDIRI - Move doubleword/quadword as direct store 2872// 2873let SchedRW = [WriteStore] in { 2874def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2875 "movdiri\t{$src, $dst|$dst, $src}", 2876 [(int_x86_directstore32 addr:$dst, GR32:$src)]>, 2877 T8PS, Requires<[HasMOVDIRI]>; 2878def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2879 "movdiri\t{$src, $dst|$dst, $src}", 2880 [(int_x86_directstore64 addr:$dst, GR64:$src)]>, 2881 T8PS, Requires<[In64BitMode, HasMOVDIRI]>; 2882} // SchedRW 2883 2884//===----------------------------------------------------------------------===// 2885// MOVDIR64B - Move 64 bytes as direct store 2886// 2887let SchedRW = [WriteStore] in { 2888def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), 2889 "movdir64b\t{$src, $dst|$dst, $src}", []>, 2890 T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>; 2891def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), 2892 "movdir64b\t{$src, $dst|$dst, $src}", 2893 [(int_x86_movdir64b GR32:$dst, addr:$src)]>, 2894 T8PD, AdSize32, Requires<[HasMOVDIR64B]>; 2895def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), 2896 "movdir64b\t{$src, $dst|$dst, $src}", 2897 [(int_x86_movdir64b GR64:$dst, addr:$src)]>, 2898 T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>; 2899} // SchedRW 2900 2901//===----------------------------------------------------------------------===// 2902// ENQCMD/S - Enqueue 64-byte command as user with 64-byte write atomicity 2903// 2904let SchedRW = [WriteStore], Defs = [EFLAGS] in { 2905 def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), 2906 "enqcmd\t{$src, $dst|$dst, $src}", 2907 [(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>, 2908 T8XD, AdSize16, Requires<[HasENQCMD, Not64BitMode]>; 2909 def ENQCMD32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), 2910 "enqcmd\t{$src, $dst|$dst, $src}", 2911 [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>, 2912 T8XD, AdSize32, Requires<[HasENQCMD]>; 2913 def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), 2914 "enqcmd\t{$src, $dst|$dst, $src}", 2915 [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>, 2916 T8XD, AdSize64, Requires<[HasENQCMD, In64BitMode]>; 2917 2918 def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), 2919 "enqcmds\t{$src, $dst|$dst, $src}", 2920 [(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>, 2921 T8XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>; 2922 def ENQCMDS32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), 2923 "enqcmds\t{$src, $dst|$dst, $src}", 2924 [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>, 2925 T8XS, AdSize32, Requires<[HasENQCMD]>; 2926 def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), 2927 "enqcmds\t{$src, $dst|$dst, $src}", 2928 [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>, 2929 T8XS, AdSize64, Requires<[HasENQCMD, In64BitMode]>; 2930} 2931 2932//===----------------------------------------------------------------------===// 2933// CLZERO Instruction 2934// 2935let SchedRW = [WriteLoad] in { 2936 let Uses = [EAX] in 2937 def CLZERO32r : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, 2938 TB, Requires<[HasCLZERO, Not64BitMode]>; 2939 let Uses = [RAX] in 2940 def CLZERO64r : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, 2941 TB, Requires<[HasCLZERO, In64BitMode]>; 2942} // SchedRW 2943 2944def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>; 2945def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>; 2946 2947//===----------------------------------------------------------------------===// 2948// INVLPGB Instruction 2949// OPCODE 0F 01 FE 2950// 2951let SchedRW = [WriteSystem] in { 2952 let Uses = [EAX, EDX] in 2953 def INVLPGB32 : I<0x01, MRM_FE, (outs), (ins), 2954 "invlpgb", []>, 2955 PS, Requires<[Not64BitMode]>; 2956 let Uses = [RAX, EDX] in 2957 def INVLPGB64 : I<0x01, MRM_FE, (outs), (ins), 2958 "invlpgb", []>, 2959 PS, Requires<[In64BitMode]>; 2960} // SchedRW 2961 2962def : InstAlias<"invlpgb\t{%eax, %edx|eax, edx}", (INVLPGB32)>, Requires<[Not64BitMode]>; 2963def : InstAlias<"invlpgb\t{%rax, %edx|rax, edx}", (INVLPGB64)>, Requires<[In64BitMode]>; 2964 2965//===----------------------------------------------------------------------===// 2966// TLBSYNC Instruction 2967// OPCODE 0F 01 FF 2968// 2969let SchedRW = [WriteSystem] in { 2970 def TLBSYNC : I<0x01, MRM_FF, (outs), (ins), 2971 "tlbsync", []>, 2972 PS, Requires<[]>; 2973} // SchedRW 2974 2975//===----------------------------------------------------------------------===// 2976// HRESET Instruction 2977// 2978let Uses = [EAX], SchedRW = [WriteSystem] in 2979 def HRESET : Ii8<0xF0, MRM_C0, (outs), (ins i32u8imm:$imm), "hreset\t$imm", []>, 2980 Requires<[HasHRESET]>, TAXS; 2981 2982//===----------------------------------------------------------------------===// 2983// SERIALIZE Instruction 2984// 2985let SchedRW = [WriteSystem] in 2986 def SERIALIZE : I<0x01, MRM_E8, (outs), (ins), "serialize", 2987 [(int_x86_serialize)]>, PS, 2988 Requires<[HasSERIALIZE]>; 2989 2990//===----------------------------------------------------------------------===// 2991// TSXLDTRK - TSX Suspend Load Address Tracking 2992// 2993let Predicates = [HasTSXLDTRK], SchedRW = [WriteSystem] in { 2994 def XSUSLDTRK : I<0x01, MRM_E8, (outs), (ins), "xsusldtrk", 2995 [(int_x86_xsusldtrk)]>, XD; 2996 def XRESLDTRK : I<0x01, MRM_E9, (outs), (ins), "xresldtrk", 2997 [(int_x86_xresldtrk)]>, XD; 2998} 2999 3000//===----------------------------------------------------------------------===// 3001// UINTR Instructions 3002// 3003let Predicates = [HasUINTR, In64BitMode], SchedRW = [WriteSystem] in { 3004 def UIRET : I<0x01, MRM_EC, (outs), (ins), "uiret", 3005 []>, XS; 3006 def CLUI : I<0x01, MRM_EE, (outs), (ins), "clui", 3007 [(int_x86_clui)]>, XS; 3008 def STUI : I<0x01, MRM_EF, (outs), (ins), "stui", 3009 [(int_x86_stui)]>, XS; 3010 3011 def SENDUIPI : I<0xC7, MRM6r, (outs), (ins GR64:$arg), "senduipi\t$arg", 3012 [(int_x86_senduipi GR64:$arg)]>, XS; 3013 3014 let Defs = [EFLAGS] in 3015 def TESTUI : I<0x01, MRM_ED, (outs), (ins), "testui", 3016 [(set EFLAGS, (X86testui))]>, XS; 3017} 3018 3019//===----------------------------------------------------------------------===// 3020// PREFETCHIT0 and PREFETCHIT1 Instructions 3021// prefetch ADDR, RW, Locality, Data 3022let Predicates = [HasPREFETCHI, In64BitMode], SchedRW = [WriteLoad] in { 3023 def PREFETCHIT0 : I<0x18, MRM7m, (outs), (ins i8mem:$src), 3024 "prefetchit0\t$src", [(prefetch addr:$src, (i32 0), (i32 3), (i32 0))]>, TB; 3025 def PREFETCHIT1 : I<0x18, MRM6m, (outs), (ins i8mem:$src), 3026 "prefetchit1\t$src", [(prefetch addr:$src, (i32 0), (i32 2), (i32 0))]>, TB; 3027} 3028 3029//===----------------------------------------------------------------------===// 3030// CMPCCXADD Instructions 3031// 3032let isCodeGenOnly = 1, ForceDisassemble = 1, mayLoad = 1, mayStore = 1, 3033 Predicates = [HasCMPCCXADD, In64BitMode], Defs = [EFLAGS], 3034 Constraints = "$dstsrc1 = $dst" in { 3035def CMPCCXADDmr32 : I<0xe0, MRMDestMem4VOp3CC, (outs GR32:$dst), 3036 (ins GR32:$dstsrc1, i32mem:$dstsrc2, GR32:$src3, ccode:$cond), 3037 "cmp${cond}xadd\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 3038 [(set GR32:$dst, (X86cmpccxadd addr:$dstsrc2, 3039 GR32:$dstsrc1, GR32:$src3, timm:$cond))]>, 3040 VEX_4V, T8PD, Sched<[WriteXCHG]>; 3041 3042def CMPCCXADDmr64 : I<0xe0, MRMDestMem4VOp3CC, (outs GR64:$dst), 3043 (ins GR64:$dstsrc1, i64mem:$dstsrc2, GR64:$src3, ccode:$cond), 3044 "cmp${cond}xadd\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 3045 [(set GR64:$dst, (X86cmpccxadd addr:$dstsrc2, 3046 GR64:$dstsrc1, GR64:$src3, timm:$cond))]>, 3047 VEX_4V, VEX_W, T8PD, Sched<[WriteXCHG]>; 3048} 3049 3050multiclass CMPCCXADD_Aliases<string Cond, int CC> { 3051 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 3052 (CMPCCXADDmr32 GR32:$dst, i32mem:$dstsrc2, GR32:$src3, CC), 0>; 3053 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 3054 (CMPCCXADDmr64 GR64:$dst, i64mem:$dstsrc2, GR64:$src3, CC), 0>; 3055} 3056 3057defm : CMPCCXADD_Aliases<"o" , 0>; 3058defm : CMPCCXADD_Aliases<"no", 1>; 3059defm : CMPCCXADD_Aliases<"b" , 2>; 3060defm : CMPCCXADD_Aliases<"ae", 3>; 3061defm : CMPCCXADD_Aliases<"nb", 3>; 3062defm : CMPCCXADD_Aliases<"e" , 4>; 3063defm : CMPCCXADD_Aliases<"z" , 4>; 3064defm : CMPCCXADD_Aliases<"ne", 5>; 3065defm : CMPCCXADD_Aliases<"nz", 5>; 3066defm : CMPCCXADD_Aliases<"be", 6>; 3067defm : CMPCCXADD_Aliases<"nbe", 7>; 3068defm : CMPCCXADD_Aliases<"a", 7>; 3069defm : CMPCCXADD_Aliases<"s" , 8>; 3070defm : CMPCCXADD_Aliases<"ns", 9>; 3071defm : CMPCCXADD_Aliases<"p" , 10>; 3072defm : CMPCCXADD_Aliases<"np", 11>; 3073defm : CMPCCXADD_Aliases<"l" , 12>; 3074defm : CMPCCXADD_Aliases<"ge", 13>; 3075defm : CMPCCXADD_Aliases<"nl", 13>; 3076defm : CMPCCXADD_Aliases<"le", 14>; 3077defm : CMPCCXADD_Aliases<"g", 15>; 3078defm : CMPCCXADD_Aliases<"nle",15>; 3079 3080//===----------------------------------------------------------------------===// 3081// Pattern fragments to auto generate TBM instructions. 3082//===----------------------------------------------------------------------===// 3083 3084let Predicates = [HasTBM] in { 3085 // FIXME: patterns for the load versions are not implemented 3086 def : Pat<(and GR32:$src, (add GR32:$src, 1)), 3087 (BLCFILL32rr GR32:$src)>; 3088 def : Pat<(and GR64:$src, (add GR64:$src, 1)), 3089 (BLCFILL64rr GR64:$src)>; 3090 3091 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), 3092 (BLCI32rr GR32:$src)>; 3093 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), 3094 (BLCI64rr GR64:$src)>; 3095 3096 // Extra patterns because opt can optimize the above patterns to this. 3097 def : Pat<(or GR32:$src, (sub -2, GR32:$src)), 3098 (BLCI32rr GR32:$src)>; 3099 def : Pat<(or GR64:$src, (sub -2, GR64:$src)), 3100 (BLCI64rr GR64:$src)>; 3101 3102 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), 3103 (BLCIC32rr GR32:$src)>; 3104 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), 3105 (BLCIC64rr GR64:$src)>; 3106 3107 def : Pat<(xor GR32:$src, (add GR32:$src, 1)), 3108 (BLCMSK32rr GR32:$src)>; 3109 def : Pat<(xor GR64:$src, (add GR64:$src, 1)), 3110 (BLCMSK64rr GR64:$src)>; 3111 3112 def : Pat<(or GR32:$src, (add GR32:$src, 1)), 3113 (BLCS32rr GR32:$src)>; 3114 def : Pat<(or GR64:$src, (add GR64:$src, 1)), 3115 (BLCS64rr GR64:$src)>; 3116 3117 def : Pat<(or GR32:$src, (add GR32:$src, -1)), 3118 (BLSFILL32rr GR32:$src)>; 3119 def : Pat<(or GR64:$src, (add GR64:$src, -1)), 3120 (BLSFILL64rr GR64:$src)>; 3121 3122 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), 3123 (BLSIC32rr GR32:$src)>; 3124 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), 3125 (BLSIC64rr GR64:$src)>; 3126 3127 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), 3128 (T1MSKC32rr GR32:$src)>; 3129 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), 3130 (T1MSKC64rr GR64:$src)>; 3131 3132 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), 3133 (TZMSK32rr GR32:$src)>; 3134 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), 3135 (TZMSK64rr GR64:$src)>; 3136 3137 // Patterns to match flag producing ops. 3138 def : Pat<(and_flag_nocf GR32:$src, (add GR32:$src, 1)), 3139 (BLCFILL32rr GR32:$src)>; 3140 def : Pat<(and_flag_nocf GR64:$src, (add GR64:$src, 1)), 3141 (BLCFILL64rr GR64:$src)>; 3142 3143 def : Pat<(or_flag_nocf GR32:$src, (not (add GR32:$src, 1))), 3144 (BLCI32rr GR32:$src)>; 3145 def : Pat<(or_flag_nocf GR64:$src, (not (add GR64:$src, 1))), 3146 (BLCI64rr GR64:$src)>; 3147 3148 // Extra patterns because opt can optimize the above patterns to this. 3149 def : Pat<(or_flag_nocf GR32:$src, (sub -2, GR32:$src)), 3150 (BLCI32rr GR32:$src)>; 3151 def : Pat<(or_flag_nocf GR64:$src, (sub -2, GR64:$src)), 3152 (BLCI64rr GR64:$src)>; 3153 3154 def : Pat<(and_flag_nocf (not GR32:$src), (add GR32:$src, 1)), 3155 (BLCIC32rr GR32:$src)>; 3156 def : Pat<(and_flag_nocf (not GR64:$src), (add GR64:$src, 1)), 3157 (BLCIC64rr GR64:$src)>; 3158 3159 def : Pat<(xor_flag_nocf GR32:$src, (add GR32:$src, 1)), 3160 (BLCMSK32rr GR32:$src)>; 3161 def : Pat<(xor_flag_nocf GR64:$src, (add GR64:$src, 1)), 3162 (BLCMSK64rr GR64:$src)>; 3163 3164 def : Pat<(or_flag_nocf GR32:$src, (add GR32:$src, 1)), 3165 (BLCS32rr GR32:$src)>; 3166 def : Pat<(or_flag_nocf GR64:$src, (add GR64:$src, 1)), 3167 (BLCS64rr GR64:$src)>; 3168 3169 def : Pat<(or_flag_nocf GR32:$src, (add GR32:$src, -1)), 3170 (BLSFILL32rr GR32:$src)>; 3171 def : Pat<(or_flag_nocf GR64:$src, (add GR64:$src, -1)), 3172 (BLSFILL64rr GR64:$src)>; 3173 3174 def : Pat<(or_flag_nocf (not GR32:$src), (add GR32:$src, -1)), 3175 (BLSIC32rr GR32:$src)>; 3176 def : Pat<(or_flag_nocf (not GR64:$src), (add GR64:$src, -1)), 3177 (BLSIC64rr GR64:$src)>; 3178 3179 def : Pat<(or_flag_nocf (not GR32:$src), (add GR32:$src, 1)), 3180 (T1MSKC32rr GR32:$src)>; 3181 def : Pat<(or_flag_nocf (not GR64:$src), (add GR64:$src, 1)), 3182 (T1MSKC64rr GR64:$src)>; 3183 3184 def : Pat<(and_flag_nocf (not GR32:$src), (add GR32:$src, -1)), 3185 (TZMSK32rr GR32:$src)>; 3186 def : Pat<(and_flag_nocf (not GR64:$src), (add GR64:$src, -1)), 3187 (TZMSK64rr GR64:$src)>; 3188} // HasTBM 3189 3190//===----------------------------------------------------------------------===// 3191// Memory Instructions 3192// 3193 3194let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in 3195def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), 3196 "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD; 3197 3198let Predicates = [HasCLWB], SchedRW = [WriteLoad] in 3199def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", 3200 [(int_x86_clwb addr:$src)]>, PD; 3201 3202let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in 3203def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src", 3204 [(int_x86_cldemote addr:$src)]>, PS; 3205 3206//===----------------------------------------------------------------------===// 3207// Subsystems. 3208//===----------------------------------------------------------------------===// 3209 3210include "X86InstrArithmetic.td" 3211include "X86InstrCMovSetCC.td" 3212include "X86InstrExtension.td" 3213include "X86InstrControl.td" 3214include "X86InstrShiftRotate.td" 3215 3216// X87 Floating Point Stack. 3217include "X86InstrFPStack.td" 3218 3219// SIMD support (SSE, MMX and AVX) 3220include "X86InstrFragmentsSIMD.td" 3221 3222// FMA - Fused Multiply-Add support (requires FMA) 3223include "X86InstrFMA.td" 3224 3225// XOP 3226include "X86InstrXOP.td" 3227 3228// SSE, MMX and 3DNow! vector support. 3229include "X86InstrSSE.td" 3230include "X86InstrAVX512.td" 3231include "X86InstrMMX.td" 3232include "X86Instr3DNow.td" 3233 3234include "X86InstrVMX.td" 3235include "X86InstrSVM.td" 3236include "X86InstrSNP.td" 3237 3238include "X86InstrTSX.td" 3239include "X86InstrSGX.td" 3240 3241include "X86InstrTDX.td" 3242 3243// Key Locker instructions 3244include "X86InstrKL.td" 3245 3246// AMX instructions 3247include "X86InstrAMX.td" 3248 3249// RAO-INT instructions 3250include "X86InstrRAOINT.td" 3251 3252// System instructions. 3253include "X86InstrSystem.td" 3254 3255// Compiler Pseudo Instructions and Pat Patterns 3256include "X86InstrCompiler.td" 3257include "X86InstrVecCompiler.td" 3258 3259//===----------------------------------------------------------------------===// 3260// Assembler Mnemonic Aliases 3261//===----------------------------------------------------------------------===// 3262 3263def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 3264def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 3265def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 3266 3267def : MnemonicAlias<"cbw", "cbtw", "att">; 3268def : MnemonicAlias<"cwde", "cwtl", "att">; 3269def : MnemonicAlias<"cwd", "cwtd", "att">; 3270def : MnemonicAlias<"cdq", "cltd", "att">; 3271def : MnemonicAlias<"cdqe", "cltq", "att">; 3272def : MnemonicAlias<"cqo", "cqto", "att">; 3273 3274// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 3275def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 3276def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 3277 3278def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 3279def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 3280 3281def : MnemonicAlias<"loopz", "loope">; 3282def : MnemonicAlias<"loopnz", "loopne">; 3283 3284def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 3285def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 3286def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 3287def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 3288def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 3289def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 3290def : MnemonicAlias<"popf", "popfq", "intel">, Requires<[In64BitMode]>; 3291def : MnemonicAlias<"popfd", "popfl", "att">; 3292def : MnemonicAlias<"popfw", "popf", "intel">, Requires<[In32BitMode]>; 3293def : MnemonicAlias<"popfw", "popf", "intel">, Requires<[In64BitMode]>; 3294 3295// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 3296// all modes. However: "push (addr)" and "push $42" should default to 3297// pushl/pushq depending on the current mode. Similar for "pop %bx" 3298def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 3299def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 3300def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 3301def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 3302def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 3303def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 3304def : MnemonicAlias<"pushf", "pushfq", "intel">, Requires<[In64BitMode]>; 3305def : MnemonicAlias<"pushfd", "pushfl", "att">; 3306def : MnemonicAlias<"pushfw", "pushf", "intel">, Requires<[In32BitMode]>; 3307def : MnemonicAlias<"pushfw", "pushf", "intel">, Requires<[In64BitMode]>; 3308 3309def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 3310def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 3311def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 3312def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 3313def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 3314def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 3315 3316def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 3317def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 3318def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 3319def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 3320 3321def : MnemonicAlias<"repe", "rep">; 3322def : MnemonicAlias<"repz", "rep">; 3323def : MnemonicAlias<"repnz", "repne">; 3324 3325def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 3326def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 3327def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 3328 3329// Apply 'ret' behavior to 'retn' 3330def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; 3331def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; 3332def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; 3333def : MnemonicAlias<"retn", "ret", "intel">; 3334 3335def : MnemonicAlias<"sal", "shl", "intel">; 3336def : MnemonicAlias<"salb", "shlb", "att">; 3337def : MnemonicAlias<"salw", "shlw", "att">; 3338def : MnemonicAlias<"sall", "shll", "att">; 3339def : MnemonicAlias<"salq", "shlq", "att">; 3340 3341def : MnemonicAlias<"smovb", "movsb", "att">; 3342def : MnemonicAlias<"smovw", "movsw", "att">; 3343def : MnemonicAlias<"smovl", "movsl", "att">; 3344def : MnemonicAlias<"smovq", "movsq", "att">; 3345 3346def : MnemonicAlias<"ud2a", "ud2", "att">; 3347def : MnemonicAlias<"ud2bw", "ud1w", "att">; 3348def : MnemonicAlias<"ud2bl", "ud1l", "att">; 3349def : MnemonicAlias<"ud2bq", "ud1q", "att">; 3350def : MnemonicAlias<"verrw", "verr", "att">; 3351 3352// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release' 3353def : MnemonicAlias<"acquire", "xacquire", "intel">; 3354def : MnemonicAlias<"release", "xrelease", "intel">; 3355 3356// System instruction aliases. 3357def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 3358def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 3359def : MnemonicAlias<"sysret", "sysretl", "att">; 3360def : MnemonicAlias<"sysexit", "sysexitl", "att">; 3361 3362def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 3363def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 3364def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 3365def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 3366def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 3367def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 3368def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 3369def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 3370def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 3371def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 3372def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 3373def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 3374def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>; 3375def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>; 3376def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>; 3377def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>; 3378def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>; 3379def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>; 3380def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>; 3381def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>; 3382 3383 3384// Floating point stack aliases. 3385def : MnemonicAlias<"fcmovz", "fcmove", "att">; 3386def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 3387def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 3388def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 3389def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 3390def : MnemonicAlias<"fcomip", "fcompi">; 3391def : MnemonicAlias<"fildq", "fildll", "att">; 3392def : MnemonicAlias<"fistpq", "fistpll", "att">; 3393def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 3394def : MnemonicAlias<"fldcww", "fldcw", "att">; 3395def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 3396def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 3397def : MnemonicAlias<"fucomip", "fucompi">; 3398def : MnemonicAlias<"fwait", "wait">; 3399 3400def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; 3401def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; 3402def : MnemonicAlias<"xsaveq", "xsave64", "att">; 3403def : MnemonicAlias<"xrstorq", "xrstor64", "att">; 3404def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; 3405def : MnemonicAlias<"xrstorsq", "xrstors64", "att">; 3406def : MnemonicAlias<"xsavecq", "xsavec64", "att">; 3407def : MnemonicAlias<"xsavesq", "xsaves64", "att">; 3408 3409class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 3410 string VariantName> 3411 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 3412 !strconcat(Prefix, NewCond, Suffix), VariantName>; 3413 3414/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 3415/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 3416/// example "setz" -> "sete". 3417multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 3418 string V = ""> { 3419 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 3420 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 3421 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 3422 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 3423 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 3424 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 3425 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 3426 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 3427 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 3428 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 3429 3430 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 3431 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 3432 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 3433 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 3434} 3435 3436// Aliases for set<CC> 3437defm : IntegerCondCodeMnemonicAlias<"set", "">; 3438// Aliases for j<CC> 3439defm : IntegerCondCodeMnemonicAlias<"j", "">; 3440// Aliases for cmov<CC>{w,l,q} 3441defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 3442defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 3443defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 3444// No size suffix for intel-style asm. 3445defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 3446 3447 3448//===----------------------------------------------------------------------===// 3449// Assembler Instruction Aliases 3450//===----------------------------------------------------------------------===// 3451 3452// aad/aam default to base 10 if no operand is specified. 3453def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>; 3454def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>; 3455 3456// Disambiguate the mem/imm form of bt-without-a-suffix as btl. 3457// Likewise for btc/btr/bts. 3458def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}", 3459 (BT32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 3460def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}", 3461 (BTC32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 3462def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}", 3463 (BTR32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 3464def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}", 3465 (BTS32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 3466 3467// clr aliases. 3468def : InstAlias<"clr{b}\t$reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 3469def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 3470def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 3471def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 3472 3473// lods aliases. Accept the destination being omitted because it's implicit 3474// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 3475// in the destination. 3476def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src), 0>; 3477def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>; 3478def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>; 3479def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 3480def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 3481def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 3482def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 3483def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 3484def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0, "intel">; 3485def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">; 3486def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">; 3487def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3488 3489 3490// stos aliases. Accept the source being omitted because it's implicit in 3491// the mnemonic, or the mnemonic suffix being omitted because it's implicit 3492// in the source. 3493def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst), 0>; 3494def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>; 3495def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>; 3496def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3497def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 3498def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 3499def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 3500def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3501def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0, "intel">; 3502def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">; 3503def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">; 3504def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 3505 3506 3507// scas aliases. Accept the destination being omitted because it's implicit 3508// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 3509// in the destination. 3510def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst), 0>; 3511def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>; 3512def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>; 3513def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3514def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 3515def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 3516def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 3517def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3518def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0, "intel">; 3519def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">; 3520def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">; 3521def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 3522 3523// cmps aliases. Mnemonic suffix being omitted because it's implicit 3524// in the destination. 3525def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 3526def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 3527def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 3528def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3529 3530// movs aliases. Mnemonic suffix being omitted because it's implicit 3531// in the destination. 3532def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 3533def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 3534def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 3535def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3536 3537// div and idiv aliases for explicit A register. 3538def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 3539def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 3540def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 3541def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 3542def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 3543def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 3544def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 3545def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 3546def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 3547def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 3548def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 3549def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 3550def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 3551def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 3552def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 3553def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 3554 3555 3556 3557// Various unary fpstack operations default to operating on ST1. 3558// For example, "fxch" -> "fxch %st(1)" 3559def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 3560def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; 3561def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 3562def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 3563def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; 3564def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 3565def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 3566def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 3567def : InstAlias<"fxch", (XCH_F ST1), 0>; 3568def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 3569def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 3570def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 3571def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 3572def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 3573def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 3574def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 3575def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 3576 3577// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 3578// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 3579// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 3580// gas. 3581multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 3582 def : InstAlias<!strconcat(Mnemonic, "\t$op"), 3583 (Inst RSTi:$op), EmitAlias>; 3584 def : InstAlias<!strconcat(Mnemonic, "\t{%st, %st|st, st}"), 3585 (Inst ST0), EmitAlias>; 3586} 3587 3588defm : FpUnaryAlias<"fadd", ADD_FST0r, 0>; 3589defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 3590defm : FpUnaryAlias<"fsub", SUB_FST0r, 0>; 3591defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0, 0>; 3592defm : FpUnaryAlias<"fsubr", SUBR_FST0r, 0>; 3593defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0, 0>; 3594defm : FpUnaryAlias<"fmul", MUL_FST0r, 0>; 3595defm : FpUnaryAlias<"fmulp", MUL_FPrST0, 0>; 3596defm : FpUnaryAlias<"fdiv", DIV_FST0r, 0>; 3597defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0, 0>; 3598defm : FpUnaryAlias<"fdivr", DIVR_FST0r, 0>; 3599defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0, 0>; 3600defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 3601defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 3602defm : FpUnaryAlias<"fcompi", COM_FIPr, 0>; 3603defm : FpUnaryAlias<"fucompi", UCOM_FIPr, 0>; 3604 3605 3606// Handle "f{mulp,addp} $op, %st(0)" the same as "f{mulp,addp} $op", since they 3607// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 3608// solely because gas supports it. 3609def : InstAlias<"faddp\t{$op, %st|st, $op}", (ADD_FPrST0 RSTi:$op), 0>; 3610def : InstAlias<"fmulp\t{$op, %st|st, $op}", (MUL_FPrST0 RSTi:$op), 0>; 3611def : InstAlias<"fsub{|r}p\t{$op, %st|st, $op}", (SUBR_FPrST0 RSTi:$op), 0>; 3612def : InstAlias<"fsub{r|}p\t{$op, %st|st, $op}", (SUB_FPrST0 RSTi:$op), 0>; 3613def : InstAlias<"fdiv{|r}p\t{$op, %st|st, $op}", (DIVR_FPrST0 RSTi:$op), 0>; 3614def : InstAlias<"fdiv{r|}p\t{$op, %st|st, $op}", (DIV_FPrST0 RSTi:$op), 0>; 3615 3616def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; 3617 3618// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 3619// this is compatible with what GAS does. 3620def : InstAlias<"lcall\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 3621def : InstAlias<"ljmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 3622def : InstAlias<"lcall\t{*}$dst", (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 3623def : InstAlias<"ljmp\t{*}$dst", (FARJMP32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 3624def : InstAlias<"lcall\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 3625def : InstAlias<"ljmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 3626def : InstAlias<"lcall\t{*}$dst", (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 3627def : InstAlias<"ljmp\t{*}$dst", (FARJMP16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 3628 3629def : InstAlias<"jmp\t{*}$dst", (JMP64m i64mem:$dst), 0, "att">, Requires<[In64BitMode]>; 3630def : InstAlias<"jmp\t{*}$dst", (JMP32m i32mem:$dst), 0, "att">, Requires<[In32BitMode]>; 3631def : InstAlias<"jmp\t{*}$dst", (JMP16m i16mem:$dst), 0, "att">, Requires<[In16BitMode]>; 3632 3633 3634// "imul <imm>, B" is an alias for "imul <imm>, B, B". 3635def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; 3636def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; 3637def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; 3638def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; 3639def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; 3640def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; 3641 3642// ins aliases. Accept the mnemonic suffix being omitted because it's implicit 3643// in the destination. 3644def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0, "intel">; 3645def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">; 3646def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">; 3647 3648// outs aliases. Accept the mnemonic suffix being omitted because it's implicit 3649// in the source. 3650def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0, "intel">; 3651def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">; 3652def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">; 3653 3654// inb %dx -> inb %al, %dx 3655def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 3656def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 3657def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 3658def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>; 3659def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>; 3660def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>; 3661 3662 3663// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 3664def : InstAlias<"call\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 3665def : InstAlias<"jmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 3666def : InstAlias<"call\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 3667def : InstAlias<"jmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 3668def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3669def : InstAlias<"jmpw\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3670def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3671def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3672 3673// Match 'movq <largeimm>, <reg>' as an alias for movabsq. 3674def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 3675 3676// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, 3677// which supports this due to an old AMD documentation bug when 64-bit mode was 3678// created. 3679def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 3680 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 3681def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 3682 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 3683 3684// movsx aliases 3685def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">; 3686def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 3687def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">; 3688def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">; 3689def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">; 3690def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">; 3691def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">; 3692 3693// movzx aliases 3694def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">; 3695def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 3696def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">; 3697def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">; 3698def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">; 3699def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">; 3700// Note: No GR32->GR64 movzx form. 3701 3702// outb %dx -> outb %al, %dx 3703def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 3704def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 3705def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 3706def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>; 3707def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>; 3708def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>; 3709 3710// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 3711// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 3712// errors, since its encoding is the most compact. 3713def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 3714 3715// shld/shrd op,op -> shld op, op, CL 3716def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 3717def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 3718def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 3719def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 3720def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 3721def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 3722 3723def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 3724def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 3725def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 3726def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 3727def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 3728def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 3729 3730/* FIXME: This is disabled because the asm matcher is currently incapable of 3731 * matching a fixed immediate like $1. 3732// "shl X, $1" is an alias for "shl X". 3733multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 3734 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 3735 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 3736 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 3737 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 3738 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 3739 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 3740 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 3741 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 3742 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 3743 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 3744 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 3745 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 3746 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 3747 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 3748 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 3749 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 3750} 3751 3752defm : ShiftRotateByOneAlias<"rcl", "RCL">; 3753defm : ShiftRotateByOneAlias<"rcr", "RCR">; 3754defm : ShiftRotateByOneAlias<"rol", "ROL">; 3755defm : ShiftRotateByOneAlias<"ror", "ROR">; 3756FIXME */ 3757 3758// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 3759def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", 3760 (TEST8mr i8mem :$mem, GR8 :$val), 0>; 3761def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", 3762 (TEST16mr i16mem:$mem, GR16:$val), 0>; 3763def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", 3764 (TEST32mr i32mem:$mem, GR32:$val), 0>; 3765def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", 3766 (TEST64mr i64mem:$mem, GR64:$val), 0>; 3767 3768// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 3769def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 3770 (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 3771def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 3772 (XCHG16rm GR16:$val, i16mem:$mem), 0>; 3773def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 3774 (XCHG32rm GR32:$val, i32mem:$mem), 0>; 3775def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 3776 (XCHG64rm GR64:$val, i64mem:$mem), 0>; 3777 3778// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 3779def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 3780def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>; 3781def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 3782 3783// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we 3784// would get by default because it's defined as NOP. But xchg %eax, %eax implies 3785// implicit zeroing of the upper 32 bits. So alias to the longer encoding. 3786def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}", 3787 (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>; 3788 3789// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this 3790// we emit an unneeded REX.w prefix. 3791def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>; 3792 3793// These aliases exist to get the parser to prioritize matching 8-bit 3794// immediate encodings over matching the implicit ax/eax/rax encodings. By 3795// explicitly mentioning the A register here, these entries will be ordered 3796// first due to the more explicit immediate type. 3797def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; 3798def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; 3799def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; 3800def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; 3801def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; 3802def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; 3803def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; 3804def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>; 3805 3806def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>; 3807def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>; 3808def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>; 3809def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>; 3810def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>; 3811def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>; 3812def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>; 3813def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>; 3814 3815def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>; 3816def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>; 3817def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>; 3818def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>; 3819def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>; 3820def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>; 3821def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>; 3822def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>; 3823