1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the X86 implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H 14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H 15 16 #include "MCTargetDesc/X86BaseInfo.h" 17 #include "X86InstrFMA3Info.h" 18 #include "X86RegisterInfo.h" 19 #include "llvm/CodeGen/ISDOpcodes.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 #include <vector> 22 23 #define GET_INSTRINFO_HEADER 24 #include "X86GenInstrInfo.inc" 25 26 namespace llvm { 27 class X86Subtarget; 28 29 namespace X86 { 30 31 enum AsmComments { 32 // For instr that was compressed from EVEX to VEX. 33 AC_EVEX_2_VEX = MachineInstr::TAsmComments 34 }; 35 36 /// Return a pair of condition code for the given predicate and whether 37 /// the instruction operands should be swaped to match the condition code. 38 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate); 39 40 /// Return a setcc opcode based on whether it has a memory operand. 41 unsigned getSETOpc(bool HasMemoryOperand = false); 42 43 /// Return a cmov opcode for the given register size in bytes, and operand type. 44 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false); 45 46 // Turn jCC instruction into condition code. 47 CondCode getCondFromBranch(const MachineInstr &MI); 48 49 // Turn setCC instruction into condition code. 50 CondCode getCondFromSETCC(const MachineInstr &MI); 51 52 // Turn CMov instruction into condition code. 53 CondCode getCondFromCMov(const MachineInstr &MI); 54 55 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 56 /// e.g. turning COND_E to COND_NE. 57 CondCode GetOppositeBranchCondition(CondCode CC); 58 59 /// Get the VPCMP immediate for the given condition. 60 unsigned getVPCMPImmForCond(ISD::CondCode CC); 61 62 /// Get the VPCMP immediate if the opcodes are swapped. 63 unsigned getSwappedVPCMPImm(unsigned Imm); 64 65 /// Get the VPCOM immediate if the opcodes are swapped. 66 unsigned getSwappedVPCOMImm(unsigned Imm); 67 68 /// Get the VCMP immediate if the opcodes are swapped. 69 unsigned getSwappedVCMPImm(unsigned Imm); 70 71 } // namespace X86 72 73 /// isGlobalStubReference - Return true if the specified TargetFlag operand is 74 /// a reference to a stub for a global, not the global itself. 75 inline static bool isGlobalStubReference(unsigned char TargetFlag) { 76 switch (TargetFlag) { 77 case X86II::MO_DLLIMPORT: // dllimport stub. 78 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 79 case X86II::MO_GOT: // normal GOT reference. 80 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 81 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 82 case X86II::MO_COFFSTUB: // COFF .refptr stub. 83 return true; 84 default: 85 return false; 86 } 87 } 88 89 /// isGlobalRelativeToPICBase - Return true if the specified global value 90 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 91 /// is true, the addressing mode has the PIC base register added in (e.g. EBX). 92 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 93 switch (TargetFlag) { 94 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 95 case X86II::MO_GOT: // isPICStyleGOT: other global. 96 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 97 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 98 case X86II::MO_TLVP: // ??? Pretty sure.. 99 return true; 100 default: 101 return false; 102 } 103 } 104 105 inline static bool isScale(const MachineOperand &MO) { 106 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 || 107 MO.getImm() == 4 || MO.getImm() == 8); 108 } 109 110 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { 111 if (MI.getOperand(Op).isFI()) 112 return true; 113 return Op + X86::AddrSegmentReg <= MI.getNumOperands() && 114 MI.getOperand(Op + X86::AddrBaseReg).isReg() && 115 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) && 116 MI.getOperand(Op + X86::AddrIndexReg).isReg() && 117 (MI.getOperand(Op + X86::AddrDisp).isImm() || 118 MI.getOperand(Op + X86::AddrDisp).isGlobal() || 119 MI.getOperand(Op + X86::AddrDisp).isCPI() || 120 MI.getOperand(Op + X86::AddrDisp).isJTI()); 121 } 122 123 inline static bool isMem(const MachineInstr &MI, unsigned Op) { 124 if (MI.getOperand(Op).isFI()) 125 return true; 126 return Op + X86::AddrNumOperands <= MI.getNumOperands() && 127 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op); 128 } 129 130 class X86InstrInfo final : public X86GenInstrInfo { 131 X86Subtarget &Subtarget; 132 const X86RegisterInfo RI; 133 134 virtual void anchor(); 135 136 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 137 MachineBasicBlock *&FBB, 138 SmallVectorImpl<MachineOperand> &Cond, 139 SmallVectorImpl<MachineInstr *> &CondBranches, 140 bool AllowModify) const; 141 142 public: 143 explicit X86InstrInfo(X86Subtarget &STI); 144 145 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 146 /// such, whenever a client has an instance of instruction info, it should 147 /// always be able to get register info as well (through this method). 148 /// 149 const X86RegisterInfo &getRegisterInfo() const { return RI; } 150 151 /// Returns the stack pointer adjustment that happens inside the frame 152 /// setup..destroy sequence (e.g. by pushes, or inside the callee). 153 int64_t getFrameAdjustment(const MachineInstr &I) const { 154 assert(isFrameInstr(I)); 155 if (isFrameSetup(I)) 156 return I.getOperand(2).getImm(); 157 return I.getOperand(1).getImm(); 158 } 159 160 /// Sets the stack pointer adjustment made inside the frame made up by this 161 /// instruction. 162 void setFrameAdjustment(MachineInstr &I, int64_t V) const { 163 assert(isFrameInstr(I)); 164 if (isFrameSetup(I)) 165 I.getOperand(2).setImm(V); 166 else 167 I.getOperand(1).setImm(V); 168 } 169 170 /// getSPAdjust - This returns the stack pointer adjustment made by 171 /// this instruction. For x86, we need to handle more complex call 172 /// sequences involving PUSHes. 173 int getSPAdjust(const MachineInstr &MI) const override; 174 175 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 176 /// extension instruction. That is, it's like a copy where it's legal for the 177 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 178 /// true, then it's expected the pre-extension value is available as a subreg 179 /// of the result register. This also returns the sub-register index in 180 /// SubIdx. 181 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, 182 Register &DstReg, unsigned &SubIdx) const override; 183 184 /// Returns true if the instruction has no behavior (specified or otherwise) 185 /// that is based on the value of any of its register operands 186 /// 187 /// Instructions are considered data invariant even if they set EFLAGS. 188 /// 189 /// A classical example of something that is inherently not data invariant is 190 /// an indirect jump -- the destination is loaded into icache based on the 191 /// bits set in the jump destination register. 192 /// 193 /// FIXME: This should become part of our instruction tables. 194 static bool isDataInvariant(MachineInstr &MI); 195 196 /// Returns true if the instruction has no behavior (specified or otherwise) 197 /// that is based on the value loaded from memory or the value of any 198 /// non-address register operands. 199 /// 200 /// For example, if the latency of the instruction is dependent on the 201 /// particular bits set in any of the registers *or* any of the bits loaded 202 /// from memory. 203 /// 204 /// Instructions are considered data invariant even if they set EFLAGS. 205 /// 206 /// A classical example of something that is inherently not data invariant is 207 /// an indirect jump -- the destination is loaded into icache based on the 208 /// bits set in the jump destination register. 209 /// 210 /// FIXME: This should become part of our instruction tables. 211 static bool isDataInvariantLoad(MachineInstr &MI); 212 213 unsigned isLoadFromStackSlot(const MachineInstr &MI, 214 int &FrameIndex) const override; 215 unsigned isLoadFromStackSlot(const MachineInstr &MI, 216 int &FrameIndex, 217 unsigned &MemBytes) const override; 218 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 219 /// stack locations as well. This uses a heuristic so it isn't 220 /// reliable for correctness. 221 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 222 int &FrameIndex) const override; 223 224 unsigned isStoreToStackSlot(const MachineInstr &MI, 225 int &FrameIndex) const override; 226 unsigned isStoreToStackSlot(const MachineInstr &MI, 227 int &FrameIndex, 228 unsigned &MemBytes) const override; 229 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 230 /// stack locations as well. This uses a heuristic so it isn't 231 /// reliable for correctness. 232 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 233 int &FrameIndex) const override; 234 235 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 236 AAResults *AA) const override; 237 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 238 Register DestReg, unsigned SubIdx, 239 const MachineInstr &Orig, 240 const TargetRegisterInfo &TRI) const override; 241 242 /// Given an operand within a MachineInstr, insert preceding code to put it 243 /// into the right format for a particular kind of LEA instruction. This may 244 /// involve using an appropriate super-register instead (with an implicit use 245 /// of the original) or creating a new virtual register and inserting COPY 246 /// instructions to get the data into the right class. 247 /// 248 /// Reference parameters are set to indicate how caller should add this 249 /// operand to the LEA instruction. 250 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, 251 unsigned LEAOpcode, bool AllowSP, Register &NewSrc, 252 bool &isKill, MachineOperand &ImplicitOp, 253 LiveVariables *LV) const; 254 255 /// convertToThreeAddress - This method must be implemented by targets that 256 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 257 /// may be able to convert a two-address instruction into a true 258 /// three-address instruction on demand. This allows the X86 target (for 259 /// example) to convert ADD and SHL instructions into LEA instructions if they 260 /// would require register copies due to two-addressness. 261 /// 262 /// This method returns a null pointer if the transformation cannot be 263 /// performed, otherwise it returns the new instruction. 264 /// 265 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 266 MachineInstr &MI, 267 LiveVariables *LV) const override; 268 269 /// Returns true iff the routine could find two commutable operands in the 270 /// given machine instruction. 271 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their 272 /// input values can be re-defined in this method only if the input values 273 /// are not pre-defined, which is designated by the special value 274 /// 'CommuteAnyOperandIndex' assigned to it. 275 /// If both of indices are pre-defined and refer to some operands, then the 276 /// method simply returns true if the corresponding operands are commutable 277 /// and returns false otherwise. 278 /// 279 /// For example, calling this method this way: 280 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 281 /// findCommutedOpIndices(MI, Op1, Op2); 282 /// can be interpreted as a query asking to find an operand that would be 283 /// commutable with the operand#1. 284 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 285 unsigned &SrcOpIdx2) const override; 286 287 /// Returns true if we have preference on the operands order in MI, the 288 /// commute decision is returned in Commute. 289 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override; 290 291 /// Returns an adjusted FMA opcode that must be used in FMA instruction that 292 /// performs the same computations as the given \p MI but which has the 293 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted. 294 /// It may return 0 if it is unsafe to commute the operands. 295 /// Note that a machine instruction (instead of its opcode) is passed as the 296 /// first parameter to make it possible to analyze the instruction's uses and 297 /// commute the first operand of FMA even when it seems unsafe when you look 298 /// at the opcode. For example, it is Ok to commute the first operand of 299 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used. 300 /// 301 /// The returned FMA opcode may differ from the opcode in the given \p MI. 302 /// For example, commuting the operands #1 and #3 in the following FMA 303 /// FMA213 #1, #2, #3 304 /// results into instruction with adjusted opcode: 305 /// FMA231 #3, #2, #1 306 unsigned 307 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, 308 unsigned SrcOpIdx2, 309 const X86InstrFMA3Group &FMA3Group) const; 310 311 // Branch analysis. 312 bool isUnconditionalTailCall(const MachineInstr &MI) const override; 313 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond, 314 const MachineInstr &TailCall) const override; 315 void replaceBranchWithTailCall(MachineBasicBlock &MBB, 316 SmallVectorImpl<MachineOperand> &Cond, 317 const MachineInstr &TailCall) const override; 318 319 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 320 MachineBasicBlock *&FBB, 321 SmallVectorImpl<MachineOperand> &Cond, 322 bool AllowModify) const override; 323 324 Optional<ExtAddrMode> 325 getAddrModeFromMemoryOp(const MachineInstr &MemI, 326 const TargetRegisterInfo *TRI) const override; 327 328 bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, 329 int64_t &ImmVal) const override; 330 331 bool preservesZeroValueInReg(const MachineInstr *MI, 332 const Register NullValueReg, 333 const TargetRegisterInfo *TRI) const override; 334 335 bool getMemOperandsWithOffsetWidth( 336 const MachineInstr &LdSt, 337 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, 338 bool &OffsetIsScalable, unsigned &Width, 339 const TargetRegisterInfo *TRI) const override; 340 bool analyzeBranchPredicate(MachineBasicBlock &MBB, 341 TargetInstrInfo::MachineBranchPredicate &MBP, 342 bool AllowModify = false) const override; 343 344 unsigned removeBranch(MachineBasicBlock &MBB, 345 int *BytesRemoved = nullptr) const override; 346 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 347 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 348 const DebugLoc &DL, 349 int *BytesAdded = nullptr) const override; 350 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 351 Register, Register, Register, int &, int &, 352 int &) const override; 353 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 354 const DebugLoc &DL, Register DstReg, 355 ArrayRef<MachineOperand> Cond, Register TrueReg, 356 Register FalseReg) const override; 357 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 358 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 359 bool KillSrc) const override; 360 void storeRegToStackSlot(MachineBasicBlock &MBB, 361 MachineBasicBlock::iterator MI, Register SrcReg, 362 bool isKill, int FrameIndex, 363 const TargetRegisterClass *RC, 364 const TargetRegisterInfo *TRI) const override; 365 366 void loadRegFromStackSlot(MachineBasicBlock &MBB, 367 MachineBasicBlock::iterator MI, Register DestReg, 368 int FrameIndex, const TargetRegisterClass *RC, 369 const TargetRegisterInfo *TRI) const override; 370 371 bool expandPostRAPseudo(MachineInstr &MI) const override; 372 373 /// Check whether the target can fold a load that feeds a subreg operand 374 /// (or a subreg operand that feeds a store). 375 bool isSubregFoldable() const override { return true; } 376 377 /// foldMemoryOperand - If this target supports it, fold a load or store of 378 /// the specified stack slot into the specified machine instruction for the 379 /// specified operand(s). If this is possible, the target should perform the 380 /// folding and return true, otherwise it should return false. If it folds 381 /// the instruction, it is likely that the MachineInstruction the iterator 382 /// references has been changed. 383 MachineInstr * 384 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 385 ArrayRef<unsigned> Ops, 386 MachineBasicBlock::iterator InsertPt, int FrameIndex, 387 LiveIntervals *LIS = nullptr, 388 VirtRegMap *VRM = nullptr) const override; 389 390 /// foldMemoryOperand - Same as the previous version except it allows folding 391 /// of any load and store from / to any address, not just from a specific 392 /// stack slot. 393 MachineInstr *foldMemoryOperandImpl( 394 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 395 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, 396 LiveIntervals *LIS = nullptr) const override; 397 398 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 399 /// a store or a load and a store into two or more instruction. If this is 400 /// possible, returns true as well as the new instructions by reference. 401 bool 402 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, 403 bool UnfoldLoad, bool UnfoldStore, 404 SmallVectorImpl<MachineInstr *> &NewMIs) const override; 405 406 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 407 SmallVectorImpl<SDNode *> &NewNodes) const override; 408 409 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 410 /// instruction after load / store are unfolded from an instruction of the 411 /// specified opcode. It returns zero if the specified unfolding is not 412 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 413 /// index of the operand which will hold the register holding the loaded 414 /// value. 415 unsigned 416 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, 417 unsigned *LoadRegIndex = nullptr) const override; 418 419 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 420 /// to determine if two loads are loading from the same base address. It 421 /// should only return true if the base pointers are the same and the 422 /// only differences between the two addresses are the offset. It also returns 423 /// the offsets by reference. 424 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 425 int64_t &Offset2) const override; 426 427 /// isSchedulingBoundary - Overrides the isSchedulingBoundary from 428 /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR 429 /// intructions and prevent it from being re-scheduled. 430 bool isSchedulingBoundary(const MachineInstr &MI, 431 const MachineBasicBlock *MBB, 432 const MachineFunction &MF) const override; 433 434 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 435 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 436 /// should be scheduled togther. On some targets if two loads are loading from 437 /// addresses in the same cache line, it's better if they are scheduled 438 /// together. This function takes two integers that represent the load offsets 439 /// from the common base address. It returns true if it decides it's desirable 440 /// to schedule the two loads together. "NumLoads" is the number of loads that 441 /// have already been scheduled after Load1. 442 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, 443 int64_t Offset2, 444 unsigned NumLoads) const override; 445 446 MCInst getNop() const override; 447 448 bool 449 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 450 451 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 452 /// instruction that defines the specified register class. 453 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; 454 455 /// True if MI has a condition code def, e.g. EFLAGS, that is 456 /// not marked dead. 457 bool hasLiveCondCodeDef(MachineInstr &MI) const; 458 459 /// getGlobalBaseReg - Return a virtual register initialized with the 460 /// the global base register value. Output instructions required to 461 /// initialize the register in the function entry block, if necessary. 462 /// 463 unsigned getGlobalBaseReg(MachineFunction *MF) const; 464 465 std::pair<uint16_t, uint16_t> 466 getExecutionDomain(const MachineInstr &MI) const override; 467 468 uint16_t getExecutionDomainCustom(const MachineInstr &MI) const; 469 470 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override; 471 472 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const; 473 474 unsigned 475 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, 476 const TargetRegisterInfo *TRI) const override; 477 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, 478 const TargetRegisterInfo *TRI) const override; 479 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, 480 const TargetRegisterInfo *TRI) const override; 481 482 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 483 unsigned OpNum, 484 ArrayRef<MachineOperand> MOs, 485 MachineBasicBlock::iterator InsertPt, 486 unsigned Size, Align Alignment, 487 bool AllowCommute) const; 488 489 bool isHighLatencyDef(int opc) const override; 490 491 bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 492 const MachineRegisterInfo *MRI, 493 const MachineInstr &DefMI, unsigned DefIdx, 494 const MachineInstr &UseMI, 495 unsigned UseIdx) const override; 496 497 bool useMachineCombiner() const override { return true; } 498 499 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 500 501 bool hasReassociableOperands(const MachineInstr &Inst, 502 const MachineBasicBlock *MBB) const override; 503 504 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 505 MachineInstr &NewMI1, 506 MachineInstr &NewMI2) const override; 507 508 /// analyzeCompare - For a comparison instruction, return the source registers 509 /// in SrcReg and SrcReg2 if having two register operands, and the value it 510 /// compares against in CmpValue. Return true if the comparison instruction 511 /// can be analyzed. 512 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 513 Register &SrcReg2, int &CmpMask, 514 int &CmpValue) const override; 515 516 /// optimizeCompareInstr - Check if there exists an earlier instruction that 517 /// operates on the same source operands and sets flags in the same way as 518 /// Compare; remove Compare if possible. 519 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 520 Register SrcReg2, int CmpMask, int CmpValue, 521 const MachineRegisterInfo *MRI) const override; 522 523 /// optimizeLoadInstr - Try to remove the load by folding it to a register 524 /// operand at the use. We fold the load instructions if and only if the 525 /// def and use are in the same BB. We only look at one load and see 526 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 527 /// defined by the load we are trying to fold. DefMI returns the machine 528 /// instruction that defines FoldAsLoadDefReg, and the function returns 529 /// the machine instruction generated due to folding. 530 MachineInstr *optimizeLoadInstr(MachineInstr &MI, 531 const MachineRegisterInfo *MRI, 532 Register &FoldAsLoadDefReg, 533 MachineInstr *&DefMI) const override; 534 535 std::pair<unsigned, unsigned> 536 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 537 538 ArrayRef<std::pair<unsigned, const char *>> 539 getSerializableDirectMachineOperandTargetFlags() const override; 540 541 virtual outliner::OutlinedFunction getOutliningCandidateInfo( 542 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 543 544 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 545 bool OutlineFromLinkOnceODRs) const override; 546 547 outliner::InstrType 548 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override; 549 550 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 551 const outliner::OutlinedFunction &OF) const override; 552 553 MachineBasicBlock::iterator 554 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 555 MachineBasicBlock::iterator &It, MachineFunction &MF, 556 const outliner::Candidate &C) const override; 557 558 #define GET_INSTRINFO_HELPER_DECLS 559 #include "X86GenInstrInfo.inc" 560 561 static bool hasLockPrefix(const MachineInstr &MI) { 562 return MI.getDesc().TSFlags & X86II::LOCK; 563 } 564 565 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, 566 Register Reg) const override; 567 568 protected: 569 /// Commutes the operands in the given instruction by changing the operands 570 /// order and/or changing the instruction's opcode and/or the immediate value 571 /// operand. 572 /// 573 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands 574 /// to be commuted. 575 /// 576 /// Do not call this method for a non-commutable instruction or 577 /// non-commutable operands. 578 /// Even though the instruction is commutable, the method may still 579 /// fail to commute the operands, null pointer is returned in such cases. 580 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 581 unsigned CommuteOpIdx1, 582 unsigned CommuteOpIdx2) const override; 583 584 /// If the specific machine instruction is a instruction that moves/copies 585 /// value from one register to another register return destination and source 586 /// registers as machine operands. 587 Optional<DestSourcePair> 588 isCopyInstrImpl(const MachineInstr &MI) const override; 589 590 private: 591 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions. 592 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit 593 /// super-register and then truncating back down to a 8/16-bit sub-register. 594 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, 595 MachineFunction::iterator &MFI, 596 MachineInstr &MI, 597 LiveVariables *LV, 598 bool Is8BitOp) const; 599 600 /// Handles memory folding for special case instructions, for instance those 601 /// requiring custom manipulation of the address. 602 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI, 603 unsigned OpNum, 604 ArrayRef<MachineOperand> MOs, 605 MachineBasicBlock::iterator InsertPt, 606 unsigned Size, Align Alignment) const; 607 608 /// isFrameOperand - Return true and the FrameIndex if the specified 609 /// operand and follow operands form a reference to the stack frame. 610 bool isFrameOperand(const MachineInstr &MI, unsigned int Op, 611 int &FrameIndex) const; 612 613 /// Returns true iff the routine could find two commutable operands in the 614 /// given machine instruction with 3 vector inputs. 615 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their 616 /// input values can be re-defined in this method only if the input values 617 /// are not pre-defined, which is designated by the special value 618 /// 'CommuteAnyOperandIndex' assigned to it. 619 /// If both of indices are pre-defined and refer to some operands, then the 620 /// method simply returns true if the corresponding operands are commutable 621 /// and returns false otherwise. 622 /// 623 /// For example, calling this method this way: 624 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 625 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2); 626 /// can be interpreted as a query asking to find an operand that would be 627 /// commutable with the operand#1. 628 /// 629 /// If IsIntrinsic is set, operand 1 will be ignored for commuting. 630 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI, 631 unsigned &SrcOpIdx1, 632 unsigned &SrcOpIdx2, 633 bool IsIntrinsic = false) const; 634 }; 635 636 } // namespace llvm 637 638 #endif 639