1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the X86 implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H 14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H 15 16 #include "MCTargetDesc/X86BaseInfo.h" 17 #include "X86InstrFMA3Info.h" 18 #include "X86RegisterInfo.h" 19 #include "llvm/CodeGen/ISDOpcodes.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 #include <vector> 22 23 #define GET_INSTRINFO_HEADER 24 #include "X86GenInstrInfo.inc" 25 26 namespace llvm { 27 class X86Subtarget; 28 29 namespace X86 { 30 31 enum AsmComments { 32 // For instr that was compressed from EVEX to VEX. 33 AC_EVEX_2_VEX = MachineInstr::TAsmComments 34 }; 35 36 /// Return a pair of condition code for the given predicate and whether 37 /// the instruction operands should be swaped to match the condition code. 38 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate); 39 40 /// Return a cmov opcode for the given register size in bytes, and operand type. 41 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false); 42 43 /// Return the source operand # for condition code by \p MCID. If the 44 /// instruction doesn't have a condition code, return -1. 45 int getCondSrcNoFromDesc(const MCInstrDesc &MCID); 46 47 /// Return the condition code of the instruction. If the instruction doesn't 48 /// have a condition code, return X86::COND_INVALID. 49 CondCode getCondFromMI(const MachineInstr &MI); 50 51 // Turn JCC instruction into condition code. 52 CondCode getCondFromBranch(const MachineInstr &MI); 53 54 // Turn SETCC instruction into condition code. 55 CondCode getCondFromSETCC(const MachineInstr &MI); 56 57 // Turn CMOV instruction into condition code. 58 CondCode getCondFromCMov(const MachineInstr &MI); 59 60 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 61 /// e.g. turning COND_E to COND_NE. 62 CondCode GetOppositeBranchCondition(CondCode CC); 63 64 /// Get the VPCMP immediate for the given condition. 65 unsigned getVPCMPImmForCond(ISD::CondCode CC); 66 67 /// Get the VPCMP immediate if the opcodes are swapped. 68 unsigned getSwappedVPCMPImm(unsigned Imm); 69 70 /// Get the VPCOM immediate if the opcodes are swapped. 71 unsigned getSwappedVPCOMImm(unsigned Imm); 72 73 /// Get the VCMP immediate if the opcodes are swapped. 74 unsigned getSwappedVCMPImm(unsigned Imm); 75 76 /// Check if the instruction is X87 instruction. 77 bool isX87Instruction(MachineInstr &MI); 78 } // namespace X86 79 80 /// isGlobalStubReference - Return true if the specified TargetFlag operand is 81 /// a reference to a stub for a global, not the global itself. 82 inline static bool isGlobalStubReference(unsigned char TargetFlag) { 83 switch (TargetFlag) { 84 case X86II::MO_DLLIMPORT: // dllimport stub. 85 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 86 case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference. 87 case X86II::MO_GOT: // normal GOT reference. 88 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 89 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 90 case X86II::MO_COFFSTUB: // COFF .refptr stub. 91 return true; 92 default: 93 return false; 94 } 95 } 96 97 /// isGlobalRelativeToPICBase - Return true if the specified global value 98 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 99 /// is true, the addressing mode has the PIC base register added in (e.g. EBX). 100 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 101 switch (TargetFlag) { 102 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 103 case X86II::MO_GOT: // isPICStyleGOT: other global. 104 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 105 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 106 case X86II::MO_TLVP: // ??? Pretty sure.. 107 return true; 108 default: 109 return false; 110 } 111 } 112 113 inline static bool isScale(const MachineOperand &MO) { 114 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 || 115 MO.getImm() == 4 || MO.getImm() == 8); 116 } 117 118 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { 119 if (MI.getOperand(Op).isFI()) 120 return true; 121 return Op + X86::AddrSegmentReg <= MI.getNumOperands() && 122 MI.getOperand(Op + X86::AddrBaseReg).isReg() && 123 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) && 124 MI.getOperand(Op + X86::AddrIndexReg).isReg() && 125 (MI.getOperand(Op + X86::AddrDisp).isImm() || 126 MI.getOperand(Op + X86::AddrDisp).isGlobal() || 127 MI.getOperand(Op + X86::AddrDisp).isCPI() || 128 MI.getOperand(Op + X86::AddrDisp).isJTI()); 129 } 130 131 inline static bool isMem(const MachineInstr &MI, unsigned Op) { 132 if (MI.getOperand(Op).isFI()) 133 return true; 134 return Op + X86::AddrNumOperands <= MI.getNumOperands() && 135 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op); 136 } 137 138 class X86InstrInfo final : public X86GenInstrInfo { 139 X86Subtarget &Subtarget; 140 const X86RegisterInfo RI; 141 142 virtual void anchor(); 143 144 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 145 MachineBasicBlock *&FBB, 146 SmallVectorImpl<MachineOperand> &Cond, 147 SmallVectorImpl<MachineInstr *> &CondBranches, 148 bool AllowModify) const; 149 150 public: 151 explicit X86InstrInfo(X86Subtarget &STI); 152 153 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 154 /// such, whenever a client has an instance of instruction info, it should 155 /// always be able to get register info as well (through this method). 156 /// 157 const X86RegisterInfo &getRegisterInfo() const { return RI; } 158 159 /// Returns the stack pointer adjustment that happens inside the frame 160 /// setup..destroy sequence (e.g. by pushes, or inside the callee). 161 int64_t getFrameAdjustment(const MachineInstr &I) const { 162 assert(isFrameInstr(I)); 163 if (isFrameSetup(I)) 164 return I.getOperand(2).getImm(); 165 return I.getOperand(1).getImm(); 166 } 167 168 /// Sets the stack pointer adjustment made inside the frame made up by this 169 /// instruction. 170 void setFrameAdjustment(MachineInstr &I, int64_t V) const { 171 assert(isFrameInstr(I)); 172 if (isFrameSetup(I)) 173 I.getOperand(2).setImm(V); 174 else 175 I.getOperand(1).setImm(V); 176 } 177 178 /// getSPAdjust - This returns the stack pointer adjustment made by 179 /// this instruction. For x86, we need to handle more complex call 180 /// sequences involving PUSHes. 181 int getSPAdjust(const MachineInstr &MI) const override; 182 183 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 184 /// extension instruction. That is, it's like a copy where it's legal for the 185 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 186 /// true, then it's expected the pre-extension value is available as a subreg 187 /// of the result register. This also returns the sub-register index in 188 /// SubIdx. 189 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, 190 Register &DstReg, unsigned &SubIdx) const override; 191 192 /// Returns true if the instruction has no behavior (specified or otherwise) 193 /// that is based on the value of any of its register operands 194 /// 195 /// Instructions are considered data invariant even if they set EFLAGS. 196 /// 197 /// A classical example of something that is inherently not data invariant is 198 /// an indirect jump -- the destination is loaded into icache based on the 199 /// bits set in the jump destination register. 200 /// 201 /// FIXME: This should become part of our instruction tables. 202 static bool isDataInvariant(MachineInstr &MI); 203 204 /// Returns true if the instruction has no behavior (specified or otherwise) 205 /// that is based on the value loaded from memory or the value of any 206 /// non-address register operands. 207 /// 208 /// For example, if the latency of the instruction is dependent on the 209 /// particular bits set in any of the registers *or* any of the bits loaded 210 /// from memory. 211 /// 212 /// Instructions are considered data invariant even if they set EFLAGS. 213 /// 214 /// A classical example of something that is inherently not data invariant is 215 /// an indirect jump -- the destination is loaded into icache based on the 216 /// bits set in the jump destination register. 217 /// 218 /// FIXME: This should become part of our instruction tables. 219 static bool isDataInvariantLoad(MachineInstr &MI); 220 221 unsigned isLoadFromStackSlot(const MachineInstr &MI, 222 int &FrameIndex) const override; 223 unsigned isLoadFromStackSlot(const MachineInstr &MI, 224 int &FrameIndex, 225 unsigned &MemBytes) const override; 226 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 227 /// stack locations as well. This uses a heuristic so it isn't 228 /// reliable for correctness. 229 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 230 int &FrameIndex) const override; 231 232 unsigned isStoreToStackSlot(const MachineInstr &MI, 233 int &FrameIndex) const override; 234 unsigned isStoreToStackSlot(const MachineInstr &MI, 235 int &FrameIndex, 236 unsigned &MemBytes) const override; 237 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 238 /// stack locations as well. This uses a heuristic so it isn't 239 /// reliable for correctness. 240 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 241 int &FrameIndex) const override; 242 243 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override; 244 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 245 Register DestReg, unsigned SubIdx, 246 const MachineInstr &Orig, 247 const TargetRegisterInfo &TRI) const override; 248 249 /// Given an operand within a MachineInstr, insert preceding code to put it 250 /// into the right format for a particular kind of LEA instruction. This may 251 /// involve using an appropriate super-register instead (with an implicit use 252 /// of the original) or creating a new virtual register and inserting COPY 253 /// instructions to get the data into the right class. 254 /// 255 /// Reference parameters are set to indicate how caller should add this 256 /// operand to the LEA instruction. 257 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, 258 unsigned LEAOpcode, bool AllowSP, Register &NewSrc, 259 bool &isKill, MachineOperand &ImplicitOp, 260 LiveVariables *LV, LiveIntervals *LIS) const; 261 262 /// convertToThreeAddress - This method must be implemented by targets that 263 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 264 /// may be able to convert a two-address instruction into a true 265 /// three-address instruction on demand. This allows the X86 target (for 266 /// example) to convert ADD and SHL instructions into LEA instructions if they 267 /// would require register copies due to two-addressness. 268 /// 269 /// This method returns a null pointer if the transformation cannot be 270 /// performed, otherwise it returns the new instruction. 271 /// 272 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, 273 LiveIntervals *LIS) const override; 274 275 /// Returns true iff the routine could find two commutable operands in the 276 /// given machine instruction. 277 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their 278 /// input values can be re-defined in this method only if the input values 279 /// are not pre-defined, which is designated by the special value 280 /// 'CommuteAnyOperandIndex' assigned to it. 281 /// If both of indices are pre-defined and refer to some operands, then the 282 /// method simply returns true if the corresponding operands are commutable 283 /// and returns false otherwise. 284 /// 285 /// For example, calling this method this way: 286 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 287 /// findCommutedOpIndices(MI, Op1, Op2); 288 /// can be interpreted as a query asking to find an operand that would be 289 /// commutable with the operand#1. 290 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 291 unsigned &SrcOpIdx2) const override; 292 293 /// Returns true if we have preference on the operands order in MI, the 294 /// commute decision is returned in Commute. 295 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override; 296 297 /// Returns an adjusted FMA opcode that must be used in FMA instruction that 298 /// performs the same computations as the given \p MI but which has the 299 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted. 300 /// It may return 0 if it is unsafe to commute the operands. 301 /// Note that a machine instruction (instead of its opcode) is passed as the 302 /// first parameter to make it possible to analyze the instruction's uses and 303 /// commute the first operand of FMA even when it seems unsafe when you look 304 /// at the opcode. For example, it is Ok to commute the first operand of 305 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used. 306 /// 307 /// The returned FMA opcode may differ from the opcode in the given \p MI. 308 /// For example, commuting the operands #1 and #3 in the following FMA 309 /// FMA213 #1, #2, #3 310 /// results into instruction with adjusted opcode: 311 /// FMA231 #3, #2, #1 312 unsigned 313 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, 314 unsigned SrcOpIdx2, 315 const X86InstrFMA3Group &FMA3Group) const; 316 317 // Branch analysis. 318 bool isUnconditionalTailCall(const MachineInstr &MI) const override; 319 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond, 320 const MachineInstr &TailCall) const override; 321 void replaceBranchWithTailCall(MachineBasicBlock &MBB, 322 SmallVectorImpl<MachineOperand> &Cond, 323 const MachineInstr &TailCall) const override; 324 325 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 326 MachineBasicBlock *&FBB, 327 SmallVectorImpl<MachineOperand> &Cond, 328 bool AllowModify) const override; 329 330 std::optional<ExtAddrMode> 331 getAddrModeFromMemoryOp(const MachineInstr &MemI, 332 const TargetRegisterInfo *TRI) const override; 333 334 bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, 335 int64_t &ImmVal) const override; 336 337 bool preservesZeroValueInReg(const MachineInstr *MI, 338 const Register NullValueReg, 339 const TargetRegisterInfo *TRI) const override; 340 341 bool getMemOperandsWithOffsetWidth( 342 const MachineInstr &LdSt, 343 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, 344 bool &OffsetIsScalable, unsigned &Width, 345 const TargetRegisterInfo *TRI) const override; 346 bool analyzeBranchPredicate(MachineBasicBlock &MBB, 347 TargetInstrInfo::MachineBranchPredicate &MBP, 348 bool AllowModify = false) const override; 349 350 unsigned removeBranch(MachineBasicBlock &MBB, 351 int *BytesRemoved = nullptr) const override; 352 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 353 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 354 const DebugLoc &DL, 355 int *BytesAdded = nullptr) const override; 356 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 357 Register, Register, Register, int &, int &, 358 int &) const override; 359 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 360 const DebugLoc &DL, Register DstReg, 361 ArrayRef<MachineOperand> Cond, Register TrueReg, 362 Register FalseReg) const override; 363 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 364 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 365 bool KillSrc) const override; 366 void storeRegToStackSlot(MachineBasicBlock &MBB, 367 MachineBasicBlock::iterator MI, Register SrcReg, 368 bool isKill, int FrameIndex, 369 const TargetRegisterClass *RC, 370 const TargetRegisterInfo *TRI, 371 Register VReg) const override; 372 373 void loadRegFromStackSlot(MachineBasicBlock &MBB, 374 MachineBasicBlock::iterator MI, Register DestReg, 375 int FrameIndex, const TargetRegisterClass *RC, 376 const TargetRegisterInfo *TRI, 377 Register VReg) const override; 378 379 void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 380 unsigned Opc, Register Reg, int FrameIdx, 381 bool isKill = false) const; 382 383 bool expandPostRAPseudo(MachineInstr &MI) const override; 384 385 /// Check whether the target can fold a load that feeds a subreg operand 386 /// (or a subreg operand that feeds a store). 387 bool isSubregFoldable() const override { return true; } 388 389 /// foldMemoryOperand - If this target supports it, fold a load or store of 390 /// the specified stack slot into the specified machine instruction for the 391 /// specified operand(s). If this is possible, the target should perform the 392 /// folding and return true, otherwise it should return false. If it folds 393 /// the instruction, it is likely that the MachineInstruction the iterator 394 /// references has been changed. 395 MachineInstr * 396 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 397 ArrayRef<unsigned> Ops, 398 MachineBasicBlock::iterator InsertPt, int FrameIndex, 399 LiveIntervals *LIS = nullptr, 400 VirtRegMap *VRM = nullptr) const override; 401 402 /// foldMemoryOperand - Same as the previous version except it allows folding 403 /// of any load and store from / to any address, not just from a specific 404 /// stack slot. 405 MachineInstr *foldMemoryOperandImpl( 406 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 407 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, 408 LiveIntervals *LIS = nullptr) const override; 409 410 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 411 /// a store or a load and a store into two or more instruction. If this is 412 /// possible, returns true as well as the new instructions by reference. 413 bool 414 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, 415 bool UnfoldLoad, bool UnfoldStore, 416 SmallVectorImpl<MachineInstr *> &NewMIs) const override; 417 418 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 419 SmallVectorImpl<SDNode *> &NewNodes) const override; 420 421 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 422 /// instruction after load / store are unfolded from an instruction of the 423 /// specified opcode. It returns zero if the specified unfolding is not 424 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 425 /// index of the operand which will hold the register holding the loaded 426 /// value. 427 unsigned 428 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, 429 unsigned *LoadRegIndex = nullptr) const override; 430 431 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 432 /// to determine if two loads are loading from the same base address. It 433 /// should only return true if the base pointers are the same and the 434 /// only differences between the two addresses are the offset. It also returns 435 /// the offsets by reference. 436 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 437 int64_t &Offset2) const override; 438 439 /// isSchedulingBoundary - Overrides the isSchedulingBoundary from 440 /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR 441 /// intructions and prevent it from being re-scheduled. 442 bool isSchedulingBoundary(const MachineInstr &MI, 443 const MachineBasicBlock *MBB, 444 const MachineFunction &MF) const override; 445 446 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 447 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 448 /// should be scheduled togther. On some targets if two loads are loading from 449 /// addresses in the same cache line, it's better if they are scheduled 450 /// together. This function takes two integers that represent the load offsets 451 /// from the common base address. It returns true if it decides it's desirable 452 /// to schedule the two loads together. "NumLoads" is the number of loads that 453 /// have already been scheduled after Load1. 454 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, 455 int64_t Offset2, 456 unsigned NumLoads) const override; 457 458 MCInst getNop() const override; 459 460 bool 461 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 462 463 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 464 /// instruction that defines the specified register class. 465 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; 466 467 /// True if MI has a condition code def, e.g. EFLAGS, that is 468 /// not marked dead. 469 bool hasLiveCondCodeDef(MachineInstr &MI) const; 470 471 /// getGlobalBaseReg - Return a virtual register initialized with the 472 /// the global base register value. Output instructions required to 473 /// initialize the register in the function entry block, if necessary. 474 /// 475 unsigned getGlobalBaseReg(MachineFunction *MF) const; 476 477 std::pair<uint16_t, uint16_t> 478 getExecutionDomain(const MachineInstr &MI) const override; 479 480 uint16_t getExecutionDomainCustom(const MachineInstr &MI) const; 481 482 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override; 483 484 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const; 485 486 unsigned 487 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, 488 const TargetRegisterInfo *TRI) const override; 489 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, 490 const TargetRegisterInfo *TRI) const override; 491 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, 492 const TargetRegisterInfo *TRI) const override; 493 494 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 495 unsigned OpNum, 496 ArrayRef<MachineOperand> MOs, 497 MachineBasicBlock::iterator InsertPt, 498 unsigned Size, Align Alignment, 499 bool AllowCommute) const; 500 501 bool isHighLatencyDef(int opc) const override; 502 503 bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 504 const MachineRegisterInfo *MRI, 505 const MachineInstr &DefMI, unsigned DefIdx, 506 const MachineInstr &UseMI, 507 unsigned UseIdx) const override; 508 509 bool useMachineCombiner() const override { return true; } 510 511 bool isAssociativeAndCommutative(const MachineInstr &Inst, 512 bool Invert) const override; 513 514 bool hasReassociableOperands(const MachineInstr &Inst, 515 const MachineBasicBlock *MBB) const override; 516 517 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 518 MachineInstr &NewMI1, 519 MachineInstr &NewMI2) const override; 520 521 /// analyzeCompare - For a comparison instruction, return the source registers 522 /// in SrcReg and SrcReg2 if having two register operands, and the value it 523 /// compares against in CmpValue. Return true if the comparison instruction 524 /// can be analyzed. 525 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 526 Register &SrcReg2, int64_t &CmpMask, 527 int64_t &CmpValue) const override; 528 529 /// optimizeCompareInstr - Check if there exists an earlier instruction that 530 /// operates on the same source operands and sets flags in the same way as 531 /// Compare; remove Compare if possible. 532 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 533 Register SrcReg2, int64_t CmpMask, int64_t CmpValue, 534 const MachineRegisterInfo *MRI) const override; 535 536 /// optimizeLoadInstr - Try to remove the load by folding it to a register 537 /// operand at the use. We fold the load instructions if and only if the 538 /// def and use are in the same BB. We only look at one load and see 539 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 540 /// defined by the load we are trying to fold. DefMI returns the machine 541 /// instruction that defines FoldAsLoadDefReg, and the function returns 542 /// the machine instruction generated due to folding. 543 MachineInstr *optimizeLoadInstr(MachineInstr &MI, 544 const MachineRegisterInfo *MRI, 545 Register &FoldAsLoadDefReg, 546 MachineInstr *&DefMI) const override; 547 548 std::pair<unsigned, unsigned> 549 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 550 551 ArrayRef<std::pair<unsigned, const char *>> 552 getSerializableDirectMachineOperandTargetFlags() const override; 553 554 outliner::OutlinedFunction getOutliningCandidateInfo( 555 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 556 557 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 558 bool OutlineFromLinkOnceODRs) const override; 559 560 outliner::InstrType 561 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override; 562 563 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 564 const outliner::OutlinedFunction &OF) const override; 565 566 MachineBasicBlock::iterator 567 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 568 MachineBasicBlock::iterator &It, MachineFunction &MF, 569 outliner::Candidate &C) const override; 570 571 bool verifyInstruction(const MachineInstr &MI, 572 StringRef &ErrInfo) const override; 573 #define GET_INSTRINFO_HELPER_DECLS 574 #include "X86GenInstrInfo.inc" 575 576 static bool hasLockPrefix(const MachineInstr &MI) { 577 return MI.getDesc().TSFlags & X86II::LOCK; 578 } 579 580 std::optional<ParamLoadedValue> 581 describeLoadedValue(const MachineInstr &MI, Register Reg) const override; 582 583 protected: 584 /// Commutes the operands in the given instruction by changing the operands 585 /// order and/or changing the instruction's opcode and/or the immediate value 586 /// operand. 587 /// 588 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands 589 /// to be commuted. 590 /// 591 /// Do not call this method for a non-commutable instruction or 592 /// non-commutable operands. 593 /// Even though the instruction is commutable, the method may still 594 /// fail to commute the operands, null pointer is returned in such cases. 595 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 596 unsigned CommuteOpIdx1, 597 unsigned CommuteOpIdx2) const override; 598 599 /// If the specific machine instruction is a instruction that moves/copies 600 /// value from one register to another register return destination and source 601 /// registers as machine operands. 602 std::optional<DestSourcePair> 603 isCopyInstrImpl(const MachineInstr &MI) const override; 604 605 private: 606 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions. 607 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit 608 /// super-register and then truncating back down to a 8/16-bit sub-register. 609 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI, 610 LiveVariables *LV, 611 LiveIntervals *LIS, 612 bool Is8BitOp) const; 613 614 /// Handles memory folding for special case instructions, for instance those 615 /// requiring custom manipulation of the address. 616 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI, 617 unsigned OpNum, 618 ArrayRef<MachineOperand> MOs, 619 MachineBasicBlock::iterator InsertPt, 620 unsigned Size, Align Alignment) const; 621 622 /// isFrameOperand - Return true and the FrameIndex if the specified 623 /// operand and follow operands form a reference to the stack frame. 624 bool isFrameOperand(const MachineInstr &MI, unsigned int Op, 625 int &FrameIndex) const; 626 627 /// Returns true iff the routine could find two commutable operands in the 628 /// given machine instruction with 3 vector inputs. 629 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their 630 /// input values can be re-defined in this method only if the input values 631 /// are not pre-defined, which is designated by the special value 632 /// 'CommuteAnyOperandIndex' assigned to it. 633 /// If both of indices are pre-defined and refer to some operands, then the 634 /// method simply returns true if the corresponding operands are commutable 635 /// and returns false otherwise. 636 /// 637 /// For example, calling this method this way: 638 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 639 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2); 640 /// can be interpreted as a query asking to find an operand that would be 641 /// commutable with the operand#1. 642 /// 643 /// If IsIntrinsic is set, operand 1 will be ignored for commuting. 644 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI, 645 unsigned &SrcOpIdx1, 646 unsigned &SrcOpIdx2, 647 bool IsIntrinsic = false) const; 648 649 /// Returns true when instruction \p FlagI produces the same flags as \p OI. 650 /// The caller should pass in the results of calling analyzeCompare on \p OI: 651 /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue. 652 /// If the flags match \p OI as if it had the input operands swapped then the 653 /// function succeeds and sets \p IsSwapped to true. 654 /// 655 /// Examples of OI, FlagI pairs returning true: 656 /// CMP %1, 42 and CMP %1, 42 657 /// CMP %1, %2 and %3 = SUB %1, %2 658 /// TEST %1, %1 and %2 = SUB %1, 0 659 /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true 660 bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg, 661 Register SrcReg2, int64_t ImmMask, int64_t ImmValue, 662 const MachineInstr &OI, bool *IsSwapped, 663 int64_t *ImmDelta) const; 664 }; 665 666 } // namespace llvm 667 668 #endif 669