1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the X86 implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H 14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H 15 16 #include "MCTargetDesc/X86BaseInfo.h" 17 #include "X86InstrFMA3Info.h" 18 #include "X86RegisterInfo.h" 19 #include "llvm/CodeGen/ISDOpcodes.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 #include <vector> 22 23 #define GET_INSTRINFO_HEADER 24 #include "X86GenInstrInfo.inc" 25 26 namespace llvm { 27 class X86Subtarget; 28 29 namespace X86 { 30 31 enum AsmComments { 32 // For instr that was compressed from EVEX to LEGACY. 33 AC_EVEX_2_LEGACY = MachineInstr::TAsmComments, 34 // For instr that was compressed from EVEX to VEX. 35 AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1, 36 // For instr that was compressed from EVEX to EVEX. 37 AC_EVEX_2_EVEX = AC_EVEX_2_VEX << 1 38 }; 39 40 /// Return a pair of condition code for the given predicate and whether 41 /// the instruction operands should be swaped to match the condition code. 42 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate); 43 44 /// Return a cmov opcode for the given register size in bytes, and operand type. 45 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false); 46 47 /// Return the source operand # for condition code by \p MCID. If the 48 /// instruction doesn't have a condition code, return -1. 49 int getCondSrcNoFromDesc(const MCInstrDesc &MCID); 50 51 /// Return the condition code of the instruction. If the instruction doesn't 52 /// have a condition code, return X86::COND_INVALID. 53 CondCode getCondFromMI(const MachineInstr &MI); 54 55 // Turn JCC instruction into condition code. 56 CondCode getCondFromBranch(const MachineInstr &MI); 57 58 // Turn SETCC instruction into condition code. 59 CondCode getCondFromSETCC(const MachineInstr &MI); 60 61 // Turn CMOV instruction into condition code. 62 CondCode getCondFromCMov(const MachineInstr &MI); 63 64 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 65 /// e.g. turning COND_E to COND_NE. 66 CondCode GetOppositeBranchCondition(CondCode CC); 67 68 /// Get the VPCMP immediate for the given condition. 69 unsigned getVPCMPImmForCond(ISD::CondCode CC); 70 71 /// Get the VPCMP immediate if the opcodes are swapped. 72 unsigned getSwappedVPCMPImm(unsigned Imm); 73 74 /// Get the VPCOM immediate if the opcodes are swapped. 75 unsigned getSwappedVPCOMImm(unsigned Imm); 76 77 /// Get the VCMP immediate if the opcodes are swapped. 78 unsigned getSwappedVCMPImm(unsigned Imm); 79 80 /// Check if the instruction is X87 instruction. 81 bool isX87Instruction(MachineInstr &MI); 82 83 /// Return the index of the instruction's first address operand, if it has a 84 /// memory reference, or -1 if it has none. Unlike X86II::getMemoryOperandNo(), 85 /// this also works for both pseudo instructions (e.g., TCRETURNmi) as well as 86 /// real instructions (e.g., JMP64m). 87 int getFirstAddrOperandIdx(const MachineInstr &MI); 88 89 /// Find any constant pool entry associated with a specific instruction operand. 90 const Constant *getConstantFromPool(const MachineInstr &MI, unsigned OpNo); 91 92 } // namespace X86 93 94 /// isGlobalStubReference - Return true if the specified TargetFlag operand is 95 /// a reference to a stub for a global, not the global itself. 96 inline static bool isGlobalStubReference(unsigned char TargetFlag) { 97 switch (TargetFlag) { 98 case X86II::MO_DLLIMPORT: // dllimport stub. 99 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 100 case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference. 101 case X86II::MO_GOT: // normal GOT reference. 102 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 103 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 104 case X86II::MO_COFFSTUB: // COFF .refptr stub. 105 return true; 106 default: 107 return false; 108 } 109 } 110 111 /// isGlobalRelativeToPICBase - Return true if the specified global value 112 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 113 /// is true, the addressing mode has the PIC base register added in (e.g. EBX). 114 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 115 switch (TargetFlag) { 116 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 117 case X86II::MO_GOT: // isPICStyleGOT: other global. 118 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 119 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 120 case X86II::MO_TLVP: // ??? Pretty sure.. 121 return true; 122 default: 123 return false; 124 } 125 } 126 127 inline static bool isScale(const MachineOperand &MO) { 128 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 || 129 MO.getImm() == 4 || MO.getImm() == 8); 130 } 131 132 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { 133 if (MI.getOperand(Op).isFI()) 134 return true; 135 return Op + X86::AddrSegmentReg <= MI.getNumOperands() && 136 MI.getOperand(Op + X86::AddrBaseReg).isReg() && 137 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) && 138 MI.getOperand(Op + X86::AddrIndexReg).isReg() && 139 (MI.getOperand(Op + X86::AddrDisp).isImm() || 140 MI.getOperand(Op + X86::AddrDisp).isGlobal() || 141 MI.getOperand(Op + X86::AddrDisp).isCPI() || 142 MI.getOperand(Op + X86::AddrDisp).isJTI()); 143 } 144 145 inline static bool isMem(const MachineInstr &MI, unsigned Op) { 146 if (MI.getOperand(Op).isFI()) 147 return true; 148 return Op + X86::AddrNumOperands <= MI.getNumOperands() && 149 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op); 150 } 151 152 class X86InstrInfo final : public X86GenInstrInfo { 153 X86Subtarget &Subtarget; 154 const X86RegisterInfo RI; 155 156 virtual void anchor(); 157 158 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 159 MachineBasicBlock *&FBB, 160 SmallVectorImpl<MachineOperand> &Cond, 161 SmallVectorImpl<MachineInstr *> &CondBranches, 162 bool AllowModify) const; 163 164 public: 165 explicit X86InstrInfo(X86Subtarget &STI); 166 167 /// Given a machine instruction descriptor, returns the register 168 /// class constraint for OpNum, or NULL. Returned register class 169 /// may be different from the definition in the TD file, e.g. 170 /// GR*RegClass (definition in TD file) 171 /// -> 172 /// GR*_NOREX2RegClass (Returned register class) 173 const TargetRegisterClass * 174 getRegClass(const MCInstrDesc &MCID, unsigned OpNum, 175 const TargetRegisterInfo *TRI, 176 const MachineFunction &MF) const override; 177 178 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 179 /// such, whenever a client has an instance of instruction info, it should 180 /// always be able to get register info as well (through this method). 181 /// 182 const X86RegisterInfo &getRegisterInfo() const { return RI; } 183 184 /// Returns the stack pointer adjustment that happens inside the frame 185 /// setup..destroy sequence (e.g. by pushes, or inside the callee). 186 int64_t getFrameAdjustment(const MachineInstr &I) const { 187 assert(isFrameInstr(I)); 188 if (isFrameSetup(I)) 189 return I.getOperand(2).getImm(); 190 return I.getOperand(1).getImm(); 191 } 192 193 /// Sets the stack pointer adjustment made inside the frame made up by this 194 /// instruction. 195 void setFrameAdjustment(MachineInstr &I, int64_t V) const { 196 assert(isFrameInstr(I)); 197 if (isFrameSetup(I)) 198 I.getOperand(2).setImm(V); 199 else 200 I.getOperand(1).setImm(V); 201 } 202 203 /// getSPAdjust - This returns the stack pointer adjustment made by 204 /// this instruction. For x86, we need to handle more complex call 205 /// sequences involving PUSHes. 206 int getSPAdjust(const MachineInstr &MI) const override; 207 208 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 209 /// extension instruction. That is, it's like a copy where it's legal for the 210 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 211 /// true, then it's expected the pre-extension value is available as a subreg 212 /// of the result register. This also returns the sub-register index in 213 /// SubIdx. 214 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, 215 Register &DstReg, unsigned &SubIdx) const override; 216 217 /// Returns true if the instruction has no behavior (specified or otherwise) 218 /// that is based on the value of any of its register operands 219 /// 220 /// Instructions are considered data invariant even if they set EFLAGS. 221 /// 222 /// A classical example of something that is inherently not data invariant is 223 /// an indirect jump -- the destination is loaded into icache based on the 224 /// bits set in the jump destination register. 225 /// 226 /// FIXME: This should become part of our instruction tables. 227 static bool isDataInvariant(MachineInstr &MI); 228 229 /// Returns true if the instruction has no behavior (specified or otherwise) 230 /// that is based on the value loaded from memory or the value of any 231 /// non-address register operands. 232 /// 233 /// For example, if the latency of the instruction is dependent on the 234 /// particular bits set in any of the registers *or* any of the bits loaded 235 /// from memory. 236 /// 237 /// Instructions are considered data invariant even if they set EFLAGS. 238 /// 239 /// A classical example of something that is inherently not data invariant is 240 /// an indirect jump -- the destination is loaded into icache based on the 241 /// bits set in the jump destination register. 242 /// 243 /// FIXME: This should become part of our instruction tables. 244 static bool isDataInvariantLoad(MachineInstr &MI); 245 246 unsigned isLoadFromStackSlot(const MachineInstr &MI, 247 int &FrameIndex) const override; 248 unsigned isLoadFromStackSlot(const MachineInstr &MI, 249 int &FrameIndex, 250 unsigned &MemBytes) const override; 251 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 252 /// stack locations as well. This uses a heuristic so it isn't 253 /// reliable for correctness. 254 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 255 int &FrameIndex) const override; 256 257 unsigned isStoreToStackSlot(const MachineInstr &MI, 258 int &FrameIndex) const override; 259 unsigned isStoreToStackSlot(const MachineInstr &MI, 260 int &FrameIndex, 261 unsigned &MemBytes) const override; 262 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 263 /// stack locations as well. This uses a heuristic so it isn't 264 /// reliable for correctness. 265 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 266 int &FrameIndex) const override; 267 268 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override; 269 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 270 Register DestReg, unsigned SubIdx, 271 const MachineInstr &Orig, 272 const TargetRegisterInfo &TRI) const override; 273 274 /// Given an operand within a MachineInstr, insert preceding code to put it 275 /// into the right format for a particular kind of LEA instruction. This may 276 /// involve using an appropriate super-register instead (with an implicit use 277 /// of the original) or creating a new virtual register and inserting COPY 278 /// instructions to get the data into the right class. 279 /// 280 /// Reference parameters are set to indicate how caller should add this 281 /// operand to the LEA instruction. 282 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, 283 unsigned LEAOpcode, bool AllowSP, Register &NewSrc, 284 bool &isKill, MachineOperand &ImplicitOp, 285 LiveVariables *LV, LiveIntervals *LIS) const; 286 287 /// convertToThreeAddress - This method must be implemented by targets that 288 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 289 /// may be able to convert a two-address instruction into a true 290 /// three-address instruction on demand. This allows the X86 target (for 291 /// example) to convert ADD and SHL instructions into LEA instructions if they 292 /// would require register copies due to two-addressness. 293 /// 294 /// This method returns a null pointer if the transformation cannot be 295 /// performed, otherwise it returns the new instruction. 296 /// 297 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, 298 LiveIntervals *LIS) const override; 299 300 /// Returns true iff the routine could find two commutable operands in the 301 /// given machine instruction. 302 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their 303 /// input values can be re-defined in this method only if the input values 304 /// are not pre-defined, which is designated by the special value 305 /// 'CommuteAnyOperandIndex' assigned to it. 306 /// If both of indices are pre-defined and refer to some operands, then the 307 /// method simply returns true if the corresponding operands are commutable 308 /// and returns false otherwise. 309 /// 310 /// For example, calling this method this way: 311 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 312 /// findCommutedOpIndices(MI, Op1, Op2); 313 /// can be interpreted as a query asking to find an operand that would be 314 /// commutable with the operand#1. 315 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 316 unsigned &SrcOpIdx2) const override; 317 318 /// Returns true if we have preference on the operands order in MI, the 319 /// commute decision is returned in Commute. 320 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override; 321 322 /// Returns an adjusted FMA opcode that must be used in FMA instruction that 323 /// performs the same computations as the given \p MI but which has the 324 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted. 325 /// It may return 0 if it is unsafe to commute the operands. 326 /// Note that a machine instruction (instead of its opcode) is passed as the 327 /// first parameter to make it possible to analyze the instruction's uses and 328 /// commute the first operand of FMA even when it seems unsafe when you look 329 /// at the opcode. For example, it is Ok to commute the first operand of 330 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used. 331 /// 332 /// The returned FMA opcode may differ from the opcode in the given \p MI. 333 /// For example, commuting the operands #1 and #3 in the following FMA 334 /// FMA213 #1, #2, #3 335 /// results into instruction with adjusted opcode: 336 /// FMA231 #3, #2, #1 337 unsigned 338 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, 339 unsigned SrcOpIdx2, 340 const X86InstrFMA3Group &FMA3Group) const; 341 342 // Branch analysis. 343 bool isUnconditionalTailCall(const MachineInstr &MI) const override; 344 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond, 345 const MachineInstr &TailCall) const override; 346 void replaceBranchWithTailCall(MachineBasicBlock &MBB, 347 SmallVectorImpl<MachineOperand> &Cond, 348 const MachineInstr &TailCall) const override; 349 350 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 351 MachineBasicBlock *&FBB, 352 SmallVectorImpl<MachineOperand> &Cond, 353 bool AllowModify) const override; 354 355 int getJumpTableIndex(const MachineInstr &MI) const override; 356 357 std::optional<ExtAddrMode> 358 getAddrModeFromMemoryOp(const MachineInstr &MemI, 359 const TargetRegisterInfo *TRI) const override; 360 361 bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, 362 int64_t &ImmVal) const override; 363 364 bool preservesZeroValueInReg(const MachineInstr *MI, 365 const Register NullValueReg, 366 const TargetRegisterInfo *TRI) const override; 367 368 bool getMemOperandsWithOffsetWidth( 369 const MachineInstr &LdSt, 370 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, 371 bool &OffsetIsScalable, unsigned &Width, 372 const TargetRegisterInfo *TRI) const override; 373 bool analyzeBranchPredicate(MachineBasicBlock &MBB, 374 TargetInstrInfo::MachineBranchPredicate &MBP, 375 bool AllowModify = false) const override; 376 377 unsigned removeBranch(MachineBasicBlock &MBB, 378 int *BytesRemoved = nullptr) const override; 379 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 380 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 381 const DebugLoc &DL, 382 int *BytesAdded = nullptr) const override; 383 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 384 Register, Register, Register, int &, int &, 385 int &) const override; 386 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 387 const DebugLoc &DL, Register DstReg, 388 ArrayRef<MachineOperand> Cond, Register TrueReg, 389 Register FalseReg) const override; 390 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 391 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 392 bool KillSrc) const override; 393 void storeRegToStackSlot(MachineBasicBlock &MBB, 394 MachineBasicBlock::iterator MI, Register SrcReg, 395 bool isKill, int FrameIndex, 396 const TargetRegisterClass *RC, 397 const TargetRegisterInfo *TRI, 398 Register VReg) const override; 399 400 void loadRegFromStackSlot(MachineBasicBlock &MBB, 401 MachineBasicBlock::iterator MI, Register DestReg, 402 int FrameIndex, const TargetRegisterClass *RC, 403 const TargetRegisterInfo *TRI, 404 Register VReg) const override; 405 406 void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 407 unsigned Opc, Register Reg, int FrameIdx, 408 bool isKill = false) const; 409 410 bool expandPostRAPseudo(MachineInstr &MI) const override; 411 412 /// Check whether the target can fold a load that feeds a subreg operand 413 /// (or a subreg operand that feeds a store). 414 bool isSubregFoldable() const override { return true; } 415 416 /// foldMemoryOperand - If this target supports it, fold a load or store of 417 /// the specified stack slot into the specified machine instruction for the 418 /// specified operand(s). If this is possible, the target should perform the 419 /// folding and return true, otherwise it should return false. If it folds 420 /// the instruction, it is likely that the MachineInstruction the iterator 421 /// references has been changed. 422 MachineInstr * 423 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 424 ArrayRef<unsigned> Ops, 425 MachineBasicBlock::iterator InsertPt, int FrameIndex, 426 LiveIntervals *LIS = nullptr, 427 VirtRegMap *VRM = nullptr) const override; 428 429 /// foldMemoryOperand - Same as the previous version except it allows folding 430 /// of any load and store from / to any address, not just from a specific 431 /// stack slot. 432 MachineInstr *foldMemoryOperandImpl( 433 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 434 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, 435 LiveIntervals *LIS = nullptr) const override; 436 437 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 438 /// a store or a load and a store into two or more instruction. If this is 439 /// possible, returns true as well as the new instructions by reference. 440 bool 441 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, 442 bool UnfoldLoad, bool UnfoldStore, 443 SmallVectorImpl<MachineInstr *> &NewMIs) const override; 444 445 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 446 SmallVectorImpl<SDNode *> &NewNodes) const override; 447 448 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 449 /// instruction after load / store are unfolded from an instruction of the 450 /// specified opcode. It returns zero if the specified unfolding is not 451 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 452 /// index of the operand which will hold the register holding the loaded 453 /// value. 454 unsigned 455 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, 456 unsigned *LoadRegIndex = nullptr) const override; 457 458 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 459 /// to determine if two loads are loading from the same base address. It 460 /// should only return true if the base pointers are the same and the 461 /// only differences between the two addresses are the offset. It also returns 462 /// the offsets by reference. 463 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 464 int64_t &Offset2) const override; 465 466 /// isSchedulingBoundary - Overrides the isSchedulingBoundary from 467 /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR 468 /// intructions and prevent it from being re-scheduled. 469 bool isSchedulingBoundary(const MachineInstr &MI, 470 const MachineBasicBlock *MBB, 471 const MachineFunction &MF) const override; 472 473 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 474 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 475 /// should be scheduled togther. On some targets if two loads are loading from 476 /// addresses in the same cache line, it's better if they are scheduled 477 /// together. This function takes two integers that represent the load offsets 478 /// from the common base address. It returns true if it decides it's desirable 479 /// to schedule the two loads together. "NumLoads" is the number of loads that 480 /// have already been scheduled after Load1. 481 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, 482 int64_t Offset2, 483 unsigned NumLoads) const override; 484 485 void insertNoop(MachineBasicBlock &MBB, 486 MachineBasicBlock::iterator MI) const override; 487 488 MCInst getNop() const override; 489 490 bool 491 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 492 493 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 494 /// instruction that defines the specified register class. 495 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; 496 497 /// True if MI has a condition code def, e.g. EFLAGS, that is 498 /// not marked dead. 499 bool hasLiveCondCodeDef(MachineInstr &MI) const; 500 501 /// getGlobalBaseReg - Return a virtual register initialized with the 502 /// the global base register value. Output instructions required to 503 /// initialize the register in the function entry block, if necessary. 504 /// 505 unsigned getGlobalBaseReg(MachineFunction *MF) const; 506 507 std::pair<uint16_t, uint16_t> 508 getExecutionDomain(const MachineInstr &MI) const override; 509 510 uint16_t getExecutionDomainCustom(const MachineInstr &MI) const; 511 512 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override; 513 514 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const; 515 516 unsigned 517 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, 518 const TargetRegisterInfo *TRI) const override; 519 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, 520 const TargetRegisterInfo *TRI) const override; 521 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, 522 const TargetRegisterInfo *TRI) const override; 523 524 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 525 unsigned OpNum, 526 ArrayRef<MachineOperand> MOs, 527 MachineBasicBlock::iterator InsertPt, 528 unsigned Size, Align Alignment, 529 bool AllowCommute) const; 530 531 bool isHighLatencyDef(int opc) const override; 532 533 bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 534 const MachineRegisterInfo *MRI, 535 const MachineInstr &DefMI, unsigned DefIdx, 536 const MachineInstr &UseMI, 537 unsigned UseIdx) const override; 538 539 bool useMachineCombiner() const override { return true; } 540 541 bool isAssociativeAndCommutative(const MachineInstr &Inst, 542 bool Invert) const override; 543 544 bool hasReassociableOperands(const MachineInstr &Inst, 545 const MachineBasicBlock *MBB) const override; 546 547 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 548 MachineInstr &NewMI1, 549 MachineInstr &NewMI2) const override; 550 551 /// analyzeCompare - For a comparison instruction, return the source registers 552 /// in SrcReg and SrcReg2 if having two register operands, and the value it 553 /// compares against in CmpValue. Return true if the comparison instruction 554 /// can be analyzed. 555 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 556 Register &SrcReg2, int64_t &CmpMask, 557 int64_t &CmpValue) const override; 558 559 /// optimizeCompareInstr - Check if there exists an earlier instruction that 560 /// operates on the same source operands and sets flags in the same way as 561 /// Compare; remove Compare if possible. 562 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 563 Register SrcReg2, int64_t CmpMask, int64_t CmpValue, 564 const MachineRegisterInfo *MRI) const override; 565 566 /// optimizeLoadInstr - Try to remove the load by folding it to a register 567 /// operand at the use. We fold the load instructions if and only if the 568 /// def and use are in the same BB. We only look at one load and see 569 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 570 /// defined by the load we are trying to fold. DefMI returns the machine 571 /// instruction that defines FoldAsLoadDefReg, and the function returns 572 /// the machine instruction generated due to folding. 573 MachineInstr *optimizeLoadInstr(MachineInstr &MI, 574 const MachineRegisterInfo *MRI, 575 Register &FoldAsLoadDefReg, 576 MachineInstr *&DefMI) const override; 577 578 bool FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg, 579 int64_t ImmVal, MachineRegisterInfo *MRI, 580 bool MakeChange) const; 581 582 /// Reg is known to be defined by a move immediate instruction, try to fold 583 /// the immediate into the use instruction. 584 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 585 MachineRegisterInfo *MRI) const override; 586 587 std::pair<unsigned, unsigned> 588 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 589 590 ArrayRef<std::pair<unsigned, const char *>> 591 getSerializableDirectMachineOperandTargetFlags() const override; 592 593 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo( 594 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 595 596 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 597 bool OutlineFromLinkOnceODRs) const override; 598 599 outliner::InstrType 600 getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override; 601 602 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 603 const outliner::OutlinedFunction &OF) const override; 604 605 MachineBasicBlock::iterator 606 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 607 MachineBasicBlock::iterator &It, MachineFunction &MF, 608 outliner::Candidate &C) const override; 609 610 void buildClearRegister(Register Reg, MachineBasicBlock &MBB, 611 MachineBasicBlock::iterator Iter, DebugLoc &DL, 612 bool AllowSideEffects = true) const override; 613 614 bool verifyInstruction(const MachineInstr &MI, 615 StringRef &ErrInfo) const override; 616 #define GET_INSTRINFO_HELPER_DECLS 617 #include "X86GenInstrInfo.inc" 618 619 static bool hasLockPrefix(const MachineInstr &MI) { 620 return MI.getDesc().TSFlags & X86II::LOCK; 621 } 622 623 std::optional<ParamLoadedValue> 624 describeLoadedValue(const MachineInstr &MI, Register Reg) const override; 625 626 protected: 627 /// Commutes the operands in the given instruction by changing the operands 628 /// order and/or changing the instruction's opcode and/or the immediate value 629 /// operand. 630 /// 631 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands 632 /// to be commuted. 633 /// 634 /// Do not call this method for a non-commutable instruction or 635 /// non-commutable operands. 636 /// Even though the instruction is commutable, the method may still 637 /// fail to commute the operands, null pointer is returned in such cases. 638 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 639 unsigned CommuteOpIdx1, 640 unsigned CommuteOpIdx2) const override; 641 642 /// If the specific machine instruction is a instruction that moves/copies 643 /// value from one register to another register return destination and source 644 /// registers as machine operands. 645 std::optional<DestSourcePair> 646 isCopyInstrImpl(const MachineInstr &MI) const override; 647 648 /// Return true when there is potentially a faster code sequence for an 649 /// instruction chain ending in \p Root. All potential patterns are listed in 650 /// the \p Pattern vector. Pattern should be sorted in priority order since 651 /// the pattern evaluator stops checking as soon as it finds a faster 652 /// sequence. 653 bool 654 getMachineCombinerPatterns(MachineInstr &Root, 655 SmallVectorImpl<MachineCombinerPattern> &Patterns, 656 bool DoRegPressureReduce) const override; 657 658 /// When getMachineCombinerPatterns() finds potential patterns, 659 /// this function generates the instructions that could replace the 660 /// original code sequence. 661 void genAlternativeCodeSequence( 662 MachineInstr &Root, MachineCombinerPattern Pattern, 663 SmallVectorImpl<MachineInstr *> &InsInstrs, 664 SmallVectorImpl<MachineInstr *> &DelInstrs, 665 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 666 667 /// When calculate the latency of the root instruction, accumulate the 668 /// latency of the sequence to the root latency. 669 /// \param Root - Instruction that could be combined with one of its operands 670 /// For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd 671 /// is not in the critical path, so the root latency only include vpmaddwd. 672 bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override { 673 return false; 674 } 675 676 void getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops, 677 int FI) const override; 678 679 private: 680 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions. 681 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit 682 /// super-register and then truncating back down to a 8/16-bit sub-register. 683 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI, 684 LiveVariables *LV, 685 LiveIntervals *LIS, 686 bool Is8BitOp) const; 687 688 /// Handles memory folding for special case instructions, for instance those 689 /// requiring custom manipulation of the address. 690 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI, 691 unsigned OpNum, 692 ArrayRef<MachineOperand> MOs, 693 MachineBasicBlock::iterator InsertPt, 694 unsigned Size, Align Alignment) const; 695 696 /// isFrameOperand - Return true and the FrameIndex if the specified 697 /// operand and follow operands form a reference to the stack frame. 698 bool isFrameOperand(const MachineInstr &MI, unsigned int Op, 699 int &FrameIndex) const; 700 701 /// Returns true iff the routine could find two commutable operands in the 702 /// given machine instruction with 3 vector inputs. 703 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their 704 /// input values can be re-defined in this method only if the input values 705 /// are not pre-defined, which is designated by the special value 706 /// 'CommuteAnyOperandIndex' assigned to it. 707 /// If both of indices are pre-defined and refer to some operands, then the 708 /// method simply returns true if the corresponding operands are commutable 709 /// and returns false otherwise. 710 /// 711 /// For example, calling this method this way: 712 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 713 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2); 714 /// can be interpreted as a query asking to find an operand that would be 715 /// commutable with the operand#1. 716 /// 717 /// If IsIntrinsic is set, operand 1 will be ignored for commuting. 718 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI, 719 unsigned &SrcOpIdx1, 720 unsigned &SrcOpIdx2, 721 bool IsIntrinsic = false) const; 722 723 /// Returns true when instruction \p FlagI produces the same flags as \p OI. 724 /// The caller should pass in the results of calling analyzeCompare on \p OI: 725 /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue. 726 /// If the flags match \p OI as if it had the input operands swapped then the 727 /// function succeeds and sets \p IsSwapped to true. 728 /// 729 /// Examples of OI, FlagI pairs returning true: 730 /// CMP %1, 42 and CMP %1, 42 731 /// CMP %1, %2 and %3 = SUB %1, %2 732 /// TEST %1, %1 and %2 = SUB %1, 0 733 /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true 734 bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg, 735 Register SrcReg2, int64_t ImmMask, int64_t ImmValue, 736 const MachineInstr &OI, bool *IsSwapped, 737 int64_t *ImmDelta) const; 738 }; 739 740 } // namespace llvm 741 742 #endif 743