xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.h (revision 2f513db72b034fd5ef7f080b11be5c711c15186a)
1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "X86InstrFMA3Info.h"
18 #include "X86RegisterInfo.h"
19 #include "llvm/CodeGen/ISDOpcodes.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include <vector>
22 
23 #define GET_INSTRINFO_HEADER
24 #include "X86GenInstrInfo.inc"
25 
26 namespace llvm {
27 class MachineInstrBuilder;
28 class X86RegisterInfo;
29 class X86Subtarget;
30 
31 namespace X86 {
32 
33 enum AsmComments {
34   // For instr that was compressed from EVEX to VEX.
35   AC_EVEX_2_VEX = MachineInstr::TAsmComments
36 };
37 
38 /// Return a pair of condition code for the given predicate and whether
39 /// the instruction operands should be swaped to match the condition code.
40 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
41 
42 /// Return a setcc opcode based on whether it has a memory operand.
43 unsigned getSETOpc(bool HasMemoryOperand = false);
44 
45 /// Return a cmov opcode for the given register size in bytes, and operand type.
46 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
47 
48 // Turn jCC instruction into condition code.
49 CondCode getCondFromBranch(const MachineInstr &MI);
50 
51 // Turn setCC instruction into condition code.
52 CondCode getCondFromSETCC(const MachineInstr &MI);
53 
54 // Turn CMov instruction into condition code.
55 CondCode getCondFromCMov(const MachineInstr &MI);
56 
57 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
58 /// e.g. turning COND_E to COND_NE.
59 CondCode GetOppositeBranchCondition(CondCode CC);
60 
61 /// Get the VPCMP immediate for the given condition.
62 unsigned getVPCMPImmForCond(ISD::CondCode CC);
63 
64 /// Get the VPCMP immediate if the opcodes are swapped.
65 unsigned getSwappedVPCMPImm(unsigned Imm);
66 
67 /// Get the VPCOM immediate if the opcodes are swapped.
68 unsigned getSwappedVPCOMImm(unsigned Imm);
69 
70 } // namespace X86
71 
72 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
73 /// a reference to a stub for a global, not the global itself.
74 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
75   switch (TargetFlag) {
76   case X86II::MO_DLLIMPORT:               // dllimport stub.
77   case X86II::MO_GOTPCREL:                // rip-relative GOT reference.
78   case X86II::MO_GOT:                     // normal GOT reference.
79   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
80   case X86II::MO_DARWIN_NONLAZY:          // Normal $non_lazy_ptr ref.
81   case X86II::MO_COFFSTUB:                // COFF .refptr stub.
82     return true;
83   default:
84     return false;
85   }
86 }
87 
88 /// isGlobalRelativeToPICBase - Return true if the specified global value
89 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg).  If this
90 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
91 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
92   switch (TargetFlag) {
93   case X86II::MO_GOTOFF:                  // isPICStyleGOT: local global.
94   case X86II::MO_GOT:                     // isPICStyleGOT: other global.
95   case X86II::MO_PIC_BASE_OFFSET:         // Darwin local global.
96   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
97   case X86II::MO_TLVP:                    // ??? Pretty sure..
98     return true;
99   default:
100     return false;
101   }
102 }
103 
104 inline static bool isScale(const MachineOperand &MO) {
105   return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
106                         MO.getImm() == 4 || MO.getImm() == 8);
107 }
108 
109 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
110   if (MI.getOperand(Op).isFI())
111     return true;
112   return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
113          MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
114          isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
115          MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
116          (MI.getOperand(Op + X86::AddrDisp).isImm() ||
117           MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
118           MI.getOperand(Op + X86::AddrDisp).isCPI() ||
119           MI.getOperand(Op + X86::AddrDisp).isJTI());
120 }
121 
122 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
123   if (MI.getOperand(Op).isFI())
124     return true;
125   return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
126          MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
127 }
128 
129 class X86InstrInfo final : public X86GenInstrInfo {
130   X86Subtarget &Subtarget;
131   const X86RegisterInfo RI;
132 
133   virtual void anchor();
134 
135   bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
136                          MachineBasicBlock *&FBB,
137                          SmallVectorImpl<MachineOperand> &Cond,
138                          SmallVectorImpl<MachineInstr *> &CondBranches,
139                          bool AllowModify) const;
140 
141 public:
142   explicit X86InstrInfo(X86Subtarget &STI);
143 
144   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
145   /// such, whenever a client has an instance of instruction info, it should
146   /// always be able to get register info as well (through this method).
147   ///
148   const X86RegisterInfo &getRegisterInfo() const { return RI; }
149 
150   /// Returns the stack pointer adjustment that happens inside the frame
151   /// setup..destroy sequence (e.g. by pushes, or inside the callee).
152   int64_t getFrameAdjustment(const MachineInstr &I) const {
153     assert(isFrameInstr(I));
154     if (isFrameSetup(I))
155       return I.getOperand(2).getImm();
156     return I.getOperand(1).getImm();
157   }
158 
159   /// Sets the stack pointer adjustment made inside the frame made up by this
160   /// instruction.
161   void setFrameAdjustment(MachineInstr &I, int64_t V) const {
162     assert(isFrameInstr(I));
163     if (isFrameSetup(I))
164       I.getOperand(2).setImm(V);
165     else
166       I.getOperand(1).setImm(V);
167   }
168 
169   /// getSPAdjust - This returns the stack pointer adjustment made by
170   /// this instruction. For x86, we need to handle more complex call
171   /// sequences involving PUSHes.
172   int getSPAdjust(const MachineInstr &MI) const override;
173 
174   /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
175   /// extension instruction. That is, it's like a copy where it's legal for the
176   /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
177   /// true, then it's expected the pre-extension value is available as a subreg
178   /// of the result register. This also returns the sub-register index in
179   /// SubIdx.
180   bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
181                              unsigned &DstReg, unsigned &SubIdx) const override;
182 
183   unsigned isLoadFromStackSlot(const MachineInstr &MI,
184                                int &FrameIndex) const override;
185   unsigned isLoadFromStackSlot(const MachineInstr &MI,
186                                int &FrameIndex,
187                                unsigned &MemBytes) const override;
188   /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
189   /// stack locations as well.  This uses a heuristic so it isn't
190   /// reliable for correctness.
191   unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
192                                      int &FrameIndex) const override;
193 
194   unsigned isStoreToStackSlot(const MachineInstr &MI,
195                               int &FrameIndex) const override;
196   unsigned isStoreToStackSlot(const MachineInstr &MI,
197                               int &FrameIndex,
198                               unsigned &MemBytes) const override;
199   /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
200   /// stack locations as well.  This uses a heuristic so it isn't
201   /// reliable for correctness.
202   unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
203                                     int &FrameIndex) const override;
204 
205   bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
206                                          AliasAnalysis *AA) const override;
207   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
208                      unsigned DestReg, unsigned SubIdx,
209                      const MachineInstr &Orig,
210                      const TargetRegisterInfo &TRI) const override;
211 
212   /// Given an operand within a MachineInstr, insert preceding code to put it
213   /// into the right format for a particular kind of LEA instruction. This may
214   /// involve using an appropriate super-register instead (with an implicit use
215   /// of the original) or creating a new virtual register and inserting COPY
216   /// instructions to get the data into the right class.
217   ///
218   /// Reference parameters are set to indicate how caller should add this
219   /// operand to the LEA instruction.
220   bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
221                       unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
222                       bool &isKill, MachineOperand &ImplicitOp,
223                       LiveVariables *LV) const;
224 
225   /// convertToThreeAddress - This method must be implemented by targets that
226   /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
227   /// may be able to convert a two-address instruction into a true
228   /// three-address instruction on demand.  This allows the X86 target (for
229   /// example) to convert ADD and SHL instructions into LEA instructions if they
230   /// would require register copies due to two-addressness.
231   ///
232   /// This method returns a null pointer if the transformation cannot be
233   /// performed, otherwise it returns the new instruction.
234   ///
235   MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
236                                       MachineInstr &MI,
237                                       LiveVariables *LV) const override;
238 
239   /// Returns true iff the routine could find two commutable operands in the
240   /// given machine instruction.
241   /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
242   /// input values can be re-defined in this method only if the input values
243   /// are not pre-defined, which is designated by the special value
244   /// 'CommuteAnyOperandIndex' assigned to it.
245   /// If both of indices are pre-defined and refer to some operands, then the
246   /// method simply returns true if the corresponding operands are commutable
247   /// and returns false otherwise.
248   ///
249   /// For example, calling this method this way:
250   ///     unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
251   ///     findCommutedOpIndices(MI, Op1, Op2);
252   /// can be interpreted as a query asking to find an operand that would be
253   /// commutable with the operand#1.
254   bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
255                              unsigned &SrcOpIdx2) const override;
256 
257   /// Returns an adjusted FMA opcode that must be used in FMA instruction that
258   /// performs the same computations as the given \p MI but which has the
259   /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
260   /// It may return 0 if it is unsafe to commute the operands.
261   /// Note that a machine instruction (instead of its opcode) is passed as the
262   /// first parameter to make it possible to analyze the instruction's uses and
263   /// commute the first operand of FMA even when it seems unsafe when you look
264   /// at the opcode. For example, it is Ok to commute the first operand of
265   /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
266   ///
267   /// The returned FMA opcode may differ from the opcode in the given \p MI.
268   /// For example, commuting the operands #1 and #3 in the following FMA
269   ///     FMA213 #1, #2, #3
270   /// results into instruction with adjusted opcode:
271   ///     FMA231 #3, #2, #1
272   unsigned
273   getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
274                                  unsigned SrcOpIdx2,
275                                  const X86InstrFMA3Group &FMA3Group) const;
276 
277   // Branch analysis.
278   bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
279   bool isUnconditionalTailCall(const MachineInstr &MI) const override;
280   bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
281                                   const MachineInstr &TailCall) const override;
282   void replaceBranchWithTailCall(MachineBasicBlock &MBB,
283                                  SmallVectorImpl<MachineOperand> &Cond,
284                                  const MachineInstr &TailCall) const override;
285 
286   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
287                      MachineBasicBlock *&FBB,
288                      SmallVectorImpl<MachineOperand> &Cond,
289                      bool AllowModify) const override;
290 
291   bool getMemOperandWithOffset(const MachineInstr &LdSt,
292                                const MachineOperand *&BaseOp,
293                                int64_t &Offset,
294                                const TargetRegisterInfo *TRI) const override;
295   bool analyzeBranchPredicate(MachineBasicBlock &MBB,
296                               TargetInstrInfo::MachineBranchPredicate &MBP,
297                               bool AllowModify = false) const override;
298 
299   unsigned removeBranch(MachineBasicBlock &MBB,
300                         int *BytesRemoved = nullptr) const override;
301   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
302                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
303                         const DebugLoc &DL,
304                         int *BytesAdded = nullptr) const override;
305   bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
306                        unsigned, unsigned, int &, int &, int &) const override;
307   void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
308                     const DebugLoc &DL, unsigned DstReg,
309                     ArrayRef<MachineOperand> Cond, unsigned TrueReg,
310                     unsigned FalseReg) const override;
311   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
312                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
313                    bool KillSrc) const override;
314   void storeRegToStackSlot(MachineBasicBlock &MBB,
315                            MachineBasicBlock::iterator MI, unsigned SrcReg,
316                            bool isKill, int FrameIndex,
317                            const TargetRegisterClass *RC,
318                            const TargetRegisterInfo *TRI) const override;
319 
320   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
321                       SmallVectorImpl<MachineOperand> &Addr,
322                       const TargetRegisterClass *RC,
323                       ArrayRef<MachineMemOperand *> MMOs,
324                       SmallVectorImpl<MachineInstr *> &NewMIs) const;
325 
326   void loadRegFromStackSlot(MachineBasicBlock &MBB,
327                             MachineBasicBlock::iterator MI, unsigned DestReg,
328                             int FrameIndex, const TargetRegisterClass *RC,
329                             const TargetRegisterInfo *TRI) const override;
330 
331   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
332                        SmallVectorImpl<MachineOperand> &Addr,
333                        const TargetRegisterClass *RC,
334                        ArrayRef<MachineMemOperand *> MMOs,
335                        SmallVectorImpl<MachineInstr *> &NewMIs) const;
336 
337   bool expandPostRAPseudo(MachineInstr &MI) const override;
338 
339   /// Check whether the target can fold a load that feeds a subreg operand
340   /// (or a subreg operand that feeds a store).
341   bool isSubregFoldable() const override { return true; }
342 
343   /// foldMemoryOperand - If this target supports it, fold a load or store of
344   /// the specified stack slot into the specified machine instruction for the
345   /// specified operand(s).  If this is possible, the target should perform the
346   /// folding and return true, otherwise it should return false.  If it folds
347   /// the instruction, it is likely that the MachineInstruction the iterator
348   /// references has been changed.
349   MachineInstr *
350   foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
351                         ArrayRef<unsigned> Ops,
352                         MachineBasicBlock::iterator InsertPt, int FrameIndex,
353                         LiveIntervals *LIS = nullptr,
354                         VirtRegMap *VRM = nullptr) const override;
355 
356   /// foldMemoryOperand - Same as the previous version except it allows folding
357   /// of any load and store from / to any address, not just from a specific
358   /// stack slot.
359   MachineInstr *foldMemoryOperandImpl(
360       MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
361       MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
362       LiveIntervals *LIS = nullptr) const override;
363 
364   /// unfoldMemoryOperand - Separate a single instruction which folded a load or
365   /// a store or a load and a store into two or more instruction. If this is
366   /// possible, returns true as well as the new instructions by reference.
367   bool
368   unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
369                       bool UnfoldLoad, bool UnfoldStore,
370                       SmallVectorImpl<MachineInstr *> &NewMIs) const override;
371 
372   bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
373                            SmallVectorImpl<SDNode *> &NewNodes) const override;
374 
375   /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
376   /// instruction after load / store are unfolded from an instruction of the
377   /// specified opcode. It returns zero if the specified unfolding is not
378   /// possible. If LoadRegIndex is non-null, it is filled in with the operand
379   /// index of the operand which will hold the register holding the loaded
380   /// value.
381   unsigned
382   getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
383                              unsigned *LoadRegIndex = nullptr) const override;
384 
385   /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
386   /// to determine if two loads are loading from the same base address. It
387   /// should only return true if the base pointers are the same and the
388   /// only differences between the two addresses are the offset. It also returns
389   /// the offsets by reference.
390   bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
391                                int64_t &Offset2) const override;
392 
393   /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
394   /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
395   /// should be scheduled togther. On some targets if two loads are loading from
396   /// addresses in the same cache line, it's better if they are scheduled
397   /// together. This function takes two integers that represent the load offsets
398   /// from the common base address. It returns true if it decides it's desirable
399   /// to schedule the two loads together. "NumLoads" is the number of loads that
400   /// have already been scheduled after Load1.
401   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
402                                int64_t Offset2,
403                                unsigned NumLoads) const override;
404 
405   void getNoop(MCInst &NopInst) const override;
406 
407   bool
408   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
409 
410   /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
411   /// instruction that defines the specified register class.
412   bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
413 
414   /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
415   /// would clobber the EFLAGS condition register. Note the result may be
416   /// conservative. If it cannot definitely determine the safety after visiting
417   /// a few instructions in each direction it assumes it's not safe.
418   bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
419                              MachineBasicBlock::iterator I) const {
420     return MBB.computeRegisterLiveness(&RI, X86::EFLAGS, I, 4) ==
421            MachineBasicBlock::LQR_Dead;
422   }
423 
424   /// True if MI has a condition code def, e.g. EFLAGS, that is
425   /// not marked dead.
426   bool hasLiveCondCodeDef(MachineInstr &MI) const;
427 
428   /// getGlobalBaseReg - Return a virtual register initialized with the
429   /// the global base register value. Output instructions required to
430   /// initialize the register in the function entry block, if necessary.
431   ///
432   unsigned getGlobalBaseReg(MachineFunction *MF) const;
433 
434   std::pair<uint16_t, uint16_t>
435   getExecutionDomain(const MachineInstr &MI) const override;
436 
437   uint16_t getExecutionDomainCustom(const MachineInstr &MI) const;
438 
439   void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
440 
441   bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
442 
443   unsigned
444   getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
445                                const TargetRegisterInfo *TRI) const override;
446   unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
447                                 const TargetRegisterInfo *TRI) const override;
448   void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
449                                  const TargetRegisterInfo *TRI) const override;
450 
451   MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
452                                       unsigned OpNum,
453                                       ArrayRef<MachineOperand> MOs,
454                                       MachineBasicBlock::iterator InsertPt,
455                                       unsigned Size, unsigned Alignment,
456                                       bool AllowCommute) const;
457 
458   bool isHighLatencyDef(int opc) const override;
459 
460   bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
461                              const MachineRegisterInfo *MRI,
462                              const MachineInstr &DefMI, unsigned DefIdx,
463                              const MachineInstr &UseMI,
464                              unsigned UseIdx) const override;
465 
466   bool useMachineCombiner() const override { return true; }
467 
468   bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
469 
470   bool hasReassociableOperands(const MachineInstr &Inst,
471                                const MachineBasicBlock *MBB) const override;
472 
473   void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
474                              MachineInstr &NewMI1,
475                              MachineInstr &NewMI2) const override;
476 
477   /// analyzeCompare - For a comparison instruction, return the source registers
478   /// in SrcReg and SrcReg2 if having two register operands, and the value it
479   /// compares against in CmpValue. Return true if the comparison instruction
480   /// can be analyzed.
481   bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
482                       unsigned &SrcReg2, int &CmpMask,
483                       int &CmpValue) const override;
484 
485   /// optimizeCompareInstr - Check if there exists an earlier instruction that
486   /// operates on the same source operands and sets flags in the same way as
487   /// Compare; remove Compare if possible.
488   bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
489                             unsigned SrcReg2, int CmpMask, int CmpValue,
490                             const MachineRegisterInfo *MRI) const override;
491 
492   /// optimizeLoadInstr - Try to remove the load by folding it to a register
493   /// operand at the use. We fold the load instructions if and only if the
494   /// def and use are in the same BB. We only look at one load and see
495   /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
496   /// defined by the load we are trying to fold. DefMI returns the machine
497   /// instruction that defines FoldAsLoadDefReg, and the function returns
498   /// the machine instruction generated due to folding.
499   MachineInstr *optimizeLoadInstr(MachineInstr &MI,
500                                   const MachineRegisterInfo *MRI,
501                                   unsigned &FoldAsLoadDefReg,
502                                   MachineInstr *&DefMI) const override;
503 
504   std::pair<unsigned, unsigned>
505   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
506 
507   ArrayRef<std::pair<unsigned, const char *>>
508   getSerializableDirectMachineOperandTargetFlags() const override;
509 
510   virtual outliner::OutlinedFunction getOutliningCandidateInfo(
511       std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
512 
513   bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
514                                    bool OutlineFromLinkOnceODRs) const override;
515 
516   outliner::InstrType
517   getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
518 
519   void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
520                           const outliner::OutlinedFunction &OF) const override;
521 
522   MachineBasicBlock::iterator
523   insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
524                      MachineBasicBlock::iterator &It, MachineFunction &MF,
525                      const outliner::Candidate &C) const override;
526 
527 #define GET_INSTRINFO_HELPER_DECLS
528 #include "X86GenInstrInfo.inc"
529 
530 protected:
531   /// Commutes the operands in the given instruction by changing the operands
532   /// order and/or changing the instruction's opcode and/or the immediate value
533   /// operand.
534   ///
535   /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
536   /// to be commuted.
537   ///
538   /// Do not call this method for a non-commutable instruction or
539   /// non-commutable operands.
540   /// Even though the instruction is commutable, the method may still
541   /// fail to commute the operands, null pointer is returned in such cases.
542   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
543                                        unsigned CommuteOpIdx1,
544                                        unsigned CommuteOpIdx2) const override;
545 
546   /// If the specific machine instruction is a instruction that moves/copies
547   /// value from one register to another register return true along with
548   /// @Source machine operand and @Destination machine operand.
549   bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
550                        const MachineOperand *&Destination) const override;
551 
552 private:
553   /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
554   /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
555   /// super-register and then truncating back down to a 8/16-bit sub-register.
556   MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
557                                              MachineFunction::iterator &MFI,
558                                              MachineInstr &MI,
559                                              LiveVariables *LV,
560                                              bool Is8BitOp) const;
561 
562   /// Handles memory folding for special case instructions, for instance those
563   /// requiring custom manipulation of the address.
564   MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
565                                         unsigned OpNum,
566                                         ArrayRef<MachineOperand> MOs,
567                                         MachineBasicBlock::iterator InsertPt,
568                                         unsigned Size, unsigned Align) const;
569 
570   /// isFrameOperand - Return true and the FrameIndex if the specified
571   /// operand and follow operands form a reference to the stack frame.
572   bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
573                       int &FrameIndex) const;
574 
575   /// Returns true iff the routine could find two commutable operands in the
576   /// given machine instruction with 3 vector inputs.
577   /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
578   /// input values can be re-defined in this method only if the input values
579   /// are not pre-defined, which is designated by the special value
580   /// 'CommuteAnyOperandIndex' assigned to it.
581   /// If both of indices are pre-defined and refer to some operands, then the
582   /// method simply returns true if the corresponding operands are commutable
583   /// and returns false otherwise.
584   ///
585   /// For example, calling this method this way:
586   ///     unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
587   ///     findThreeSrcCommutedOpIndices(MI, Op1, Op2);
588   /// can be interpreted as a query asking to find an operand that would be
589   /// commutable with the operand#1.
590   ///
591   /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
592   bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
593                                      unsigned &SrcOpIdx1,
594                                      unsigned &SrcOpIdx2,
595                                      bool IsIntrinsic = false) const;
596 };
597 
598 } // namespace llvm
599 
600 #endif
601