1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the X86 implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H 14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H 15 16 #include "MCTargetDesc/X86BaseInfo.h" 17 #include "X86InstrFMA3Info.h" 18 #include "X86RegisterInfo.h" 19 #include "llvm/CodeGen/ISDOpcodes.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 #include <vector> 22 23 #define GET_INSTRINFO_HEADER 24 #include "X86GenInstrInfo.inc" 25 26 namespace llvm { 27 class X86Subtarget; 28 29 namespace X86 { 30 31 enum AsmComments { 32 // For instr that was compressed from EVEX to LEGACY. 33 AC_EVEX_2_LEGACY = MachineInstr::TAsmComments, 34 // For instr that was compressed from EVEX to VEX. 35 AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1 36 }; 37 38 /// Return a pair of condition code for the given predicate and whether 39 /// the instruction operands should be swaped to match the condition code. 40 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate); 41 42 /// Return a cmov opcode for the given register size in bytes, and operand type. 43 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false); 44 45 /// Return the source operand # for condition code by \p MCID. If the 46 /// instruction doesn't have a condition code, return -1. 47 int getCondSrcNoFromDesc(const MCInstrDesc &MCID); 48 49 /// Return the condition code of the instruction. If the instruction doesn't 50 /// have a condition code, return X86::COND_INVALID. 51 CondCode getCondFromMI(const MachineInstr &MI); 52 53 // Turn JCC instruction into condition code. 54 CondCode getCondFromBranch(const MachineInstr &MI); 55 56 // Turn SETCC instruction into condition code. 57 CondCode getCondFromSETCC(const MachineInstr &MI); 58 59 // Turn CMOV instruction into condition code. 60 CondCode getCondFromCMov(const MachineInstr &MI); 61 62 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 63 /// e.g. turning COND_E to COND_NE. 64 CondCode GetOppositeBranchCondition(CondCode CC); 65 66 /// Get the VPCMP immediate for the given condition. 67 unsigned getVPCMPImmForCond(ISD::CondCode CC); 68 69 /// Get the VPCMP immediate if the opcodes are swapped. 70 unsigned getSwappedVPCMPImm(unsigned Imm); 71 72 /// Get the VPCOM immediate if the opcodes are swapped. 73 unsigned getSwappedVPCOMImm(unsigned Imm); 74 75 /// Get the VCMP immediate if the opcodes are swapped. 76 unsigned getSwappedVCMPImm(unsigned Imm); 77 78 /// Check if the instruction is X87 instruction. 79 bool isX87Instruction(MachineInstr &MI); 80 } // namespace X86 81 82 /// isGlobalStubReference - Return true if the specified TargetFlag operand is 83 /// a reference to a stub for a global, not the global itself. 84 inline static bool isGlobalStubReference(unsigned char TargetFlag) { 85 switch (TargetFlag) { 86 case X86II::MO_DLLIMPORT: // dllimport stub. 87 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 88 case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference. 89 case X86II::MO_GOT: // normal GOT reference. 90 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 91 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 92 case X86II::MO_COFFSTUB: // COFF .refptr stub. 93 return true; 94 default: 95 return false; 96 } 97 } 98 99 /// isGlobalRelativeToPICBase - Return true if the specified global value 100 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 101 /// is true, the addressing mode has the PIC base register added in (e.g. EBX). 102 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 103 switch (TargetFlag) { 104 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 105 case X86II::MO_GOT: // isPICStyleGOT: other global. 106 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 107 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 108 case X86II::MO_TLVP: // ??? Pretty sure.. 109 return true; 110 default: 111 return false; 112 } 113 } 114 115 inline static bool isScale(const MachineOperand &MO) { 116 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 || 117 MO.getImm() == 4 || MO.getImm() == 8); 118 } 119 120 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { 121 if (MI.getOperand(Op).isFI()) 122 return true; 123 return Op + X86::AddrSegmentReg <= MI.getNumOperands() && 124 MI.getOperand(Op + X86::AddrBaseReg).isReg() && 125 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) && 126 MI.getOperand(Op + X86::AddrIndexReg).isReg() && 127 (MI.getOperand(Op + X86::AddrDisp).isImm() || 128 MI.getOperand(Op + X86::AddrDisp).isGlobal() || 129 MI.getOperand(Op + X86::AddrDisp).isCPI() || 130 MI.getOperand(Op + X86::AddrDisp).isJTI()); 131 } 132 133 inline static bool isMem(const MachineInstr &MI, unsigned Op) { 134 if (MI.getOperand(Op).isFI()) 135 return true; 136 return Op + X86::AddrNumOperands <= MI.getNumOperands() && 137 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op); 138 } 139 140 class X86InstrInfo final : public X86GenInstrInfo { 141 X86Subtarget &Subtarget; 142 const X86RegisterInfo RI; 143 144 virtual void anchor(); 145 146 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 147 MachineBasicBlock *&FBB, 148 SmallVectorImpl<MachineOperand> &Cond, 149 SmallVectorImpl<MachineInstr *> &CondBranches, 150 bool AllowModify) const; 151 152 public: 153 explicit X86InstrInfo(X86Subtarget &STI); 154 155 /// Given a machine instruction descriptor, returns the register 156 /// class constraint for OpNum, or NULL. Returned register class 157 /// may be different from the definition in the TD file, e.g. 158 /// GR*RegClass (definition in TD file) 159 /// -> 160 /// GR*_NOREX2RegClass (Returned register class) 161 const TargetRegisterClass * 162 getRegClass(const MCInstrDesc &MCID, unsigned OpNum, 163 const TargetRegisterInfo *TRI, 164 const MachineFunction &MF) const override; 165 166 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 167 /// such, whenever a client has an instance of instruction info, it should 168 /// always be able to get register info as well (through this method). 169 /// 170 const X86RegisterInfo &getRegisterInfo() const { return RI; } 171 172 /// Returns the stack pointer adjustment that happens inside the frame 173 /// setup..destroy sequence (e.g. by pushes, or inside the callee). 174 int64_t getFrameAdjustment(const MachineInstr &I) const { 175 assert(isFrameInstr(I)); 176 if (isFrameSetup(I)) 177 return I.getOperand(2).getImm(); 178 return I.getOperand(1).getImm(); 179 } 180 181 /// Sets the stack pointer adjustment made inside the frame made up by this 182 /// instruction. 183 void setFrameAdjustment(MachineInstr &I, int64_t V) const { 184 assert(isFrameInstr(I)); 185 if (isFrameSetup(I)) 186 I.getOperand(2).setImm(V); 187 else 188 I.getOperand(1).setImm(V); 189 } 190 191 /// getSPAdjust - This returns the stack pointer adjustment made by 192 /// this instruction. For x86, we need to handle more complex call 193 /// sequences involving PUSHes. 194 int getSPAdjust(const MachineInstr &MI) const override; 195 196 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 197 /// extension instruction. That is, it's like a copy where it's legal for the 198 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 199 /// true, then it's expected the pre-extension value is available as a subreg 200 /// of the result register. This also returns the sub-register index in 201 /// SubIdx. 202 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, 203 Register &DstReg, unsigned &SubIdx) const override; 204 205 /// Returns true if the instruction has no behavior (specified or otherwise) 206 /// that is based on the value of any of its register operands 207 /// 208 /// Instructions are considered data invariant even if they set EFLAGS. 209 /// 210 /// A classical example of something that is inherently not data invariant is 211 /// an indirect jump -- the destination is loaded into icache based on the 212 /// bits set in the jump destination register. 213 /// 214 /// FIXME: This should become part of our instruction tables. 215 static bool isDataInvariant(MachineInstr &MI); 216 217 /// Returns true if the instruction has no behavior (specified or otherwise) 218 /// that is based on the value loaded from memory or the value of any 219 /// non-address register operands. 220 /// 221 /// For example, if the latency of the instruction is dependent on the 222 /// particular bits set in any of the registers *or* any of the bits loaded 223 /// from memory. 224 /// 225 /// Instructions are considered data invariant even if they set EFLAGS. 226 /// 227 /// A classical example of something that is inherently not data invariant is 228 /// an indirect jump -- the destination is loaded into icache based on the 229 /// bits set in the jump destination register. 230 /// 231 /// FIXME: This should become part of our instruction tables. 232 static bool isDataInvariantLoad(MachineInstr &MI); 233 234 unsigned isLoadFromStackSlot(const MachineInstr &MI, 235 int &FrameIndex) const override; 236 unsigned isLoadFromStackSlot(const MachineInstr &MI, 237 int &FrameIndex, 238 unsigned &MemBytes) const override; 239 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 240 /// stack locations as well. This uses a heuristic so it isn't 241 /// reliable for correctness. 242 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 243 int &FrameIndex) const override; 244 245 unsigned isStoreToStackSlot(const MachineInstr &MI, 246 int &FrameIndex) const override; 247 unsigned isStoreToStackSlot(const MachineInstr &MI, 248 int &FrameIndex, 249 unsigned &MemBytes) const override; 250 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 251 /// stack locations as well. This uses a heuristic so it isn't 252 /// reliable for correctness. 253 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 254 int &FrameIndex) const override; 255 256 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override; 257 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 258 Register DestReg, unsigned SubIdx, 259 const MachineInstr &Orig, 260 const TargetRegisterInfo &TRI) const override; 261 262 /// Given an operand within a MachineInstr, insert preceding code to put it 263 /// into the right format for a particular kind of LEA instruction. This may 264 /// involve using an appropriate super-register instead (with an implicit use 265 /// of the original) or creating a new virtual register and inserting COPY 266 /// instructions to get the data into the right class. 267 /// 268 /// Reference parameters are set to indicate how caller should add this 269 /// operand to the LEA instruction. 270 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, 271 unsigned LEAOpcode, bool AllowSP, Register &NewSrc, 272 bool &isKill, MachineOperand &ImplicitOp, 273 LiveVariables *LV, LiveIntervals *LIS) const; 274 275 /// convertToThreeAddress - This method must be implemented by targets that 276 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 277 /// may be able to convert a two-address instruction into a true 278 /// three-address instruction on demand. This allows the X86 target (for 279 /// example) to convert ADD and SHL instructions into LEA instructions if they 280 /// would require register copies due to two-addressness. 281 /// 282 /// This method returns a null pointer if the transformation cannot be 283 /// performed, otherwise it returns the new instruction. 284 /// 285 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, 286 LiveIntervals *LIS) const override; 287 288 /// Returns true iff the routine could find two commutable operands in the 289 /// given machine instruction. 290 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their 291 /// input values can be re-defined in this method only if the input values 292 /// are not pre-defined, which is designated by the special value 293 /// 'CommuteAnyOperandIndex' assigned to it. 294 /// If both of indices are pre-defined and refer to some operands, then the 295 /// method simply returns true if the corresponding operands are commutable 296 /// and returns false otherwise. 297 /// 298 /// For example, calling this method this way: 299 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 300 /// findCommutedOpIndices(MI, Op1, Op2); 301 /// can be interpreted as a query asking to find an operand that would be 302 /// commutable with the operand#1. 303 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 304 unsigned &SrcOpIdx2) const override; 305 306 /// Returns true if we have preference on the operands order in MI, the 307 /// commute decision is returned in Commute. 308 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override; 309 310 /// Returns an adjusted FMA opcode that must be used in FMA instruction that 311 /// performs the same computations as the given \p MI but which has the 312 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted. 313 /// It may return 0 if it is unsafe to commute the operands. 314 /// Note that a machine instruction (instead of its opcode) is passed as the 315 /// first parameter to make it possible to analyze the instruction's uses and 316 /// commute the first operand of FMA even when it seems unsafe when you look 317 /// at the opcode. For example, it is Ok to commute the first operand of 318 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used. 319 /// 320 /// The returned FMA opcode may differ from the opcode in the given \p MI. 321 /// For example, commuting the operands #1 and #3 in the following FMA 322 /// FMA213 #1, #2, #3 323 /// results into instruction with adjusted opcode: 324 /// FMA231 #3, #2, #1 325 unsigned 326 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, 327 unsigned SrcOpIdx2, 328 const X86InstrFMA3Group &FMA3Group) const; 329 330 // Branch analysis. 331 bool isUnconditionalTailCall(const MachineInstr &MI) const override; 332 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond, 333 const MachineInstr &TailCall) const override; 334 void replaceBranchWithTailCall(MachineBasicBlock &MBB, 335 SmallVectorImpl<MachineOperand> &Cond, 336 const MachineInstr &TailCall) const override; 337 338 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 339 MachineBasicBlock *&FBB, 340 SmallVectorImpl<MachineOperand> &Cond, 341 bool AllowModify) const override; 342 343 int getJumpTableIndex(const MachineInstr &MI) const override; 344 345 std::optional<ExtAddrMode> 346 getAddrModeFromMemoryOp(const MachineInstr &MemI, 347 const TargetRegisterInfo *TRI) const override; 348 349 bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, 350 int64_t &ImmVal) const override; 351 352 bool preservesZeroValueInReg(const MachineInstr *MI, 353 const Register NullValueReg, 354 const TargetRegisterInfo *TRI) const override; 355 356 bool getMemOperandsWithOffsetWidth( 357 const MachineInstr &LdSt, 358 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, 359 bool &OffsetIsScalable, unsigned &Width, 360 const TargetRegisterInfo *TRI) const override; 361 bool analyzeBranchPredicate(MachineBasicBlock &MBB, 362 TargetInstrInfo::MachineBranchPredicate &MBP, 363 bool AllowModify = false) const override; 364 365 unsigned removeBranch(MachineBasicBlock &MBB, 366 int *BytesRemoved = nullptr) const override; 367 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 368 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 369 const DebugLoc &DL, 370 int *BytesAdded = nullptr) const override; 371 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 372 Register, Register, Register, int &, int &, 373 int &) const override; 374 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 375 const DebugLoc &DL, Register DstReg, 376 ArrayRef<MachineOperand> Cond, Register TrueReg, 377 Register FalseReg) const override; 378 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 379 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 380 bool KillSrc) const override; 381 void storeRegToStackSlot(MachineBasicBlock &MBB, 382 MachineBasicBlock::iterator MI, Register SrcReg, 383 bool isKill, int FrameIndex, 384 const TargetRegisterClass *RC, 385 const TargetRegisterInfo *TRI, 386 Register VReg) const override; 387 388 void loadRegFromStackSlot(MachineBasicBlock &MBB, 389 MachineBasicBlock::iterator MI, Register DestReg, 390 int FrameIndex, const TargetRegisterClass *RC, 391 const TargetRegisterInfo *TRI, 392 Register VReg) const override; 393 394 void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 395 unsigned Opc, Register Reg, int FrameIdx, 396 bool isKill = false) const; 397 398 bool expandPostRAPseudo(MachineInstr &MI) const override; 399 400 /// Check whether the target can fold a load that feeds a subreg operand 401 /// (or a subreg operand that feeds a store). 402 bool isSubregFoldable() const override { return true; } 403 404 /// foldMemoryOperand - If this target supports it, fold a load or store of 405 /// the specified stack slot into the specified machine instruction for the 406 /// specified operand(s). If this is possible, the target should perform the 407 /// folding and return true, otherwise it should return false. If it folds 408 /// the instruction, it is likely that the MachineInstruction the iterator 409 /// references has been changed. 410 MachineInstr * 411 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 412 ArrayRef<unsigned> Ops, 413 MachineBasicBlock::iterator InsertPt, int FrameIndex, 414 LiveIntervals *LIS = nullptr, 415 VirtRegMap *VRM = nullptr) const override; 416 417 /// foldMemoryOperand - Same as the previous version except it allows folding 418 /// of any load and store from / to any address, not just from a specific 419 /// stack slot. 420 MachineInstr *foldMemoryOperandImpl( 421 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 422 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, 423 LiveIntervals *LIS = nullptr) const override; 424 425 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 426 /// a store or a load and a store into two or more instruction. If this is 427 /// possible, returns true as well as the new instructions by reference. 428 bool 429 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, 430 bool UnfoldLoad, bool UnfoldStore, 431 SmallVectorImpl<MachineInstr *> &NewMIs) const override; 432 433 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 434 SmallVectorImpl<SDNode *> &NewNodes) const override; 435 436 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 437 /// instruction after load / store are unfolded from an instruction of the 438 /// specified opcode. It returns zero if the specified unfolding is not 439 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 440 /// index of the operand which will hold the register holding the loaded 441 /// value. 442 unsigned 443 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, 444 unsigned *LoadRegIndex = nullptr) const override; 445 446 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 447 /// to determine if two loads are loading from the same base address. It 448 /// should only return true if the base pointers are the same and the 449 /// only differences between the two addresses are the offset. It also returns 450 /// the offsets by reference. 451 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 452 int64_t &Offset2) const override; 453 454 /// isSchedulingBoundary - Overrides the isSchedulingBoundary from 455 /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR 456 /// intructions and prevent it from being re-scheduled. 457 bool isSchedulingBoundary(const MachineInstr &MI, 458 const MachineBasicBlock *MBB, 459 const MachineFunction &MF) const override; 460 461 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 462 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 463 /// should be scheduled togther. On some targets if two loads are loading from 464 /// addresses in the same cache line, it's better if they are scheduled 465 /// together. This function takes two integers that represent the load offsets 466 /// from the common base address. It returns true if it decides it's desirable 467 /// to schedule the two loads together. "NumLoads" is the number of loads that 468 /// have already been scheduled after Load1. 469 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, 470 int64_t Offset2, 471 unsigned NumLoads) const override; 472 473 void insertNoop(MachineBasicBlock &MBB, 474 MachineBasicBlock::iterator MI) const override; 475 476 MCInst getNop() const override; 477 478 bool 479 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 480 481 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 482 /// instruction that defines the specified register class. 483 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; 484 485 /// True if MI has a condition code def, e.g. EFLAGS, that is 486 /// not marked dead. 487 bool hasLiveCondCodeDef(MachineInstr &MI) const; 488 489 /// getGlobalBaseReg - Return a virtual register initialized with the 490 /// the global base register value. Output instructions required to 491 /// initialize the register in the function entry block, if necessary. 492 /// 493 unsigned getGlobalBaseReg(MachineFunction *MF) const; 494 495 std::pair<uint16_t, uint16_t> 496 getExecutionDomain(const MachineInstr &MI) const override; 497 498 uint16_t getExecutionDomainCustom(const MachineInstr &MI) const; 499 500 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override; 501 502 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const; 503 504 unsigned 505 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, 506 const TargetRegisterInfo *TRI) const override; 507 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, 508 const TargetRegisterInfo *TRI) const override; 509 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, 510 const TargetRegisterInfo *TRI) const override; 511 512 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 513 unsigned OpNum, 514 ArrayRef<MachineOperand> MOs, 515 MachineBasicBlock::iterator InsertPt, 516 unsigned Size, Align Alignment, 517 bool AllowCommute) const; 518 519 bool isHighLatencyDef(int opc) const override; 520 521 bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 522 const MachineRegisterInfo *MRI, 523 const MachineInstr &DefMI, unsigned DefIdx, 524 const MachineInstr &UseMI, 525 unsigned UseIdx) const override; 526 527 bool useMachineCombiner() const override { return true; } 528 529 bool isAssociativeAndCommutative(const MachineInstr &Inst, 530 bool Invert) const override; 531 532 bool hasReassociableOperands(const MachineInstr &Inst, 533 const MachineBasicBlock *MBB) const override; 534 535 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 536 MachineInstr &NewMI1, 537 MachineInstr &NewMI2) const override; 538 539 /// analyzeCompare - For a comparison instruction, return the source registers 540 /// in SrcReg and SrcReg2 if having two register operands, and the value it 541 /// compares against in CmpValue. Return true if the comparison instruction 542 /// can be analyzed. 543 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 544 Register &SrcReg2, int64_t &CmpMask, 545 int64_t &CmpValue) const override; 546 547 /// optimizeCompareInstr - Check if there exists an earlier instruction that 548 /// operates on the same source operands and sets flags in the same way as 549 /// Compare; remove Compare if possible. 550 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 551 Register SrcReg2, int64_t CmpMask, int64_t CmpValue, 552 const MachineRegisterInfo *MRI) const override; 553 554 /// optimizeLoadInstr - Try to remove the load by folding it to a register 555 /// operand at the use. We fold the load instructions if and only if the 556 /// def and use are in the same BB. We only look at one load and see 557 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 558 /// defined by the load we are trying to fold. DefMI returns the machine 559 /// instruction that defines FoldAsLoadDefReg, and the function returns 560 /// the machine instruction generated due to folding. 561 MachineInstr *optimizeLoadInstr(MachineInstr &MI, 562 const MachineRegisterInfo *MRI, 563 Register &FoldAsLoadDefReg, 564 MachineInstr *&DefMI) const override; 565 566 bool FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg, 567 int64_t ImmVal, MachineRegisterInfo *MRI, 568 bool MakeChange) const; 569 570 /// Reg is known to be defined by a move immediate instruction, try to fold 571 /// the immediate into the use instruction. 572 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 573 MachineRegisterInfo *MRI) const override; 574 575 std::pair<unsigned, unsigned> 576 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 577 578 ArrayRef<std::pair<unsigned, const char *>> 579 getSerializableDirectMachineOperandTargetFlags() const override; 580 581 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo( 582 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 583 584 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 585 bool OutlineFromLinkOnceODRs) const override; 586 587 outliner::InstrType 588 getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override; 589 590 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 591 const outliner::OutlinedFunction &OF) const override; 592 593 MachineBasicBlock::iterator 594 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 595 MachineBasicBlock::iterator &It, MachineFunction &MF, 596 outliner::Candidate &C) const override; 597 598 void buildClearRegister(Register Reg, MachineBasicBlock &MBB, 599 MachineBasicBlock::iterator Iter, DebugLoc &DL, 600 bool AllowSideEffects = true) const override; 601 602 bool verifyInstruction(const MachineInstr &MI, 603 StringRef &ErrInfo) const override; 604 #define GET_INSTRINFO_HELPER_DECLS 605 #include "X86GenInstrInfo.inc" 606 607 static bool hasLockPrefix(const MachineInstr &MI) { 608 return MI.getDesc().TSFlags & X86II::LOCK; 609 } 610 611 std::optional<ParamLoadedValue> 612 describeLoadedValue(const MachineInstr &MI, Register Reg) const override; 613 614 protected: 615 /// Commutes the operands in the given instruction by changing the operands 616 /// order and/or changing the instruction's opcode and/or the immediate value 617 /// operand. 618 /// 619 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands 620 /// to be commuted. 621 /// 622 /// Do not call this method for a non-commutable instruction or 623 /// non-commutable operands. 624 /// Even though the instruction is commutable, the method may still 625 /// fail to commute the operands, null pointer is returned in such cases. 626 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 627 unsigned CommuteOpIdx1, 628 unsigned CommuteOpIdx2) const override; 629 630 /// If the specific machine instruction is a instruction that moves/copies 631 /// value from one register to another register return destination and source 632 /// registers as machine operands. 633 std::optional<DestSourcePair> 634 isCopyInstrImpl(const MachineInstr &MI) const override; 635 636 /// Return true when there is potentially a faster code sequence for an 637 /// instruction chain ending in \p Root. All potential patterns are listed in 638 /// the \p Pattern vector. Pattern should be sorted in priority order since 639 /// the pattern evaluator stops checking as soon as it finds a faster 640 /// sequence. 641 bool 642 getMachineCombinerPatterns(MachineInstr &Root, 643 SmallVectorImpl<MachineCombinerPattern> &Patterns, 644 bool DoRegPressureReduce) const override; 645 646 /// When getMachineCombinerPatterns() finds potential patterns, 647 /// this function generates the instructions that could replace the 648 /// original code sequence. 649 void genAlternativeCodeSequence( 650 MachineInstr &Root, MachineCombinerPattern Pattern, 651 SmallVectorImpl<MachineInstr *> &InsInstrs, 652 SmallVectorImpl<MachineInstr *> &DelInstrs, 653 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 654 655 /// When calculate the latency of the root instruction, accumulate the 656 /// latency of the sequence to the root latency. 657 /// \param Root - Instruction that could be combined with one of its operands 658 /// For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd 659 /// is not in the critical path, so the root latency only include vpmaddwd. 660 bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override { 661 return false; 662 } 663 664 void getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops, 665 int FI) const override; 666 667 private: 668 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions. 669 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit 670 /// super-register and then truncating back down to a 8/16-bit sub-register. 671 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI, 672 LiveVariables *LV, 673 LiveIntervals *LIS, 674 bool Is8BitOp) const; 675 676 /// Handles memory folding for special case instructions, for instance those 677 /// requiring custom manipulation of the address. 678 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI, 679 unsigned OpNum, 680 ArrayRef<MachineOperand> MOs, 681 MachineBasicBlock::iterator InsertPt, 682 unsigned Size, Align Alignment) const; 683 684 /// isFrameOperand - Return true and the FrameIndex if the specified 685 /// operand and follow operands form a reference to the stack frame. 686 bool isFrameOperand(const MachineInstr &MI, unsigned int Op, 687 int &FrameIndex) const; 688 689 /// Returns true iff the routine could find two commutable operands in the 690 /// given machine instruction with 3 vector inputs. 691 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their 692 /// input values can be re-defined in this method only if the input values 693 /// are not pre-defined, which is designated by the special value 694 /// 'CommuteAnyOperandIndex' assigned to it. 695 /// If both of indices are pre-defined and refer to some operands, then the 696 /// method simply returns true if the corresponding operands are commutable 697 /// and returns false otherwise. 698 /// 699 /// For example, calling this method this way: 700 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 701 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2); 702 /// can be interpreted as a query asking to find an operand that would be 703 /// commutable with the operand#1. 704 /// 705 /// If IsIntrinsic is set, operand 1 will be ignored for commuting. 706 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI, 707 unsigned &SrcOpIdx1, 708 unsigned &SrcOpIdx2, 709 bool IsIntrinsic = false) const; 710 711 /// Returns true when instruction \p FlagI produces the same flags as \p OI. 712 /// The caller should pass in the results of calling analyzeCompare on \p OI: 713 /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue. 714 /// If the flags match \p OI as if it had the input operands swapped then the 715 /// function succeeds and sets \p IsSwapped to true. 716 /// 717 /// Examples of OI, FlagI pairs returning true: 718 /// CMP %1, 42 and CMP %1, 42 719 /// CMP %1, %2 and %3 = SUB %1, %2 720 /// TEST %1, %1 and %2 = SUB %1, 0 721 /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true 722 bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg, 723 Register SrcReg2, int64_t ImmMask, int64_t ImmValue, 724 const MachineInstr &OI, bool *IsSwapped, 725 int64_t *ImmDelta) const; 726 }; 727 728 } // namespace llvm 729 730 #endif 731