1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the X86 implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H 14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H 15 16 #include "MCTargetDesc/X86BaseInfo.h" 17 #include "X86InstrFMA3Info.h" 18 #include "X86RegisterInfo.h" 19 #include "llvm/CodeGen/ISDOpcodes.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 #include <vector> 22 23 #define GET_INSTRINFO_HEADER 24 #include "X86GenInstrInfo.inc" 25 26 namespace llvm { 27 class X86Subtarget; 28 29 namespace X86 { 30 31 enum AsmComments { 32 // For instr that was compressed from EVEX to VEX. 33 AC_EVEX_2_VEX = MachineInstr::TAsmComments 34 }; 35 36 /// Return a pair of condition code for the given predicate and whether 37 /// the instruction operands should be swaped to match the condition code. 38 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate); 39 40 /// Return a cmov opcode for the given register size in bytes, and operand type. 41 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false); 42 43 /// Return the source operand # for condition code by \p MCID. If the 44 /// instruction doesn't have a condition code, return -1. 45 int getCondSrcNoFromDesc(const MCInstrDesc &MCID); 46 47 /// Return the condition code of the instruction. If the instruction doesn't 48 /// have a condition code, return X86::COND_INVALID. 49 CondCode getCondFromMI(const MachineInstr &MI); 50 51 // Turn JCC instruction into condition code. 52 CondCode getCondFromBranch(const MachineInstr &MI); 53 54 // Turn SETCC instruction into condition code. 55 CondCode getCondFromSETCC(const MachineInstr &MI); 56 57 // Turn CMOV instruction into condition code. 58 CondCode getCondFromCMov(const MachineInstr &MI); 59 60 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 61 /// e.g. turning COND_E to COND_NE. 62 CondCode GetOppositeBranchCondition(CondCode CC); 63 64 /// Get the VPCMP immediate for the given condition. 65 unsigned getVPCMPImmForCond(ISD::CondCode CC); 66 67 /// Get the VPCMP immediate if the opcodes are swapped. 68 unsigned getSwappedVPCMPImm(unsigned Imm); 69 70 /// Get the VPCOM immediate if the opcodes are swapped. 71 unsigned getSwappedVPCOMImm(unsigned Imm); 72 73 /// Get the VCMP immediate if the opcodes are swapped. 74 unsigned getSwappedVCMPImm(unsigned Imm); 75 76 /// Check if the instruction is X87 instruction. 77 bool isX87Instruction(MachineInstr &MI); 78 } // namespace X86 79 80 /// isGlobalStubReference - Return true if the specified TargetFlag operand is 81 /// a reference to a stub for a global, not the global itself. 82 inline static bool isGlobalStubReference(unsigned char TargetFlag) { 83 switch (TargetFlag) { 84 case X86II::MO_DLLIMPORT: // dllimport stub. 85 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 86 case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference. 87 case X86II::MO_GOT: // normal GOT reference. 88 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 89 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 90 case X86II::MO_COFFSTUB: // COFF .refptr stub. 91 return true; 92 default: 93 return false; 94 } 95 } 96 97 /// isGlobalRelativeToPICBase - Return true if the specified global value 98 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 99 /// is true, the addressing mode has the PIC base register added in (e.g. EBX). 100 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 101 switch (TargetFlag) { 102 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 103 case X86II::MO_GOT: // isPICStyleGOT: other global. 104 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 105 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 106 case X86II::MO_TLVP: // ??? Pretty sure.. 107 return true; 108 default: 109 return false; 110 } 111 } 112 113 inline static bool isScale(const MachineOperand &MO) { 114 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 || 115 MO.getImm() == 4 || MO.getImm() == 8); 116 } 117 118 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { 119 if (MI.getOperand(Op).isFI()) 120 return true; 121 return Op + X86::AddrSegmentReg <= MI.getNumOperands() && 122 MI.getOperand(Op + X86::AddrBaseReg).isReg() && 123 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) && 124 MI.getOperand(Op + X86::AddrIndexReg).isReg() && 125 (MI.getOperand(Op + X86::AddrDisp).isImm() || 126 MI.getOperand(Op + X86::AddrDisp).isGlobal() || 127 MI.getOperand(Op + X86::AddrDisp).isCPI() || 128 MI.getOperand(Op + X86::AddrDisp).isJTI()); 129 } 130 131 inline static bool isMem(const MachineInstr &MI, unsigned Op) { 132 if (MI.getOperand(Op).isFI()) 133 return true; 134 return Op + X86::AddrNumOperands <= MI.getNumOperands() && 135 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op); 136 } 137 138 class X86InstrInfo final : public X86GenInstrInfo { 139 X86Subtarget &Subtarget; 140 const X86RegisterInfo RI; 141 142 virtual void anchor(); 143 144 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 145 MachineBasicBlock *&FBB, 146 SmallVectorImpl<MachineOperand> &Cond, 147 SmallVectorImpl<MachineInstr *> &CondBranches, 148 bool AllowModify) const; 149 150 public: 151 explicit X86InstrInfo(X86Subtarget &STI); 152 153 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 154 /// such, whenever a client has an instance of instruction info, it should 155 /// always be able to get register info as well (through this method). 156 /// 157 const X86RegisterInfo &getRegisterInfo() const { return RI; } 158 159 /// Returns the stack pointer adjustment that happens inside the frame 160 /// setup..destroy sequence (e.g. by pushes, or inside the callee). 161 int64_t getFrameAdjustment(const MachineInstr &I) const { 162 assert(isFrameInstr(I)); 163 if (isFrameSetup(I)) 164 return I.getOperand(2).getImm(); 165 return I.getOperand(1).getImm(); 166 } 167 168 /// Sets the stack pointer adjustment made inside the frame made up by this 169 /// instruction. 170 void setFrameAdjustment(MachineInstr &I, int64_t V) const { 171 assert(isFrameInstr(I)); 172 if (isFrameSetup(I)) 173 I.getOperand(2).setImm(V); 174 else 175 I.getOperand(1).setImm(V); 176 } 177 178 /// getSPAdjust - This returns the stack pointer adjustment made by 179 /// this instruction. For x86, we need to handle more complex call 180 /// sequences involving PUSHes. 181 int getSPAdjust(const MachineInstr &MI) const override; 182 183 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 184 /// extension instruction. That is, it's like a copy where it's legal for the 185 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 186 /// true, then it's expected the pre-extension value is available as a subreg 187 /// of the result register. This also returns the sub-register index in 188 /// SubIdx. 189 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, 190 Register &DstReg, unsigned &SubIdx) const override; 191 192 /// Returns true if the instruction has no behavior (specified or otherwise) 193 /// that is based on the value of any of its register operands 194 /// 195 /// Instructions are considered data invariant even if they set EFLAGS. 196 /// 197 /// A classical example of something that is inherently not data invariant is 198 /// an indirect jump -- the destination is loaded into icache based on the 199 /// bits set in the jump destination register. 200 /// 201 /// FIXME: This should become part of our instruction tables. 202 static bool isDataInvariant(MachineInstr &MI); 203 204 /// Returns true if the instruction has no behavior (specified or otherwise) 205 /// that is based on the value loaded from memory or the value of any 206 /// non-address register operands. 207 /// 208 /// For example, if the latency of the instruction is dependent on the 209 /// particular bits set in any of the registers *or* any of the bits loaded 210 /// from memory. 211 /// 212 /// Instructions are considered data invariant even if they set EFLAGS. 213 /// 214 /// A classical example of something that is inherently not data invariant is 215 /// an indirect jump -- the destination is loaded into icache based on the 216 /// bits set in the jump destination register. 217 /// 218 /// FIXME: This should become part of our instruction tables. 219 static bool isDataInvariantLoad(MachineInstr &MI); 220 221 unsigned isLoadFromStackSlot(const MachineInstr &MI, 222 int &FrameIndex) const override; 223 unsigned isLoadFromStackSlot(const MachineInstr &MI, 224 int &FrameIndex, 225 unsigned &MemBytes) const override; 226 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 227 /// stack locations as well. This uses a heuristic so it isn't 228 /// reliable for correctness. 229 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 230 int &FrameIndex) const override; 231 232 unsigned isStoreToStackSlot(const MachineInstr &MI, 233 int &FrameIndex) const override; 234 unsigned isStoreToStackSlot(const MachineInstr &MI, 235 int &FrameIndex, 236 unsigned &MemBytes) const override; 237 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 238 /// stack locations as well. This uses a heuristic so it isn't 239 /// reliable for correctness. 240 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 241 int &FrameIndex) const override; 242 243 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override; 244 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 245 Register DestReg, unsigned SubIdx, 246 const MachineInstr &Orig, 247 const TargetRegisterInfo &TRI) const override; 248 249 /// Given an operand within a MachineInstr, insert preceding code to put it 250 /// into the right format for a particular kind of LEA instruction. This may 251 /// involve using an appropriate super-register instead (with an implicit use 252 /// of the original) or creating a new virtual register and inserting COPY 253 /// instructions to get the data into the right class. 254 /// 255 /// Reference parameters are set to indicate how caller should add this 256 /// operand to the LEA instruction. 257 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, 258 unsigned LEAOpcode, bool AllowSP, Register &NewSrc, 259 bool &isKill, MachineOperand &ImplicitOp, 260 LiveVariables *LV, LiveIntervals *LIS) const; 261 262 /// convertToThreeAddress - This method must be implemented by targets that 263 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 264 /// may be able to convert a two-address instruction into a true 265 /// three-address instruction on demand. This allows the X86 target (for 266 /// example) to convert ADD and SHL instructions into LEA instructions if they 267 /// would require register copies due to two-addressness. 268 /// 269 /// This method returns a null pointer if the transformation cannot be 270 /// performed, otherwise it returns the new instruction. 271 /// 272 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, 273 LiveIntervals *LIS) const override; 274 275 /// Returns true iff the routine could find two commutable operands in the 276 /// given machine instruction. 277 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their 278 /// input values can be re-defined in this method only if the input values 279 /// are not pre-defined, which is designated by the special value 280 /// 'CommuteAnyOperandIndex' assigned to it. 281 /// If both of indices are pre-defined and refer to some operands, then the 282 /// method simply returns true if the corresponding operands are commutable 283 /// and returns false otherwise. 284 /// 285 /// For example, calling this method this way: 286 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 287 /// findCommutedOpIndices(MI, Op1, Op2); 288 /// can be interpreted as a query asking to find an operand that would be 289 /// commutable with the operand#1. 290 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 291 unsigned &SrcOpIdx2) const override; 292 293 /// Returns true if we have preference on the operands order in MI, the 294 /// commute decision is returned in Commute. 295 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override; 296 297 /// Returns an adjusted FMA opcode that must be used in FMA instruction that 298 /// performs the same computations as the given \p MI but which has the 299 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted. 300 /// It may return 0 if it is unsafe to commute the operands. 301 /// Note that a machine instruction (instead of its opcode) is passed as the 302 /// first parameter to make it possible to analyze the instruction's uses and 303 /// commute the first operand of FMA even when it seems unsafe when you look 304 /// at the opcode. For example, it is Ok to commute the first operand of 305 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used. 306 /// 307 /// The returned FMA opcode may differ from the opcode in the given \p MI. 308 /// For example, commuting the operands #1 and #3 in the following FMA 309 /// FMA213 #1, #2, #3 310 /// results into instruction with adjusted opcode: 311 /// FMA231 #3, #2, #1 312 unsigned 313 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, 314 unsigned SrcOpIdx2, 315 const X86InstrFMA3Group &FMA3Group) const; 316 317 // Branch analysis. 318 bool isUnconditionalTailCall(const MachineInstr &MI) const override; 319 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond, 320 const MachineInstr &TailCall) const override; 321 void replaceBranchWithTailCall(MachineBasicBlock &MBB, 322 SmallVectorImpl<MachineOperand> &Cond, 323 const MachineInstr &TailCall) const override; 324 325 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 326 MachineBasicBlock *&FBB, 327 SmallVectorImpl<MachineOperand> &Cond, 328 bool AllowModify) const override; 329 330 int getJumpTableIndex(const MachineInstr &MI) const override; 331 332 std::optional<ExtAddrMode> 333 getAddrModeFromMemoryOp(const MachineInstr &MemI, 334 const TargetRegisterInfo *TRI) const override; 335 336 bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, 337 int64_t &ImmVal) const override; 338 339 bool preservesZeroValueInReg(const MachineInstr *MI, 340 const Register NullValueReg, 341 const TargetRegisterInfo *TRI) const override; 342 343 bool getMemOperandsWithOffsetWidth( 344 const MachineInstr &LdSt, 345 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, 346 bool &OffsetIsScalable, unsigned &Width, 347 const TargetRegisterInfo *TRI) const override; 348 bool analyzeBranchPredicate(MachineBasicBlock &MBB, 349 TargetInstrInfo::MachineBranchPredicate &MBP, 350 bool AllowModify = false) const override; 351 352 unsigned removeBranch(MachineBasicBlock &MBB, 353 int *BytesRemoved = nullptr) const override; 354 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 355 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 356 const DebugLoc &DL, 357 int *BytesAdded = nullptr) const override; 358 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 359 Register, Register, Register, int &, int &, 360 int &) const override; 361 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 362 const DebugLoc &DL, Register DstReg, 363 ArrayRef<MachineOperand> Cond, Register TrueReg, 364 Register FalseReg) const override; 365 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 366 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 367 bool KillSrc) const override; 368 void storeRegToStackSlot(MachineBasicBlock &MBB, 369 MachineBasicBlock::iterator MI, Register SrcReg, 370 bool isKill, int FrameIndex, 371 const TargetRegisterClass *RC, 372 const TargetRegisterInfo *TRI, 373 Register VReg) const override; 374 375 void loadRegFromStackSlot(MachineBasicBlock &MBB, 376 MachineBasicBlock::iterator MI, Register DestReg, 377 int FrameIndex, const TargetRegisterClass *RC, 378 const TargetRegisterInfo *TRI, 379 Register VReg) const override; 380 381 void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 382 unsigned Opc, Register Reg, int FrameIdx, 383 bool isKill = false) const; 384 385 bool expandPostRAPseudo(MachineInstr &MI) const override; 386 387 /// Check whether the target can fold a load that feeds a subreg operand 388 /// (or a subreg operand that feeds a store). 389 bool isSubregFoldable() const override { return true; } 390 391 /// foldMemoryOperand - If this target supports it, fold a load or store of 392 /// the specified stack slot into the specified machine instruction for the 393 /// specified operand(s). If this is possible, the target should perform the 394 /// folding and return true, otherwise it should return false. If it folds 395 /// the instruction, it is likely that the MachineInstruction the iterator 396 /// references has been changed. 397 MachineInstr * 398 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 399 ArrayRef<unsigned> Ops, 400 MachineBasicBlock::iterator InsertPt, int FrameIndex, 401 LiveIntervals *LIS = nullptr, 402 VirtRegMap *VRM = nullptr) const override; 403 404 /// foldMemoryOperand - Same as the previous version except it allows folding 405 /// of any load and store from / to any address, not just from a specific 406 /// stack slot. 407 MachineInstr *foldMemoryOperandImpl( 408 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 409 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, 410 LiveIntervals *LIS = nullptr) const override; 411 412 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 413 /// a store or a load and a store into two or more instruction. If this is 414 /// possible, returns true as well as the new instructions by reference. 415 bool 416 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, 417 bool UnfoldLoad, bool UnfoldStore, 418 SmallVectorImpl<MachineInstr *> &NewMIs) const override; 419 420 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 421 SmallVectorImpl<SDNode *> &NewNodes) const override; 422 423 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 424 /// instruction after load / store are unfolded from an instruction of the 425 /// specified opcode. It returns zero if the specified unfolding is not 426 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 427 /// index of the operand which will hold the register holding the loaded 428 /// value. 429 unsigned 430 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, 431 unsigned *LoadRegIndex = nullptr) const override; 432 433 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 434 /// to determine if two loads are loading from the same base address. It 435 /// should only return true if the base pointers are the same and the 436 /// only differences between the two addresses are the offset. It also returns 437 /// the offsets by reference. 438 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 439 int64_t &Offset2) const override; 440 441 /// isSchedulingBoundary - Overrides the isSchedulingBoundary from 442 /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR 443 /// intructions and prevent it from being re-scheduled. 444 bool isSchedulingBoundary(const MachineInstr &MI, 445 const MachineBasicBlock *MBB, 446 const MachineFunction &MF) const override; 447 448 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 449 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 450 /// should be scheduled togther. On some targets if two loads are loading from 451 /// addresses in the same cache line, it's better if they are scheduled 452 /// together. This function takes two integers that represent the load offsets 453 /// from the common base address. It returns true if it decides it's desirable 454 /// to schedule the two loads together. "NumLoads" is the number of loads that 455 /// have already been scheduled after Load1. 456 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, 457 int64_t Offset2, 458 unsigned NumLoads) const override; 459 460 MCInst getNop() const override; 461 462 bool 463 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 464 465 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 466 /// instruction that defines the specified register class. 467 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; 468 469 /// True if MI has a condition code def, e.g. EFLAGS, that is 470 /// not marked dead. 471 bool hasLiveCondCodeDef(MachineInstr &MI) const; 472 473 /// getGlobalBaseReg - Return a virtual register initialized with the 474 /// the global base register value. Output instructions required to 475 /// initialize the register in the function entry block, if necessary. 476 /// 477 unsigned getGlobalBaseReg(MachineFunction *MF) const; 478 479 std::pair<uint16_t, uint16_t> 480 getExecutionDomain(const MachineInstr &MI) const override; 481 482 uint16_t getExecutionDomainCustom(const MachineInstr &MI) const; 483 484 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override; 485 486 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const; 487 488 unsigned 489 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, 490 const TargetRegisterInfo *TRI) const override; 491 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, 492 const TargetRegisterInfo *TRI) const override; 493 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, 494 const TargetRegisterInfo *TRI) const override; 495 496 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 497 unsigned OpNum, 498 ArrayRef<MachineOperand> MOs, 499 MachineBasicBlock::iterator InsertPt, 500 unsigned Size, Align Alignment, 501 bool AllowCommute) const; 502 503 bool isHighLatencyDef(int opc) const override; 504 505 bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 506 const MachineRegisterInfo *MRI, 507 const MachineInstr &DefMI, unsigned DefIdx, 508 const MachineInstr &UseMI, 509 unsigned UseIdx) const override; 510 511 bool useMachineCombiner() const override { return true; } 512 513 bool isAssociativeAndCommutative(const MachineInstr &Inst, 514 bool Invert) const override; 515 516 bool hasReassociableOperands(const MachineInstr &Inst, 517 const MachineBasicBlock *MBB) const override; 518 519 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 520 MachineInstr &NewMI1, 521 MachineInstr &NewMI2) const override; 522 523 /// analyzeCompare - For a comparison instruction, return the source registers 524 /// in SrcReg and SrcReg2 if having two register operands, and the value it 525 /// compares against in CmpValue. Return true if the comparison instruction 526 /// can be analyzed. 527 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 528 Register &SrcReg2, int64_t &CmpMask, 529 int64_t &CmpValue) const override; 530 531 /// optimizeCompareInstr - Check if there exists an earlier instruction that 532 /// operates on the same source operands and sets flags in the same way as 533 /// Compare; remove Compare if possible. 534 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 535 Register SrcReg2, int64_t CmpMask, int64_t CmpValue, 536 const MachineRegisterInfo *MRI) const override; 537 538 /// optimizeLoadInstr - Try to remove the load by folding it to a register 539 /// operand at the use. We fold the load instructions if and only if the 540 /// def and use are in the same BB. We only look at one load and see 541 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 542 /// defined by the load we are trying to fold. DefMI returns the machine 543 /// instruction that defines FoldAsLoadDefReg, and the function returns 544 /// the machine instruction generated due to folding. 545 MachineInstr *optimizeLoadInstr(MachineInstr &MI, 546 const MachineRegisterInfo *MRI, 547 Register &FoldAsLoadDefReg, 548 MachineInstr *&DefMI) const override; 549 550 std::pair<unsigned, unsigned> 551 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 552 553 ArrayRef<std::pair<unsigned, const char *>> 554 getSerializableDirectMachineOperandTargetFlags() const override; 555 556 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo( 557 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 558 559 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 560 bool OutlineFromLinkOnceODRs) const override; 561 562 outliner::InstrType 563 getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override; 564 565 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 566 const outliner::OutlinedFunction &OF) const override; 567 568 MachineBasicBlock::iterator 569 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 570 MachineBasicBlock::iterator &It, MachineFunction &MF, 571 outliner::Candidate &C) const override; 572 573 bool verifyInstruction(const MachineInstr &MI, 574 StringRef &ErrInfo) const override; 575 #define GET_INSTRINFO_HELPER_DECLS 576 #include "X86GenInstrInfo.inc" 577 578 static bool hasLockPrefix(const MachineInstr &MI) { 579 return MI.getDesc().TSFlags & X86II::LOCK; 580 } 581 582 std::optional<ParamLoadedValue> 583 describeLoadedValue(const MachineInstr &MI, Register Reg) const override; 584 585 protected: 586 /// Commutes the operands in the given instruction by changing the operands 587 /// order and/or changing the instruction's opcode and/or the immediate value 588 /// operand. 589 /// 590 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands 591 /// to be commuted. 592 /// 593 /// Do not call this method for a non-commutable instruction or 594 /// non-commutable operands. 595 /// Even though the instruction is commutable, the method may still 596 /// fail to commute the operands, null pointer is returned in such cases. 597 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 598 unsigned CommuteOpIdx1, 599 unsigned CommuteOpIdx2) const override; 600 601 /// If the specific machine instruction is a instruction that moves/copies 602 /// value from one register to another register return destination and source 603 /// registers as machine operands. 604 std::optional<DestSourcePair> 605 isCopyInstrImpl(const MachineInstr &MI) const override; 606 607 /// Return true when there is potentially a faster code sequence for an 608 /// instruction chain ending in \p Root. All potential patterns are listed in 609 /// the \p Pattern vector. Pattern should be sorted in priority order since 610 /// the pattern evaluator stops checking as soon as it finds a faster 611 /// sequence. 612 bool 613 getMachineCombinerPatterns(MachineInstr &Root, 614 SmallVectorImpl<MachineCombinerPattern> &Patterns, 615 bool DoRegPressureReduce) const override; 616 617 /// When getMachineCombinerPatterns() finds potential patterns, 618 /// this function generates the instructions that could replace the 619 /// original code sequence. 620 void genAlternativeCodeSequence( 621 MachineInstr &Root, MachineCombinerPattern Pattern, 622 SmallVectorImpl<MachineInstr *> &InsInstrs, 623 SmallVectorImpl<MachineInstr *> &DelInstrs, 624 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 625 626 /// When calculate the latency of the root instruction, accumulate the 627 /// latency of the sequence to the root latency. 628 /// \param Root - Instruction that could be combined with one of its operands 629 /// For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd 630 /// is not in the critical path, so the root latency only include vpmaddwd. 631 bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override { 632 return false; 633 } 634 635 private: 636 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions. 637 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit 638 /// super-register and then truncating back down to a 8/16-bit sub-register. 639 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI, 640 LiveVariables *LV, 641 LiveIntervals *LIS, 642 bool Is8BitOp) const; 643 644 /// Handles memory folding for special case instructions, for instance those 645 /// requiring custom manipulation of the address. 646 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI, 647 unsigned OpNum, 648 ArrayRef<MachineOperand> MOs, 649 MachineBasicBlock::iterator InsertPt, 650 unsigned Size, Align Alignment) const; 651 652 /// isFrameOperand - Return true and the FrameIndex if the specified 653 /// operand and follow operands form a reference to the stack frame. 654 bool isFrameOperand(const MachineInstr &MI, unsigned int Op, 655 int &FrameIndex) const; 656 657 /// Returns true iff the routine could find two commutable operands in the 658 /// given machine instruction with 3 vector inputs. 659 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their 660 /// input values can be re-defined in this method only if the input values 661 /// are not pre-defined, which is designated by the special value 662 /// 'CommuteAnyOperandIndex' assigned to it. 663 /// If both of indices are pre-defined and refer to some operands, then the 664 /// method simply returns true if the corresponding operands are commutable 665 /// and returns false otherwise. 666 /// 667 /// For example, calling this method this way: 668 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; 669 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2); 670 /// can be interpreted as a query asking to find an operand that would be 671 /// commutable with the operand#1. 672 /// 673 /// If IsIntrinsic is set, operand 1 will be ignored for commuting. 674 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI, 675 unsigned &SrcOpIdx1, 676 unsigned &SrcOpIdx2, 677 bool IsIntrinsic = false) const; 678 679 /// Returns true when instruction \p FlagI produces the same flags as \p OI. 680 /// The caller should pass in the results of calling analyzeCompare on \p OI: 681 /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue. 682 /// If the flags match \p OI as if it had the input operands swapped then the 683 /// function succeeds and sets \p IsSwapped to true. 684 /// 685 /// Examples of OI, FlagI pairs returning true: 686 /// CMP %1, 42 and CMP %1, 42 687 /// CMP %1, %2 and %3 = SUB %1, %2 688 /// TEST %1, %1 and %2 = SUB %1, 0 689 /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true 690 bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg, 691 Register SrcReg2, int64_t ImmMask, int64_t ImmValue, 692 const MachineInstr &OI, bool *IsSwapped, 693 int64_t *ImmDelta) const; 694 }; 695 696 } // namespace llvm 697 698 #endif 699