1//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file provides pattern fragments useful for SIMD instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// MMX specific DAG Nodes. 15//===----------------------------------------------------------------------===// 16 17// Low word of MMX to GPR. 18def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1, 19 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>; 20// GPR to low word of MMX. 21def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1, 22 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>; 23 24//===----------------------------------------------------------------------===// 25// MMX Pattern Fragments 26//===----------------------------------------------------------------------===// 27 28def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>; 29 30//===----------------------------------------------------------------------===// 31// SSE specific DAG Nodes. 32//===----------------------------------------------------------------------===// 33 34def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, 35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 36 SDTCisVT<3, i8>]>; 37 38def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; 39def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; 40def X86fmins : SDNode<"X86ISD::FMINS", SDTFPBinOp>; 41def X86fmaxs : SDNode<"X86ISD::FMAXS", SDTFPBinOp>; 42 43// Commutative and Associative FMIN and FMAX. 44def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp, 45 [SDNPCommutative, SDNPAssociative]>; 46def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp, 47 [SDNPCommutative, SDNPAssociative]>; 48 49def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, 50 [SDNPCommutative, SDNPAssociative]>; 51def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, 52 [SDNPCommutative, SDNPAssociative]>; 53def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, 54 [SDNPCommutative, SDNPAssociative]>; 55def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp>; 56def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; 57def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; 58def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; 59def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; 60def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>; 61def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>; 62def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; 63def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; 64def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>; 65def X86pshufb : SDNode<"X86ISD::PSHUFB", 66 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>, 67 SDTCisSameAs<0,2>]>>; 68def X86psadbw : SDNode<"X86ISD::PSADBW", 69 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 70 SDTCVecEltisVT<1, i8>, 71 SDTCisSameSizeAs<0,1>, 72 SDTCisSameAs<1,2>]>, [SDNPCommutative]>; 73def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW", 74 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>, 75 SDTCVecEltisVT<1, i8>, 76 SDTCisSameSizeAs<0,1>, 77 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>>; 78def X86andnp : SDNode<"X86ISD::ANDNP", 79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 80 SDTCisSameAs<0,2>]>>; 81def X86multishift : SDNode<"X86ISD::MULTISHIFT", 82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 83 SDTCisSameAs<1,2>]>>; 84def X86pextrb : SDNode<"X86ISD::PEXTRB", 85 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>, 86 SDTCisPtrTy<2>]>>; 87def X86pextrw : SDNode<"X86ISD::PEXTRW", 88 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>, 89 SDTCisPtrTy<2>]>>; 90def X86pinsrb : SDNode<"X86ISD::PINSRB", 91 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 92 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 93def X86pinsrw : SDNode<"X86ISD::PINSRW", 94 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, 95 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 96def X86insertps : SDNode<"X86ISD::INSERTPS", 97 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, 98 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>; 99def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", 100 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; 101 102def X86vzld : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, 103 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 104def X86vextractst : SDNode<"X86ISD::VEXTRACT_STORE", SDTStore, 105 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 106 107def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 108 SDTCisInt<0>, SDTCisInt<1>, 109 SDTCisOpSmallerThanOp<0, 1>]>; 110def SDTVmtrunc : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 111 SDTCisInt<0>, SDTCisInt<1>, 112 SDTCisOpSmallerThanOp<0, 1>, 113 SDTCisSameAs<0, 2>, 114 SDTCVecEltisVT<3, i1>, 115 SDTCisSameNumEltsAs<1, 3>]>; 116 117def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>; 118def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>; 119def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>; 120def X86vmtrunc : SDNode<"X86ISD::VMTRUNC", SDTVmtrunc>; 121def X86vmtruncs : SDNode<"X86ISD::VMTRUNCS", SDTVmtrunc>; 122def X86vmtruncus : SDNode<"X86ISD::VMTRUNCUS", SDTVmtrunc>; 123 124def X86vfpext : SDNode<"X86ISD::VFPEXT", 125 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, 126 SDTCVecEltisVT<1, f32>, 127 SDTCisSameSizeAs<0, 1>]>>; 128def X86vfpround: SDNode<"X86ISD::VFPROUND", 129 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 130 SDTCVecEltisVT<1, f64>, 131 SDTCisOpSmallerThanOp<0, 1>]>>; 132 133def X86frounds : SDNode<"X86ISD::VFPROUNDS", 134 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, 135 SDTCisSameAs<0, 1>, 136 SDTCVecEltisVT<2, f64>, 137 SDTCisSameSizeAs<0, 2>]>>; 138 139def X86froundsRnd: SDNode<"X86ISD::VFPROUNDS_RND", 140 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 141 SDTCisSameAs<0, 1>, 142 SDTCVecEltisVT<2, f64>, 143 SDTCisSameSizeAs<0, 2>, 144 SDTCisVT<3, i32>]>>; 145 146def X86fpexts : SDNode<"X86ISD::VFPEXTS", 147 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>, 148 SDTCisSameAs<0, 1>, 149 SDTCVecEltisVT<2, f32>, 150 SDTCisSameSizeAs<0, 2>]>>; 151def X86fpextsSAE : SDNode<"X86ISD::VFPEXTS_SAE", 152 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>, 153 SDTCisSameAs<0, 1>, 154 SDTCVecEltisVT<2, f32>, 155 SDTCisSameSizeAs<0, 2>]>>; 156 157def X86vmfpround: SDNode<"X86ISD::VMFPROUND", 158 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 159 SDTCVecEltisVT<1, f64>, 160 SDTCisSameSizeAs<0, 1>, 161 SDTCisSameAs<0, 2>, 162 SDTCVecEltisVT<3, i1>, 163 SDTCisSameNumEltsAs<1, 3>]>>; 164 165def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 166 SDTCisVT<2, i8>, SDTCisInt<0>]>; 167 168def X86vshldq : SDNode<"X86ISD::VSHLDQ", X86vshiftimm>; 169def X86vshrdq : SDNode<"X86ISD::VSRLDQ", X86vshiftimm>; 170def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>; 171def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>; 172def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>; 173 174def X86CmpMaskCC : 175 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>, 176 SDTCisVec<1>, SDTCisSameAs<2, 1>, 177 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>; 178def X86CmpMaskCCScalar : 179 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>, 180 SDTCisVT<3, i8>]>; 181 182def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>; 183def X86cmpmSAE : SDNode<"X86ISD::CMPM_SAE", X86CmpMaskCC>; 184def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>; 185def X86cmpmsSAE : SDNode<"X86ISD::FSETCCM_SAE", X86CmpMaskCCScalar>; 186 187def X86phminpos: SDNode<"X86ISD::PHMINPOS", 188 SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>; 189 190def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 191 SDTCisVec<2>, SDTCisInt<0>, 192 SDTCisInt<2>]>; 193 194def X86vshl : SDNode<"X86ISD::VSHL", X86vshiftuniform>; 195def X86vsrl : SDNode<"X86ISD::VSRL", X86vshiftuniform>; 196def X86vsra : SDNode<"X86ISD::VSRA", X86vshiftuniform>; 197 198def X86vshiftvariable : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 199 SDTCisSameAs<0,2>, SDTCisInt<0>]>; 200 201def X86vshlv : SDNode<"X86ISD::VSHLV", X86vshiftvariable>; 202def X86vsrlv : SDNode<"X86ISD::VSRLV", X86vshiftvariable>; 203def X86vsrav : SDNode<"X86ISD::VSRAV", X86vshiftvariable>; 204 205def X86vshli : SDNode<"X86ISD::VSHLI", X86vshiftimm>; 206def X86vsrli : SDNode<"X86ISD::VSRLI", X86vshiftimm>; 207def X86vsrai : SDNode<"X86ISD::VSRAI", X86vshiftimm>; 208 209def X86kshiftl : SDNode<"X86ISD::KSHIFTL", 210 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 211 SDTCisSameAs<0, 1>, 212 SDTCisVT<2, i8>]>>; 213def X86kshiftr : SDNode<"X86ISD::KSHIFTR", 214 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 215 SDTCisSameAs<0, 1>, 216 SDTCisVT<2, i8>]>>; 217 218def X86kadd : SDNode<"X86ISD::KADD", SDTIntBinOp, [SDNPCommutative]>; 219 220def X86vrotli : SDNode<"X86ISD::VROTLI", X86vshiftimm>; 221def X86vrotri : SDNode<"X86ISD::VROTRI", X86vshiftimm>; 222 223def X86vpshl : SDNode<"X86ISD::VPSHL", X86vshiftvariable>; 224def X86vpsha : SDNode<"X86ISD::VPSHA", X86vshiftvariable>; 225 226def X86vpcom : SDNode<"X86ISD::VPCOM", 227 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 228 SDTCisSameAs<0,2>, 229 SDTCisVT<3, i8>, SDTCisInt<0>]>>; 230def X86vpcomu : SDNode<"X86ISD::VPCOMU", 231 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 232 SDTCisSameAs<0,2>, 233 SDTCisVT<3, i8>, SDTCisInt<0>]>>; 234def X86vpermil2 : SDNode<"X86ISD::VPERMIL2", 235 SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>, 236 SDTCisSameAs<0,2>, 237 SDTCisFP<0>, SDTCisInt<3>, 238 SDTCisSameNumEltsAs<0, 3>, 239 SDTCisSameSizeAs<0,3>, 240 SDTCisVT<4, i8>]>>; 241def X86vpperm : SDNode<"X86ISD::VPPERM", 242 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 243 SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>; 244 245def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 246 SDTCisVec<1>, 247 SDTCisSameAs<2, 1>]>; 248 249def X86mulhrs : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>; 250def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>; 251def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; 252def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>; 253def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>; 254def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>; 255 256def X86movmsk : SDNode<"X86ISD::MOVMSK", 257 SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>; 258 259def X86selects : SDNode<"X86ISD::SELECTS", 260 SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>, 261 SDTCisSameAs<0, 2>, 262 SDTCisSameAs<2, 3>]>>; 263 264def X86pmuludq : SDNode<"X86ISD::PMULUDQ", 265 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 266 SDTCisSameAs<0,1>, 267 SDTCisSameAs<1,2>]>, 268 [SDNPCommutative]>; 269def X86pmuldq : SDNode<"X86ISD::PMULDQ", 270 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 271 SDTCisSameAs<0,1>, 272 SDTCisSameAs<1,2>]>, 273 [SDNPCommutative]>; 274 275def X86extrqi : SDNode<"X86ISD::EXTRQI", 276 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, 277 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>; 278def X86insertqi : SDNode<"X86ISD::INSERTQI", 279 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, 280 SDTCisSameAs<1,2>, SDTCisVT<3, i8>, 281 SDTCisVT<4, i8>]>>; 282 283// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get 284// translated into one of the target nodes below during lowering. 285// Note: this is a work in progress... 286def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 287def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 288 SDTCisSameAs<0,2>]>; 289def SDTShuff2OpFP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 290 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>; 291 292def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 293 SDTCisFP<0>, SDTCisInt<2>, 294 SDTCisSameNumEltsAs<0,2>, 295 SDTCisSameSizeAs<0,2>]>; 296def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>, 297 SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>; 298def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 299 SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>; 300def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, 301 SDTCisSameAs<0,1>, 302 SDTCisSameAs<0,2>, 303 SDTCisVT<3, i32>]>; 304def SDTFPTernaryOpImm: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisSameAs<0,1>, 305 SDTCisSameAs<0,2>, 306 SDTCisInt<3>, 307 SDTCisSameSizeAs<0, 3>, 308 SDTCisSameNumEltsAs<0, 3>, 309 SDTCisVT<4, i32>]>; 310def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>, 311 SDTCisSameAs<0,1>, 312 SDTCisVT<2, i32>]>; 313 314def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 315def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>, 316 SDTCisInt<0>, SDTCisInt<1>]>; 317 318def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 319 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>; 320 321def SDTTernlog : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>, 322 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, 323 SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>; 324 325def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc. 326 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>; 327 328def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc. 329 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>; 330 331def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>, 332 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, 333 SDTCisFP<0>, SDTCisVT<4, i32>]>; 334 335def X86PAlignr : SDNode<"X86ISD::PALIGNR", 336 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>, 337 SDTCisSameAs<0,1>, 338 SDTCisSameAs<0,2>, 339 SDTCisVT<3, i8>]>>; 340def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>; 341 342def X86VShld : SDNode<"X86ISD::VSHLD", SDTShuff3OpI>; 343def X86VShrd : SDNode<"X86ISD::VSHRD", SDTShuff3OpI>; 344def X86VShldv : SDNode<"X86ISD::VSHLDV", 345 SDTypeProfile<1, 3, [SDTCisVec<0>, 346 SDTCisSameAs<0,1>, 347 SDTCisSameAs<0,2>, 348 SDTCisSameAs<0,3>]>>; 349def X86VShrdv : SDNode<"X86ISD::VSHRDV", 350 SDTypeProfile<1, 3, [SDTCisVec<0>, 351 SDTCisSameAs<0,1>, 352 SDTCisSameAs<0,2>, 353 SDTCisSameAs<0,3>]>>; 354 355def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>; 356 357def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; 358def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; 359def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; 360 361def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>; 362def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>; 363 364def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>; 365def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; 366def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; 367 368def X86Movsd : SDNode<"X86ISD::MOVSD", 369 SDTypeProfile<1, 2, [SDTCisVT<0, v2f64>, 370 SDTCisVT<1, v2f64>, 371 SDTCisVT<2, v2f64>]>>; 372def X86Movss : SDNode<"X86ISD::MOVSS", 373 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 374 SDTCisVT<1, v4f32>, 375 SDTCisVT<2, v4f32>]>>; 376 377def X86Movlhps : SDNode<"X86ISD::MOVLHPS", 378 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 379 SDTCisVT<1, v4f32>, 380 SDTCisVT<2, v4f32>]>>; 381def X86Movhlps : SDNode<"X86ISD::MOVHLPS", 382 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 383 SDTCisVT<1, v4f32>, 384 SDTCisVT<2, v4f32>]>>; 385 386def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>, 387 SDTCisVec<1>, SDTCisInt<1>, 388 SDTCisSameSizeAs<0,1>, 389 SDTCisSameAs<1,2>, 390 SDTCisOpSmallerThanOp<0, 1>]>; 391def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>; 392def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>; 393 394def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>; 395def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>; 396 397def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW", 398 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, 399 SDTCVecEltisVT<1, i8>, 400 SDTCisSameSizeAs<0,1>, 401 SDTCisSameAs<1,2>]>>; 402def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD", 403 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>, 404 SDTCVecEltisVT<1, i16>, 405 SDTCisSameSizeAs<0,1>, 406 SDTCisSameAs<1,2>]>, 407 [SDNPCommutative]>; 408 409def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>; 410def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>; 411def X86VPermv : SDNode<"X86ISD::VPERMV", 412 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>, 413 SDTCisSameNumEltsAs<0,1>, 414 SDTCisSameSizeAs<0,1>, 415 SDTCisSameAs<0,2>]>>; 416def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>; 417def X86VPermt2 : SDNode<"X86ISD::VPERMV3", 418 SDTypeProfile<1, 3, [SDTCisVec<0>, 419 SDTCisSameAs<0,1>, SDTCisInt<2>, 420 SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>, 421 SDTCisSameSizeAs<0,2>, 422 SDTCisSameAs<0,3>]>, []>; 423 424def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>; 425 426def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>; 427 428def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImm>; 429def X86VFixupimmSAE : SDNode<"X86ISD::VFIXUPIMM_SAE", SDTFPTernaryOpImm>; 430def X86VFixupimms : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImm>; 431def X86VFixupimmSAEs : SDNode<"X86ISD::VFIXUPIMMS_SAE", SDTFPTernaryOpImm>; 432def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImm>; 433def X86VRangeSAE : SDNode<"X86ISD::VRANGE_SAE", SDTFPBinOpImm>; 434def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImm>; 435def X86VReduceSAE : SDNode<"X86ISD::VREDUCE_SAE", SDTFPUnaryOpImm>; 436def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImm>; 437def X86VRndScaleSAE: SDNode<"X86ISD::VRNDSCALE_SAE", SDTFPUnaryOpImm>; 438def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImm>; 439def X86VGetMantSAE : SDNode<"X86ISD::VGETMANT_SAE", SDTFPUnaryOpImm>; 440def X86Vfpclass : SDNode<"X86ISD::VFPCLASS", 441 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 442 SDTCisFP<1>, 443 SDTCisSameNumEltsAs<0,1>, 444 SDTCisVT<2, i32>]>, []>; 445def X86Vfpclasss : SDNode<"X86ISD::VFPCLASSS", 446 SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>, 447 SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>; 448 449def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST", 450 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 451 SDTCisSubVecOfVec<1, 0>]>, []>; 452 453def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; 454def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>; 455 456def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>; 457def X86Blendv : SDNode<"X86ISD::BLENDV", 458 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<1>, 459 SDTCisSameAs<0, 2>, 460 SDTCisSameAs<2, 3>, 461 SDTCisSameNumEltsAs<0, 1>, 462 SDTCisSameSizeAs<0, 1>]>>; 463 464def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>; 465 466def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>; 467def X86fadds : SDNode<"X86ISD::FADDS", SDTFPBinOp>; 468def X86faddRnds : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>; 469def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>; 470def X86fsubs : SDNode<"X86ISD::FSUBS", SDTFPBinOp>; 471def X86fsubRnds : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>; 472def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>; 473def X86fmuls : SDNode<"X86ISD::FMULS", SDTFPBinOp>; 474def X86fmulRnds : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>; 475def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>; 476def X86fdivs : SDNode<"X86ISD::FDIVS", SDTFPBinOp>; 477def X86fdivRnds : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>; 478def X86fmaxSAE : SDNode<"X86ISD::FMAX_SAE", SDTFPBinOp>; 479def X86fmaxSAEs : SDNode<"X86ISD::FMAXS_SAE", SDTFPBinOp>; 480def X86fminSAE : SDNode<"X86ISD::FMIN_SAE", SDTFPBinOp>; 481def X86fminSAEs : SDNode<"X86ISD::FMINS_SAE", SDTFPBinOp>; 482def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOp>; 483def X86scalefRnd : SDNode<"X86ISD::SCALEF_RND", SDTFPBinOpRound>; 484def X86scalefs : SDNode<"X86ISD::SCALEFS", SDTFPBinOp>; 485def X86scalefsRnd: SDNode<"X86ISD::SCALEFS_RND", SDTFPBinOpRound>; 486def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>; 487def X86fsqrts : SDNode<"X86ISD::FSQRTS", SDTFPBinOp>; 488def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>; 489def X86fgetexp : SDNode<"X86ISD::FGETEXP", SDTFPUnaryOp>; 490def X86fgetexpSAE : SDNode<"X86ISD::FGETEXP_SAE", SDTFPUnaryOp>; 491def X86fgetexps : SDNode<"X86ISD::FGETEXPS", SDTFPBinOp>; 492def X86fgetexpSAEs : SDNode<"X86ISD::FGETEXPS_SAE", SDTFPBinOp>; 493 494def X86Fmadd : SDNode<"ISD::FMA", SDTFPTernaryOp, [SDNPCommutative]>; 495def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFPTernaryOp, [SDNPCommutative]>; 496def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>; 497def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFPTernaryOp, [SDNPCommutative]>; 498def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFPTernaryOp, [SDNPCommutative]>; 499def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFPTernaryOp, [SDNPCommutative]>; 500 501def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound, [SDNPCommutative]>; 502def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound, [SDNPCommutative]>; 503def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound, [SDNPCommutative]>; 504def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound, [SDNPCommutative]>; 505def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound, [SDNPCommutative]>; 506def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound, [SDNPCommutative]>; 507 508def X86vp2intersect : SDNode<"X86ISD::VP2INTERSECT", 509 SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 510 SDTCisVec<1>, SDTCisSameAs<1, 2>]>>; 511 512def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>, 513 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 514def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>; 515def x86vpmadd52h : SDNode<"X86ISD::VPMADD52H", SDTIFma, [SDNPCommutative]>; 516 517def X86rsqrt14 : SDNode<"X86ISD::RSQRT14", SDTFPUnaryOp>; 518def X86rcp14 : SDNode<"X86ISD::RCP14", SDTFPUnaryOp>; 519 520// VNNI 521def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 522 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 523def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnni>; 524def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>; 525def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnni>; 526def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>; 527 528def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOp>; 529def X86rsqrt28SAE: SDNode<"X86ISD::RSQRT28_SAE", SDTFPUnaryOp>; 530def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOp>; 531def X86rcp28SAE : SDNode<"X86ISD::RCP28_SAE", SDTFPUnaryOp>; 532def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOp>; 533def X86exp2SAE : SDNode<"X86ISD::EXP2_SAE", SDTFPUnaryOp>; 534 535def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>; 536def X86rcp14s : SDNode<"X86ISD::RCP14S", SDTFPBinOp>; 537def X86rsqrt28s : SDNode<"X86ISD::RSQRT28S", SDTFPBinOp>; 538def X86rsqrt28SAEs : SDNode<"X86ISD::RSQRT28S_SAE", SDTFPBinOp>; 539def X86rcp28s : SDNode<"X86ISD::RCP28S", SDTFPBinOp>; 540def X86rcp28SAEs : SDNode<"X86ISD::RCP28S_SAE", SDTFPBinOp>; 541def X86Ranges : SDNode<"X86ISD::VRANGES", SDTFPBinOpImm>; 542def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>; 543def X86Reduces : SDNode<"X86ISD::VREDUCES", SDTFPBinOpImm>; 544def X86GetMants : SDNode<"X86ISD::VGETMANTS", SDTFPBinOpImm>; 545def X86RangesSAE : SDNode<"X86ISD::VRANGES_SAE", SDTFPBinOpImm>; 546def X86RndScalesSAE : SDNode<"X86ISD::VRNDSCALES_SAE", SDTFPBinOpImm>; 547def X86ReducesSAE : SDNode<"X86ISD::VREDUCES_SAE", SDTFPBinOpImm>; 548def X86GetMantsSAE : SDNode<"X86ISD::VGETMANTS_SAE", SDTFPBinOpImm>; 549 550def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3, 551 [SDTCisSameAs<0, 1>, SDTCisVec<1>, 552 SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>, 553 SDTCisSameNumEltsAs<0, 3>]>, []>; 554def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3, 555 [SDTCisSameAs<0, 1>, SDTCisVec<1>, 556 SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>, 557 SDTCisSameNumEltsAs<0, 3>]>, []>; 558 559// vpshufbitqmb 560def X86Vpshufbitqmb : SDNode<"X86ISD::VPSHUFBITQMB", 561 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 562 SDTCisSameAs<1,2>, 563 SDTCVecEltisVT<0,i1>, 564 SDTCisSameNumEltsAs<0,1>]>>; 565 566def SDTintToFP: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 567 SDTCisSameAs<0,1>, SDTCisInt<2>]>; 568def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, 569 SDTCisSameAs<0,1>, SDTCisInt<2>, 570 SDTCisVT<3, i32>]>; 571 572def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 573 SDTCisInt<0>, SDTCisFP<1>]>; 574def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 575 SDTCisInt<0>, SDTCisFP<1>, 576 SDTCisVT<2, i32>]>; 577def SDTSFloatToInt: SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisFP<1>, 578 SDTCisVec<1>]>; 579def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>, 580 SDTCisVec<1>, SDTCisVT<2, i32>]>; 581 582def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 583 SDTCisFP<0>, SDTCisInt<1>]>; 584def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 585 SDTCisFP<0>, SDTCisInt<1>, 586 SDTCisVT<2, i32>]>; 587 588// Scalar 589def X86SintToFp : SDNode<"X86ISD::SCALAR_SINT_TO_FP", SDTintToFP>; 590def X86SintToFpRnd : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND", SDTintToFPRound>; 591def X86UintToFp : SDNode<"X86ISD::SCALAR_UINT_TO_FP", SDTintToFP>; 592def X86UintToFpRnd : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND", SDTintToFPRound>; 593 594def X86cvtts2Int : SDNode<"X86ISD::CVTTS2SI", SDTSFloatToInt>; 595def X86cvtts2UInt : SDNode<"X86ISD::CVTTS2UI", SDTSFloatToInt>; 596def X86cvtts2IntSAE : SDNode<"X86ISD::CVTTS2SI_SAE", SDTSFloatToInt>; 597def X86cvtts2UIntSAE : SDNode<"X86ISD::CVTTS2UI_SAE", SDTSFloatToInt>; 598 599def X86cvts2si : SDNode<"X86ISD::CVTS2SI", SDTSFloatToInt>; 600def X86cvts2usi : SDNode<"X86ISD::CVTS2UI", SDTSFloatToInt>; 601def X86cvts2siRnd : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>; 602def X86cvts2usiRnd : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>; 603 604// Vector with rounding mode 605 606// cvtt fp-to-int staff 607def X86cvttp2siSAE : SDNode<"X86ISD::CVTTP2SI_SAE", SDTFloatToInt>; 608def X86cvttp2uiSAE : SDNode<"X86ISD::CVTTP2UI_SAE", SDTFloatToInt>; 609 610def X86VSintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTVintToFPRound>; 611def X86VUintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTVintToFPRound>; 612 613// cvt fp-to-int staff 614def X86cvtp2IntRnd : SDNode<"X86ISD::CVTP2SI_RND", SDTFloatToIntRnd>; 615def X86cvtp2UIntRnd : SDNode<"X86ISD::CVTP2UI_RND", SDTFloatToIntRnd>; 616 617// Vector without rounding mode 618 619// cvtt fp-to-int staff 620def X86cvttp2si : SDNode<"X86ISD::CVTTP2SI", SDTFloatToInt>; 621def X86cvttp2ui : SDNode<"X86ISD::CVTTP2UI", SDTFloatToInt>; 622 623def X86VSintToFP : SDNode<"X86ISD::CVTSI2P", SDTVintToFP>; 624def X86VUintToFP : SDNode<"X86ISD::CVTUI2P", SDTVintToFP>; 625 626// cvt int-to-fp staff 627def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>; 628def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>; 629 630 631// Masked versions of above 632def SDTMVintToFP: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 633 SDTCisFP<0>, SDTCisInt<1>, 634 SDTCisSameSizeAs<0, 1>, 635 SDTCisSameAs<0, 2>, 636 SDTCVecEltisVT<3, i1>, 637 SDTCisSameNumEltsAs<1, 3>]>; 638def SDTMFloatToInt: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 639 SDTCisInt<0>, SDTCisFP<1>, 640 SDTCisSameSizeAs<0, 1>, 641 SDTCisSameAs<0, 2>, 642 SDTCVecEltisVT<3, i1>, 643 SDTCisSameNumEltsAs<1, 3>]>; 644 645def X86VMSintToFP : SDNode<"X86ISD::MCVTSI2P", SDTMVintToFP>; 646def X86VMUintToFP : SDNode<"X86ISD::MCVTUI2P", SDTMVintToFP>; 647 648def X86mcvtp2Int : SDNode<"X86ISD::MCVTP2SI", SDTMFloatToInt>; 649def X86mcvtp2UInt : SDNode<"X86ISD::MCVTP2UI", SDTMFloatToInt>; 650def X86mcvttp2si : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>; 651def X86mcvttp2ui : SDNode<"X86ISD::MCVTTP2UI", SDTMFloatToInt>; 652 653 654def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS", 655 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 656 SDTCVecEltisVT<1, i16>]> >; 657 658def X86cvtph2psSAE : SDNode<"X86ISD::CVTPH2PS_SAE", 659 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 660 SDTCVecEltisVT<1, i16>]> >; 661 662def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH", 663 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, 664 SDTCVecEltisVT<1, f32>, 665 SDTCisVT<2, i32>]> >; 666def X86mcvtps2ph : SDNode<"X86ISD::MCVTPS2PH", 667 SDTypeProfile<1, 4, [SDTCVecEltisVT<0, i16>, 668 SDTCVecEltisVT<1, f32>, 669 SDTCisVT<2, i32>, 670 SDTCisSameAs<0, 3>, 671 SDTCVecEltisVT<4, i1>, 672 SDTCisSameNumEltsAs<1, 4>]> >; 673def X86vfpextSAE : SDNode<"X86ISD::VFPEXT_SAE", 674 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, 675 SDTCVecEltisVT<1, f32>, 676 SDTCisOpSmallerThanOp<1, 0>]>>; 677def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND", 678 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, 679 SDTCVecEltisVT<1, f64>, 680 SDTCisOpSmallerThanOp<0, 1>, 681 SDTCisVT<2, i32>]>>; 682 683// cvt fp to bfloat16 684def X86cvtne2ps2bf16 : SDNode<"X86ISD::CVTNE2PS2BF16", 685 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 686 SDTCisSameAs<1,2>]>>; 687def X86mcvtneps2bf16 : SDNode<"X86ISD::MCVTNEPS2BF16", 688 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>, 689 SDTCVecEltisVT<1, f32>, 690 SDTCisSameAs<0, 2>, 691 SDTCVecEltisVT<3, i1>, 692 SDTCisSameNumEltsAs<1, 3>]>>; 693def X86cvtneps2bf16 : SDNode<"X86ISD::CVTNEPS2BF16", 694 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i16>, 695 SDTCVecEltisVT<1, f32>]>>; 696def X86dpbf16ps : SDNode<"X86ISD::DPBF16PS", 697 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 698 SDTCisSameAs<0,1>, 699 SDTCVecEltisVT<2, i32>, 700 SDTCisSameAs<2,3>]>>; 701 702// galois field arithmetic 703def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>; 704def X86GF2P8affineqb : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>; 705def X86GF2P8mulb : SDNode<"X86ISD::GF2P8MULB", SDTIntBinOp>; 706 707//===----------------------------------------------------------------------===// 708// SSE Complex Patterns 709//===----------------------------------------------------------------------===// 710 711// These are 'extloads' from a scalar to the low element of a vector, zeroing 712// the top elements. These are used for the SSE 'ss' and 'sd' instruction 713// forms. 714def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [], 715 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 716 SDNPWantRoot, SDNPWantParent]>; 717def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [], 718 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 719 SDNPWantRoot, SDNPWantParent]>; 720 721def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>; 722def sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>; 723 724//===----------------------------------------------------------------------===// 725// SSE pattern fragments 726//===----------------------------------------------------------------------===// 727 728// 128-bit load pattern fragments 729def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; 730def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; 731def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; 732def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>; 733def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>; 734def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>; 735 736// 256-bit load pattern fragments 737def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; 738def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; 739def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; 740def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>; 741def loadv16i16 : PatFrag<(ops node:$ptr), (v16i16 (load node:$ptr))>; 742def loadv32i8 : PatFrag<(ops node:$ptr), (v32i8 (load node:$ptr))>; 743 744// 512-bit load pattern fragments 745def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>; 746def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>; 747def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>; 748def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>; 749def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>; 750def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>; 751 752// 128-/256-/512-bit extload pattern fragments 753def extloadv2f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 754def extloadv4f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 755def extloadv8f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 756 757// Like 'store', but always requires vector size alignment. 758def alignedstore : PatFrag<(ops node:$val, node:$ptr), 759 (store node:$val, node:$ptr), [{ 760 auto *St = cast<StoreSDNode>(N); 761 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 762}]>; 763 764// Like 'load', but always requires vector size alignment. 765def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 766 auto *Ld = cast<LoadSDNode>(N); 767 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 768}]>; 769 770// 128-bit aligned load pattern fragments 771// NOTE: all 128-bit integer vector loads are promoted to v2i64 772def alignedloadv4f32 : PatFrag<(ops node:$ptr), 773 (v4f32 (alignedload node:$ptr))>; 774def alignedloadv2f64 : PatFrag<(ops node:$ptr), 775 (v2f64 (alignedload node:$ptr))>; 776def alignedloadv2i64 : PatFrag<(ops node:$ptr), 777 (v2i64 (alignedload node:$ptr))>; 778def alignedloadv4i32 : PatFrag<(ops node:$ptr), 779 (v4i32 (alignedload node:$ptr))>; 780def alignedloadv8i16 : PatFrag<(ops node:$ptr), 781 (v8i16 (alignedload node:$ptr))>; 782def alignedloadv16i8 : PatFrag<(ops node:$ptr), 783 (v16i8 (alignedload node:$ptr))>; 784 785// 256-bit aligned load pattern fragments 786// NOTE: all 256-bit integer vector loads are promoted to v4i64 787def alignedloadv8f32 : PatFrag<(ops node:$ptr), 788 (v8f32 (alignedload node:$ptr))>; 789def alignedloadv4f64 : PatFrag<(ops node:$ptr), 790 (v4f64 (alignedload node:$ptr))>; 791def alignedloadv4i64 : PatFrag<(ops node:$ptr), 792 (v4i64 (alignedload node:$ptr))>; 793def alignedloadv8i32 : PatFrag<(ops node:$ptr), 794 (v8i32 (alignedload node:$ptr))>; 795def alignedloadv16i16 : PatFrag<(ops node:$ptr), 796 (v16i16 (alignedload node:$ptr))>; 797def alignedloadv32i8 : PatFrag<(ops node:$ptr), 798 (v32i8 (alignedload node:$ptr))>; 799 800// 512-bit aligned load pattern fragments 801def alignedloadv16f32 : PatFrag<(ops node:$ptr), 802 (v16f32 (alignedload node:$ptr))>; 803def alignedloadv8f64 : PatFrag<(ops node:$ptr), 804 (v8f64 (alignedload node:$ptr))>; 805def alignedloadv8i64 : PatFrag<(ops node:$ptr), 806 (v8i64 (alignedload node:$ptr))>; 807def alignedloadv16i32 : PatFrag<(ops node:$ptr), 808 (v16i32 (alignedload node:$ptr))>; 809def alignedloadv32i16 : PatFrag<(ops node:$ptr), 810 (v32i16 (alignedload node:$ptr))>; 811def alignedloadv64i8 : PatFrag<(ops node:$ptr), 812 (v64i8 (alignedload node:$ptr))>; 813 814// Like 'load', but uses special alignment checks suitable for use in 815// memory operands in most SSE instructions, which are required to 816// be naturally aligned on some targets but not on others. If the subtarget 817// allows unaligned accesses, match any load, though this may require 818// setting a feature bit in the processor (on startup, for example). 819// Opteron 10h and later implement such a feature. 820def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 821 auto *Ld = cast<LoadSDNode>(N); 822 return Subtarget->hasSSEUnalignedMem() || 823 Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 824}]>; 825 826// 128-bit memop pattern fragments 827// NOTE: all 128-bit integer vector loads are promoted to v2i64 828def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; 829def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; 830def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; 831def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>; 832def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>; 833def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; 834 835def X86masked_gather : SDNode<"X86ISD::MGATHER", 836 SDTypeProfile<2, 3, [SDTCisVec<0>, 837 SDTCisVec<1>, SDTCisInt<1>, 838 SDTCisSameAs<0, 2>, 839 SDTCisSameAs<1, 3>, 840 SDTCisPtrTy<4>]>, 841 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 842 843def X86masked_scatter : SDNode<"X86ISD::MSCATTER", 844 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 845 SDTCisSameAs<0, 2>, 846 SDTCVecEltisVT<0, i1>, 847 SDTCisPtrTy<3>]>, 848 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 849 850def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 851 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 852 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 853 return Mgt->getIndex().getValueType() == MVT::v4i32; 854}]>; 855 856def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 857 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 858 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 859 return Mgt->getIndex().getValueType() == MVT::v8i32; 860}]>; 861 862def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 863 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 864 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 865 return Mgt->getIndex().getValueType() == MVT::v2i64; 866}]>; 867def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 868 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 869 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 870 return Mgt->getIndex().getValueType() == MVT::v4i64; 871}]>; 872def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 873 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 874 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 875 return Mgt->getIndex().getValueType() == MVT::v8i64; 876}]>; 877def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 878 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 879 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 880 return Mgt->getIndex().getValueType() == MVT::v16i32; 881}]>; 882 883def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 884 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 885 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 886 return Sc->getIndex().getValueType() == MVT::v2i64; 887}]>; 888 889def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 890 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 891 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 892 return Sc->getIndex().getValueType() == MVT::v4i32; 893}]>; 894 895def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 896 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 897 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 898 return Sc->getIndex().getValueType() == MVT::v4i64; 899}]>; 900 901def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 902 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 903 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 904 return Sc->getIndex().getValueType() == MVT::v8i32; 905}]>; 906 907def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 908 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 909 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 910 return Sc->getIndex().getValueType() == MVT::v8i64; 911}]>; 912def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 913 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 914 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 915 return Sc->getIndex().getValueType() == MVT::v16i32; 916}]>; 917 918// 128-bit bitconvert pattern fragments 919def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; 920def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; 921def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; 922def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; 923def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; 924def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; 925 926// 256-bit bitconvert pattern fragments 927def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>; 928def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>; 929def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>; 930def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>; 931def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>; 932def bc_v4f64 : PatFrag<(ops node:$in), (v4f64 (bitconvert node:$in))>; 933 934// 512-bit bitconvert pattern fragments 935def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>; 936def bc_v32i16 : PatFrag<(ops node:$in), (v32i16 (bitconvert node:$in))>; 937def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>; 938def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>; 939def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>; 940def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>; 941 942def X86vzload32 : PatFrag<(ops node:$src), 943 (X86vzld node:$src), [{ 944 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 4; 945}]>; 946 947def X86vzload64 : PatFrag<(ops node:$src), 948 (X86vzld node:$src), [{ 949 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8; 950}]>; 951 952def X86vextractstore64 : PatFrag<(ops node:$val, node:$ptr), 953 (X86vextractst node:$val, node:$ptr), [{ 954 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8; 955}]>; 956 957 958def fp32imm0 : PatLeaf<(f32 fpimm), [{ 959 return N->isExactlyValue(+0.0); 960}]>; 961 962def fp64imm0 : PatLeaf<(f64 fpimm), [{ 963 return N->isExactlyValue(+0.0); 964}]>; 965 966// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index 967// to VEXTRACTF128/VEXTRACTI128 imm. 968def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{ 969 return getExtractVEXTRACTImmediate(N, 128, SDLoc(N)); 970}]>; 971 972// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to 973// VINSERTF128/VINSERTI128 imm. 974def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{ 975 return getInsertVINSERTImmediate(N, 128, SDLoc(N)); 976}]>; 977 978// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index 979// to VEXTRACTF64x4 imm. 980def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{ 981 return getExtractVEXTRACTImmediate(N, 256, SDLoc(N)); 982}]>; 983 984// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to 985// VINSERTF64x4 imm. 986def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{ 987 return getInsertVINSERTImmediate(N, 256, SDLoc(N)); 988}]>; 989 990def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index), 991 (extract_subvector node:$bigvec, 992 node:$index), [{ 993 // Index 0 can be handled via extract_subreg. 994 return !isNullConstant(N->getOperand(1)); 995}], EXTRACT_get_vextract128_imm>; 996 997def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 998 node:$index), 999 (insert_subvector node:$bigvec, node:$smallvec, 1000 node:$index), [{}], 1001 INSERT_get_vinsert128_imm>; 1002 1003def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index), 1004 (extract_subvector node:$bigvec, 1005 node:$index), [{ 1006 // Index 0 can be handled via extract_subreg. 1007 return !isNullConstant(N->getOperand(1)); 1008}], EXTRACT_get_vextract256_imm>; 1009 1010def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 1011 node:$index), 1012 (insert_subvector node:$bigvec, node:$smallvec, 1013 node:$index), [{}], 1014 INSERT_get_vinsert256_imm>; 1015 1016def masked_load : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1017 (masked_ld node:$src1, node:$src2, node:$src3), [{ 1018 return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() && 1019 cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 1020}]>; 1021 1022def masked_load_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1023 (masked_load node:$src1, node:$src2, node:$src3), [{ 1024 // Use the node type to determine the size the alignment needs to match. 1025 // We can't use memory VT because type widening changes the node VT, but 1026 // not the memory VT. 1027 auto *Ld = cast<MaskedLoadSDNode>(N); 1028 return Ld->getAlignment() >= Ld->getValueType(0).getStoreSize(); 1029}]>; 1030 1031def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1032 (masked_ld node:$src1, node:$src2, node:$src3), [{ 1033 return cast<MaskedLoadSDNode>(N)->isExpandingLoad(); 1034}]>; 1035 1036// Masked store fragments. 1037// X86mstore can't be implemented in core DAG files because some targets 1038// do not support vector types (llvm-tblgen will fail). 1039def masked_store : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1040 (masked_st node:$src1, node:$src2, node:$src3), [{ 1041 return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) && 1042 (!cast<MaskedStoreSDNode>(N)->isCompressingStore()); 1043}]>; 1044 1045def masked_store_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1046 (masked_store node:$src1, node:$src2, node:$src3), [{ 1047 // Use the node type to determine the size the alignment needs to match. 1048 // We can't use memory VT because type widening changes the node VT, but 1049 // not the memory VT. 1050 auto *St = cast<MaskedStoreSDNode>(N); 1051 return St->getAlignment() >= St->getOperand(1).getValueType().getStoreSize(); 1052}]>; 1053 1054def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1055 (masked_st node:$src1, node:$src2, node:$src3), [{ 1056 return cast<MaskedStoreSDNode>(N)->isCompressingStore(); 1057}]>; 1058 1059// masked truncstore fragments 1060// X86mtruncstore can't be implemented in core DAG files because some targets 1061// doesn't support vector type ( llvm-tblgen will fail) 1062def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1063 (masked_st node:$src1, node:$src2, node:$src3), [{ 1064 return cast<MaskedStoreSDNode>(N)->isTruncatingStore(); 1065}]>; 1066def masked_truncstorevi8 : 1067 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1068 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1069 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1070}]>; 1071def masked_truncstorevi16 : 1072 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1073 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1074 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1075}]>; 1076def masked_truncstorevi32 : 1077 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1078 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1079 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1080}]>; 1081 1082def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES", SDTStore, 1083 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1084 1085def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS", SDTStore, 1086 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1087 1088def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES", SDTMaskedStore, 1089 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1090 1091def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS", SDTMaskedStore, 1092 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1093 1094def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr), 1095 (X86TruncSStore node:$val, node:$ptr), [{ 1096 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1097}]>; 1098 1099def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr), 1100 (X86TruncUSStore node:$val, node:$ptr), [{ 1101 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1102}]>; 1103 1104def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr), 1105 (X86TruncSStore node:$val, node:$ptr), [{ 1106 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1107}]>; 1108 1109def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr), 1110 (X86TruncUSStore node:$val, node:$ptr), [{ 1111 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1112}]>; 1113 1114def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr), 1115 (X86TruncSStore node:$val, node:$ptr), [{ 1116 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1117}]>; 1118 1119def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr), 1120 (X86TruncUSStore node:$val, node:$ptr), [{ 1121 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1122}]>; 1123 1124def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1125 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1126 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1127}]>; 1128 1129def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1130 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1131 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1132}]>; 1133 1134def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1135 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1136 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1137}]>; 1138 1139def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1140 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1141 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1142}]>; 1143 1144def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1145 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1146 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1147}]>; 1148 1149def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1150 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1151 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1152}]>; 1153