1//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file provides pattern fragments useful for SIMD instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// MMX specific DAG Nodes. 15//===----------------------------------------------------------------------===// 16 17// Low word of MMX to GPR. 18def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1, 19 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>; 20// GPR to low word of MMX. 21def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1, 22 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>; 23 24//===----------------------------------------------------------------------===// 25// MMX Pattern Fragments 26//===----------------------------------------------------------------------===// 27 28def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>; 29 30//===----------------------------------------------------------------------===// 31// SSE specific DAG Nodes. 32//===----------------------------------------------------------------------===// 33 34def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, 35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 36 SDTCisVT<3, i8>]>; 37 38def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; 39def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; 40def X86fmins : SDNode<"X86ISD::FMINS", SDTFPBinOp>; 41def X86fmaxs : SDNode<"X86ISD::FMAXS", SDTFPBinOp>; 42 43// Commutative and Associative FMIN and FMAX. 44def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp, 45 [SDNPCommutative, SDNPAssociative]>; 46def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp, 47 [SDNPCommutative, SDNPAssociative]>; 48 49def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, 50 [SDNPCommutative, SDNPAssociative]>; 51def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, 52 [SDNPCommutative, SDNPAssociative]>; 53def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, 54 [SDNPCommutative, SDNPAssociative]>; 55def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp>; 56def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; 57def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; 58def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; 59def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; 60def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>; 61def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>; 62def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; 63def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; 64def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>; 65def X86pshufb : SDNode<"X86ISD::PSHUFB", 66 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>, 67 SDTCisSameAs<0,2>]>>; 68def X86psadbw : SDNode<"X86ISD::PSADBW", 69 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 70 SDTCVecEltisVT<1, i8>, 71 SDTCisSameSizeAs<0,1>, 72 SDTCisSameAs<1,2>]>, [SDNPCommutative]>; 73def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW", 74 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>, 75 SDTCVecEltisVT<1, i8>, 76 SDTCisSameSizeAs<0,1>, 77 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>>; 78def X86andnp : SDNode<"X86ISD::ANDNP", 79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 80 SDTCisSameAs<0,2>]>>; 81def X86multishift : SDNode<"X86ISD::MULTISHIFT", 82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 83 SDTCisSameAs<1,2>]>>; 84def X86pextrb : SDNode<"X86ISD::PEXTRB", 85 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>, 86 SDTCisPtrTy<2>]>>; 87def X86pextrw : SDNode<"X86ISD::PEXTRW", 88 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>, 89 SDTCisPtrTy<2>]>>; 90def X86pinsrb : SDNode<"X86ISD::PINSRB", 91 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 92 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 93def X86pinsrw : SDNode<"X86ISD::PINSRW", 94 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, 95 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 96def X86insertps : SDNode<"X86ISD::INSERTPS", 97 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, 98 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>; 99def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", 100 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; 101 102def X86vzld : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, 103 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 104def X86vextractst : SDNode<"X86ISD::VEXTRACT_STORE", SDTStore, 105 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 106def X86VBroadcastld : SDNode<"X86ISD::VBROADCAST_LOAD", SDTLoad, 107 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 108 109def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 110 SDTCisInt<0>, SDTCisInt<1>, 111 SDTCisOpSmallerThanOp<0, 1>]>; 112def SDTVmtrunc : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 113 SDTCisInt<0>, SDTCisInt<1>, 114 SDTCisOpSmallerThanOp<0, 1>, 115 SDTCisSameAs<0, 2>, 116 SDTCVecEltisVT<3, i1>, 117 SDTCisSameNumEltsAs<1, 3>]>; 118 119def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>; 120def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>; 121def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>; 122def X86vmtrunc : SDNode<"X86ISD::VMTRUNC", SDTVmtrunc>; 123def X86vmtruncs : SDNode<"X86ISD::VMTRUNCS", SDTVmtrunc>; 124def X86vmtruncus : SDNode<"X86ISD::VMTRUNCUS", SDTVmtrunc>; 125 126def X86vfpext : SDNode<"X86ISD::VFPEXT", 127 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, 128 SDTCVecEltisVT<1, f32>, 129 SDTCisSameSizeAs<0, 1>]>>; 130def X86vfpround: SDNode<"X86ISD::VFPROUND", 131 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 132 SDTCVecEltisVT<1, f64>, 133 SDTCisOpSmallerThanOp<0, 1>]>>; 134 135def X86frounds : SDNode<"X86ISD::VFPROUNDS", 136 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, 137 SDTCisSameAs<0, 1>, 138 SDTCVecEltisVT<2, f64>, 139 SDTCisSameSizeAs<0, 2>]>>; 140 141def X86froundsRnd: SDNode<"X86ISD::VFPROUNDS_RND", 142 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 143 SDTCisSameAs<0, 1>, 144 SDTCVecEltisVT<2, f64>, 145 SDTCisSameSizeAs<0, 2>, 146 SDTCisVT<3, i32>]>>; 147 148def X86fpexts : SDNode<"X86ISD::VFPEXTS", 149 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>, 150 SDTCisSameAs<0, 1>, 151 SDTCVecEltisVT<2, f32>, 152 SDTCisSameSizeAs<0, 2>]>>; 153def X86fpextsSAE : SDNode<"X86ISD::VFPEXTS_SAE", 154 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>, 155 SDTCisSameAs<0, 1>, 156 SDTCVecEltisVT<2, f32>, 157 SDTCisSameSizeAs<0, 2>]>>; 158 159def X86vmfpround: SDNode<"X86ISD::VMFPROUND", 160 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 161 SDTCVecEltisVT<1, f64>, 162 SDTCisSameSizeAs<0, 1>, 163 SDTCisSameAs<0, 2>, 164 SDTCVecEltisVT<3, i1>, 165 SDTCisSameNumEltsAs<1, 3>]>>; 166 167def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 168 SDTCisVT<2, i8>, SDTCisInt<0>]>; 169 170def X86vshldq : SDNode<"X86ISD::VSHLDQ", X86vshiftimm>; 171def X86vshrdq : SDNode<"X86ISD::VSRLDQ", X86vshiftimm>; 172def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>; 173def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>; 174def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>; 175 176def X86CmpMaskCC : 177 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>, 178 SDTCisVec<1>, SDTCisSameAs<2, 1>, 179 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>; 180def X86CmpMaskCCScalar : 181 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>, 182 SDTCisVT<3, i8>]>; 183 184def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>; 185def X86cmpmSAE : SDNode<"X86ISD::CMPM_SAE", X86CmpMaskCC>; 186def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>; 187def X86cmpmsSAE : SDNode<"X86ISD::FSETCCM_SAE", X86CmpMaskCCScalar>; 188 189def X86phminpos: SDNode<"X86ISD::PHMINPOS", 190 SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>; 191 192def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 193 SDTCisVec<2>, SDTCisInt<0>, 194 SDTCisInt<2>]>; 195 196def X86vshl : SDNode<"X86ISD::VSHL", X86vshiftuniform>; 197def X86vsrl : SDNode<"X86ISD::VSRL", X86vshiftuniform>; 198def X86vsra : SDNode<"X86ISD::VSRA", X86vshiftuniform>; 199 200def X86vshiftvariable : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 201 SDTCisSameAs<0,2>, SDTCisInt<0>]>; 202 203def X86vshlv : SDNode<"X86ISD::VSHLV", X86vshiftvariable>; 204def X86vsrlv : SDNode<"X86ISD::VSRLV", X86vshiftvariable>; 205def X86vsrav : SDNode<"X86ISD::VSRAV", X86vshiftvariable>; 206 207def X86vshli : SDNode<"X86ISD::VSHLI", X86vshiftimm>; 208def X86vsrli : SDNode<"X86ISD::VSRLI", X86vshiftimm>; 209def X86vsrai : SDNode<"X86ISD::VSRAI", X86vshiftimm>; 210 211def X86kshiftl : SDNode<"X86ISD::KSHIFTL", 212 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 213 SDTCisSameAs<0, 1>, 214 SDTCisVT<2, i8>]>>; 215def X86kshiftr : SDNode<"X86ISD::KSHIFTR", 216 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 217 SDTCisSameAs<0, 1>, 218 SDTCisVT<2, i8>]>>; 219 220def X86kadd : SDNode<"X86ISD::KADD", SDTIntBinOp, [SDNPCommutative]>; 221 222def X86vrotli : SDNode<"X86ISD::VROTLI", X86vshiftimm>; 223def X86vrotri : SDNode<"X86ISD::VROTRI", X86vshiftimm>; 224 225def X86vpshl : SDNode<"X86ISD::VPSHL", X86vshiftvariable>; 226def X86vpsha : SDNode<"X86ISD::VPSHA", X86vshiftvariable>; 227 228def X86vpcom : SDNode<"X86ISD::VPCOM", 229 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 230 SDTCisSameAs<0,2>, 231 SDTCisVT<3, i8>, SDTCisInt<0>]>>; 232def X86vpcomu : SDNode<"X86ISD::VPCOMU", 233 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 234 SDTCisSameAs<0,2>, 235 SDTCisVT<3, i8>, SDTCisInt<0>]>>; 236def X86vpermil2 : SDNode<"X86ISD::VPERMIL2", 237 SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>, 238 SDTCisSameAs<0,2>, 239 SDTCisFP<0>, SDTCisInt<3>, 240 SDTCisSameNumEltsAs<0, 3>, 241 SDTCisSameSizeAs<0,3>, 242 SDTCisVT<4, i8>]>>; 243def X86vpperm : SDNode<"X86ISD::VPPERM", 244 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 245 SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>; 246 247def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 248 SDTCisVec<1>, 249 SDTCisSameAs<2, 1>]>; 250 251def X86mulhrs : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>; 252def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>; 253def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; 254def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>; 255def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>; 256def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>; 257 258def X86movmsk : SDNode<"X86ISD::MOVMSK", 259 SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>; 260 261def X86selects : SDNode<"X86ISD::SELECTS", 262 SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>, 263 SDTCisSameAs<0, 2>, 264 SDTCisSameAs<2, 3>]>>; 265 266def X86pmuludq : SDNode<"X86ISD::PMULUDQ", 267 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 268 SDTCisSameAs<0,1>, 269 SDTCisSameAs<1,2>]>, 270 [SDNPCommutative]>; 271def X86pmuldq : SDNode<"X86ISD::PMULDQ", 272 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 273 SDTCisSameAs<0,1>, 274 SDTCisSameAs<1,2>]>, 275 [SDNPCommutative]>; 276 277def X86extrqi : SDNode<"X86ISD::EXTRQI", 278 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, 279 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>; 280def X86insertqi : SDNode<"X86ISD::INSERTQI", 281 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, 282 SDTCisSameAs<1,2>, SDTCisVT<3, i8>, 283 SDTCisVT<4, i8>]>>; 284 285// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get 286// translated into one of the target nodes below during lowering. 287// Note: this is a work in progress... 288def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 289def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 290 SDTCisSameAs<0,2>]>; 291def SDTShuff2OpFP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 292 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>; 293 294def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 295 SDTCisFP<0>, SDTCisInt<2>, 296 SDTCisSameNumEltsAs<0,2>, 297 SDTCisSameSizeAs<0,2>]>; 298def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>, 299 SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>; 300def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 301 SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>; 302def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, 303 SDTCisSameAs<0,1>, 304 SDTCisSameAs<0,2>, 305 SDTCisVT<3, i32>]>; 306def SDTFPTernaryOpImm: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisSameAs<0,1>, 307 SDTCisSameAs<0,2>, 308 SDTCisInt<3>, 309 SDTCisSameSizeAs<0, 3>, 310 SDTCisSameNumEltsAs<0, 3>, 311 SDTCisVT<4, i32>]>; 312def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>, 313 SDTCisSameAs<0,1>, 314 SDTCisVT<2, i32>]>; 315 316def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 317def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>, 318 SDTCisInt<0>, SDTCisInt<1>]>; 319 320def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 321 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>; 322 323def SDTTernlog : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>, 324 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, 325 SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>; 326 327def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc. 328 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>; 329 330def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc. 331 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>; 332 333def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>, 334 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, 335 SDTCisFP<0>, SDTCisVT<4, i32>]>; 336 337def X86PAlignr : SDNode<"X86ISD::PALIGNR", 338 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>, 339 SDTCisSameAs<0,1>, 340 SDTCisSameAs<0,2>, 341 SDTCisVT<3, i8>]>>; 342def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>; 343 344def X86VShld : SDNode<"X86ISD::VSHLD", SDTShuff3OpI>; 345def X86VShrd : SDNode<"X86ISD::VSHRD", SDTShuff3OpI>; 346def X86VShldv : SDNode<"X86ISD::VSHLDV", 347 SDTypeProfile<1, 3, [SDTCisVec<0>, 348 SDTCisSameAs<0,1>, 349 SDTCisSameAs<0,2>, 350 SDTCisSameAs<0,3>]>>; 351def X86VShrdv : SDNode<"X86ISD::VSHRDV", 352 SDTypeProfile<1, 3, [SDTCisVec<0>, 353 SDTCisSameAs<0,1>, 354 SDTCisSameAs<0,2>, 355 SDTCisSameAs<0,3>]>>; 356 357def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>; 358 359def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; 360def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; 361def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; 362 363def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>; 364def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>; 365 366def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>; 367def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; 368def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; 369 370def X86Movsd : SDNode<"X86ISD::MOVSD", 371 SDTypeProfile<1, 2, [SDTCisVT<0, v2f64>, 372 SDTCisVT<1, v2f64>, 373 SDTCisVT<2, v2f64>]>>; 374def X86Movss : SDNode<"X86ISD::MOVSS", 375 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 376 SDTCisVT<1, v4f32>, 377 SDTCisVT<2, v4f32>]>>; 378 379def X86Movlhps : SDNode<"X86ISD::MOVLHPS", 380 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 381 SDTCisVT<1, v4f32>, 382 SDTCisVT<2, v4f32>]>>; 383def X86Movhlps : SDNode<"X86ISD::MOVHLPS", 384 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 385 SDTCisVT<1, v4f32>, 386 SDTCisVT<2, v4f32>]>>; 387 388def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>, 389 SDTCisVec<1>, SDTCisInt<1>, 390 SDTCisSameSizeAs<0,1>, 391 SDTCisSameAs<1,2>, 392 SDTCisOpSmallerThanOp<0, 1>]>; 393def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>; 394def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>; 395 396def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>; 397def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>; 398 399def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW", 400 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, 401 SDTCVecEltisVT<1, i8>, 402 SDTCisSameSizeAs<0,1>, 403 SDTCisSameAs<1,2>]>>; 404def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD", 405 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>, 406 SDTCVecEltisVT<1, i16>, 407 SDTCisSameSizeAs<0,1>, 408 SDTCisSameAs<1,2>]>, 409 [SDNPCommutative]>; 410 411def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>; 412def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>; 413def X86VPermv : SDNode<"X86ISD::VPERMV", 414 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>, 415 SDTCisSameNumEltsAs<0,1>, 416 SDTCisSameSizeAs<0,1>, 417 SDTCisSameAs<0,2>]>>; 418def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>; 419def X86VPermt2 : SDNode<"X86ISD::VPERMV3", 420 SDTypeProfile<1, 3, [SDTCisVec<0>, 421 SDTCisSameAs<0,1>, SDTCisInt<2>, 422 SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>, 423 SDTCisSameSizeAs<0,2>, 424 SDTCisSameAs<0,3>]>, []>; 425 426def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>; 427 428def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>; 429 430def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImm>; 431def X86VFixupimmSAE : SDNode<"X86ISD::VFIXUPIMM_SAE", SDTFPTernaryOpImm>; 432def X86VFixupimms : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImm>; 433def X86VFixupimmSAEs : SDNode<"X86ISD::VFIXUPIMMS_SAE", SDTFPTernaryOpImm>; 434def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImm>; 435def X86VRangeSAE : SDNode<"X86ISD::VRANGE_SAE", SDTFPBinOpImm>; 436def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImm>; 437def X86VReduceSAE : SDNode<"X86ISD::VREDUCE_SAE", SDTFPUnaryOpImm>; 438def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImm>; 439def X86VRndScaleSAE: SDNode<"X86ISD::VRNDSCALE_SAE", SDTFPUnaryOpImm>; 440def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImm>; 441def X86VGetMantSAE : SDNode<"X86ISD::VGETMANT_SAE", SDTFPUnaryOpImm>; 442def X86Vfpclass : SDNode<"X86ISD::VFPCLASS", 443 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 444 SDTCisFP<1>, 445 SDTCisSameNumEltsAs<0,1>, 446 SDTCisVT<2, i32>]>, []>; 447def X86Vfpclasss : SDNode<"X86ISD::VFPCLASSS", 448 SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>, 449 SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>; 450 451def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST", 452 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 453 SDTCisSubVecOfVec<1, 0>]>, []>; 454 455def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; 456def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>; 457 458def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>; 459def X86Blendv : SDNode<"X86ISD::BLENDV", 460 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<1>, 461 SDTCisSameAs<0, 2>, 462 SDTCisSameAs<2, 3>, 463 SDTCisSameNumEltsAs<0, 1>, 464 SDTCisSameSizeAs<0, 1>]>>; 465 466def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>; 467 468def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>; 469def X86fadds : SDNode<"X86ISD::FADDS", SDTFPBinOp>; 470def X86faddRnds : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>; 471def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>; 472def X86fsubs : SDNode<"X86ISD::FSUBS", SDTFPBinOp>; 473def X86fsubRnds : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>; 474def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>; 475def X86fmuls : SDNode<"X86ISD::FMULS", SDTFPBinOp>; 476def X86fmulRnds : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>; 477def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>; 478def X86fdivs : SDNode<"X86ISD::FDIVS", SDTFPBinOp>; 479def X86fdivRnds : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>; 480def X86fmaxSAE : SDNode<"X86ISD::FMAX_SAE", SDTFPBinOp>; 481def X86fmaxSAEs : SDNode<"X86ISD::FMAXS_SAE", SDTFPBinOp>; 482def X86fminSAE : SDNode<"X86ISD::FMIN_SAE", SDTFPBinOp>; 483def X86fminSAEs : SDNode<"X86ISD::FMINS_SAE", SDTFPBinOp>; 484def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOp>; 485def X86scalefRnd : SDNode<"X86ISD::SCALEF_RND", SDTFPBinOpRound>; 486def X86scalefs : SDNode<"X86ISD::SCALEFS", SDTFPBinOp>; 487def X86scalefsRnd: SDNode<"X86ISD::SCALEFS_RND", SDTFPBinOpRound>; 488def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>; 489def X86fsqrts : SDNode<"X86ISD::FSQRTS", SDTFPBinOp>; 490def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>; 491def X86fgetexp : SDNode<"X86ISD::FGETEXP", SDTFPUnaryOp>; 492def X86fgetexpSAE : SDNode<"X86ISD::FGETEXP_SAE", SDTFPUnaryOp>; 493def X86fgetexps : SDNode<"X86ISD::FGETEXPS", SDTFPBinOp>; 494def X86fgetexpSAEs : SDNode<"X86ISD::FGETEXPS_SAE", SDTFPBinOp>; 495 496def X86Fmadd : SDNode<"ISD::FMA", SDTFPTernaryOp, [SDNPCommutative]>; 497def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFPTernaryOp, [SDNPCommutative]>; 498def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>; 499def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFPTernaryOp, [SDNPCommutative]>; 500def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFPTernaryOp, [SDNPCommutative]>; 501def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFPTernaryOp, [SDNPCommutative]>; 502 503def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound, [SDNPCommutative]>; 504def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound, [SDNPCommutative]>; 505def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound, [SDNPCommutative]>; 506def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound, [SDNPCommutative]>; 507def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound, [SDNPCommutative]>; 508def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound, [SDNPCommutative]>; 509 510def X86vp2intersect : SDNode<"X86ISD::VP2INTERSECT", 511 SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 512 SDTCisVec<1>, SDTCisSameAs<1, 2>]>>; 513 514def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>, 515 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 516def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>; 517def x86vpmadd52h : SDNode<"X86ISD::VPMADD52H", SDTIFma, [SDNPCommutative]>; 518 519def X86rsqrt14 : SDNode<"X86ISD::RSQRT14", SDTFPUnaryOp>; 520def X86rcp14 : SDNode<"X86ISD::RCP14", SDTFPUnaryOp>; 521 522// VNNI 523def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 524 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 525def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnni>; 526def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>; 527def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnni>; 528def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>; 529 530def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOp>; 531def X86rsqrt28SAE: SDNode<"X86ISD::RSQRT28_SAE", SDTFPUnaryOp>; 532def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOp>; 533def X86rcp28SAE : SDNode<"X86ISD::RCP28_SAE", SDTFPUnaryOp>; 534def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOp>; 535def X86exp2SAE : SDNode<"X86ISD::EXP2_SAE", SDTFPUnaryOp>; 536 537def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>; 538def X86rcp14s : SDNode<"X86ISD::RCP14S", SDTFPBinOp>; 539def X86rsqrt28s : SDNode<"X86ISD::RSQRT28S", SDTFPBinOp>; 540def X86rsqrt28SAEs : SDNode<"X86ISD::RSQRT28S_SAE", SDTFPBinOp>; 541def X86rcp28s : SDNode<"X86ISD::RCP28S", SDTFPBinOp>; 542def X86rcp28SAEs : SDNode<"X86ISD::RCP28S_SAE", SDTFPBinOp>; 543def X86Ranges : SDNode<"X86ISD::VRANGES", SDTFPBinOpImm>; 544def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>; 545def X86Reduces : SDNode<"X86ISD::VREDUCES", SDTFPBinOpImm>; 546def X86GetMants : SDNode<"X86ISD::VGETMANTS", SDTFPBinOpImm>; 547def X86RangesSAE : SDNode<"X86ISD::VRANGES_SAE", SDTFPBinOpImm>; 548def X86RndScalesSAE : SDNode<"X86ISD::VRNDSCALES_SAE", SDTFPBinOpImm>; 549def X86ReducesSAE : SDNode<"X86ISD::VREDUCES_SAE", SDTFPBinOpImm>; 550def X86GetMantsSAE : SDNode<"X86ISD::VGETMANTS_SAE", SDTFPBinOpImm>; 551 552def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3, 553 [SDTCisSameAs<0, 1>, SDTCisVec<1>, 554 SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>, 555 SDTCisSameNumEltsAs<0, 3>]>, []>; 556def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3, 557 [SDTCisSameAs<0, 1>, SDTCisVec<1>, 558 SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>, 559 SDTCisSameNumEltsAs<0, 3>]>, []>; 560 561// vpshufbitqmb 562def X86Vpshufbitqmb : SDNode<"X86ISD::VPSHUFBITQMB", 563 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 564 SDTCisSameAs<1,2>, 565 SDTCVecEltisVT<0,i1>, 566 SDTCisSameNumEltsAs<0,1>]>>; 567 568def SDTintToFP: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 569 SDTCisSameAs<0,1>, SDTCisInt<2>]>; 570def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, 571 SDTCisSameAs<0,1>, SDTCisInt<2>, 572 SDTCisVT<3, i32>]>; 573 574def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 575 SDTCisInt<0>, SDTCisFP<1>]>; 576def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 577 SDTCisInt<0>, SDTCisFP<1>, 578 SDTCisVT<2, i32>]>; 579def SDTSFloatToInt: SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisFP<1>, 580 SDTCisVec<1>]>; 581def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>, 582 SDTCisVec<1>, SDTCisVT<2, i32>]>; 583 584def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 585 SDTCisFP<0>, SDTCisInt<1>]>; 586def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 587 SDTCisFP<0>, SDTCisInt<1>, 588 SDTCisVT<2, i32>]>; 589 590// Scalar 591def X86SintToFp : SDNode<"X86ISD::SCALAR_SINT_TO_FP", SDTintToFP>; 592def X86SintToFpRnd : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND", SDTintToFPRound>; 593def X86UintToFp : SDNode<"X86ISD::SCALAR_UINT_TO_FP", SDTintToFP>; 594def X86UintToFpRnd : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND", SDTintToFPRound>; 595 596def X86cvtts2Int : SDNode<"X86ISD::CVTTS2SI", SDTSFloatToInt>; 597def X86cvtts2UInt : SDNode<"X86ISD::CVTTS2UI", SDTSFloatToInt>; 598def X86cvtts2IntSAE : SDNode<"X86ISD::CVTTS2SI_SAE", SDTSFloatToInt>; 599def X86cvtts2UIntSAE : SDNode<"X86ISD::CVTTS2UI_SAE", SDTSFloatToInt>; 600 601def X86cvts2si : SDNode<"X86ISD::CVTS2SI", SDTSFloatToInt>; 602def X86cvts2usi : SDNode<"X86ISD::CVTS2UI", SDTSFloatToInt>; 603def X86cvts2siRnd : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>; 604def X86cvts2usiRnd : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>; 605 606// Vector with rounding mode 607 608// cvtt fp-to-int staff 609def X86cvttp2siSAE : SDNode<"X86ISD::CVTTP2SI_SAE", SDTFloatToInt>; 610def X86cvttp2uiSAE : SDNode<"X86ISD::CVTTP2UI_SAE", SDTFloatToInt>; 611 612def X86VSintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTVintToFPRound>; 613def X86VUintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTVintToFPRound>; 614 615// cvt fp-to-int staff 616def X86cvtp2IntRnd : SDNode<"X86ISD::CVTP2SI_RND", SDTFloatToIntRnd>; 617def X86cvtp2UIntRnd : SDNode<"X86ISD::CVTP2UI_RND", SDTFloatToIntRnd>; 618 619// Vector without rounding mode 620 621// cvtt fp-to-int staff 622def X86cvttp2si : SDNode<"X86ISD::CVTTP2SI", SDTFloatToInt>; 623def X86cvttp2ui : SDNode<"X86ISD::CVTTP2UI", SDTFloatToInt>; 624 625def X86VSintToFP : SDNode<"X86ISD::CVTSI2P", SDTVintToFP>; 626def X86VUintToFP : SDNode<"X86ISD::CVTUI2P", SDTVintToFP>; 627 628// cvt int-to-fp staff 629def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>; 630def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>; 631 632 633// Masked versions of above 634def SDTMVintToFP: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 635 SDTCisFP<0>, SDTCisInt<1>, 636 SDTCisSameSizeAs<0, 1>, 637 SDTCisSameAs<0, 2>, 638 SDTCVecEltisVT<3, i1>, 639 SDTCisSameNumEltsAs<1, 3>]>; 640def SDTMFloatToInt: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 641 SDTCisInt<0>, SDTCisFP<1>, 642 SDTCisSameSizeAs<0, 1>, 643 SDTCisSameAs<0, 2>, 644 SDTCVecEltisVT<3, i1>, 645 SDTCisSameNumEltsAs<1, 3>]>; 646 647def X86VMSintToFP : SDNode<"X86ISD::MCVTSI2P", SDTMVintToFP>; 648def X86VMUintToFP : SDNode<"X86ISD::MCVTUI2P", SDTMVintToFP>; 649 650def X86mcvtp2Int : SDNode<"X86ISD::MCVTP2SI", SDTMFloatToInt>; 651def X86mcvtp2UInt : SDNode<"X86ISD::MCVTP2UI", SDTMFloatToInt>; 652def X86mcvttp2si : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>; 653def X86mcvttp2ui : SDNode<"X86ISD::MCVTTP2UI", SDTMFloatToInt>; 654 655 656def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS", 657 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 658 SDTCVecEltisVT<1, i16>]> >; 659 660def X86cvtph2psSAE : SDNode<"X86ISD::CVTPH2PS_SAE", 661 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 662 SDTCVecEltisVT<1, i16>]> >; 663 664def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH", 665 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, 666 SDTCVecEltisVT<1, f32>, 667 SDTCisVT<2, i32>]> >; 668def X86mcvtps2ph : SDNode<"X86ISD::MCVTPS2PH", 669 SDTypeProfile<1, 4, [SDTCVecEltisVT<0, i16>, 670 SDTCVecEltisVT<1, f32>, 671 SDTCisVT<2, i32>, 672 SDTCisSameAs<0, 3>, 673 SDTCVecEltisVT<4, i1>, 674 SDTCisSameNumEltsAs<1, 4>]> >; 675def X86vfpextSAE : SDNode<"X86ISD::VFPEXT_SAE", 676 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, 677 SDTCVecEltisVT<1, f32>, 678 SDTCisOpSmallerThanOp<1, 0>]>>; 679def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND", 680 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, 681 SDTCVecEltisVT<1, f64>, 682 SDTCisOpSmallerThanOp<0, 1>, 683 SDTCisVT<2, i32>]>>; 684 685// cvt fp to bfloat16 686def X86cvtne2ps2bf16 : SDNode<"X86ISD::CVTNE2PS2BF16", 687 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 688 SDTCisSameAs<1,2>]>>; 689def X86mcvtneps2bf16 : SDNode<"X86ISD::MCVTNEPS2BF16", 690 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>, 691 SDTCVecEltisVT<1, f32>, 692 SDTCisSameAs<0, 2>, 693 SDTCVecEltisVT<3, i1>, 694 SDTCisSameNumEltsAs<1, 3>]>>; 695def X86cvtneps2bf16 : SDNode<"X86ISD::CVTNEPS2BF16", 696 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i16>, 697 SDTCVecEltisVT<1, f32>]>>; 698def X86dpbf16ps : SDNode<"X86ISD::DPBF16PS", 699 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 700 SDTCisSameAs<0,1>, 701 SDTCVecEltisVT<2, i32>, 702 SDTCisSameAs<2,3>]>>; 703 704// galois field arithmetic 705def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>; 706def X86GF2P8affineqb : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>; 707def X86GF2P8mulb : SDNode<"X86ISD::GF2P8MULB", SDTIntBinOp>; 708 709//===----------------------------------------------------------------------===// 710// SSE Complex Patterns 711//===----------------------------------------------------------------------===// 712 713// These are 'extloads' from a scalar to the low element of a vector, zeroing 714// the top elements. These are used for the SSE 'ss' and 'sd' instruction 715// forms. 716def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [], 717 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 718 SDNPWantRoot, SDNPWantParent]>; 719def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [], 720 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 721 SDNPWantRoot, SDNPWantParent]>; 722 723def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>; 724def sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>; 725 726//===----------------------------------------------------------------------===// 727// SSE pattern fragments 728//===----------------------------------------------------------------------===// 729 730// 128-bit load pattern fragments 731def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; 732def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; 733def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; 734def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>; 735def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>; 736def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>; 737 738// 256-bit load pattern fragments 739def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; 740def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; 741def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; 742def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>; 743def loadv16i16 : PatFrag<(ops node:$ptr), (v16i16 (load node:$ptr))>; 744def loadv32i8 : PatFrag<(ops node:$ptr), (v32i8 (load node:$ptr))>; 745 746// 512-bit load pattern fragments 747def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>; 748def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>; 749def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>; 750def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>; 751def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>; 752def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>; 753 754// 128-/256-/512-bit extload pattern fragments 755def extloadv2f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 756def extloadv4f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 757def extloadv8f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 758 759// Like 'store', but always requires vector size alignment. 760def alignedstore : PatFrag<(ops node:$val, node:$ptr), 761 (store node:$val, node:$ptr), [{ 762 auto *St = cast<StoreSDNode>(N); 763 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 764}]>; 765 766// Like 'load', but always requires vector size alignment. 767def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 768 auto *Ld = cast<LoadSDNode>(N); 769 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 770}]>; 771 772// 128-bit aligned load pattern fragments 773// NOTE: all 128-bit integer vector loads are promoted to v2i64 774def alignedloadv4f32 : PatFrag<(ops node:$ptr), 775 (v4f32 (alignedload node:$ptr))>; 776def alignedloadv2f64 : PatFrag<(ops node:$ptr), 777 (v2f64 (alignedload node:$ptr))>; 778def alignedloadv2i64 : PatFrag<(ops node:$ptr), 779 (v2i64 (alignedload node:$ptr))>; 780def alignedloadv4i32 : PatFrag<(ops node:$ptr), 781 (v4i32 (alignedload node:$ptr))>; 782def alignedloadv8i16 : PatFrag<(ops node:$ptr), 783 (v8i16 (alignedload node:$ptr))>; 784def alignedloadv16i8 : PatFrag<(ops node:$ptr), 785 (v16i8 (alignedload node:$ptr))>; 786 787// 256-bit aligned load pattern fragments 788// NOTE: all 256-bit integer vector loads are promoted to v4i64 789def alignedloadv8f32 : PatFrag<(ops node:$ptr), 790 (v8f32 (alignedload node:$ptr))>; 791def alignedloadv4f64 : PatFrag<(ops node:$ptr), 792 (v4f64 (alignedload node:$ptr))>; 793def alignedloadv4i64 : PatFrag<(ops node:$ptr), 794 (v4i64 (alignedload node:$ptr))>; 795def alignedloadv8i32 : PatFrag<(ops node:$ptr), 796 (v8i32 (alignedload node:$ptr))>; 797def alignedloadv16i16 : PatFrag<(ops node:$ptr), 798 (v16i16 (alignedload node:$ptr))>; 799def alignedloadv32i8 : PatFrag<(ops node:$ptr), 800 (v32i8 (alignedload node:$ptr))>; 801 802// 512-bit aligned load pattern fragments 803def alignedloadv16f32 : PatFrag<(ops node:$ptr), 804 (v16f32 (alignedload node:$ptr))>; 805def alignedloadv8f64 : PatFrag<(ops node:$ptr), 806 (v8f64 (alignedload node:$ptr))>; 807def alignedloadv8i64 : PatFrag<(ops node:$ptr), 808 (v8i64 (alignedload node:$ptr))>; 809def alignedloadv16i32 : PatFrag<(ops node:$ptr), 810 (v16i32 (alignedload node:$ptr))>; 811def alignedloadv32i16 : PatFrag<(ops node:$ptr), 812 (v32i16 (alignedload node:$ptr))>; 813def alignedloadv64i8 : PatFrag<(ops node:$ptr), 814 (v64i8 (alignedload node:$ptr))>; 815 816// Like 'load', but uses special alignment checks suitable for use in 817// memory operands in most SSE instructions, which are required to 818// be naturally aligned on some targets but not on others. If the subtarget 819// allows unaligned accesses, match any load, though this may require 820// setting a feature bit in the processor (on startup, for example). 821// Opteron 10h and later implement such a feature. 822def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 823 auto *Ld = cast<LoadSDNode>(N); 824 return Subtarget->hasSSEUnalignedMem() || 825 Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 826}]>; 827 828// 128-bit memop pattern fragments 829// NOTE: all 128-bit integer vector loads are promoted to v2i64 830def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; 831def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; 832def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; 833def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>; 834def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>; 835def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; 836 837def X86masked_gather : SDNode<"X86ISD::MGATHER", 838 SDTypeProfile<2, 3, [SDTCisVec<0>, 839 SDTCisVec<1>, SDTCisInt<1>, 840 SDTCisSameAs<0, 2>, 841 SDTCisSameAs<1, 3>, 842 SDTCisPtrTy<4>]>, 843 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 844 845def X86masked_scatter : SDNode<"X86ISD::MSCATTER", 846 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 847 SDTCisSameAs<0, 2>, 848 SDTCVecEltisVT<0, i1>, 849 SDTCisPtrTy<3>]>, 850 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 851 852def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 853 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 854 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 855 return Mgt->getIndex().getValueType() == MVT::v4i32; 856}]>; 857 858def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 859 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 860 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 861 return Mgt->getIndex().getValueType() == MVT::v8i32; 862}]>; 863 864def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 865 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 866 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 867 return Mgt->getIndex().getValueType() == MVT::v2i64; 868}]>; 869def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 870 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 871 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 872 return Mgt->getIndex().getValueType() == MVT::v4i64; 873}]>; 874def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 875 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 876 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 877 return Mgt->getIndex().getValueType() == MVT::v8i64; 878}]>; 879def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 880 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 881 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 882 return Mgt->getIndex().getValueType() == MVT::v16i32; 883}]>; 884 885def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 886 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 887 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 888 return Sc->getIndex().getValueType() == MVT::v2i64; 889}]>; 890 891def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 892 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 893 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 894 return Sc->getIndex().getValueType() == MVT::v4i32; 895}]>; 896 897def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 898 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 899 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 900 return Sc->getIndex().getValueType() == MVT::v4i64; 901}]>; 902 903def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 904 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 905 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 906 return Sc->getIndex().getValueType() == MVT::v8i32; 907}]>; 908 909def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 910 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 911 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 912 return Sc->getIndex().getValueType() == MVT::v8i64; 913}]>; 914def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 915 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 916 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 917 return Sc->getIndex().getValueType() == MVT::v16i32; 918}]>; 919 920// 128-bit bitconvert pattern fragments 921def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; 922def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; 923def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; 924def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; 925def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; 926def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; 927 928// 256-bit bitconvert pattern fragments 929def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>; 930def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>; 931def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>; 932def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>; 933def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>; 934def bc_v4f64 : PatFrag<(ops node:$in), (v4f64 (bitconvert node:$in))>; 935 936// 512-bit bitconvert pattern fragments 937def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>; 938def bc_v32i16 : PatFrag<(ops node:$in), (v32i16 (bitconvert node:$in))>; 939def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>; 940def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>; 941def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>; 942def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>; 943 944def X86vzload32 : PatFrag<(ops node:$src), 945 (X86vzld node:$src), [{ 946 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 4; 947}]>; 948 949def X86vzload64 : PatFrag<(ops node:$src), 950 (X86vzld node:$src), [{ 951 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8; 952}]>; 953 954def X86vextractstore64 : PatFrag<(ops node:$val, node:$ptr), 955 (X86vextractst node:$val, node:$ptr), [{ 956 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8; 957}]>; 958 959def X86VBroadcastld8 : PatFrag<(ops node:$src), 960 (X86VBroadcastld node:$src), [{ 961 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 1; 962}]>; 963 964def X86VBroadcastld16 : PatFrag<(ops node:$src), 965 (X86VBroadcastld node:$src), [{ 966 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 2; 967}]>; 968 969def X86VBroadcastld32 : PatFrag<(ops node:$src), 970 (X86VBroadcastld node:$src), [{ 971 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 4; 972}]>; 973 974def X86VBroadcastld64 : PatFrag<(ops node:$src), 975 (X86VBroadcastld node:$src), [{ 976 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8; 977}]>; 978 979 980def fp32imm0 : PatLeaf<(f32 fpimm), [{ 981 return N->isExactlyValue(+0.0); 982}]>; 983 984def fp64imm0 : PatLeaf<(f64 fpimm), [{ 985 return N->isExactlyValue(+0.0); 986}]>; 987 988def fp128imm0 : PatLeaf<(f128 fpimm), [{ 989 return N->isExactlyValue(+0.0); 990}]>; 991 992// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index 993// to VEXTRACTF128/VEXTRACTI128 imm. 994def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{ 995 return getExtractVEXTRACTImmediate(N, 128, SDLoc(N)); 996}]>; 997 998// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to 999// VINSERTF128/VINSERTI128 imm. 1000def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{ 1001 return getInsertVINSERTImmediate(N, 128, SDLoc(N)); 1002}]>; 1003 1004// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index 1005// to VEXTRACTF64x4 imm. 1006def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{ 1007 return getExtractVEXTRACTImmediate(N, 256, SDLoc(N)); 1008}]>; 1009 1010// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to 1011// VINSERTF64x4 imm. 1012def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{ 1013 return getInsertVINSERTImmediate(N, 256, SDLoc(N)); 1014}]>; 1015 1016def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index), 1017 (extract_subvector node:$bigvec, 1018 node:$index), [{ 1019 // Index 0 can be handled via extract_subreg. 1020 return !isNullConstant(N->getOperand(1)); 1021}], EXTRACT_get_vextract128_imm>; 1022 1023def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 1024 node:$index), 1025 (insert_subvector node:$bigvec, node:$smallvec, 1026 node:$index), [{}], 1027 INSERT_get_vinsert128_imm>; 1028 1029def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index), 1030 (extract_subvector node:$bigvec, 1031 node:$index), [{ 1032 // Index 0 can be handled via extract_subreg. 1033 return !isNullConstant(N->getOperand(1)); 1034}], EXTRACT_get_vextract256_imm>; 1035 1036def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 1037 node:$index), 1038 (insert_subvector node:$bigvec, node:$smallvec, 1039 node:$index), [{}], 1040 INSERT_get_vinsert256_imm>; 1041 1042def masked_load : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1043 (masked_ld node:$src1, node:$src2, node:$src3), [{ 1044 return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() && 1045 cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 1046}]>; 1047 1048def masked_load_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1049 (masked_load node:$src1, node:$src2, node:$src3), [{ 1050 // Use the node type to determine the size the alignment needs to match. 1051 // We can't use memory VT because type widening changes the node VT, but 1052 // not the memory VT. 1053 auto *Ld = cast<MaskedLoadSDNode>(N); 1054 return Ld->getAlignment() >= Ld->getValueType(0).getStoreSize(); 1055}]>; 1056 1057def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1058 (masked_ld node:$src1, node:$src2, node:$src3), [{ 1059 return cast<MaskedLoadSDNode>(N)->isExpandingLoad(); 1060}]>; 1061 1062// Masked store fragments. 1063// X86mstore can't be implemented in core DAG files because some targets 1064// do not support vector types (llvm-tblgen will fail). 1065def masked_store : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1066 (masked_st node:$src1, node:$src2, node:$src3), [{ 1067 return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) && 1068 (!cast<MaskedStoreSDNode>(N)->isCompressingStore()); 1069}]>; 1070 1071def masked_store_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1072 (masked_store node:$src1, node:$src2, node:$src3), [{ 1073 // Use the node type to determine the size the alignment needs to match. 1074 // We can't use memory VT because type widening changes the node VT, but 1075 // not the memory VT. 1076 auto *St = cast<MaskedStoreSDNode>(N); 1077 return St->getAlignment() >= St->getOperand(1).getValueType().getStoreSize(); 1078}]>; 1079 1080def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1081 (masked_st node:$src1, node:$src2, node:$src3), [{ 1082 return cast<MaskedStoreSDNode>(N)->isCompressingStore(); 1083}]>; 1084 1085// masked truncstore fragments 1086// X86mtruncstore can't be implemented in core DAG files because some targets 1087// doesn't support vector type ( llvm-tblgen will fail) 1088def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1089 (masked_st node:$src1, node:$src2, node:$src3), [{ 1090 return cast<MaskedStoreSDNode>(N)->isTruncatingStore(); 1091}]>; 1092def masked_truncstorevi8 : 1093 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1094 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1095 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1096}]>; 1097def masked_truncstorevi16 : 1098 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1099 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1100 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1101}]>; 1102def masked_truncstorevi32 : 1103 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1104 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1105 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1106}]>; 1107 1108def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES", SDTStore, 1109 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1110 1111def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS", SDTStore, 1112 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1113 1114def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES", SDTMaskedStore, 1115 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1116 1117def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS", SDTMaskedStore, 1118 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1119 1120def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr), 1121 (X86TruncSStore node:$val, node:$ptr), [{ 1122 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1123}]>; 1124 1125def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr), 1126 (X86TruncUSStore node:$val, node:$ptr), [{ 1127 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1128}]>; 1129 1130def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr), 1131 (X86TruncSStore node:$val, node:$ptr), [{ 1132 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1133}]>; 1134 1135def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr), 1136 (X86TruncUSStore node:$val, node:$ptr), [{ 1137 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1138}]>; 1139 1140def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr), 1141 (X86TruncSStore node:$val, node:$ptr), [{ 1142 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1143}]>; 1144 1145def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr), 1146 (X86TruncUSStore node:$val, node:$ptr), [{ 1147 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1148}]>; 1149 1150def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1151 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1152 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1153}]>; 1154 1155def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1156 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1157 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1158}]>; 1159 1160def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1161 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1162 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1163}]>; 1164 1165def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1166 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1167 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1168}]>; 1169 1170def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1171 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1172 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1173}]>; 1174 1175def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1176 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1177 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1178}]>; 1179