1//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file provides pattern fragments useful for SIMD instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// MMX specific DAG Nodes. 15//===----------------------------------------------------------------------===// 16 17// Low word of MMX to GPR. 18def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1, 19 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>; 20// GPR to low word of MMX. 21def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1, 22 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>; 23 24//===----------------------------------------------------------------------===// 25// MMX Pattern Fragments 26//===----------------------------------------------------------------------===// 27 28def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>; 29 30//===----------------------------------------------------------------------===// 31// SSE specific DAG Nodes. 32//===----------------------------------------------------------------------===// 33 34def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, 35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 36 SDTCisVT<3, i8>]>; 37 38def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; 39def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; 40def X86fmins : SDNode<"X86ISD::FMINS", SDTFPBinOp>; 41def X86fmaxs : SDNode<"X86ISD::FMAXS", SDTFPBinOp>; 42 43// Commutative and Associative FMIN and FMAX. 44def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp, 45 [SDNPCommutative, SDNPAssociative]>; 46def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp, 47 [SDNPCommutative, SDNPAssociative]>; 48 49def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, 50 [SDNPCommutative, SDNPAssociative]>; 51def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, 52 [SDNPCommutative, SDNPAssociative]>; 53def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, 54 [SDNPCommutative, SDNPAssociative]>; 55def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp>; 56def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; 57def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; 58def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; 59def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; 60def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>; 61def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>; 62def X86comi : SDNode<"X86ISD::COMI", SDTX86FCmp>; 63def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86FCmp>; 64 65def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<0, 1>, 66 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 67def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>; 68 69def X86pshufb : SDNode<"X86ISD::PSHUFB", 70 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>, 71 SDTCisSameAs<0,2>]>>; 72def X86psadbw : SDNode<"X86ISD::PSADBW", 73 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 74 SDTCVecEltisVT<1, i8>, 75 SDTCisSameSizeAs<0,1>, 76 SDTCisSameAs<1,2>]>, [SDNPCommutative]>; 77def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW", 78 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>, 79 SDTCVecEltisVT<1, i8>, 80 SDTCisSameSizeAs<0,1>, 81 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>>; 82def X86andnp : SDNode<"X86ISD::ANDNP", 83 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 84 SDTCisSameAs<0,2>]>>; 85def X86multishift : SDNode<"X86ISD::MULTISHIFT", 86 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 87 SDTCisSameAs<1,2>]>>; 88def X86pextrb : SDNode<"X86ISD::PEXTRB", 89 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>, 90 SDTCisVT<2, i8>]>>; 91def X86pextrw : SDNode<"X86ISD::PEXTRW", 92 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>, 93 SDTCisVT<2, i8>]>>; 94def X86pinsrb : SDNode<"X86ISD::PINSRB", 95 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 96 SDTCisVT<2, i32>, SDTCisVT<3, i8>]>>; 97def X86pinsrw : SDNode<"X86ISD::PINSRW", 98 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, 99 SDTCisVT<2, i32>, SDTCisVT<3, i8>]>>; 100def X86insertps : SDNode<"X86ISD::INSERTPS", 101 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, 102 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>; 103def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", 104 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; 105 106def X86vzld : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, 107 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 108def X86vextractst : SDNode<"X86ISD::VEXTRACT_STORE", SDTStore, 109 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 110def X86VBroadcastld : SDNode<"X86ISD::VBROADCAST_LOAD", SDTLoad, 111 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 112def X86SubVBroadcastld : SDNode<"X86ISD::SUBV_BROADCAST_LOAD", SDTLoad, 113 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 114 115def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 116 SDTCisInt<0>, SDTCisInt<1>, 117 SDTCisOpSmallerThanOp<0, 1>]>; 118def SDTVmtrunc : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 119 SDTCisInt<0>, SDTCisInt<1>, 120 SDTCisOpSmallerThanOp<0, 1>, 121 SDTCisSameAs<0, 2>, 122 SDTCVecEltisVT<3, i1>, 123 SDTCisSameNumEltsAs<1, 3>]>; 124 125def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>; 126def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>; 127def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>; 128def X86vmtrunc : SDNode<"X86ISD::VMTRUNC", SDTVmtrunc>; 129def X86vmtruncs : SDNode<"X86ISD::VMTRUNCS", SDTVmtrunc>; 130def X86vmtruncus : SDNode<"X86ISD::VMTRUNCUS", SDTVmtrunc>; 131 132def X86vfpext : SDNode<"X86ISD::VFPEXT", 133 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, 134 SDTCVecEltisVT<1, f32>, 135 SDTCisSameSizeAs<0, 1>]>>; 136 137def X86strict_vfpext : SDNode<"X86ISD::STRICT_VFPEXT", 138 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, 139 SDTCVecEltisVT<1, f32>, 140 SDTCisSameSizeAs<0, 1>]>, 141 [SDNPHasChain]>; 142 143def X86any_vfpext : PatFrags<(ops node:$src), 144 [(X86strict_vfpext node:$src), 145 (X86vfpext node:$src)]>; 146 147def X86vfpround: SDNode<"X86ISD::VFPROUND", 148 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 149 SDTCVecEltisVT<1, f64>, 150 SDTCisOpSmallerThanOp<0, 1>]>>; 151 152def X86strict_vfpround: SDNode<"X86ISD::STRICT_VFPROUND", 153 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 154 SDTCVecEltisVT<1, f64>, 155 SDTCisOpSmallerThanOp<0, 1>]>, 156 [SDNPHasChain]>; 157 158def X86any_vfpround : PatFrags<(ops node:$src), 159 [(X86strict_vfpround node:$src), 160 (X86vfpround node:$src)]>; 161 162def X86frounds : SDNode<"X86ISD::VFPROUNDS", 163 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, 164 SDTCisSameAs<0, 1>, 165 SDTCVecEltisVT<2, f64>, 166 SDTCisSameSizeAs<0, 2>]>>; 167 168def X86froundsRnd: SDNode<"X86ISD::VFPROUNDS_RND", 169 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 170 SDTCisSameAs<0, 1>, 171 SDTCVecEltisVT<2, f64>, 172 SDTCisSameSizeAs<0, 2>, 173 SDTCisVT<3, i32>]>>; 174 175def X86fpexts : SDNode<"X86ISD::VFPEXTS", 176 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>, 177 SDTCisSameAs<0, 1>, 178 SDTCVecEltisVT<2, f32>, 179 SDTCisSameSizeAs<0, 2>]>>; 180def X86fpextsSAE : SDNode<"X86ISD::VFPEXTS_SAE", 181 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>, 182 SDTCisSameAs<0, 1>, 183 SDTCVecEltisVT<2, f32>, 184 SDTCisSameSizeAs<0, 2>]>>; 185 186def X86vmfpround: SDNode<"X86ISD::VMFPROUND", 187 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 188 SDTCVecEltisVT<1, f64>, 189 SDTCisSameSizeAs<0, 1>, 190 SDTCisSameAs<0, 2>, 191 SDTCVecEltisVT<3, i1>, 192 SDTCisSameNumEltsAs<1, 3>]>>; 193 194def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 195 SDTCisVT<2, i8>, SDTCisInt<0>]>; 196 197def X86vshldq : SDNode<"X86ISD::VSHLDQ", X86vshiftimm>; 198def X86vshrdq : SDNode<"X86ISD::VSRLDQ", X86vshiftimm>; 199def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>; 200def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>; 201 202def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>; 203def X86strict_cmpp : SDNode<"X86ISD::STRICT_CMPP", SDTX86VFCMP, [SDNPHasChain]>; 204def X86any_cmpp : PatFrags<(ops node:$src1, node:$src2, node:$src3), 205 [(X86strict_cmpp node:$src1, node:$src2, node:$src3), 206 (X86cmpp node:$src1, node:$src2, node:$src3)]>; 207 208def X86CmpMaskCC : 209 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>, 210 SDTCisVec<1>, SDTCisSameAs<2, 1>, 211 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>; 212def X86MaskCmpMaskCC : 213 SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>, 214 SDTCisVec<1>, SDTCisSameAs<2, 1>, 215 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>, SDTCisSameAs<4, 0>]>; 216def X86CmpMaskCCScalar : 217 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>, 218 SDTCisVT<3, i8>]>; 219 220def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>; 221def X86cmpmm : SDNode<"X86ISD::CMPMM", X86MaskCmpMaskCC>; 222def X86strict_cmpm : SDNode<"X86ISD::STRICT_CMPM", X86CmpMaskCC, [SDNPHasChain]>; 223def X86any_cmpm : PatFrags<(ops node:$src1, node:$src2, node:$src3), 224 [(X86strict_cmpm node:$src1, node:$src2, node:$src3), 225 (X86cmpm node:$src1, node:$src2, node:$src3)]>; 226def X86cmpmmSAE : SDNode<"X86ISD::CMPMM_SAE", X86MaskCmpMaskCC>; 227def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>; 228def X86cmpmsSAE : SDNode<"X86ISD::FSETCCM_SAE", X86CmpMaskCCScalar>; 229 230def X86phminpos: SDNode<"X86ISD::PHMINPOS", 231 SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>; 232 233def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 234 SDTCisVec<2>, SDTCisInt<0>, 235 SDTCisInt<2>]>; 236 237def X86vshl : SDNode<"X86ISD::VSHL", X86vshiftuniform>; 238def X86vsrl : SDNode<"X86ISD::VSRL", X86vshiftuniform>; 239def X86vsra : SDNode<"X86ISD::VSRA", X86vshiftuniform>; 240 241def X86vshiftvariable : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 242 SDTCisSameAs<0,2>, SDTCisInt<0>]>; 243 244def X86vshlv : SDNode<"X86ISD::VSHLV", X86vshiftvariable>; 245def X86vsrlv : SDNode<"X86ISD::VSRLV", X86vshiftvariable>; 246def X86vsrav : SDNode<"X86ISD::VSRAV", X86vshiftvariable>; 247 248def X86vshli : SDNode<"X86ISD::VSHLI", X86vshiftimm>; 249def X86vsrli : SDNode<"X86ISD::VSRLI", X86vshiftimm>; 250def X86vsrai : SDNode<"X86ISD::VSRAI", X86vshiftimm>; 251 252def X86kshiftl : SDNode<"X86ISD::KSHIFTL", 253 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 254 SDTCisSameAs<0, 1>, 255 SDTCisVT<2, i8>]>>; 256def X86kshiftr : SDNode<"X86ISD::KSHIFTR", 257 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 258 SDTCisSameAs<0, 1>, 259 SDTCisVT<2, i8>]>>; 260 261def X86kadd : SDNode<"X86ISD::KADD", SDTIntBinOp, [SDNPCommutative]>; 262 263def X86vrotli : SDNode<"X86ISD::VROTLI", X86vshiftimm>; 264def X86vrotri : SDNode<"X86ISD::VROTRI", X86vshiftimm>; 265 266def X86vpshl : SDNode<"X86ISD::VPSHL", X86vshiftvariable>; 267def X86vpsha : SDNode<"X86ISD::VPSHA", X86vshiftvariable>; 268 269def X86vpcom : SDNode<"X86ISD::VPCOM", 270 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 271 SDTCisSameAs<0,2>, 272 SDTCisVT<3, i8>, SDTCisInt<0>]>>; 273def X86vpcomu : SDNode<"X86ISD::VPCOMU", 274 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 275 SDTCisSameAs<0,2>, 276 SDTCisVT<3, i8>, SDTCisInt<0>]>>; 277def X86vpermil2 : SDNode<"X86ISD::VPERMIL2", 278 SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>, 279 SDTCisSameAs<0,2>, 280 SDTCisFP<0>, SDTCisInt<3>, 281 SDTCisSameNumEltsAs<0, 3>, 282 SDTCisSameSizeAs<0,3>, 283 SDTCisVT<4, i8>]>>; 284def X86vpperm : SDNode<"X86ISD::VPPERM", 285 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 286 SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>; 287 288def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 289 SDTCisVec<1>, 290 SDTCisSameAs<2, 1>]>; 291 292def X86mulhrs : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>; 293def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>; 294def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; 295def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>; 296def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>; 297def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>; 298 299def X86movmsk : SDNode<"X86ISD::MOVMSK", 300 SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>; 301 302def X86selects : SDNode<"X86ISD::SELECTS", 303 SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>, 304 SDTCisSameAs<0, 2>, 305 SDTCisSameAs<2, 3>]>>; 306 307def X86pmuludq : SDNode<"X86ISD::PMULUDQ", 308 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 309 SDTCisSameAs<0,1>, 310 SDTCisSameAs<1,2>]>, 311 [SDNPCommutative]>; 312def X86pmuldq : SDNode<"X86ISD::PMULDQ", 313 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 314 SDTCisSameAs<0,1>, 315 SDTCisSameAs<1,2>]>, 316 [SDNPCommutative]>; 317 318def X86extrqi : SDNode<"X86ISD::EXTRQI", 319 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, 320 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>; 321def X86insertqi : SDNode<"X86ISD::INSERTQI", 322 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, 323 SDTCisSameAs<1,2>, SDTCisVT<3, i8>, 324 SDTCisVT<4, i8>]>>; 325 326// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get 327// translated into one of the target nodes below during lowering. 328// Note: this is a work in progress... 329def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 330def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 331 SDTCisSameAs<0,2>]>; 332def SDTShuff2OpFP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 333 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>; 334 335def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 336 SDTCisFP<0>, SDTCisInt<2>, 337 SDTCisSameNumEltsAs<0,2>, 338 SDTCisSameSizeAs<0,2>]>; 339def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>, 340 SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>; 341def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 342 SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>; 343def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, 344 SDTCisSameAs<0,1>, 345 SDTCisSameAs<0,2>, 346 SDTCisVT<3, i32>]>; 347def SDTFPTernaryOpImm: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisSameAs<0,1>, 348 SDTCisSameAs<0,2>, 349 SDTCisInt<3>, 350 SDTCisSameSizeAs<0, 3>, 351 SDTCisSameNumEltsAs<0, 3>, 352 SDTCisVT<4, i32>]>; 353def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>, 354 SDTCisSameAs<0,1>, 355 SDTCisVT<2, i32>]>; 356 357def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 358def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>, 359 SDTCisInt<0>, SDTCisInt<1>]>; 360 361def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 362 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>; 363 364def SDTTernlog : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>, 365 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, 366 SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>; 367 368def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc. 369 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>; 370 371def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc. 372 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>; 373 374def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>, 375 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, 376 SDTCisFP<0>, SDTCisVT<4, i32>]>; 377 378def X86PAlignr : SDNode<"X86ISD::PALIGNR", 379 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>, 380 SDTCisSameAs<0,1>, 381 SDTCisSameAs<0,2>, 382 SDTCisVT<3, i8>]>>; 383def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>; 384 385def X86VShld : SDNode<"X86ISD::VSHLD", SDTShuff3OpI>; 386def X86VShrd : SDNode<"X86ISD::VSHRD", SDTShuff3OpI>; 387def X86VShldv : SDNode<"X86ISD::VSHLDV", 388 SDTypeProfile<1, 3, [SDTCisVec<0>, 389 SDTCisSameAs<0,1>, 390 SDTCisSameAs<0,2>, 391 SDTCisSameAs<0,3>]>>; 392def X86VShrdv : SDNode<"X86ISD::VSHRDV", 393 SDTypeProfile<1, 3, [SDTCisVec<0>, 394 SDTCisSameAs<0,1>, 395 SDTCisSameAs<0,2>, 396 SDTCisSameAs<0,3>]>>; 397 398def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>; 399 400def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; 401def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; 402def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; 403 404def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>; 405def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>; 406 407def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>; 408def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; 409def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; 410 411def X86Movsd : SDNode<"X86ISD::MOVSD", 412 SDTypeProfile<1, 2, [SDTCisVT<0, v2f64>, 413 SDTCisVT<1, v2f64>, 414 SDTCisVT<2, v2f64>]>>; 415def X86Movss : SDNode<"X86ISD::MOVSS", 416 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 417 SDTCisVT<1, v4f32>, 418 SDTCisVT<2, v4f32>]>>; 419 420def X86Movlhps : SDNode<"X86ISD::MOVLHPS", 421 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 422 SDTCisVT<1, v4f32>, 423 SDTCisVT<2, v4f32>]>>; 424def X86Movhlps : SDNode<"X86ISD::MOVHLPS", 425 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 426 SDTCisVT<1, v4f32>, 427 SDTCisVT<2, v4f32>]>>; 428 429def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>, 430 SDTCisVec<1>, SDTCisInt<1>, 431 SDTCisSameSizeAs<0,1>, 432 SDTCisSameAs<1,2>, 433 SDTCisOpSmallerThanOp<0, 1>]>; 434def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>; 435def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>; 436 437def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>; 438def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>; 439 440def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW", 441 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, 442 SDTCVecEltisVT<1, i8>, 443 SDTCisSameSizeAs<0,1>, 444 SDTCisSameAs<1,2>]>>; 445def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD", 446 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>, 447 SDTCVecEltisVT<1, i16>, 448 SDTCisSameSizeAs<0,1>, 449 SDTCisSameAs<1,2>]>, 450 [SDNPCommutative]>; 451 452def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>; 453def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>; 454def X86VPermv : SDNode<"X86ISD::VPERMV", 455 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>, 456 SDTCisSameNumEltsAs<0,1>, 457 SDTCisSameSizeAs<0,1>, 458 SDTCisSameAs<0,2>]>>; 459def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>; 460def X86VPermt2 : SDNode<"X86ISD::VPERMV3", 461 SDTypeProfile<1, 3, [SDTCisVec<0>, 462 SDTCisSameAs<0,1>, SDTCisInt<2>, 463 SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>, 464 SDTCisSameSizeAs<0,2>, 465 SDTCisSameAs<0,3>]>, []>; 466 467def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>; 468 469def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>; 470 471def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImm>; 472def X86VFixupimmSAE : SDNode<"X86ISD::VFIXUPIMM_SAE", SDTFPTernaryOpImm>; 473def X86VFixupimms : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImm>; 474def X86VFixupimmSAEs : SDNode<"X86ISD::VFIXUPIMMS_SAE", SDTFPTernaryOpImm>; 475def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImm>; 476def X86VRangeSAE : SDNode<"X86ISD::VRANGE_SAE", SDTFPBinOpImm>; 477def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImm>; 478def X86VReduceSAE : SDNode<"X86ISD::VREDUCE_SAE", SDTFPUnaryOpImm>; 479def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImm>; 480def X86strict_VRndScale : SDNode<"X86ISD::STRICT_VRNDSCALE", SDTFPUnaryOpImm, 481 [SDNPHasChain]>; 482def X86any_VRndScale : PatFrags<(ops node:$src1, node:$src2), 483 [(X86strict_VRndScale node:$src1, node:$src2), 484 (X86VRndScale node:$src1, node:$src2)]>; 485 486def X86VRndScaleSAE: SDNode<"X86ISD::VRNDSCALE_SAE", SDTFPUnaryOpImm>; 487def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImm>; 488def X86VGetMantSAE : SDNode<"X86ISD::VGETMANT_SAE", SDTFPUnaryOpImm>; 489def X86Vfpclass : SDNode<"X86ISD::VFPCLASS", 490 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 491 SDTCisFP<1>, 492 SDTCisSameNumEltsAs<0,1>, 493 SDTCisVT<2, i32>]>, []>; 494def X86Vfpclasss : SDNode<"X86ISD::VFPCLASSS", 495 SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>, 496 SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>; 497 498def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; 499def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>; 500 501def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>; 502def X86Blendv : SDNode<"X86ISD::BLENDV", 503 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<1>, 504 SDTCisSameAs<0, 2>, 505 SDTCisSameAs<2, 3>, 506 SDTCisSameNumEltsAs<0, 1>, 507 SDTCisSameSizeAs<0, 1>]>>; 508 509def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>; 510 511def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>; 512def X86fadds : SDNode<"X86ISD::FADDS", SDTFPBinOp>; 513def X86faddRnds : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>; 514def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>; 515def X86fsubs : SDNode<"X86ISD::FSUBS", SDTFPBinOp>; 516def X86fsubRnds : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>; 517def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>; 518def X86fmuls : SDNode<"X86ISD::FMULS", SDTFPBinOp>; 519def X86fmulRnds : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>; 520def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>; 521def X86fdivs : SDNode<"X86ISD::FDIVS", SDTFPBinOp>; 522def X86fdivRnds : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>; 523def X86fmaxSAE : SDNode<"X86ISD::FMAX_SAE", SDTFPBinOp>; 524def X86fmaxSAEs : SDNode<"X86ISD::FMAXS_SAE", SDTFPBinOp>; 525def X86fminSAE : SDNode<"X86ISD::FMIN_SAE", SDTFPBinOp>; 526def X86fminSAEs : SDNode<"X86ISD::FMINS_SAE", SDTFPBinOp>; 527def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOp>; 528def X86scalefRnd : SDNode<"X86ISD::SCALEF_RND", SDTFPBinOpRound>; 529def X86scalefs : SDNode<"X86ISD::SCALEFS", SDTFPBinOp>; 530def X86scalefsRnd: SDNode<"X86ISD::SCALEFS_RND", SDTFPBinOpRound>; 531def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>; 532def X86fsqrts : SDNode<"X86ISD::FSQRTS", SDTFPBinOp>; 533def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>; 534def X86fgetexp : SDNode<"X86ISD::FGETEXP", SDTFPUnaryOp>; 535def X86fgetexpSAE : SDNode<"X86ISD::FGETEXP_SAE", SDTFPUnaryOp>; 536def X86fgetexps : SDNode<"X86ISD::FGETEXPS", SDTFPBinOp>; 537def X86fgetexpSAEs : SDNode<"X86ISD::FGETEXPS_SAE", SDTFPBinOp>; 538 539def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFPTernaryOp, [SDNPCommutative]>; 540def X86strict_Fnmadd : SDNode<"X86ISD::STRICT_FNMADD", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>; 541def X86any_Fnmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3), 542 [(X86strict_Fnmadd node:$src1, node:$src2, node:$src3), 543 (X86Fnmadd node:$src1, node:$src2, node:$src3)]>; 544def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>; 545def X86strict_Fmsub : SDNode<"X86ISD::STRICT_FMSUB", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>; 546def X86any_Fmsub : PatFrags<(ops node:$src1, node:$src2, node:$src3), 547 [(X86strict_Fmsub node:$src1, node:$src2, node:$src3), 548 (X86Fmsub node:$src1, node:$src2, node:$src3)]>; 549def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFPTernaryOp, [SDNPCommutative]>; 550def X86strict_Fnmsub : SDNode<"X86ISD::STRICT_FNMSUB", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>; 551def X86any_Fnmsub : PatFrags<(ops node:$src1, node:$src2, node:$src3), 552 [(X86strict_Fnmsub node:$src1, node:$src2, node:$src3), 553 (X86Fnmsub node:$src1, node:$src2, node:$src3)]>; 554def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFPTernaryOp, [SDNPCommutative]>; 555def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFPTernaryOp, [SDNPCommutative]>; 556 557def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound, [SDNPCommutative]>; 558def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound, [SDNPCommutative]>; 559def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound, [SDNPCommutative]>; 560def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound, [SDNPCommutative]>; 561def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound, [SDNPCommutative]>; 562def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound, [SDNPCommutative]>; 563 564def X86vp2intersect : SDNode<"X86ISD::VP2INTERSECT", 565 SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 566 SDTCisVec<1>, SDTCisSameAs<1, 2>]>>; 567 568def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>, 569 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 570def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>; 571def x86vpmadd52h : SDNode<"X86ISD::VPMADD52H", SDTIFma, [SDNPCommutative]>; 572 573def X86rsqrt14 : SDNode<"X86ISD::RSQRT14", SDTFPUnaryOp>; 574def X86rcp14 : SDNode<"X86ISD::RCP14", SDTFPUnaryOp>; 575 576// VNNI 577def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 578 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 579def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnni>; 580def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>; 581def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnni>; 582def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>; 583 584def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOp>; 585def X86rsqrt28SAE: SDNode<"X86ISD::RSQRT28_SAE", SDTFPUnaryOp>; 586def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOp>; 587def X86rcp28SAE : SDNode<"X86ISD::RCP28_SAE", SDTFPUnaryOp>; 588def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOp>; 589def X86exp2SAE : SDNode<"X86ISD::EXP2_SAE", SDTFPUnaryOp>; 590 591def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>; 592def X86rcp14s : SDNode<"X86ISD::RCP14S", SDTFPBinOp>; 593def X86rsqrt28s : SDNode<"X86ISD::RSQRT28S", SDTFPBinOp>; 594def X86rsqrt28SAEs : SDNode<"X86ISD::RSQRT28S_SAE", SDTFPBinOp>; 595def X86rcp28s : SDNode<"X86ISD::RCP28S", SDTFPBinOp>; 596def X86rcp28SAEs : SDNode<"X86ISD::RCP28S_SAE", SDTFPBinOp>; 597def X86Ranges : SDNode<"X86ISD::VRANGES", SDTFPBinOpImm>; 598def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>; 599def X86Reduces : SDNode<"X86ISD::VREDUCES", SDTFPBinOpImm>; 600def X86GetMants : SDNode<"X86ISD::VGETMANTS", SDTFPBinOpImm>; 601def X86RangesSAE : SDNode<"X86ISD::VRANGES_SAE", SDTFPBinOpImm>; 602def X86RndScalesSAE : SDNode<"X86ISD::VRNDSCALES_SAE", SDTFPBinOpImm>; 603def X86ReducesSAE : SDNode<"X86ISD::VREDUCES_SAE", SDTFPBinOpImm>; 604def X86GetMantsSAE : SDNode<"X86ISD::VGETMANTS_SAE", SDTFPBinOpImm>; 605 606def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3, 607 [SDTCisSameAs<0, 1>, SDTCisVec<1>, 608 SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>, 609 SDTCisSameNumEltsAs<0, 3>]>, []>; 610def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3, 611 [SDTCisSameAs<0, 1>, SDTCisVec<1>, 612 SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>, 613 SDTCisSameNumEltsAs<0, 3>]>, []>; 614 615// vpshufbitqmb 616def X86Vpshufbitqmb : SDNode<"X86ISD::VPSHUFBITQMB", 617 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 618 SDTCisSameAs<1,2>, 619 SDTCVecEltisVT<0,i1>, 620 SDTCisSameNumEltsAs<0,1>]>>; 621 622def SDTintToFP: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 623 SDTCisSameAs<0,1>, SDTCisInt<2>]>; 624def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, 625 SDTCisSameAs<0,1>, SDTCisInt<2>, 626 SDTCisVT<3, i32>]>; 627 628def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 629 SDTCisInt<0>, SDTCisFP<1>]>; 630def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 631 SDTCisInt<0>, SDTCisFP<1>, 632 SDTCisVT<2, i32>]>; 633def SDTSFloatToInt: SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisFP<1>, 634 SDTCisVec<1>]>; 635def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>, 636 SDTCisVec<1>, SDTCisVT<2, i32>]>; 637 638def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 639 SDTCisFP<0>, SDTCisInt<1>]>; 640def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 641 SDTCisFP<0>, SDTCisInt<1>, 642 SDTCisVT<2, i32>]>; 643 644// Scalar 645def X86SintToFp : SDNode<"X86ISD::SCALAR_SINT_TO_FP", SDTintToFP>; 646def X86SintToFpRnd : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND", SDTintToFPRound>; 647def X86UintToFp : SDNode<"X86ISD::SCALAR_UINT_TO_FP", SDTintToFP>; 648def X86UintToFpRnd : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND", SDTintToFPRound>; 649 650def X86cvtts2Int : SDNode<"X86ISD::CVTTS2SI", SDTSFloatToInt>; 651def X86cvtts2UInt : SDNode<"X86ISD::CVTTS2UI", SDTSFloatToInt>; 652def X86cvtts2IntSAE : SDNode<"X86ISD::CVTTS2SI_SAE", SDTSFloatToInt>; 653def X86cvtts2UIntSAE : SDNode<"X86ISD::CVTTS2UI_SAE", SDTSFloatToInt>; 654 655def X86cvts2si : SDNode<"X86ISD::CVTS2SI", SDTSFloatToInt>; 656def X86cvts2usi : SDNode<"X86ISD::CVTS2UI", SDTSFloatToInt>; 657def X86cvts2siRnd : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>; 658def X86cvts2usiRnd : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>; 659 660// Vector with rounding mode 661 662// cvtt fp-to-int staff 663def X86cvttp2siSAE : SDNode<"X86ISD::CVTTP2SI_SAE", SDTFloatToInt>; 664def X86cvttp2uiSAE : SDNode<"X86ISD::CVTTP2UI_SAE", SDTFloatToInt>; 665 666def X86VSintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTVintToFPRound>; 667def X86VUintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTVintToFPRound>; 668 669// cvt fp-to-int staff 670def X86cvtp2IntRnd : SDNode<"X86ISD::CVTP2SI_RND", SDTFloatToIntRnd>; 671def X86cvtp2UIntRnd : SDNode<"X86ISD::CVTP2UI_RND", SDTFloatToIntRnd>; 672 673// Vector without rounding mode 674 675// cvtt fp-to-int staff 676def X86cvttp2si : SDNode<"X86ISD::CVTTP2SI", SDTFloatToInt>; 677def X86cvttp2ui : SDNode<"X86ISD::CVTTP2UI", SDTFloatToInt>; 678def X86strict_cvttp2si : SDNode<"X86ISD::STRICT_CVTTP2SI", SDTFloatToInt, [SDNPHasChain]>; 679def X86strict_cvttp2ui : SDNode<"X86ISD::STRICT_CVTTP2UI", SDTFloatToInt, [SDNPHasChain]>; 680def X86any_cvttp2si : PatFrags<(ops node:$src), 681 [(X86strict_cvttp2si node:$src), 682 (X86cvttp2si node:$src)]>; 683def X86any_cvttp2ui : PatFrags<(ops node:$src), 684 [(X86strict_cvttp2ui node:$src), 685 (X86cvttp2ui node:$src)]>; 686 687def X86VSintToFP : SDNode<"X86ISD::CVTSI2P", SDTVintToFP>; 688def X86VUintToFP : SDNode<"X86ISD::CVTUI2P", SDTVintToFP>; 689def X86strict_VSintToFP : SDNode<"X86ISD::STRICT_CVTSI2P", SDTVintToFP, [SDNPHasChain]>; 690def X86strict_VUintToFP : SDNode<"X86ISD::STRICT_CVTUI2P", SDTVintToFP, [SDNPHasChain]>; 691def X86any_VSintToFP : PatFrags<(ops node:$src), 692 [(X86strict_VSintToFP node:$src), 693 (X86VSintToFP node:$src)]>; 694def X86any_VUintToFP : PatFrags<(ops node:$src), 695 [(X86strict_VUintToFP node:$src), 696 (X86VUintToFP node:$src)]>; 697 698 699// cvt int-to-fp staff 700def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>; 701def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>; 702 703 704// Masked versions of above 705def SDTMVintToFP: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 706 SDTCisFP<0>, SDTCisInt<1>, 707 SDTCisSameSizeAs<0, 1>, 708 SDTCisSameAs<0, 2>, 709 SDTCVecEltisVT<3, i1>, 710 SDTCisSameNumEltsAs<1, 3>]>; 711def SDTMFloatToInt: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 712 SDTCisInt<0>, SDTCisFP<1>, 713 SDTCisSameSizeAs<0, 1>, 714 SDTCisSameAs<0, 2>, 715 SDTCVecEltisVT<3, i1>, 716 SDTCisSameNumEltsAs<1, 3>]>; 717 718def X86VMSintToFP : SDNode<"X86ISD::MCVTSI2P", SDTMVintToFP>; 719def X86VMUintToFP : SDNode<"X86ISD::MCVTUI2P", SDTMVintToFP>; 720 721def X86mcvtp2Int : SDNode<"X86ISD::MCVTP2SI", SDTMFloatToInt>; 722def X86mcvtp2UInt : SDNode<"X86ISD::MCVTP2UI", SDTMFloatToInt>; 723def X86mcvttp2si : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>; 724def X86mcvttp2ui : SDNode<"X86ISD::MCVTTP2UI", SDTMFloatToInt>; 725 726def SDTcvtph2ps : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 727 SDTCVecEltisVT<1, i16>]>; 728def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS", SDTcvtph2ps>; 729def X86strict_cvtph2ps : SDNode<"X86ISD::STRICT_CVTPH2PS", SDTcvtph2ps, 730 [SDNPHasChain]>; 731def X86any_cvtph2ps : PatFrags<(ops node:$src), 732 [(X86strict_cvtph2ps node:$src), 733 (X86cvtph2ps node:$src)]>; 734 735def X86cvtph2psSAE : SDNode<"X86ISD::CVTPH2PS_SAE", SDTcvtph2ps>; 736 737def SDTcvtps2ph : SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, 738 SDTCVecEltisVT<1, f32>, 739 SDTCisVT<2, i32>]>; 740def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH", SDTcvtps2ph>; 741def X86strict_cvtps2ph : SDNode<"X86ISD::STRICT_CVTPS2PH", SDTcvtps2ph, 742 [SDNPHasChain]>; 743def X86any_cvtps2ph : PatFrags<(ops node:$src1, node:$src2), 744 [(X86strict_cvtps2ph node:$src1, node:$src2), 745 (X86cvtps2ph node:$src1, node:$src2)]>; 746 747def X86mcvtps2ph : SDNode<"X86ISD::MCVTPS2PH", 748 SDTypeProfile<1, 4, [SDTCVecEltisVT<0, i16>, 749 SDTCVecEltisVT<1, f32>, 750 SDTCisVT<2, i32>, 751 SDTCisSameAs<0, 3>, 752 SDTCVecEltisVT<4, i1>, 753 SDTCisSameNumEltsAs<1, 4>]> >; 754def X86vfpextSAE : SDNode<"X86ISD::VFPEXT_SAE", 755 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, 756 SDTCVecEltisVT<1, f32>, 757 SDTCisOpSmallerThanOp<1, 0>]>>; 758def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND", 759 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, 760 SDTCVecEltisVT<1, f64>, 761 SDTCisOpSmallerThanOp<0, 1>, 762 SDTCisVT<2, i32>]>>; 763 764// cvt fp to bfloat16 765def X86cvtne2ps2bf16 : SDNode<"X86ISD::CVTNE2PS2BF16", 766 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, 767 SDTCVecEltisVT<1, f32>, 768 SDTCisSameSizeAs<0,1>, 769 SDTCisSameAs<1,2>]>>; 770def X86mcvtneps2bf16 : SDNode<"X86ISD::MCVTNEPS2BF16", 771 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>, 772 SDTCVecEltisVT<1, f32>, 773 SDTCisSameAs<0, 2>, 774 SDTCVecEltisVT<3, i1>, 775 SDTCisSameNumEltsAs<1, 3>]>>; 776def X86cvtneps2bf16 : SDNode<"X86ISD::CVTNEPS2BF16", 777 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i16>, 778 SDTCVecEltisVT<1, f32>]>>; 779def X86dpbf16ps : SDNode<"X86ISD::DPBF16PS", 780 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 781 SDTCisSameAs<0,1>, 782 SDTCVecEltisVT<2, i32>, 783 SDTCisSameAs<2,3>]>>; 784 785// galois field arithmetic 786def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>; 787def X86GF2P8affineqb : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>; 788def X86GF2P8mulb : SDNode<"X86ISD::GF2P8MULB", SDTIntBinOp>; 789 790def SDTX86MaskedStore: SDTypeProfile<0, 3, [ // masked store 791 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2> 792]>; 793 794//===----------------------------------------------------------------------===// 795// SSE pattern fragments 796//===----------------------------------------------------------------------===// 797 798// 128-bit load pattern fragments 799def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; 800def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; 801def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; 802def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>; 803def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>; 804def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>; 805 806// 256-bit load pattern fragments 807def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; 808def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; 809def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; 810def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>; 811def loadv16i16 : PatFrag<(ops node:$ptr), (v16i16 (load node:$ptr))>; 812def loadv32i8 : PatFrag<(ops node:$ptr), (v32i8 (load node:$ptr))>; 813 814// 512-bit load pattern fragments 815def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>; 816def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>; 817def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>; 818def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>; 819def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>; 820def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>; 821 822// 128-/256-/512-bit extload pattern fragments 823def extloadv2f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 824def extloadv4f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 825def extloadv8f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 826 827// Like 'store', but always requires vector size alignment. 828def alignedstore : PatFrag<(ops node:$val, node:$ptr), 829 (store node:$val, node:$ptr), [{ 830 auto *St = cast<StoreSDNode>(N); 831 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 832}]>; 833 834// Like 'load', but always requires vector size alignment. 835def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 836 auto *Ld = cast<LoadSDNode>(N); 837 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 838}]>; 839 840// 128-bit aligned load pattern fragments 841// NOTE: all 128-bit integer vector loads are promoted to v2i64 842def alignedloadv4f32 : PatFrag<(ops node:$ptr), 843 (v4f32 (alignedload node:$ptr))>; 844def alignedloadv2f64 : PatFrag<(ops node:$ptr), 845 (v2f64 (alignedload node:$ptr))>; 846def alignedloadv2i64 : PatFrag<(ops node:$ptr), 847 (v2i64 (alignedload node:$ptr))>; 848def alignedloadv4i32 : PatFrag<(ops node:$ptr), 849 (v4i32 (alignedload node:$ptr))>; 850def alignedloadv8i16 : PatFrag<(ops node:$ptr), 851 (v8i16 (alignedload node:$ptr))>; 852def alignedloadv16i8 : PatFrag<(ops node:$ptr), 853 (v16i8 (alignedload node:$ptr))>; 854 855// 256-bit aligned load pattern fragments 856// NOTE: all 256-bit integer vector loads are promoted to v4i64 857def alignedloadv8f32 : PatFrag<(ops node:$ptr), 858 (v8f32 (alignedload node:$ptr))>; 859def alignedloadv4f64 : PatFrag<(ops node:$ptr), 860 (v4f64 (alignedload node:$ptr))>; 861def alignedloadv4i64 : PatFrag<(ops node:$ptr), 862 (v4i64 (alignedload node:$ptr))>; 863def alignedloadv8i32 : PatFrag<(ops node:$ptr), 864 (v8i32 (alignedload node:$ptr))>; 865def alignedloadv16i16 : PatFrag<(ops node:$ptr), 866 (v16i16 (alignedload node:$ptr))>; 867def alignedloadv32i8 : PatFrag<(ops node:$ptr), 868 (v32i8 (alignedload node:$ptr))>; 869 870// 512-bit aligned load pattern fragments 871def alignedloadv16f32 : PatFrag<(ops node:$ptr), 872 (v16f32 (alignedload node:$ptr))>; 873def alignedloadv8f64 : PatFrag<(ops node:$ptr), 874 (v8f64 (alignedload node:$ptr))>; 875def alignedloadv8i64 : PatFrag<(ops node:$ptr), 876 (v8i64 (alignedload node:$ptr))>; 877def alignedloadv16i32 : PatFrag<(ops node:$ptr), 878 (v16i32 (alignedload node:$ptr))>; 879def alignedloadv32i16 : PatFrag<(ops node:$ptr), 880 (v32i16 (alignedload node:$ptr))>; 881def alignedloadv64i8 : PatFrag<(ops node:$ptr), 882 (v64i8 (alignedload node:$ptr))>; 883 884// Like 'load', but uses special alignment checks suitable for use in 885// memory operands in most SSE instructions, which are required to 886// be naturally aligned on some targets but not on others. If the subtarget 887// allows unaligned accesses, match any load, though this may require 888// setting a feature bit in the processor (on startup, for example). 889// Opteron 10h and later implement such a feature. 890def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 891 auto *Ld = cast<LoadSDNode>(N); 892 return Subtarget->hasSSEUnalignedMem() || 893 Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 894}]>; 895 896// 128-bit memop pattern fragments 897// NOTE: all 128-bit integer vector loads are promoted to v2i64 898def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; 899def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; 900def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; 901def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>; 902def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>; 903def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; 904 905// 128-bit bitconvert pattern fragments 906def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; 907def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; 908def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; 909def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; 910def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; 911def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; 912 913// 256-bit bitconvert pattern fragments 914def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>; 915def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>; 916def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>; 917def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>; 918def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>; 919def bc_v4f64 : PatFrag<(ops node:$in), (v4f64 (bitconvert node:$in))>; 920 921// 512-bit bitconvert pattern fragments 922def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>; 923def bc_v32i16 : PatFrag<(ops node:$in), (v32i16 (bitconvert node:$in))>; 924def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>; 925def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>; 926def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>; 927def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>; 928 929def X86vzload32 : PatFrag<(ops node:$src), 930 (X86vzld node:$src), [{ 931 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 4; 932}]>; 933 934def X86vzload64 : PatFrag<(ops node:$src), 935 (X86vzld node:$src), [{ 936 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8; 937}]>; 938 939def X86vextractstore64 : PatFrag<(ops node:$val, node:$ptr), 940 (X86vextractst node:$val, node:$ptr), [{ 941 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8; 942}]>; 943 944def X86VBroadcastld8 : PatFrag<(ops node:$src), 945 (X86VBroadcastld node:$src), [{ 946 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 1; 947}]>; 948 949def X86VBroadcastld16 : PatFrag<(ops node:$src), 950 (X86VBroadcastld node:$src), [{ 951 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 2; 952}]>; 953 954def X86VBroadcastld32 : PatFrag<(ops node:$src), 955 (X86VBroadcastld node:$src), [{ 956 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 4; 957}]>; 958 959def X86VBroadcastld64 : PatFrag<(ops node:$src), 960 (X86VBroadcastld node:$src), [{ 961 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8; 962}]>; 963 964def X86SubVBroadcastld128 : PatFrag<(ops node:$src), 965 (X86SubVBroadcastld node:$src), [{ 966 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 16; 967}]>; 968 969def X86SubVBroadcastld256 : PatFrag<(ops node:$src), 970 (X86SubVBroadcastld node:$src), [{ 971 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 32; 972}]>; 973 974// Scalar SSE intrinsic fragments to match several different types of loads. 975// Used by scalar SSE intrinsic instructions which have 128 bit types, but 976// only load a single element. 977// FIXME: We should add more canolicalizing in DAGCombine. Particulary removing 978// the simple_load case. 979def sse_load_f32 : PatFrags<(ops node:$ptr), 980 [(v4f32 (simple_load node:$ptr)), 981 (v4f32 (X86vzload32 node:$ptr)), 982 (v4f32 (scalar_to_vector (loadf32 node:$ptr)))]>; 983def sse_load_f64 : PatFrags<(ops node:$ptr), 984 [(v2f64 (simple_load node:$ptr)), 985 (v2f64 (X86vzload64 node:$ptr)), 986 (v2f64 (scalar_to_vector (loadf64 node:$ptr)))]>; 987 988def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>; 989def sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>; 990 991 992def fp32imm0 : PatLeaf<(f32 fpimm), [{ 993 return N->isExactlyValue(+0.0); 994}]>; 995 996def fp64imm0 : PatLeaf<(f64 fpimm), [{ 997 return N->isExactlyValue(+0.0); 998}]>; 999 1000def fp128imm0 : PatLeaf<(f128 fpimm), [{ 1001 return N->isExactlyValue(+0.0); 1002}]>; 1003 1004// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index 1005// to VEXTRACTF128/VEXTRACTI128 imm. 1006def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{ 1007 return getExtractVEXTRACTImmediate(N, 128, SDLoc(N)); 1008}]>; 1009 1010// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to 1011// VINSERTF128/VINSERTI128 imm. 1012def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{ 1013 return getInsertVINSERTImmediate(N, 128, SDLoc(N)); 1014}]>; 1015 1016// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index 1017// to VEXTRACTF64x4 imm. 1018def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{ 1019 return getExtractVEXTRACTImmediate(N, 256, SDLoc(N)); 1020}]>; 1021 1022// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to 1023// VINSERTF64x4 imm. 1024def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{ 1025 return getInsertVINSERTImmediate(N, 256, SDLoc(N)); 1026}]>; 1027 1028def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index), 1029 (extract_subvector node:$bigvec, 1030 node:$index), [{ 1031 // Index 0 can be handled via extract_subreg. 1032 return !isNullConstant(N->getOperand(1)); 1033}], EXTRACT_get_vextract128_imm>; 1034 1035def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 1036 node:$index), 1037 (insert_subvector node:$bigvec, node:$smallvec, 1038 node:$index), [{}], 1039 INSERT_get_vinsert128_imm>; 1040 1041def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index), 1042 (extract_subvector node:$bigvec, 1043 node:$index), [{ 1044 // Index 0 can be handled via extract_subreg. 1045 return !isNullConstant(N->getOperand(1)); 1046}], EXTRACT_get_vextract256_imm>; 1047 1048def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 1049 node:$index), 1050 (insert_subvector node:$bigvec, node:$smallvec, 1051 node:$index), [{}], 1052 INSERT_get_vinsert256_imm>; 1053 1054def masked_load : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1055 (masked_ld node:$src1, undef, node:$src2, node:$src3), [{ 1056 return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() && 1057 cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD && 1058 cast<MaskedLoadSDNode>(N)->isUnindexed(); 1059}]>; 1060 1061def masked_load_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1062 (masked_load node:$src1, node:$src2, node:$src3), [{ 1063 // Use the node type to determine the size the alignment needs to match. 1064 // We can't use memory VT because type widening changes the node VT, but 1065 // not the memory VT. 1066 auto *Ld = cast<MaskedLoadSDNode>(N); 1067 return Ld->getAlignment() >= Ld->getValueType(0).getStoreSize(); 1068}]>; 1069 1070def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1071 (masked_ld node:$src1, undef, node:$src2, node:$src3), [{ 1072 return cast<MaskedLoadSDNode>(N)->isExpandingLoad() && 1073 cast<MaskedLoadSDNode>(N)->isUnindexed(); 1074}]>; 1075 1076// Masked store fragments. 1077// X86mstore can't be implemented in core DAG files because some targets 1078// do not support vector types (llvm-tblgen will fail). 1079def masked_store : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1080 (masked_st node:$src1, node:$src2, undef, node:$src3), [{ 1081 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore() && 1082 !cast<MaskedStoreSDNode>(N)->isCompressingStore() && 1083 cast<MaskedStoreSDNode>(N)->isUnindexed(); 1084}]>; 1085 1086def masked_store_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1087 (masked_store node:$src1, node:$src2, node:$src3), [{ 1088 // Use the node type to determine the size the alignment needs to match. 1089 // We can't use memory VT because type widening changes the node VT, but 1090 // not the memory VT. 1091 auto *St = cast<MaskedStoreSDNode>(N); 1092 return St->getAlignment() >= St->getOperand(1).getValueType().getStoreSize(); 1093}]>; 1094 1095def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1096 (masked_st node:$src1, node:$src2, undef, node:$src3), [{ 1097 return cast<MaskedStoreSDNode>(N)->isCompressingStore() && 1098 cast<MaskedStoreSDNode>(N)->isUnindexed(); 1099}]>; 1100 1101// masked truncstore fragments 1102// X86mtruncstore can't be implemented in core DAG files because some targets 1103// doesn't support vector type ( llvm-tblgen will fail) 1104def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1105 (masked_st node:$src1, node:$src2, undef, node:$src3), [{ 1106 return cast<MaskedStoreSDNode>(N)->isTruncatingStore() && 1107 cast<MaskedStoreSDNode>(N)->isUnindexed(); 1108}]>; 1109def masked_truncstorevi8 : 1110 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1111 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1112 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1113}]>; 1114def masked_truncstorevi16 : 1115 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1116 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1117 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1118}]>; 1119def masked_truncstorevi32 : 1120 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1121 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1122 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1123}]>; 1124 1125def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES", SDTStore, 1126 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1127 1128def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS", SDTStore, 1129 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1130 1131def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES", SDTX86MaskedStore, 1132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1133 1134def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS", SDTX86MaskedStore, 1135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1136 1137def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr), 1138 (X86TruncSStore node:$val, node:$ptr), [{ 1139 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1140}]>; 1141 1142def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr), 1143 (X86TruncUSStore node:$val, node:$ptr), [{ 1144 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1145}]>; 1146 1147def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr), 1148 (X86TruncSStore node:$val, node:$ptr), [{ 1149 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1150}]>; 1151 1152def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr), 1153 (X86TruncUSStore node:$val, node:$ptr), [{ 1154 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1155}]>; 1156 1157def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr), 1158 (X86TruncSStore node:$val, node:$ptr), [{ 1159 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1160}]>; 1161 1162def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr), 1163 (X86TruncUSStore node:$val, node:$ptr), [{ 1164 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1165}]>; 1166 1167def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1168 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1169 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1170}]>; 1171 1172def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1173 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1174 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1175}]>; 1176 1177def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1178 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1179 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1180}]>; 1181 1182def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1183 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1184 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1185}]>; 1186 1187def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1188 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1189 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1190}]>; 1191 1192def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1193 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1194 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1195}]>; 1196