1//===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// X86 Instruction Format Definitions. 11// 12 13// Format specifies the encoding used by the instruction. This is part of the 14// ad-hoc solution used to emit machine instruction encodings by our machine 15// code emitter. 16class Format<bits<7> val> { 17 bits<7> Value = val; 18} 19 20def Pseudo : Format<0>; 21def RawFrm : Format<1>; 22def AddRegFrm : Format<2>; 23def RawFrmMemOffs : Format<3>; 24def RawFrmSrc : Format<4>; 25def RawFrmDst : Format<5>; 26def RawFrmDstSrc : Format<6>; 27def RawFrmImm8 : Format<7>; 28def RawFrmImm16 : Format<8>; 29def AddCCFrm : Format<9>; 30def PrefixByte : Format<10>; 31def MRMr0 : Format<21>; 32def MRMSrcMemFSIB : Format<22>; 33def MRMDestMemFSIB : Format<23>; 34def MRMDestMem : Format<24>; 35def MRMSrcMem : Format<25>; 36def MRMSrcMem4VOp3 : Format<26>; 37def MRMSrcMemOp4 : Format<27>; 38def MRMSrcMemCC : Format<28>; 39def MRMXmCC: Format<30>; 40def MRMXm : Format<31>; 41def MRM0m : Format<32>; def MRM1m : Format<33>; def MRM2m : Format<34>; 42def MRM3m : Format<35>; def MRM4m : Format<36>; def MRM5m : Format<37>; 43def MRM6m : Format<38>; def MRM7m : Format<39>; 44def MRMDestReg : Format<40>; 45def MRMSrcReg : Format<41>; 46def MRMSrcReg4VOp3 : Format<42>; 47def MRMSrcRegOp4 : Format<43>; 48def MRMSrcRegCC : Format<44>; 49def MRMXrCC: Format<46>; 50def MRMXr : Format<47>; 51def MRM0r : Format<48>; def MRM1r : Format<49>; def MRM2r : Format<50>; 52def MRM3r : Format<51>; def MRM4r : Format<52>; def MRM5r : Format<53>; 53def MRM6r : Format<54>; def MRM7r : Format<55>; 54def MRM0X : Format<56>; def MRM1X : Format<57>; def MRM2X : Format<58>; 55def MRM3X : Format<59>; def MRM4X : Format<60>; def MRM5X : Format<61>; 56def MRM6X : Format<62>; def MRM7X : Format<63>; 57def MRM_C0 : Format<64>; def MRM_C1 : Format<65>; def MRM_C2 : Format<66>; 58def MRM_C3 : Format<67>; def MRM_C4 : Format<68>; def MRM_C5 : Format<69>; 59def MRM_C6 : Format<70>; def MRM_C7 : Format<71>; def MRM_C8 : Format<72>; 60def MRM_C9 : Format<73>; def MRM_CA : Format<74>; def MRM_CB : Format<75>; 61def MRM_CC : Format<76>; def MRM_CD : Format<77>; def MRM_CE : Format<78>; 62def MRM_CF : Format<79>; def MRM_D0 : Format<80>; def MRM_D1 : Format<81>; 63def MRM_D2 : Format<82>; def MRM_D3 : Format<83>; def MRM_D4 : Format<84>; 64def MRM_D5 : Format<85>; def MRM_D6 : Format<86>; def MRM_D7 : Format<87>; 65def MRM_D8 : Format<88>; def MRM_D9 : Format<89>; def MRM_DA : Format<90>; 66def MRM_DB : Format<91>; def MRM_DC : Format<92>; def MRM_DD : Format<93>; 67def MRM_DE : Format<94>; def MRM_DF : Format<95>; def MRM_E0 : Format<96>; 68def MRM_E1 : Format<97>; def MRM_E2 : Format<98>; def MRM_E3 : Format<99>; 69def MRM_E4 : Format<100>; def MRM_E5 : Format<101>; def MRM_E6 : Format<102>; 70def MRM_E7 : Format<103>; def MRM_E8 : Format<104>; def MRM_E9 : Format<105>; 71def MRM_EA : Format<106>; def MRM_EB : Format<107>; def MRM_EC : Format<108>; 72def MRM_ED : Format<109>; def MRM_EE : Format<110>; def MRM_EF : Format<111>; 73def MRM_F0 : Format<112>; def MRM_F1 : Format<113>; def MRM_F2 : Format<114>; 74def MRM_F3 : Format<115>; def MRM_F4 : Format<116>; def MRM_F5 : Format<117>; 75def MRM_F6 : Format<118>; def MRM_F7 : Format<119>; def MRM_F8 : Format<120>; 76def MRM_F9 : Format<121>; def MRM_FA : Format<122>; def MRM_FB : Format<123>; 77def MRM_FC : Format<124>; def MRM_FD : Format<125>; def MRM_FE : Format<126>; 78def MRM_FF : Format<127>; 79 80// ImmType - This specifies the immediate type used by an instruction. This is 81// part of the ad-hoc solution used to emit machine instruction encodings by our 82// machine code emitter. 83class ImmType<bits<4> val> { 84 bits<4> Value = val; 85} 86def NoImm : ImmType<0>; 87def Imm8 : ImmType<1>; 88def Imm8PCRel : ImmType<2>; 89def Imm8Reg : ImmType<3>; // Register encoded in [7:4]. 90def Imm16 : ImmType<4>; 91def Imm16PCRel : ImmType<5>; 92def Imm32 : ImmType<6>; 93def Imm32PCRel : ImmType<7>; 94def Imm32S : ImmType<8>; 95def Imm64 : ImmType<9>; 96 97// FPFormat - This specifies what form this FP instruction has. This is used by 98// the Floating-Point stackifier pass. 99class FPFormat<bits<3> val> { 100 bits<3> Value = val; 101} 102def NotFP : FPFormat<0>; 103def ZeroArgFP : FPFormat<1>; 104def OneArgFP : FPFormat<2>; 105def OneArgFPRW : FPFormat<3>; 106def TwoArgFP : FPFormat<4>; 107def CompareFP : FPFormat<5>; 108def CondMovFP : FPFormat<6>; 109def SpecialFP : FPFormat<7>; 110 111// Class specifying the SSE execution domain, used by the SSEDomainFix pass. 112// Keep in sync with tables in X86InstrInfo.cpp. 113class Domain<bits<2> val> { 114 bits<2> Value = val; 115} 116def GenericDomain : Domain<0>; 117def SSEPackedSingle : Domain<1>; 118def SSEPackedDouble : Domain<2>; 119def SSEPackedInt : Domain<3>; 120 121// Class specifying the vector form of the decompressed 122// displacement of 8-bit. 123class CD8VForm<bits<3> val> { 124 bits<3> Value = val; 125} 126def CD8VF : CD8VForm<0>; // v := VL 127def CD8VH : CD8VForm<1>; // v := VL/2 128def CD8VQ : CD8VForm<2>; // v := VL/4 129def CD8VO : CD8VForm<3>; // v := VL/8 130// The tuple (subvector) forms. 131def CD8VT1 : CD8VForm<4>; // v := 1 132def CD8VT2 : CD8VForm<5>; // v := 2 133def CD8VT4 : CD8VForm<6>; // v := 4 134def CD8VT8 : CD8VForm<7>; // v := 8 135 136// Class specifying the prefix used an opcode extension. 137class Prefix<bits<3> val> { 138 bits<3> Value = val; 139} 140def NoPrfx : Prefix<0>; 141def PD : Prefix<1>; 142def XS : Prefix<2>; 143def XD : Prefix<3>; 144def PS : Prefix<4>; // Similar to NoPrfx, but disassembler uses this to know 145 // that other instructions with this opcode use PD/XS/XD 146 // and if any of those is not supported they shouldn't 147 // decode to this instruction. e.g. ANDSS/ANDSD don't 148 // exist, but the 0xf2/0xf3 encoding shouldn't 149 // disable to ANDPS. 150 151// Class specifying the opcode map. 152class Map<bits<3> val> { 153 bits<3> Value = val; 154} 155def OB : Map<0>; 156def TB : Map<1>; 157def T8 : Map<2>; 158def TA : Map<3>; 159def XOP8 : Map<4>; 160def XOP9 : Map<5>; 161def XOPA : Map<6>; 162def ThreeDNow : Map<7>; 163 164// Class specifying the encoding 165class Encoding<bits<2> val> { 166 bits<2> Value = val; 167} 168def EncNormal : Encoding<0>; 169def EncVEX : Encoding<1>; 170def EncXOP : Encoding<2>; 171def EncEVEX : Encoding<3>; 172 173// Operand size for encodings that change based on mode. 174class OperandSize<bits<2> val> { 175 bits<2> Value = val; 176} 177def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix. 178def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode. 179def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode. 180 181// Address size for encodings that change based on mode. 182class AddressSize<bits<2> val> { 183 bits<2> Value = val; 184} 185def AdSizeX : AddressSize<0>; // Address size determined using addr operand. 186def AdSize16 : AddressSize<1>; // Encodes a 16-bit address. 187def AdSize32 : AddressSize<2>; // Encodes a 32-bit address. 188def AdSize64 : AddressSize<3>; // Encodes a 64-bit address. 189 190// Prefix byte classes which are used to indicate to the ad-hoc machine code 191// emitter that various prefix bytes are required. 192class OpSize16 { OperandSize OpSize = OpSize16; } 193class OpSize32 { OperandSize OpSize = OpSize32; } 194class AdSize16 { AddressSize AdSize = AdSize16; } 195class AdSize32 { AddressSize AdSize = AdSize32; } 196class AdSize64 { AddressSize AdSize = AdSize64; } 197class REX_W { bit hasREX_WPrefix = 1; } 198class LOCK { bit hasLockPrefix = 1; } 199class REP { bit hasREPPrefix = 1; } 200class TB { Map OpMap = TB; } 201class T8 { Map OpMap = T8; } 202class TA { Map OpMap = TA; } 203class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; } 204class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; } 205class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; } 206class ThreeDNow { Map OpMap = ThreeDNow; } 207class OBXS { Prefix OpPrefix = XS; } 208class PS : TB { Prefix OpPrefix = PS; } 209class PD : TB { Prefix OpPrefix = PD; } 210class XD : TB { Prefix OpPrefix = XD; } 211class XS : TB { Prefix OpPrefix = XS; } 212class T8PS : T8 { Prefix OpPrefix = PS; } 213class T8PD : T8 { Prefix OpPrefix = PD; } 214class T8XD : T8 { Prefix OpPrefix = XD; } 215class T8XS : T8 { Prefix OpPrefix = XS; } 216class TAPS : TA { Prefix OpPrefix = PS; } 217class TAPD : TA { Prefix OpPrefix = PD; } 218class TAXD : TA { Prefix OpPrefix = XD; } 219class VEX { Encoding OpEnc = EncVEX; } 220class VEX_W { bit HasVEX_W = 1; } 221class VEX_WIG { bit IgnoresVEX_W = 1; } 222// Special version of VEX_W that can be changed to VEX.W==0 for EVEX2VEX. 223class VEX_W1X { bit HasVEX_W = 1; bit EVEX_W1_VEX_W0 = 1; } 224class VEX_4V : VEX { bit hasVEX_4V = 1; } 225class VEX_L { bit hasVEX_L = 1; } 226class VEX_LIG { bit ignoresVEX_L = 1; } 227class EVEX { Encoding OpEnc = EncEVEX; } 228class EVEX_4V : EVEX { bit hasVEX_4V = 1; } 229class EVEX_K { bit hasEVEX_K = 1; } 230class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; } 231class EVEX_B { bit hasEVEX_B = 1; } 232class EVEX_RC { bit hasEVEX_RC = 1; } 233class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; } 234class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; } 235class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; } 236class NOTRACK { bit hasNoTrackPrefix = 1; } 237class SIMD_EXC { list<Register> Uses = [MXCSR]; bit mayRaiseFPException = 1; } 238 239// Specify AVX512 8-bit compressed displacement encoding based on the vector 240// element size in bits (8, 16, 32, 64) and the CDisp8 form. 241class EVEX_CD8<int esize, CD8VForm form> { 242 int CD8_EltSize = !srl(esize, 3); 243 bits<3> CD8_Form = form.Value; 244} 245 246class XOP { Encoding OpEnc = EncXOP; } 247class XOP_4V : XOP { bit hasVEX_4V = 1; } 248 249// Specify the alternative register form instruction to replace the current 250// instruction in case it was picked during generation of memory folding tables 251class FoldGenData<string _RegisterForm> { 252 string FoldGenRegForm = _RegisterForm; 253} 254 255// Provide a specific instruction to be used by the EVEX2VEX conversion. 256class EVEX2VEXOverride<string VEXInstrName> { 257 string EVEX2VEXOverride = VEXInstrName; 258} 259 260// Mark the instruction as "illegal to memory fold/unfold" 261class NotMemoryFoldable { bit isMemoryFoldable = 0; } 262 263// Prevent EVEX->VEX conversion from considering this instruction. 264class NotEVEX2VEXConvertible { bit notEVEX2VEXConvertible = 1; } 265 266class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, 267 string AsmStr, Domain d = GenericDomain> 268 : Instruction { 269 let Namespace = "X86"; 270 271 bits<8> Opcode = opcod; 272 Format Form = f; 273 bits<7> FormBits = Form.Value; 274 ImmType ImmT = i; 275 276 dag OutOperandList = outs; 277 dag InOperandList = ins; 278 string AsmString = AsmStr; 279 280 // If this is a pseudo instruction, mark it isCodeGenOnly. 281 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 282 283 // 284 // Attributes specific to X86 instructions... 285 // 286 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's 287 // isCodeGenonly. Needed to hide an ambiguous 288 // AsmString from the parser, but still disassemble. 289 290 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change 291 // based on operand size of the mode? 292 bits<2> OpSizeBits = OpSize.Value; 293 AddressSize AdSize = AdSizeX; // Does this instruction's encoding change 294 // based on address size of the mode? 295 bits<2> AdSizeBits = AdSize.Value; 296 297 Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have? 298 bits<3> OpPrefixBits = OpPrefix.Value; 299 Map OpMap = OB; // Which opcode map does this inst have? 300 bits<3> OpMapBits = OpMap.Value; 301 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? 302 FPFormat FPForm = NotFP; // What flavor of FP instruction is this? 303 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? 304 Domain ExeDomain = d; 305 bit hasREPPrefix = 0; // Does this inst have a REP prefix? 306 Encoding OpEnc = EncNormal; // Encoding used by this instruction 307 bits<2> OpEncBits = OpEnc.Value; 308 bit HasVEX_W = 0; // Does this inst set the VEX_W field? 309 bit IgnoresVEX_W = 0; // Does this inst ignore VEX_W field? 310 bit EVEX_W1_VEX_W0 = 0; // This EVEX inst with VEX.W==1 can become a VEX 311 // instruction with VEX.W == 0. 312 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field? 313 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers? 314 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit 315 bit hasEVEX_K = 0; // Does this inst require masking? 316 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field? 317 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field? 318 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field? 319 bits<3> CD8_Form = 0; // Compressed disp8 form - vector-width. 320 // Declare it int rather than bits<4> so that all bits are defined when 321 // assigning to bits<7>. 322 int CD8_EltSize = 0; // Compressed disp8 form - element-size in bytes. 323 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction. 324 bit hasNoTrackPrefix = 0; // Does this inst has 0x3E (NoTrack) prefix? 325 326 // Vector size in bytes. 327 bits<7> VectSize = !if(hasEVEX_L2, 64, !if(hasVEX_L, 32, 16)); 328 329 // The scaling factor for AVX512's compressed displacement is either 330 // - the size of a power-of-two number of elements or 331 // - the size of a single element for broadcasts or 332 // - the total vector size divided by a power-of-two number. 333 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64. 334 bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value), 335 !if (CD8_Form{2}, 336 !shl(CD8_EltSize, CD8_Form{1-0}), 337 !if (hasEVEX_B, 338 CD8_EltSize, 339 !srl(VectSize, CD8_Form{1-0}))), 0); 340 341 // Used in the memory folding generation (TableGen backend) to point to an alternative 342 // instruction to replace the current one in case it got picked during generation. 343 string FoldGenRegForm = ?; 344 345 // Used to prevent an explicit EVEX2VEX override for this instruction. 346 string EVEX2VEXOverride = ?; 347 348 bit isMemoryFoldable = 1; // Is it allowed to memory fold/unfold this instruction? 349 bit notEVEX2VEXConvertible = 0; // Prevent EVEX->VEX conversion. 350 351 // TSFlags layout should be kept in sync with X86BaseInfo.h. 352 let TSFlags{6-0} = FormBits; 353 let TSFlags{8-7} = OpSizeBits; 354 let TSFlags{10-9} = AdSizeBits; 355 // No need for 3rd bit, we don't need to distinguish NoPrfx from PS. 356 let TSFlags{12-11} = OpPrefixBits{1-0}; 357 let TSFlags{15-13} = OpMapBits; 358 let TSFlags{16} = hasREX_WPrefix; 359 let TSFlags{20-17} = ImmT.Value; 360 let TSFlags{23-21} = FPForm.Value; 361 let TSFlags{24} = hasLockPrefix; 362 let TSFlags{25} = hasREPPrefix; 363 let TSFlags{27-26} = ExeDomain.Value; 364 let TSFlags{29-28} = OpEncBits; 365 let TSFlags{37-30} = Opcode; 366 // Currently no need for second bit in TSFlags - W Ignore is equivalent to 0. 367 let TSFlags{38} = HasVEX_W; 368 let TSFlags{39} = hasVEX_4V; 369 let TSFlags{40} = hasVEX_L; 370 let TSFlags{41} = hasEVEX_K; 371 let TSFlags{42} = hasEVEX_Z; 372 let TSFlags{43} = hasEVEX_L2; 373 let TSFlags{44} = hasEVEX_B; 374 // If we run out of TSFlags bits, it's possible to encode this in 3 bits. 375 let TSFlags{51-45} = CD8_Scale; 376 let TSFlags{52} = hasEVEX_RC; 377 let TSFlags{53} = hasNoTrackPrefix; 378} 379 380class PseudoI<dag oops, dag iops, list<dag> pattern> 381 : X86Inst<0, Pseudo, NoImm, oops, iops, ""> { 382 let Pattern = pattern; 383} 384 385class I<bits<8> o, Format f, dag outs, dag ins, string asm, 386 list<dag> pattern, Domain d = GenericDomain> 387 : X86Inst<o, f, NoImm, outs, ins, asm, d> { 388 let Pattern = pattern; 389 let CodeSize = 3; 390} 391class Ii8<bits<8> o, Format f, dag outs, dag ins, string asm, 392 list<dag> pattern, Domain d = GenericDomain> 393 : X86Inst<o, f, Imm8, outs, ins, asm, d> { 394 let Pattern = pattern; 395 let CodeSize = 3; 396} 397class Ii8Reg<bits<8> o, Format f, dag outs, dag ins, string asm, 398 list<dag> pattern, Domain d = GenericDomain> 399 : X86Inst<o, f, Imm8Reg, outs, ins, asm, d> { 400 let Pattern = pattern; 401 let CodeSize = 3; 402} 403class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 404 list<dag> pattern> 405 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> { 406 let Pattern = pattern; 407 let CodeSize = 3; 408} 409class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, 410 list<dag> pattern> 411 : X86Inst<o, f, Imm16, outs, ins, asm> { 412 let Pattern = pattern; 413 let CodeSize = 3; 414} 415class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, 416 list<dag> pattern> 417 : X86Inst<o, f, Imm32, outs, ins, asm> { 418 let Pattern = pattern; 419 let CodeSize = 3; 420} 421class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm, 422 list<dag> pattern> 423 : X86Inst<o, f, Imm32S, outs, ins, asm> { 424 let Pattern = pattern; 425 let CodeSize = 3; 426} 427 428class Ii64<bits<8> o, Format f, dag outs, dag ins, string asm, 429 list<dag> pattern> 430 : X86Inst<o, f, Imm64, outs, ins, asm> { 431 let Pattern = pattern; 432 let CodeSize = 3; 433} 434 435class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 436 list<dag> pattern> 437 : X86Inst<o, f, Imm16PCRel, outs, ins, asm> { 438 let Pattern = pattern; 439 let CodeSize = 3; 440} 441 442class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 443 list<dag> pattern> 444 : X86Inst<o, f, Imm32PCRel, outs, ins, asm> { 445 let Pattern = pattern; 446 let CodeSize = 3; 447} 448 449// FPStack Instruction Templates: 450// FPI - Floating Point Instruction template. 451class FPI<bits<8> o, Format F, dag outs, dag ins, string asm> 452 : I<o, F, outs, ins, asm, []> { 453 let Defs = [FPSW]; 454} 455 456// FpI_ - Floating Point Pseudo Instruction template. Not Predicated. 457class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern> 458 : PseudoI<outs, ins, pattern> { 459 let FPForm = fp; 460 let Defs = [FPSW]; 461} 462 463// Templates for instructions that use a 16- or 32-bit segmented address as 464// their only operand: lcall (FAR CALL) and ljmp (FAR JMP) 465// 466// Iseg16 - 16-bit segment selector, 16-bit offset 467// Iseg32 - 16-bit segment selector, 32-bit offset 468 469class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm, 470 list<dag> pattern> 471 : X86Inst<o, f, Imm16, outs, ins, asm> { 472 let Pattern = pattern; 473 let CodeSize = 3; 474} 475 476class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm, 477 list<dag> pattern> 478 : X86Inst<o, f, Imm32, outs, ins, asm> { 479 let Pattern = pattern; 480 let CodeSize = 3; 481} 482 483// SI - SSE 1 & 2 scalar instructions 484class SI<bits<8> o, Format F, dag outs, dag ins, string asm, 485 list<dag> pattern, Domain d = GenericDomain> 486 : I<o, F, outs, ins, asm, pattern, d> { 487 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 488 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], 489 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], 490 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], 491 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 492 [UseSSE1]))))); 493 494 // AVX instructions have a 'v' prefix in the mnemonic 495 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 496 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 497 asm)); 498} 499 500// SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512 501class SI_Int<bits<8> o, Format F, dag outs, dag ins, string asm, 502 list<dag> pattern, Domain d = GenericDomain> 503 : I<o, F, outs, ins, asm, pattern, d> { 504 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 505 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], 506 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], 507 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], 508 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 509 [UseSSE1]))))); 510 511 // AVX instructions have a 'v' prefix in the mnemonic 512 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 513 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 514 asm)); 515} 516// SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512 517class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 518 list<dag> pattern> 519 : Ii8<o, F, outs, ins, asm, pattern> { 520 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 521 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 522 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], 523 [UseSSE2]))); 524 525 // AVX instructions have a 'v' prefix in the mnemonic 526 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 527 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 528 asm)); 529} 530 531// PI - SSE 1 & 2 packed instructions 532class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, 533 Domain d> 534 : I<o, F, outs, ins, asm, pattern, d> { 535 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 536 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 537 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 538 [UseSSE1]))); 539 540 // AVX instructions have a 'v' prefix in the mnemonic 541 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 542 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 543 asm)); 544} 545 546// MMXPI - SSE 1 & 2 packed instructions with MMX operands 547class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, 548 Domain d> 549 : I<o, F, outs, ins, asm, pattern, d> { 550 let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasMMX, HasSSE2], 551 [HasMMX, HasSSE1]); 552} 553 554// PIi8 - SSE 1 & 2 packed instructions with immediate 555class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 556 list<dag> pattern, Domain d> 557 : Ii8<o, F, outs, ins, asm, pattern, d> { 558 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 559 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 560 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 561 [UseSSE1]))); 562 563 // AVX instructions have a 'v' prefix in the mnemonic 564 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 565 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 566 asm)); 567} 568 569// SSE1 Instruction Templates: 570// 571// SSI - SSE1 instructions with XS prefix. 572// PSI - SSE1 instructions with PS prefix. 573// PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix. 574// VSSI - SSE1 instructions with XS prefix in AVX form. 575// VPSI - SSE1 instructions with PS prefix in AVX form, packed single. 576 577class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, 578 list<dag> pattern> 579 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE1]>; 580class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 581 list<dag> pattern> 582 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE1]>; 583class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, 584 list<dag> pattern> 585 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, PS, 586 Requires<[UseSSE1]>; 587class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 588 list<dag> pattern> 589 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, PS, 590 Requires<[UseSSE1]>; 591class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm, 592 list<dag> pattern> 593 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS, 594 Requires<[HasAVX]>; 595class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm, 596 list<dag> pattern> 597 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>, PS, 598 Requires<[HasAVX]>; 599 600// SSE2 Instruction Templates: 601// 602// SDI - SSE2 instructions with XD prefix. 603// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. 604// S2SI - SSE2 instructions with XS prefix. 605// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. 606// PDI - SSE2 instructions with PD prefix, packed double domain. 607// PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix. 608// VSDI - SSE2 scalar instructions with XD prefix in AVX form. 609// VPDI - SSE2 vector instructions with PD prefix in AVX form, 610// packed double domain. 611// VS2I - SSE2 scalar instructions with PD prefix in AVX form. 612// S2I - SSE2 scalar instructions with PD prefix. 613// MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as 614// MMX operands. 615// MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as 616// MMX operands. 617 618class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, 619 list<dag> pattern> 620 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[UseSSE2]>; 621class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 622 list<dag> pattern> 623 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[UseSSE2]>; 624class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm, 625 list<dag> pattern> 626 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>; 627class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 628 list<dag> pattern> 629 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>; 630class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, 631 list<dag> pattern> 632 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, PD, 633 Requires<[UseSSE2]>; 634class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 635 list<dag> pattern> 636 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, PD, 637 Requires<[UseSSE2]>; 638class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm, 639 list<dag> pattern> 640 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XD, 641 Requires<[UseAVX]>; 642class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm, 643 list<dag> pattern> 644 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS, 645 Requires<[HasAVX]>; 646class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm, 647 list<dag> pattern> 648 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>, 649 PD, Requires<[HasAVX]>; 650class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 651 list<dag> pattern> 652 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, PD, 653 Requires<[UseAVX]>; 654class S2I<bits<8> o, Format F, dag outs, dag ins, string asm, 655 list<dag> pattern> 656 : I<o, F, outs, ins, asm, pattern>, PD, Requires<[UseSSE2]>; 657class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 658 list<dag> pattern> 659 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX, HasSSE2]>; 660class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 661 list<dag> pattern> 662 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX, HasSSE2]>; 663 664// SSE3 Instruction Templates: 665// 666// S3I - SSE3 instructions with PD prefixes. 667// S3SI - SSE3 instructions with XS prefix. 668// S3DI - SSE3 instructions with XD prefix. 669 670class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, 671 list<dag> pattern> 672 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS, 673 Requires<[UseSSE3]>; 674class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, 675 list<dag> pattern> 676 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD, 677 Requires<[UseSSE3]>; 678class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, 679 list<dag> pattern> 680 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, PD, 681 Requires<[UseSSE3]>; 682 683 684// SSSE3 Instruction Templates: 685// 686// SS38I - SSSE3 instructions with T8 prefix. 687// SS3AI - SSSE3 instructions with TA prefix. 688// MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands. 689// MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands. 690// 691// Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version 692// uses the MMX registers. The 64-bit versions are grouped with the MMX 693// classes. They need to be enabled even if AVX is enabled. 694 695class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm, 696 list<dag> pattern> 697 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 698 Requires<[UseSSSE3]>; 699class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, 700 list<dag> pattern> 701 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 702 Requires<[UseSSSE3]>; 703class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm, 704 list<dag> pattern> 705 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PS, 706 Requires<[HasMMX, HasSSSE3]>; 707class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, 708 list<dag> pattern> 709 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPS, 710 Requires<[HasMMX, HasSSSE3]>; 711 712// SSE4.1 Instruction Templates: 713// 714// SS48I - SSE 4.1 instructions with T8 prefix. 715// SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. 716// 717class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm, 718 list<dag> pattern> 719 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 720 Requires<[UseSSE41]>; 721class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 722 list<dag> pattern> 723 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 724 Requires<[UseSSE41]>; 725 726// SSE4.2 Instruction Templates: 727// 728// SS428I - SSE 4.2 instructions with T8 prefix. 729class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm, 730 list<dag> pattern> 731 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 732 Requires<[UseSSE42]>; 733 734// SS42FI - SSE 4.2 instructions with T8XD prefix. 735// NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns. 736class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm, 737 list<dag> pattern> 738 : I<o, F, outs, ins, asm, pattern>, T8XD, Requires<[HasSSE42]>; 739 740// SS42AI = SSE 4.2 instructions with TA prefix 741class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm, 742 list<dag> pattern> 743 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 744 Requires<[UseSSE42]>; 745 746// AVX Instruction Templates: 747// Instructions introduced in AVX (no SSE equivalent forms) 748// 749// AVX8I - AVX instructions with T8PD prefix. 750// AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8. 751class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm, 752 list<dag> pattern> 753 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 754 Requires<[HasAVX]>; 755class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 756 list<dag> pattern> 757 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 758 Requires<[HasAVX]>; 759 760// AVX2 Instruction Templates: 761// Instructions introduced in AVX2 (no SSE equivalent forms) 762// 763// AVX28I - AVX2 instructions with T8PD prefix. 764// AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8. 765class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm, 766 list<dag> pattern> 767 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 768 Requires<[HasAVX2]>; 769class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 770 list<dag> pattern> 771 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 772 Requires<[HasAVX2]>; 773 774 775// AVX-512 Instruction Templates: 776// Instructions introduced in AVX-512 (no SSE equivalent forms) 777// 778// AVX5128I - AVX-512 instructions with T8PD prefix. 779// AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8. 780// AVX512PDI - AVX-512 instructions with PD, double packed. 781// AVX512PSI - AVX-512 instructions with PS, single packed. 782// AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. 783// AVX512XSI - AVX-512 instructions with XS prefix, generic domain. 784// AVX512BI - AVX-512 instructions with PD, int packed domain. 785// AVX512SI - AVX-512 scalar instructions with PD prefix. 786 787class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm, 788 list<dag> pattern> 789 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 790 Requires<[HasAVX512]>; 791class AVX5128IBase : T8PD { 792 Domain ExeDomain = SSEPackedInt; 793} 794class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm, 795 list<dag> pattern> 796 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8XS, 797 Requires<[HasAVX512]>; 798class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm, 799 list<dag> pattern> 800 : I<o, F, outs, ins, asm, pattern>, XS, 801 Requires<[HasAVX512]>; 802class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm, 803 list<dag> pattern> 804 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, XD, 805 Requires<[HasAVX512]>; 806class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm, 807 list<dag> pattern> 808 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, PD, 809 Requires<[HasAVX512]>; 810class AVX512BIBase : PD { 811 Domain ExeDomain = SSEPackedInt; 812} 813class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 814 list<dag> pattern> 815 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, PD, 816 Requires<[HasAVX512]>; 817class AVX512BIi8Base : PD { 818 Domain ExeDomain = SSEPackedInt; 819 ImmType ImmT = Imm8; 820} 821class AVX512XSIi8Base : XS { 822 Domain ExeDomain = SSEPackedInt; 823 ImmType ImmT = Imm8; 824} 825class AVX512XDIi8Base : XD { 826 Domain ExeDomain = SSEPackedInt; 827 ImmType ImmT = Imm8; 828} 829class AVX512PSIi8Base : PS { 830 Domain ExeDomain = SSEPackedSingle; 831 ImmType ImmT = Imm8; 832} 833class AVX512PDIi8Base : PD { 834 Domain ExeDomain = SSEPackedDouble; 835 ImmType ImmT = Imm8; 836} 837class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 838 list<dag> pattern> 839 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 840 Requires<[HasAVX512]>; 841class AVX512AIi8Base : TAPD { 842 ImmType ImmT = Imm8; 843} 844class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm, 845 list<dag> pattern> 846 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, 847 Requires<[HasAVX512]>; 848class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm, 849 list<dag> pattern> 850 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, PD, 851 Requires<[HasAVX512]>; 852class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm, 853 list<dag> pattern> 854 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, PS, 855 Requires<[HasAVX512]>; 856class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 857 list<dag> pattern, Domain d> 858 : Ii8<o, F, outs, ins, asm, pattern, d>, Requires<[HasAVX512]>; 859class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm, 860 list<dag> pattern, Domain d> 861 : I<o, F, outs, ins, asm, pattern, d>, Requires<[HasAVX512]>; 862class AVX512FMA3S<bits<8> o, Format F, dag outs, dag ins, string asm, 863 list<dag>pattern> 864 : I<o, F, outs, ins, asm, pattern>, T8PD, 865 EVEX_4V, Requires<[HasAVX512]>; 866class AVX512FMA3Base : T8PD, EVEX_4V; 867 868class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm, 869 list<dag>pattern> 870 : I<o, F, outs, ins, asm, pattern>, Requires<[HasAVX512]>; 871 872// AES Instruction Templates: 873// 874// AES8I 875// These use the same encoding as the SSE4.2 T8 and TA encodings. 876class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm, 877 list<dag>pattern> 878 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 879 Requires<[NoAVX, HasAES]>; 880 881class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm, 882 list<dag> pattern> 883 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 884 Requires<[NoAVX, HasAES]>; 885 886// PCLMUL Instruction Templates 887class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 888 list<dag>pattern> 889 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD; 890 891// FMA3 Instruction Templates 892class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm, 893 list<dag>pattern> 894 : I<o, F, outs, ins, asm, pattern>, T8PD, 895 VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>; 896class FMA3S<bits<8> o, Format F, dag outs, dag ins, string asm, 897 list<dag>pattern> 898 : I<o, F, outs, ins, asm, pattern>, T8PD, 899 VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>; 900class FMA3S_Int<bits<8> o, Format F, dag outs, dag ins, string asm, 901 list<dag>pattern> 902 : I<o, F, outs, ins, asm, pattern>, T8PD, 903 VEX_4V, FMASC, Requires<[HasFMA, NoAVX512]>; 904 905// FMA4 Instruction Templates 906class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm, 907 list<dag>pattern> 908 : Ii8Reg<o, F, outs, ins, asm, pattern>, TAPD, 909 VEX_4V, FMASC, Requires<[HasFMA4, NoVLX]>; 910class FMA4S<bits<8> o, Format F, dag outs, dag ins, string asm, 911 list<dag>pattern> 912 : Ii8Reg<o, F, outs, ins, asm, pattern>, TAPD, 913 VEX_4V, FMASC, Requires<[HasFMA4, NoAVX512]>; 914class FMA4S_Int<bits<8> o, Format F, dag outs, dag ins, string asm, 915 list<dag>pattern> 916 : Ii8Reg<o, F, outs, ins, asm, pattern>, TAPD, 917 VEX_4V, FMASC, Requires<[HasFMA4]>; 918 919// XOP 2, 3 and 4 Operand Instruction Template 920class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm, 921 list<dag> pattern> 922 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, 923 XOP9, Requires<[HasXOP]>; 924 925// XOP 2 and 3 Operand Instruction Templates with imm byte 926class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm, 927 list<dag> pattern> 928 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, 929 XOP8, Requires<[HasXOP]>; 930// XOP 4 Operand Instruction Templates with imm byte 931class IXOPi8Reg<bits<8> o, Format F, dag outs, dag ins, string asm, 932 list<dag> pattern> 933 : Ii8Reg<o, F, outs, ins, asm, pattern, SSEPackedDouble>, 934 XOP8, Requires<[HasXOP]>; 935 936// XOP 5 operand instruction (VEX encoding!) 937class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm, 938 list<dag>pattern> 939 : Ii8Reg<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 940 VEX_4V, Requires<[HasXOP]>; 941 942// X86-64 Instruction templates... 943// 944 945class RI<bits<8> o, Format F, dag outs, dag ins, string asm, 946 list<dag> pattern> 947 : I<o, F, outs, ins, asm, pattern>, REX_W; 948class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm, 949 list<dag> pattern> 950 : Ii8<o, F, outs, ins, asm, pattern>, REX_W; 951class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm, 952 list<dag> pattern> 953 : Ii16<o, F, outs, ins, asm, pattern>, REX_W; 954class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm, 955 list<dag> pattern> 956 : Ii32<o, F, outs, ins, asm, pattern>, REX_W; 957class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm, 958 list<dag> pattern> 959 : Ii32S<o, F, outs, ins, asm, pattern>, REX_W; 960class RIi64<bits<8> o, Format F, dag outs, dag ins, string asm, 961 list<dag> pattern> 962 : Ii64<o, F, outs, ins, asm, pattern>, REX_W; 963 964class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 965 list<dag> pattern> 966 : S2I<o, F, outs, ins, asm, pattern>, REX_W; 967class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 968 list<dag> pattern> 969 : VS2I<o, F, outs, ins, asm, pattern>, VEX_W; 970 971// MMX Instruction templates 972// 973 974// MMXI - MMX instructions with TB prefix. 975// MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode. 976// MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. 977// MMX2I - MMX / SSE2 instructions with PD prefix. 978// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. 979// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. 980// MMXID - MMX instructions with XD prefix. 981// MMXIS - MMX instructions with XS prefix. 982class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, 983 list<dag> pattern> 984 : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX]>; 985class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm, 986 list<dag> pattern> 987 : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX,Not64BitMode]>; 988class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm, 989 list<dag> pattern> 990 : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX,In64BitMode]>; 991class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, 992 list<dag> pattern> 993 : I<o, F, outs, ins, asm, pattern>, PS, REX_W, Requires<[HasMMX]>; 994class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, 995 list<dag> pattern> 996 : I<o, F, outs, ins, asm, pattern>, PD, Requires<[HasMMX]>; 997class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 998 list<dag> pattern> 999 : Ii8<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX]>; 1000class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, 1001 list<dag> pattern> 1002 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>; 1003class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, 1004 list<dag> pattern> 1005 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>; 1006