xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86InstrFormats.td (revision b1879975794772ee51f0b4865753364c7d7626c3)
1//===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// X86 Instruction Format Definitions.
11//
12
13// Format specifies the encoding used by the instruction.  This is part of the
14// ad-hoc solution used to emit machine instruction encodings by our machine
15// code emitter.
16class Format<bits<7> val> {
17  bits<7> Value = val;
18}
19
20def Pseudo        : Format<0>;
21def RawFrm        : Format<1>;
22def AddRegFrm     : Format<2>;
23def RawFrmMemOffs : Format<3>;
24def RawFrmSrc     : Format<4>;
25def RawFrmDst     : Format<5>;
26def RawFrmDstSrc  : Format<6>;
27def RawFrmImm8    : Format<7>;
28def RawFrmImm16   : Format<8>;
29def AddCCFrm      : Format<9>;
30def PrefixByte    : Format<10>;
31def MRMDestRegCC  : Format<18>;
32def MRMDestMemCC  : Format<19>;
33def MRMDestMem4VOp3CC : Format<20>;
34def MRMr0          : Format<21>;
35def MRMSrcMemFSIB  : Format<22>;
36def MRMDestMemFSIB : Format<23>;
37def MRMDestMem     : Format<24>;
38def MRMSrcMem      : Format<25>;
39def MRMSrcMem4VOp3 : Format<26>;
40def MRMSrcMemOp4   : Format<27>;
41def MRMSrcMemCC    : Format<28>;
42def MRMXmCC: Format<30>;
43def MRMXm  : Format<31>;
44def MRM0m  : Format<32>;  def MRM1m  : Format<33>;  def MRM2m  : Format<34>;
45def MRM3m  : Format<35>;  def MRM4m  : Format<36>;  def MRM5m  : Format<37>;
46def MRM6m  : Format<38>;  def MRM7m  : Format<39>;
47def MRMDestReg     : Format<40>;
48def MRMSrcReg      : Format<41>;
49def MRMSrcReg4VOp3 : Format<42>;
50def MRMSrcRegOp4   : Format<43>;
51def MRMSrcRegCC    : Format<44>;
52def MRMXrCC: Format<46>;
53def MRMXr  : Format<47>;
54def MRM0r  : Format<48>;  def MRM1r  : Format<49>;  def MRM2r  : Format<50>;
55def MRM3r  : Format<51>;  def MRM4r  : Format<52>;  def MRM5r  : Format<53>;
56def MRM6r  : Format<54>;  def MRM7r  : Format<55>;
57def MRM0X  : Format<56>;  def MRM1X  : Format<57>;  def MRM2X  : Format<58>;
58def MRM3X  : Format<59>;  def MRM4X  : Format<60>;  def MRM5X  : Format<61>;
59def MRM6X  : Format<62>;  def MRM7X  : Format<63>;
60def MRM_C0 : Format<64>;  def MRM_C1 : Format<65>;  def MRM_C2 : Format<66>;
61def MRM_C3 : Format<67>;  def MRM_C4 : Format<68>;  def MRM_C5 : Format<69>;
62def MRM_C6 : Format<70>;  def MRM_C7 : Format<71>;  def MRM_C8 : Format<72>;
63def MRM_C9 : Format<73>;  def MRM_CA : Format<74>;  def MRM_CB : Format<75>;
64def MRM_CC : Format<76>;  def MRM_CD : Format<77>;  def MRM_CE : Format<78>;
65def MRM_CF : Format<79>;  def MRM_D0 : Format<80>;  def MRM_D1 : Format<81>;
66def MRM_D2 : Format<82>;  def MRM_D3 : Format<83>;  def MRM_D4 : Format<84>;
67def MRM_D5 : Format<85>;  def MRM_D6 : Format<86>;  def MRM_D7 : Format<87>;
68def MRM_D8 : Format<88>;  def MRM_D9 : Format<89>;  def MRM_DA : Format<90>;
69def MRM_DB : Format<91>;  def MRM_DC : Format<92>;  def MRM_DD : Format<93>;
70def MRM_DE : Format<94>;  def MRM_DF : Format<95>;  def MRM_E0 : Format<96>;
71def MRM_E1 : Format<97>;  def MRM_E2 : Format<98>;  def MRM_E3 : Format<99>;
72def MRM_E4 : Format<100>; def MRM_E5 : Format<101>; def MRM_E6 : Format<102>;
73def MRM_E7 : Format<103>; def MRM_E8 : Format<104>; def MRM_E9 : Format<105>;
74def MRM_EA : Format<106>; def MRM_EB : Format<107>; def MRM_EC : Format<108>;
75def MRM_ED : Format<109>; def MRM_EE : Format<110>; def MRM_EF : Format<111>;
76def MRM_F0 : Format<112>; def MRM_F1 : Format<113>; def MRM_F2 : Format<114>;
77def MRM_F3 : Format<115>; def MRM_F4 : Format<116>; def MRM_F5 : Format<117>;
78def MRM_F6 : Format<118>; def MRM_F7 : Format<119>; def MRM_F8 : Format<120>;
79def MRM_F9 : Format<121>; def MRM_FA : Format<122>; def MRM_FB : Format<123>;
80def MRM_FC : Format<124>; def MRM_FD : Format<125>; def MRM_FE : Format<126>;
81def MRM_FF : Format<127>;
82
83// ImmType - This specifies the immediate type used by an instruction. This is
84// part of the ad-hoc solution used to emit machine instruction encodings by our
85// machine code emitter.
86class ImmType<bits<4> val> {
87  bits<4> Value = val;
88}
89def NoImm      : ImmType<0>;
90def Imm8       : ImmType<1>;
91def Imm8PCRel  : ImmType<2>;
92def Imm8Reg    : ImmType<3>; // Register encoded in [7:4].
93def Imm16      : ImmType<4>;
94def Imm16PCRel : ImmType<5>;
95def Imm32      : ImmType<6>;
96def Imm32PCRel : ImmType<7>;
97def Imm32S     : ImmType<8>;
98def Imm64      : ImmType<9>;
99
100// FPFormat - This specifies what form this FP instruction has.  This is used by
101// the Floating-Point stackifier pass.
102class FPFormat<bits<3> val> {
103  bits<3> Value = val;
104}
105def NotFP      : FPFormat<0>;
106def ZeroArgFP  : FPFormat<1>;
107def OneArgFP   : FPFormat<2>;
108def OneArgFPRW : FPFormat<3>;
109def TwoArgFP   : FPFormat<4>;
110def CompareFP  : FPFormat<5>;
111def CondMovFP  : FPFormat<6>;
112def SpecialFP  : FPFormat<7>;
113
114// Class specifying the SSE execution domain, used by the SSEDomainFix pass.
115// Keep in sync with tables in X86InstrInfo.cpp.
116class Domain<bits<2> val> {
117  bits<2> Value = val;
118}
119def GenericDomain   : Domain<0>;
120def SSEPackedSingle : Domain<1>;
121def SSEPackedDouble : Domain<2>;
122def SSEPackedInt    : Domain<3>;
123
124// Class specifying the vector form of the decompressed
125// displacement of 8-bit.
126class CD8VForm<bits<3> val> {
127  bits<3> Value = val;
128}
129def CD8VF  : CD8VForm<0>;  // v := VL
130def CD8VH  : CD8VForm<1>;  // v := VL/2
131def CD8VQ  : CD8VForm<2>;  // v := VL/4
132def CD8VO  : CD8VForm<3>;  // v := VL/8
133// The tuple (subvector) forms.
134def CD8VT1 : CD8VForm<4>;  // v := 1
135def CD8VT2 : CD8VForm<5>;  // v := 2
136def CD8VT4 : CD8VForm<6>;  // v := 4
137def CD8VT8 : CD8VForm<7>;  // v := 8
138
139// Class specifying the prefix used an opcode extension.
140class Prefix<bits<3> val> {
141  bits<3> Value = val;
142}
143def NoPrfx : Prefix<0>;
144def PD     : Prefix<1>;
145def XS     : Prefix<2>;
146def XD     : Prefix<3>;
147def PS     : Prefix<4>; // Similar to NoPrfx, but disassembler uses this to know
148                        // that other instructions with this opcode use PD/XS/XD
149                        // and if any of those is not supported they shouldn't
150                        // decode to this instruction. e.g. ANDSS/ANDSD don't
151                        // exist, but the 0xf2/0xf3 encoding shouldn't
152                        // disable to ANDPS.
153
154// Class specifying the opcode map.
155class Map<bits<4> val> {
156  bits<4> Value = val;
157}
158def OB        : Map<0>;
159def TB        : Map<1>;
160def T8        : Map<2>;
161def TA        : Map<3>;
162def XOP8      : Map<4>;
163def XOP9      : Map<5>;
164def XOPA      : Map<6>;
165def ThreeDNow : Map<7>;
166def T_MAP4    : Map<8>;
167def T_MAP5    : Map<9>;
168def T_MAP6    : Map<10>;
169def T_MAP7    : Map<11>;
170
171// Class specifying the encoding
172class Encoding<bits<2> val> {
173  bits<2> Value = val;
174}
175def EncNormal : Encoding<0>;
176def EncVEX    : Encoding<1>;
177def EncXOP    : Encoding<2>;
178def EncEVEX   : Encoding<3>;
179
180// Operand size for encodings that change based on mode.
181class OperandSize<bits<2> val> {
182  bits<2> Value = val;
183}
184def OpSizeFixed  : OperandSize<0>; // Never needs a 0x66 prefix.
185def OpSize16     : OperandSize<1>; // Needs 0x66 prefix in 32/64-bit mode.
186def OpSize32     : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
187
188// Address size for encodings that change based on mode.
189class AddressSize<bits<2> val> {
190  bits<2> Value = val;
191}
192def AdSizeX  : AddressSize<0>; // Address size determined using addr operand.
193def AdSize16 : AddressSize<1>; // Encodes a 16-bit address.
194def AdSize32 : AddressSize<2>; // Encodes a 32-bit address.
195def AdSize64 : AddressSize<3>; // Encodes a 64-bit address.
196
197// Force the instruction to use REX2/VEX/EVEX encoding.
198class ExplicitOpPrefix<bits<2> val> {
199  bits<2> Value = val;
200}
201def NoExplicitOpPrefix : ExplicitOpPrefix<0>;
202def ExplicitREX2       : ExplicitOpPrefix<1>;
203def ExplicitVEX        : ExplicitOpPrefix<2>;
204def ExplicitEVEX       : ExplicitOpPrefix<3>;
205
206class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
207              string AsmStr, Domain d = GenericDomain>
208  : Instruction {
209  let Namespace = "X86";
210
211  bits<8> Opcode = opcod;
212  Format Form = f;
213  bits<7> FormBits = Form.Value;
214  ImmType ImmT = i;
215
216  dag OutOperandList = outs;
217  dag InOperandList = ins;
218  string AsmString = AsmStr;
219
220  // If this is a pseudo instruction, mark it isCodeGenOnly.
221  let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
222
223  let HasPositionOrder = 1;
224
225  //
226  // Attributes specific to X86 instructions...
227  //
228  bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
229                            // isCodeGenonly. Needed to hide an ambiguous
230                            // AsmString from the parser, but still disassemble.
231
232  OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
233                                    // based on operand size of the mode?
234  bits<2> OpSizeBits = OpSize.Value;
235  AddressSize AdSize = AdSizeX; // Does this instruction's encoding change
236                                // based on address size of the mode?
237  bits<2> AdSizeBits = AdSize.Value;
238
239  Encoding OpEnc = EncNormal; // Encoding used by this instruction
240  // Which prefix byte does this inst have?
241  Prefix OpPrefix = !if(!eq(OpEnc, EncNormal), NoPrfx, PS);
242  bits<3> OpPrefixBits = OpPrefix.Value;
243  Map OpMap = OB;           // Which opcode map does this inst have?
244  bits<4> OpMapBits = OpMap.Value;
245  bit hasREX_W  = 0;  // Does this inst require the REX.W prefix?
246  FPFormat FPForm = NotFP;  // What flavor of FP instruction is this?
247  bit hasLockPrefix = 0;    // Does this inst have a 0xF0 prefix?
248  Domain ExeDomain = d;
249  bit hasREPPrefix = 0;     // Does this inst have a REP prefix?
250  bits<2> OpEncBits = OpEnc.Value;
251  bit IgnoresW = 0;         // Does this inst ignore REX_W field?
252  bit hasVEX_4V = 0;        // Does this inst require the VEX.VVVV field?
253  bit hasVEX_L = 0;         // Does this inst use large (256-bit) registers?
254  bit ignoresVEX_L = 0;     // Does this instruction ignore the L-bit
255  bit hasEVEX_K = 0;        // Does this inst require masking?
256  bit hasEVEX_Z = 0;        // Does this inst set the EVEX_Z field?
257  bit hasEVEX_L2 = 0;       // Does this inst set the EVEX_L2 field?
258  bit hasEVEX_B = 0;        // Does this inst set the EVEX_B field?
259  bit hasEVEX_NF = 0;       // Does this inst set the EVEX_NF field?
260  bit hasTwoConditionalOps = 0;   // Does this inst have two conditional operands?
261  bits<3> CD8_Form = 0;     // Compressed disp8 form - vector-width.
262  // Declare it int rather than bits<4> so that all bits are defined when
263  // assigning to bits<7>.
264  int CD8_EltSize = 0;      // Compressed disp8 form - element-size in bytes.
265  bit hasEVEX_RC = 0;       // Explicitly specified rounding control in FP instruction.
266  bit hasNoTrackPrefix = 0; // Does this inst has 0x3E (NoTrack) prefix?
267
268  // Vector size in bytes.
269  bits<7> VectSize = !if(hasEVEX_L2, 64, !if(hasVEX_L, 32, 16));
270
271  // The scaling factor for AVX512's compressed displacement is either
272  //   - the size of a  power-of-two number of elements or
273  //   - the size of a single element for broadcasts or
274  //   - the total vector size divided by a power-of-two number.
275  // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64.
276  bits<7> CD8_Scale = !if (!eq (OpEnc.Value, EncEVEX.Value),
277                           !if (CD8_Form{2},
278                                !shl(CD8_EltSize, CD8_Form{1-0}),
279                                !if (hasEVEX_B,
280                                     CD8_EltSize,
281                                     !srl(VectSize, CD8_Form{1-0}))), 0);
282
283  ExplicitOpPrefix explicitOpPrefix = NoExplicitOpPrefix;
284  bits<2> explicitOpPrefixBits = explicitOpPrefix.Value;
285  // TSFlags layout should be kept in sync with X86BaseInfo.h.
286  let TSFlags{6-0}   = FormBits;
287  let TSFlags{8-7}   = OpSizeBits;
288  let TSFlags{10-9}  = AdSizeBits;
289  // No need for 3rd bit, we don't need to distinguish NoPrfx from PS.
290  let TSFlags{12-11} = OpPrefixBits{1-0};
291  let TSFlags{16-13} = OpMapBits;
292  let TSFlags{17}    = hasREX_W;
293  let TSFlags{21-18} = ImmT.Value;
294  let TSFlags{24-22} = FPForm.Value;
295  let TSFlags{25}    = hasLockPrefix;
296  let TSFlags{26}    = hasREPPrefix;
297  let TSFlags{28-27} = ExeDomain.Value;
298  let TSFlags{30-29} = OpEncBits;
299  let TSFlags{38-31} = Opcode;
300  let TSFlags{39}    = hasVEX_4V;
301  let TSFlags{40}    = hasVEX_L;
302  let TSFlags{41}    = hasEVEX_K;
303  let TSFlags{42}    = hasEVEX_Z;
304  let TSFlags{43}    = hasEVEX_L2;
305  let TSFlags{44}    = hasEVEX_B;
306  let TSFlags{47-45} = !if(!eq(CD8_Scale, 0), 0, !add(!logtwo(CD8_Scale), 1));
307  let TSFlags{48}    = hasEVEX_RC;
308  let TSFlags{49}    = hasNoTrackPrefix;
309  let TSFlags{51-50} = explicitOpPrefixBits;
310  let TSFlags{52}    = hasEVEX_NF;
311  let TSFlags{53}    = hasTwoConditionalOps;
312}
313