1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 x87 FPU instruction set, defining the 10// instructions, and properties of the instructions which are needed for code 11// generation, machine code emission, and analysis. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// FPStack specific DAG Nodes. 17//===----------------------------------------------------------------------===// 18 19def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, 20 SDTCisPtrTy<1>]>; 21def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, 22 SDTCisPtrTy<1>]>; 23def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 24def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 25 26def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 27def SDTX86CwdLoad : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 28def SDTX86FPEnv : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 29 30def X86fp80_add : SDNode<"X86ISD::FP80_ADD", SDTFPBinOp, [SDNPCommutative]>; 31def X86strict_fp80_add : SDNode<"X86ISD::STRICT_FP80_ADD", SDTFPBinOp, 32 [SDNPHasChain,SDNPCommutative]>; 33def any_X86fp80_add : PatFrags<(ops node:$lhs, node:$rhs), 34 [(X86strict_fp80_add node:$lhs, node:$rhs), 35 (X86fp80_add node:$lhs, node:$rhs)]>; 36 37def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 38 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 39def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 40 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 41def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 42 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 43def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist, 44 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 45def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, 46 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 47def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 48 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 49 SDNPMemOperand]>; 50def X86fp_cwd_set16 : SDNode<"X86ISD::FLDCW16m", SDTX86CwdLoad, 51 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 52 SDNPMemOperand]>; 53def X86fpenv_get : SDNode<"X86ISD::FNSTENVm", SDTX86FPEnv, 54 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 55 SDNPMemOperand]>; 56def X86fpenv_set : SDNode<"X86ISD::FLDENVm", SDTX86FPEnv, 57 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 58 SDNPMemOperand]>; 59 60def X86fstf32 : PatFrag<(ops node:$val, node:$ptr), 61 (X86fst node:$val, node:$ptr), [{ 62 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 63}]>; 64def X86fstf64 : PatFrag<(ops node:$val, node:$ptr), 65 (X86fst node:$val, node:$ptr), [{ 66 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 67}]>; 68def X86fstf80 : PatFrag<(ops node:$val, node:$ptr), 69 (X86fst node:$val, node:$ptr), [{ 70 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 71}]>; 72 73def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 74 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 75}]>; 76def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 77 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 78}]>; 79def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 80 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 81}]>; 82 83def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 84 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 85}]>; 86def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 87 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 88}]>; 89def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 90 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 91}]>; 92 93def X86fist32 : PatFrag<(ops node:$val, node:$ptr), 94 (X86fist node:$val, node:$ptr), [{ 95 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 96}]>; 97 98def X86fist64 : PatFrag<(ops node:$val, node:$ptr), 99 (X86fist node:$val, node:$ptr), [{ 100 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 101}]>; 102 103def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), 104 (X86fp_to_mem node:$val, node:$ptr), [{ 105 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 106}]>; 107def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), 108 (X86fp_to_mem node:$val, node:$ptr), [{ 109 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 110}]>; 111def X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr), 112 (X86fp_to_mem node:$val, node:$ptr), [{ 113 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 114}]>; 115 116//===----------------------------------------------------------------------===// 117// FPStack pattern fragments 118//===----------------------------------------------------------------------===// 119 120def fpimm0 : FPImmLeaf<fAny, [{ 121 return Imm.isExactlyValue(+0.0); 122}]>; 123 124def fpimmneg0 : FPImmLeaf<fAny, [{ 125 return Imm.isExactlyValue(-0.0); 126}]>; 127 128def fpimm1 : FPImmLeaf<fAny, [{ 129 return Imm.isExactlyValue(+1.0); 130}]>; 131 132def fpimmneg1 : FPImmLeaf<fAny, [{ 133 return Imm.isExactlyValue(-1.0); 134}]>; 135 136// Some 'special' instructions - expanded after instruction selection. 137// Clobbers EFLAGS due to OR instruction used internally. 138// FIXME: Can we model this in SelectionDAG? 139let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in { 140 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 141 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 142 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 143 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 144 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 145 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 146 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 147 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 148 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 149 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 150 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 151 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 152 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 153 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 154 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 155 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 156 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 157 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 158 159 def FP80_ADDr : PseudoI<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 160 [(set RFP80:$dst, 161 (any_X86fp80_add RFP80:$src1, RFP80:$src2))]>; 162 def FP80_ADDm32 : PseudoI<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), 163 [(set RFP80:$dst, 164 (any_X86fp80_add RFP80:$src1, 165 (f80 (extloadf32 addr:$src2))))]>; 166} 167 168// All FP Stack operations are represented with four instructions here. The 169// first three instructions, generated by the instruction selector, use "RFP32" 170// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 171// 64-bit or 80-bit floating point values. These sizes apply to the values, 172// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 173// copied to each other without losing information. These instructions are all 174// pseudo instructions and use the "_Fp" suffix. 175// In some cases there are additional variants with a mixture of different 176// register sizes. 177// The second instruction is defined with FPI, which is the actual instruction 178// emitted by the assembler. These use "RST" registers, although frequently 179// the actual register(s) used are implicit. These are always 80 bits. 180// The FP stackifier pass converts one to the other after register allocation 181// occurs. 182// 183// Note that the FpI instruction should have instruction selection info (e.g. 184// a pattern) and the FPI instruction should have emission info (e.g. opcode 185// encoding and asm printing info). 186 187// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 188// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 189// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 190// f80 instructions cannot use SSE and use neither of these. 191class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 192 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 193class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 194 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 195 196// Factoring for arithmetic. 197multiclass FPBinary_rr<SDPatternOperator OpNode> { 198// Register op register -> register 199// These are separated out because they have no reversed form. 200def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 201 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 202def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 203 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 204def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 205 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 206} 207// The FopST0 series are not included here because of the irregularities 208// in where the 'r' goes in assembly output. 209// These instructions cannot address 80-bit memory. 210multiclass FPBinary<SDPatternOperator OpNode, Format fp, string asmstring, 211 bit Forward = 1> { 212// ST(0) = ST(0) + [mem] 213def _Fp32m : FpIf32<(outs RFP32:$dst), 214 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 215 [!if(Forward, 216 (set RFP32:$dst, 217 (OpNode RFP32:$src1, (loadf32 addr:$src2))), 218 (set RFP32:$dst, 219 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; 220def _Fp64m : FpIf64<(outs RFP64:$dst), 221 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 222 [!if(Forward, 223 (set RFP64:$dst, 224 (OpNode RFP64:$src1, (loadf64 addr:$src2))), 225 (set RFP64:$dst, 226 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; 227def _Fp64m32: FpIf64<(outs RFP64:$dst), 228 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 229 [!if(Forward, 230 (set RFP64:$dst, 231 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 232 (set RFP64:$dst, 233 (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 234def _Fp80m32: FpI_<(outs RFP80:$dst), 235 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 236 [!if(Forward, 237 (set RFP80:$dst, 238 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), 239 (set RFP80:$dst, 240 (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; 241def _Fp80m64: FpI_<(outs RFP80:$dst), 242 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 243 [!if(Forward, 244 (set RFP80:$dst, 245 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), 246 (set RFP80:$dst, 247 (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; 248let mayLoad = 1 in 249def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 250 !strconcat("f", asmstring, "{s}\t$src")>; 251let mayLoad = 1 in 252def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 253 !strconcat("f", asmstring, "{l}\t$src")>; 254// ST(0) = ST(0) + [memint] 255def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 256 OneArgFPRW, 257 [!if(Forward, 258 (set RFP32:$dst, 259 (OpNode RFP32:$src1, (X86fild16 addr:$src2))), 260 (set RFP32:$dst, 261 (OpNode (X86fild16 addr:$src2), RFP32:$src1)))]>; 262def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 263 OneArgFPRW, 264 [!if(Forward, 265 (set RFP32:$dst, 266 (OpNode RFP32:$src1, (X86fild32 addr:$src2))), 267 (set RFP32:$dst, 268 (OpNode (X86fild32 addr:$src2), RFP32:$src1)))]>; 269def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 270 OneArgFPRW, 271 [!if(Forward, 272 (set RFP64:$dst, 273 (OpNode RFP64:$src1, (X86fild16 addr:$src2))), 274 (set RFP64:$dst, 275 (OpNode (X86fild16 addr:$src2), RFP64:$src1)))]>; 276def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 277 OneArgFPRW, 278 [!if(Forward, 279 (set RFP64:$dst, 280 (OpNode RFP64:$src1, (X86fild32 addr:$src2))), 281 (set RFP64:$dst, 282 (OpNode (X86fild32 addr:$src2), RFP64:$src1)))]>; 283def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 284 OneArgFPRW, 285 [!if(Forward, 286 (set RFP80:$dst, 287 (OpNode RFP80:$src1, (X86fild16 addr:$src2))), 288 (set RFP80:$dst, 289 (OpNode (X86fild16 addr:$src2), RFP80:$src1)))]>; 290def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 291 OneArgFPRW, 292 [!if(Forward, 293 (set RFP80:$dst, 294 (OpNode RFP80:$src1, (X86fild32 addr:$src2))), 295 (set RFP80:$dst, 296 (OpNode (X86fild32 addr:$src2), RFP80:$src1)))]>; 297let mayLoad = 1 in 298def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 299 !strconcat("fi", asmstring, "{s}\t$src")>; 300let mayLoad = 1 in 301def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 302 !strconcat("fi", asmstring, "{l}\t$src")>; 303} 304 305let Uses = [FPCW], mayRaiseFPException = 1 in { 306// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 307// resources. 308let hasNoSchedulingInfo = 1 in { 309defm ADD : FPBinary_rr<any_fadd>; 310defm SUB : FPBinary_rr<any_fsub>; 311defm MUL : FPBinary_rr<any_fmul>; 312defm DIV : FPBinary_rr<any_fdiv>; 313} 314 315// Sets the scheduling resources for the actual NAME#_F<size>m definitions. 316let SchedRW = [WriteFAddLd] in { 317defm ADD : FPBinary<any_fadd, MRM0m, "add">; 318defm SUB : FPBinary<any_fsub, MRM4m, "sub">; 319defm SUBR: FPBinary<any_fsub ,MRM5m, "subr", 0>; 320} 321 322let SchedRW = [WriteFMulLd] in { 323defm MUL : FPBinary<any_fmul, MRM1m, "mul">; 324} 325 326let SchedRW = [WriteFDivLd] in { 327defm DIV : FPBinary<any_fdiv, MRM6m, "div">; 328defm DIVR: FPBinary<any_fdiv, MRM7m, "divr", 0>; 329} 330} // Uses = [FPCW], mayRaiseFPException = 1 331 332class FPST0rInst<Format fp, string asm> 333 : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>; 334class FPrST0Inst<Format fp, string asm> 335 : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>; 336class FPrST0PInst<Format fp, string asm> 337 : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>; 338 339// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 340// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 341// we have to put some 'r's in and take them out of weird places. 342let SchedRW = [WriteFAdd], Uses = [FPCW], mayRaiseFPException = 1 in { 343def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">; 344def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">; 345def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">; 346def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">; 347def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">; 348def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">; 349def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">; 350def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">; 351def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">; 352} // SchedRW 353let SchedRW = [WriteFCom], Uses = [FPCW], mayRaiseFPException = 1 in { 354def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 355def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 356} // SchedRW 357let SchedRW = [WriteFMul], Uses = [FPCW], mayRaiseFPException = 1 in { 358def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">; 359def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; 360def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">; 361} // SchedRW 362let SchedRW = [WriteFDiv], Uses = [FPCW], mayRaiseFPException = 1 in { 363def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">; 364def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">; 365def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">; 366def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">; 367def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">; 368def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">; 369} // SchedRW 370 371// Unary operations. 372multiclass FPUnary<SDPatternOperator OpNode, Format fp, string asmstring> { 373def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 374 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 375def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 376 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 377def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 378 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 379def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 380} 381 382let SchedRW = [WriteFSign] in { 383defm CHS : FPUnary<fneg, MRM_E0, "fchs">; 384defm ABS : FPUnary<fabs, MRM_E1, "fabs">; 385} 386 387let Uses = [FPCW], mayRaiseFPException = 1 in { 388let SchedRW = [WriteFSqrt80] in 389defm SQRT: FPUnary<any_fsqrt,MRM_FA, "fsqrt">; 390 391let SchedRW = [WriteFCom] in { 392let hasSideEffects = 0 in { 393def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 394def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 395def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 396} // hasSideEffects 397 398def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 399} // SchedRW 400} // Uses = [FPCW], mayRaiseFPException = 1 401 402let SchedRW = [WriteFTest], Defs = [FPSW] in { 403def XAM_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 404def XAM_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 405def XAM_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 406def XAM_F : FPI<0xD9, MRM_E5, (outs), (ins), "fxam">; 407} // SchedRW 408 409// Versions of FP instructions that take a single memory operand. Added for the 410// disassembler; remove as they are included with patterns elsewhere. 411let SchedRW = [WriteFComLd], Uses = [FPCW], mayRaiseFPException = 1, 412 mayLoad = 1 in { 413def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 414def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 415 416def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 417def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 418 419def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 420def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 421 422def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 423def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 424} // SchedRW 425 426let SchedRW = [WriteMicrocoded] in { 427let Defs = [FPSW, FPCW], mayLoad = 1 in { 428def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins anymem:$src), "frstor\t$src">; 429let Predicates = [HasX87] in 430def FLDENVm : I<0xD9, MRM4m, (outs), (ins anymem:$src), "fldenv\t$src", 431 [(X86fpenv_set addr:$src)]>; 432} 433 434let Defs = [FPSW, FPCW], Uses = [FPSW, FPCW], mayStore = 1 in { 435def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins anymem:$dst), "fnsave\t$dst">; 436let Predicates = [HasX87] in 437def FSTENVm : I<0xD9, MRM6m, (outs), (ins anymem:$dst), "fnstenv\t$dst", 438 [(X86fpenv_get addr:$dst)]>; 439} 440 441let Uses = [FPSW], mayStore = 1 in 442def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; 443 444let mayLoad = 1 in 445def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; 446let Uses = [FPCW] ,mayRaiseFPException = 1, mayStore = 1 in 447def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; 448} // SchedRW 449 450// Floating point cmovs. 451class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 452 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMOV]>; 453class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 454 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMOV]>; 455 456multiclass FPCMov<PatLeaf cc> { 457 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 458 CondMovFP, 459 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 460 cc, EFLAGS))]>; 461 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 462 CondMovFP, 463 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 464 cc, EFLAGS))]>; 465 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 466 CondMovFP, 467 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 468 cc, EFLAGS))]>, 469 Requires<[HasCMOV]>; 470} 471 472let SchedRW = [WriteFCMOV] in { 473let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 474defm CMOVB : FPCMov<X86_COND_B>; 475defm CMOVBE : FPCMov<X86_COND_BE>; 476defm CMOVE : FPCMov<X86_COND_E>; 477defm CMOVP : FPCMov<X86_COND_P>; 478defm CMOVNB : FPCMov<X86_COND_AE>; 479defm CMOVNBE: FPCMov<X86_COND_A>; 480defm CMOVNE : FPCMov<X86_COND_NE>; 481defm CMOVNP : FPCMov<X86_COND_NP>; 482} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 483 484let Predicates = [HasCMOV] in { 485// These are not factored because there's no clean way to pass DA/DB. 486def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op), 487 "fcmovb\t{$op, %st|st, $op}">; 488def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op), 489 "fcmovbe\t{$op, %st|st, $op}">; 490def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op), 491 "fcmove\t{$op, %st|st, $op}">; 492def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op), 493 "fcmovu\t{$op, %st|st, $op}">; 494def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op), 495 "fcmovnb\t{$op, %st|st, $op}">; 496def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op), 497 "fcmovnbe\t{$op, %st|st, $op}">; 498def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op), 499 "fcmovne\t{$op, %st|st, $op}">; 500def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op), 501 "fcmovnu\t{$op, %st|st, $op}">; 502} // Predicates = [HasCMOV] 503} // SchedRW 504 505let mayRaiseFPException = 1 in { 506// Floating point loads & stores. 507let SchedRW = [WriteLoad], Uses = [FPCW] in { 508let canFoldAsLoad = 1 in { 509def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 510 [(set RFP32:$dst, (loadf32 addr:$src))]>; 511def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 512 [(set RFP64:$dst, (loadf64 addr:$src))]>; 513def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 514 [(set RFP80:$dst, (loadf80 addr:$src))]>; 515} // canFoldAsLoad 516def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 517 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 518def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 519 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 520def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 521 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 522let mayRaiseFPException = 0 in { 523def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 524 [(set RFP32:$dst, (X86fild16 addr:$src))]>; 525def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 526 [(set RFP32:$dst, (X86fild32 addr:$src))]>; 527def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 528 [(set RFP32:$dst, (X86fild64 addr:$src))]>; 529def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 530 [(set RFP64:$dst, (X86fild16 addr:$src))]>; 531def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 532 [(set RFP64:$dst, (X86fild32 addr:$src))]>; 533def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 534 [(set RFP64:$dst, (X86fild64 addr:$src))]>; 535def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 536 [(set RFP80:$dst, (X86fild16 addr:$src))]>; 537def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 538 [(set RFP80:$dst, (X86fild32 addr:$src))]>; 539def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 540 [(set RFP80:$dst, (X86fild64 addr:$src))]>; 541} // mayRaiseFPException = 0 542} // SchedRW 543 544let SchedRW = [WriteStore], Uses = [FPCW] in { 545def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 546 [(store RFP32:$src, addr:$op)]>; 547def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 548 [(truncstoref32 RFP64:$src, addr:$op)]>; 549def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 550 [(store RFP64:$src, addr:$op)]>; 551def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 552 [(truncstoref32 RFP80:$src, addr:$op)]>; 553def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 554 [(truncstoref64 RFP80:$src, addr:$op)]>; 555// FST does not support 80-bit memory target; FSTP must be used. 556 557let mayStore = 1, hasSideEffects = 0 in { 558def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 559def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 560def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 561def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 562def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 563} // mayStore 564 565def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 566 [(store RFP80:$src, addr:$op)]>; 567 568let mayStore = 1, hasSideEffects = 0 in { 569def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 570def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 571 [(X86fist32 RFP32:$src, addr:$op)]>; 572def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 573 [(X86fist64 RFP32:$src, addr:$op)]>; 574def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 575def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 576 [(X86fist32 RFP64:$src, addr:$op)]>; 577def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 578 [(X86fist64 RFP64:$src, addr:$op)]>; 579def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 580def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 581 [(X86fist32 RFP80:$src, addr:$op)]>; 582def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 583 [(X86fist64 RFP80:$src, addr:$op)]>; 584} // mayStore 585} // SchedRW, Uses = [FPCW] 586 587let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in { 588def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; 589def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; 590def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; 591let mayRaiseFPException = 0 in { 592def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; 593def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; 594def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; 595} 596} 597let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 598def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; 599def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; 600def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; 601def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; 602def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; 603def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; 604def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; 605def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; 606def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; 607def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; 608} 609 610// FISTTP requires SSE3 even though it's a FPStack op. 611let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in { 612def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 613 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 614def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 615 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 616def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 617 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 618def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 619 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 620def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 621 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 622def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 623 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 624def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 625 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 626def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 627 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 628def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 629 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 630} // Predicates = [HasSSE3] 631 632let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 633def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; 634def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; 635def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; 636} 637 638// FP Stack manipulation instructions. 639let SchedRW = [WriteMove], Uses = [FPCW] in { 640def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">; 641def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">; 642def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">; 643let mayRaiseFPException = 0 in 644def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">; 645} 646 647// Floating point constant loads. 648let SchedRW = [WriteZero], Uses = [FPCW] in { 649def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 650 [(set RFP32:$dst, fpimm0)]>; 651def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 652 [(set RFP32:$dst, fpimm1)]>; 653def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 654 [(set RFP64:$dst, fpimm0)]>; 655def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 656 [(set RFP64:$dst, fpimm1)]>; 657def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 658 [(set RFP80:$dst, fpimm0)]>; 659def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 660 [(set RFP80:$dst, fpimm1)]>; 661} 662 663let SchedRW = [WriteFLD0], Uses = [FPCW], mayRaiseFPException = 0 in 664def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; 665 666let SchedRW = [WriteFLD1], Uses = [FPCW], mayRaiseFPException = 0 in 667def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; 668 669let SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW], mayRaiseFPException = 0 in { 670def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; 671def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; 672def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; 673def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>; 674def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>; 675} // SchedRW 676 677// Floating point compares. 678let SchedRW = [WriteFCom], Uses = [FPCW], hasSideEffects = 0 in { 679def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>; 680def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>; 681def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, []>; 682def COM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, []>; 683def COM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, []>; 684def COM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, []>; 685} // SchedRW 686} // mayRaiseFPException = 1 687 688let SchedRW = [WriteFCom], mayRaiseFPException = 1 in { 689// CC = ST(0) cmp ST(i) 690let Defs = [EFLAGS, FPSW], Uses = [FPCW] in { 691def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 692 [(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>, 693 Requires<[FPStackf32, HasCMOV]>; 694def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 695 [(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>, 696 Requires<[FPStackf64, HasCMOV]>; 697def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 698 [(set EFLAGS, (X86any_fcmp RFP80:$lhs, RFP80:$rhs))]>, 699 Requires<[HasCMOV]>; 700def COM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 701 [(set EFLAGS, (X86strict_fcmps RFP32:$lhs, RFP32:$rhs))]>, 702 Requires<[FPStackf32, HasCMOV]>; 703def COM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 704 [(set EFLAGS, (X86strict_fcmps RFP64:$lhs, RFP64:$rhs))]>, 705 Requires<[FPStackf64, HasCMOV]>; 706def COM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 707 [(set EFLAGS, (X86strict_fcmps RFP80:$lhs, RFP80:$rhs))]>, 708 Requires<[HasCMOV]>; 709} 710 711let Uses = [ST0, FPCW] in { 712def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 713 (outs), (ins RSTi:$reg), "fucom\t$reg">; 714def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 715 (outs), (ins RSTi:$reg), "fucomp\t$reg">; 716def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 717 (outs), (ins), "fucompp">; 718} 719 720let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in { 721def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 722 (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">; 723def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 724 (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">; 725 726def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg), 727 "fcomi\t{$reg, %st|st, $reg}">; 728def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg), 729 "fcompi\t{$reg, %st|st, $reg}">; 730} 731} // SchedRW 732 733// Floating point flag ops. 734let SchedRW = [WriteALU] in { 735let Defs = [AX, FPSW], Uses = [FPSW], hasSideEffects = 0 in 736def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 737 (outs), (ins), "fnstsw\t{%ax|ax}", []>; 738let Defs = [FPSW], Uses = [FPCW] in 739def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 740 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 741 [(X86fp_cwd_get16 addr:$dst)]>; 742} // SchedRW 743let Defs = [FPSW,FPCW], mayLoad = 1 in 744def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 745 (outs), (ins i16mem:$dst), "fldcw\t$dst", 746 [(X86fp_cwd_set16 addr:$dst)]>, 747 Sched<[WriteLoad]>; 748 749// FPU control instructions 750let SchedRW = [WriteMicrocoded] in { 751def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">; 752def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">; 753 754let Defs = [FPSW, FPCW] in 755def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; 756// Clear exceptions 757let Defs = [FPSW] in 758def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; 759} // SchedRW 760 761// Operand-less floating-point instructions for the disassembler. 762let Defs = [FPSW] in 763def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>; 764 765let SchedRW = [WriteMicrocoded] in { 766let Defs = [FPSW] in { 767def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; 768def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>; 769def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>; 770let Uses = [FPCW], mayRaiseFPException = 1 in { 771def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>; 772def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>; 773def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>; 774def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>; 775def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>; 776def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>; 777def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>; 778def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>; 779def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>; 780def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>; 781def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; 782def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>; 783def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>; 784def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>; 785} // Uses = [FPCW], mayRaiseFPException = 1 786} // Defs = [FPSW] 787 788let Uses = [FPSW, FPCW] in { 789def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 790 "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, PS, 791 Requires<[HasFXSR]>; 792def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 793 "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>, 794 PS, Requires<[HasFXSR, In64BitMode]>; 795} // Uses = [FPSW, FPCW] 796 797let Defs = [FPSW, FPCW] in { 798def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src), 799 "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>, 800 PS, Requires<[HasFXSR]>; 801def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), 802 "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>, 803 PS, Requires<[HasFXSR, In64BitMode]>; 804} // Defs = [FPSW, FPCW] 805} // SchedRW 806 807//===----------------------------------------------------------------------===// 808// Non-Instruction Patterns 809//===----------------------------------------------------------------------===// 810 811// Required for RET of f32 / f64 / f80 values. 812def : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>; 813def : Pat<(X86fldf32 addr:$src), (LD_Fp32m64 addr:$src)>; 814def : Pat<(X86fldf64 addr:$src), (LD_Fp64m addr:$src)>; 815def : Pat<(X86fldf32 addr:$src), (LD_Fp32m80 addr:$src)>; 816def : Pat<(X86fldf64 addr:$src), (LD_Fp64m80 addr:$src)>; 817def : Pat<(X86fldf80 addr:$src), (LD_Fp80m addr:$src)>; 818 819// Required for CALL which return f32 / f64 / f80 values. 820def : Pat<(X86fstf32 RFP32:$src, addr:$op), (ST_Fp32m addr:$op, RFP32:$src)>; 821def : Pat<(X86fstf32 RFP64:$src, addr:$op), (ST_Fp64m32 addr:$op, RFP64:$src)>; 822def : Pat<(X86fstf64 RFP64:$src, addr:$op), (ST_Fp64m addr:$op, RFP64:$src)>; 823def : Pat<(X86fstf32 RFP80:$src, addr:$op), (ST_Fp80m32 addr:$op, RFP80:$src)>; 824def : Pat<(X86fstf64 RFP80:$src, addr:$op), (ST_Fp80m64 addr:$op, RFP80:$src)>; 825def : Pat<(X86fstf80 RFP80:$src, addr:$op), (ST_FpP80m addr:$op, RFP80:$src)>; 826 827// Floating point constant -0.0 and -1.0 828def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 829def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 830def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 831def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 832def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 833def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 834 835// FP extensions map onto simple pseudo-value conversions if they are to/from 836// the FP stack. 837def : Pat<(f64 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 838 Requires<[FPStackf32]>; 839def : Pat<(f80 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 840 Requires<[FPStackf32]>; 841def : Pat<(f80 (any_fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 842 Requires<[FPStackf64]>; 843 844// FP truncations map onto simple pseudo-value conversions if they are to/from 845// the FP stack. We have validated that only value-preserving truncations make 846// it through isel. 847def : Pat<(f32 (any_fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 848 Requires<[FPStackf32]>; 849def : Pat<(f32 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 850 Requires<[FPStackf32]>; 851def : Pat<(f64 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 852 Requires<[FPStackf64]>; 853