1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 x87 FPU instruction set, defining the 10// instructions, and properties of the instructions which are needed for code 11// generation, machine code emission, and analysis. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// FPStack specific DAG Nodes. 17//===----------------------------------------------------------------------===// 18 19def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, 20 SDTCisPtrTy<1>]>; 21def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, 22 SDTCisPtrTy<1>]>; 23def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 24def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 25def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 26 27def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 28 29def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 30 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 31def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 32 [SDNPHasChain, SDNPInGlue, SDNPMayStore, 33 SDNPMemOperand]>; 34def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 35 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 36def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, 37 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, 38 SDNPMemOperand]>; 39def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist, 40 [SDNPHasChain, SDNPInGlue, SDNPMayStore, 41 SDNPMemOperand]>; 42def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; 43def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, 44 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 45def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 46 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 47 SDNPMemOperand]>; 48 49def X86fstf32 : PatFrag<(ops node:$val, node:$ptr), 50 (X86fst node:$val, node:$ptr), [{ 51 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 52}]>; 53def X86fstf64 : PatFrag<(ops node:$val, node:$ptr), 54 (X86fst node:$val, node:$ptr), [{ 55 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 56}]>; 57def X86fstf80 : PatFrag<(ops node:$val, node:$ptr), 58 (X86fst node:$val, node:$ptr), [{ 59 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 60}]>; 61 62def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 63 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 64}]>; 65def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 66 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 67}]>; 68def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 69 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 70}]>; 71 72def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 73 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 74}]>; 75def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 76 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 77}]>; 78def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 79 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 80}]>; 81 82def X86fildflag64 : PatFrag<(ops node:$ptr), (X86fildflag node:$ptr), [{ 83 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 84}]>; 85 86def X86fist64 : PatFrag<(ops node:$val, node:$ptr), 87 (X86fist node:$val, node:$ptr), [{ 88 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 89}]>; 90 91def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), 92 (X86fp_to_mem node:$val, node:$ptr), [{ 93 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 94}]>; 95def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), 96 (X86fp_to_mem node:$val, node:$ptr), [{ 97 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 98}]>; 99def X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr), 100 (X86fp_to_mem node:$val, node:$ptr), [{ 101 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 102}]>; 103 104//===----------------------------------------------------------------------===// 105// FPStack pattern fragments 106//===----------------------------------------------------------------------===// 107 108def fpimm0 : FPImmLeaf<fAny, [{ 109 return Imm.isExactlyValue(+0.0); 110}]>; 111 112def fpimmneg0 : FPImmLeaf<fAny, [{ 113 return Imm.isExactlyValue(-0.0); 114}]>; 115 116def fpimm1 : FPImmLeaf<fAny, [{ 117 return Imm.isExactlyValue(+1.0); 118}]>; 119 120def fpimmneg1 : FPImmLeaf<fAny, [{ 121 return Imm.isExactlyValue(-1.0); 122}]>; 123 124// Some 'special' instructions - expanded after instruction selection. 125// Clobbers EFLAGS due to OR instruction used internally. 126// FIXME: Can we model this in SelectionDAG? 127let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in { 128 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 129 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 130 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 131 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 132 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 133 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 134 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 135 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 136 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 137 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 138 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 139 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 140 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 141 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 142 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 143 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 144 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 145 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 146} 147 148// All FP Stack operations are represented with four instructions here. The 149// first three instructions, generated by the instruction selector, use "RFP32" 150// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 151// 64-bit or 80-bit floating point values. These sizes apply to the values, 152// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 153// copied to each other without losing information. These instructions are all 154// pseudo instructions and use the "_Fp" suffix. 155// In some cases there are additional variants with a mixture of different 156// register sizes. 157// The second instruction is defined with FPI, which is the actual instruction 158// emitted by the assembler. These use "RST" registers, although frequently 159// the actual register(s) used are implicit. These are always 80 bits. 160// The FP stackifier pass converts one to the other after register allocation 161// occurs. 162// 163// Note that the FpI instruction should have instruction selection info (e.g. 164// a pattern) and the FPI instruction should have emission info (e.g. opcode 165// encoding and asm printing info). 166 167// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 168// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 169// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 170// f80 instructions cannot use SSE and use neither of these. 171class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 172 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 173class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 174 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 175 176// Factoring for arithmetic. 177multiclass FPBinary_rr<SDNode OpNode> { 178// Register op register -> register 179// These are separated out because they have no reversed form. 180def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 181 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 182def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 183 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 184def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 185 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 186} 187// The FopST0 series are not included here because of the irregularities 188// in where the 'r' goes in assembly output. 189// These instructions cannot address 80-bit memory. 190multiclass FPBinary<SDNode OpNode, Format fp, string asmstring, 191 bit Forward = 1> { 192// ST(0) = ST(0) + [mem] 193def _Fp32m : FpIf32<(outs RFP32:$dst), 194 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 195 [!if(Forward, 196 (set RFP32:$dst, 197 (OpNode RFP32:$src1, (loadf32 addr:$src2))), 198 (set RFP32:$dst, 199 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; 200def _Fp64m : FpIf64<(outs RFP64:$dst), 201 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 202 [!if(Forward, 203 (set RFP64:$dst, 204 (OpNode RFP64:$src1, (loadf64 addr:$src2))), 205 (set RFP64:$dst, 206 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; 207def _Fp64m32: FpIf64<(outs RFP64:$dst), 208 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 209 [!if(Forward, 210 (set RFP64:$dst, 211 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 212 (set RFP64:$dst, 213 (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 214def _Fp80m32: FpI_<(outs RFP80:$dst), 215 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 216 [!if(Forward, 217 (set RFP80:$dst, 218 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), 219 (set RFP80:$dst, 220 (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; 221def _Fp80m64: FpI_<(outs RFP80:$dst), 222 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 223 [!if(Forward, 224 (set RFP80:$dst, 225 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), 226 (set RFP80:$dst, 227 (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; 228let mayLoad = 1 in 229def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 230 !strconcat("f", asmstring, "{s}\t$src")>; 231let mayLoad = 1 in 232def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 233 !strconcat("f", asmstring, "{l}\t$src")>; 234// ST(0) = ST(0) + [memint] 235def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 236 OneArgFPRW, 237 [!if(Forward, 238 (set RFP32:$dst, 239 (OpNode RFP32:$src1, (X86fild16 addr:$src2))), 240 (set RFP32:$dst, 241 (OpNode (X86fild16 addr:$src2), RFP32:$src1)))]>; 242def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 243 OneArgFPRW, 244 [!if(Forward, 245 (set RFP32:$dst, 246 (OpNode RFP32:$src1, (X86fild32 addr:$src2))), 247 (set RFP32:$dst, 248 (OpNode (X86fild32 addr:$src2), RFP32:$src1)))]>; 249def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 250 OneArgFPRW, 251 [!if(Forward, 252 (set RFP64:$dst, 253 (OpNode RFP64:$src1, (X86fild16 addr:$src2))), 254 (set RFP64:$dst, 255 (OpNode (X86fild16 addr:$src2), RFP64:$src1)))]>; 256def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 257 OneArgFPRW, 258 [!if(Forward, 259 (set RFP64:$dst, 260 (OpNode RFP64:$src1, (X86fild32 addr:$src2))), 261 (set RFP64:$dst, 262 (OpNode (X86fild32 addr:$src2), RFP64:$src1)))]>; 263def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 264 OneArgFPRW, 265 [!if(Forward, 266 (set RFP80:$dst, 267 (OpNode RFP80:$src1, (X86fild16 addr:$src2))), 268 (set RFP80:$dst, 269 (OpNode (X86fild16 addr:$src2), RFP80:$src1)))]>; 270def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 271 OneArgFPRW, 272 [!if(Forward, 273 (set RFP80:$dst, 274 (OpNode RFP80:$src1, (X86fild32 addr:$src2))), 275 (set RFP80:$dst, 276 (OpNode (X86fild32 addr:$src2), RFP80:$src1)))]>; 277let mayLoad = 1 in 278def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 279 !strconcat("fi", asmstring, "{s}\t$src")>; 280let mayLoad = 1 in 281def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 282 !strconcat("fi", asmstring, "{l}\t$src")>; 283} 284 285let Defs = [FPSW], Uses = [FPCW] in { 286// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 287// resources. 288let hasNoSchedulingInfo = 1 in { 289defm ADD : FPBinary_rr<fadd>; 290defm SUB : FPBinary_rr<fsub>; 291defm MUL : FPBinary_rr<fmul>; 292defm DIV : FPBinary_rr<fdiv>; 293} 294 295// Sets the scheduling resources for the actual NAME#_F<size>m defintions. 296let SchedRW = [WriteFAddLd] in { 297defm ADD : FPBinary<fadd, MRM0m, "add">; 298defm SUB : FPBinary<fsub, MRM4m, "sub">; 299defm SUBR: FPBinary<fsub ,MRM5m, "subr", 0>; 300} 301 302let SchedRW = [WriteFMulLd] in { 303defm MUL : FPBinary<fmul, MRM1m, "mul">; 304} 305 306let SchedRW = [WriteFDivLd] in { 307defm DIV : FPBinary<fdiv, MRM6m, "div">; 308defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>; 309} 310} // Defs = [FPSW] 311 312class FPST0rInst<Format fp, string asm> 313 : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>; 314class FPrST0Inst<Format fp, string asm> 315 : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>; 316class FPrST0PInst<Format fp, string asm> 317 : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>; 318 319// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 320// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 321// we have to put some 'r's in and take them out of weird places. 322let SchedRW = [WriteFAdd], Defs = [FPSW], Uses = [FPCW] in { 323def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">; 324def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">; 325def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">; 326def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">; 327def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">; 328def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">; 329def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">; 330def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">; 331def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">; 332} // SchedRW 333let SchedRW = [WriteFCom], Defs = [FPSW], Uses = [FPCW] in { 334def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 335def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 336} // SchedRW 337let SchedRW = [WriteFMul], Defs = [FPSW], Uses = [FPCW] in { 338def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">; 339def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; 340def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">; 341} // SchedRW 342let SchedRW = [WriteFDiv], Defs = [FPSW], Uses = [FPCW] in { 343def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">; 344def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">; 345def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">; 346def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">; 347def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">; 348def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">; 349} // SchedRW 350 351// Unary operations. 352multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> { 353def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 354 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 355def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 356 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 357def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 358 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 359def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 360} 361 362let Defs = [FPSW], Uses = [FPCW] in { 363 364let SchedRW = [WriteFSign] in { 365defm CHS : FPUnary<fneg, MRM_E0, "fchs">; 366defm ABS : FPUnary<fabs, MRM_E1, "fabs">; 367} 368 369let SchedRW = [WriteFSqrt80] in 370defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">; 371 372let SchedRW = [WriteMicrocoded] in { 373defm SIN : FPUnary<fsin, MRM_FE, "fsin">; 374defm COS : FPUnary<fcos, MRM_FF, "fcos">; 375} 376 377let SchedRW = [WriteFCom] in { 378let hasSideEffects = 0 in { 379def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 380def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 381def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 382} // hasSideEffects 383 384def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 385} // SchedRW 386} // Defs = [FPSW] 387 388// Versions of FP instructions that take a single memory operand. Added for the 389// disassembler; remove as they are included with patterns elsewhere. 390let SchedRW = [WriteFComLd], Defs = [FPSW], Uses = [FPCW] in { 391def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 392def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 393 394def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 395def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 396 397def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 398def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 399 400def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 401def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 402} // SchedRW 403 404let SchedRW = [WriteMicrocoded] in { 405def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; 406def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">; 407 408def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">; 409def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">; 410def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; 411 412def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; 413def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; 414} // SchedRW 415 416// Floating point cmovs. 417class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 418 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 419class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 420 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 421 422multiclass FPCMov<PatLeaf cc> { 423 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 424 CondMovFP, 425 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 426 cc, EFLAGS))]>; 427 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 428 CondMovFP, 429 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 430 cc, EFLAGS))]>; 431 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 432 CondMovFP, 433 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 434 cc, EFLAGS))]>, 435 Requires<[HasCMov]>; 436} 437 438let Defs = [FPSW] in { 439let SchedRW = [WriteFCMOV] in { 440let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 441defm CMOVB : FPCMov<X86_COND_B>; 442defm CMOVBE : FPCMov<X86_COND_BE>; 443defm CMOVE : FPCMov<X86_COND_E>; 444defm CMOVP : FPCMov<X86_COND_P>; 445defm CMOVNB : FPCMov<X86_COND_AE>; 446defm CMOVNBE: FPCMov<X86_COND_A>; 447defm CMOVNE : FPCMov<X86_COND_NE>; 448defm CMOVNP : FPCMov<X86_COND_NP>; 449} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 450 451let Predicates = [HasCMov] in { 452// These are not factored because there's no clean way to pass DA/DB. 453def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op), 454 "fcmovb\t{$op, %st|st, $op}">; 455def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op), 456 "fcmovbe\t{$op, %st|st, $op}">; 457def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op), 458 "fcmove\t{$op, %st|st, $op}">; 459def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op), 460 "fcmovu\t{$op, %st|st, $op}">; 461def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op), 462 "fcmovnb\t{$op, %st|st, $op}">; 463def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op), 464 "fcmovnbe\t{$op, %st|st, $op}">; 465def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op), 466 "fcmovne\t{$op, %st|st, $op}">; 467def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op), 468 "fcmovnu\t{$op, %st|st, $op}">; 469} // Predicates = [HasCMov] 470} // SchedRW 471 472// Floating point loads & stores. 473let SchedRW = [WriteLoad], Uses = [FPCW] in { 474let canFoldAsLoad = 1 in { 475def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 476 [(set RFP32:$dst, (loadf32 addr:$src))]>; 477def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 478 [(set RFP64:$dst, (loadf64 addr:$src))]>; 479def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 480 [(set RFP80:$dst, (loadf80 addr:$src))]>; 481} // canFoldAsLoad 482def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 483 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 484def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 485 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 486def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 487 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 488def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 489 [(set RFP32:$dst, (X86fild16 addr:$src))]>; 490def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 491 [(set RFP32:$dst, (X86fild32 addr:$src))]>; 492def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 493 [(set RFP32:$dst, (X86fild64 addr:$src))]>; 494def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 495 [(set RFP64:$dst, (X86fild16 addr:$src))]>; 496def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 497 [(set RFP64:$dst, (X86fild32 addr:$src))]>; 498def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 499 [(set RFP64:$dst, (X86fild64 addr:$src))]>; 500def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 501 [(set RFP80:$dst, (X86fild16 addr:$src))]>; 502def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 503 [(set RFP80:$dst, (X86fild32 addr:$src))]>; 504def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 505 [(set RFP80:$dst, (X86fild64 addr:$src))]>; 506} // SchedRW 507 508let SchedRW = [WriteStore], Uses = [FPCW] in { 509def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 510 [(store RFP32:$src, addr:$op)]>; 511def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 512 [(truncstoref32 RFP64:$src, addr:$op)]>; 513def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 514 [(store RFP64:$src, addr:$op)]>; 515def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 516 [(truncstoref32 RFP80:$src, addr:$op)]>; 517def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 518 [(truncstoref64 RFP80:$src, addr:$op)]>; 519// FST does not support 80-bit memory target; FSTP must be used. 520 521let mayStore = 1, hasSideEffects = 0 in { 522def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 523def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 524def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 525def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 526def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 527} // mayStore 528 529def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 530 [(store RFP80:$src, addr:$op)]>; 531 532let mayStore = 1, hasSideEffects = 0 in { 533def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 534def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; 535def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; 536def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 537def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; 538def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; 539def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 540def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; 541def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; 542} // mayStore 543} // SchedRW, Uses = [FPCW] 544 545let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in { 546def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; 547def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; 548def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; 549def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; 550def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; 551def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; 552} 553let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 554def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; 555def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; 556def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; 557def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; 558def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; 559def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; 560def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; 561def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; 562def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; 563def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; 564} 565 566// FISTTP requires SSE3 even though it's a FPStack op. 567let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in { 568def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 569 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 570def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 571 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 572def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 573 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 574def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 575 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 576def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 577 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 578def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 579 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 580def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 581 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 582def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 583 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 584def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 585 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 586} // Predicates = [HasSSE3] 587 588let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 589def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; 590def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; 591def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; 592} 593 594// FP Stack manipulation instructions. 595let SchedRW = [WriteMove], Uses = [FPCW] in { 596def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">; 597def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">; 598def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">; 599def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">; 600} 601 602// Floating point constant loads. 603let SchedRW = [WriteZero], Uses = [FPCW] in { 604def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 605 [(set RFP32:$dst, fpimm0)]>; 606def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 607 [(set RFP32:$dst, fpimm1)]>; 608def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 609 [(set RFP64:$dst, fpimm0)]>; 610def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 611 [(set RFP64:$dst, fpimm1)]>; 612def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 613 [(set RFP80:$dst, fpimm0)]>; 614def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 615 [(set RFP80:$dst, fpimm1)]>; 616} 617 618let SchedRW = [WriteFLD0], Uses = [FPCW] in 619def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; 620 621let SchedRW = [WriteFLD1], Uses = [FPCW] in 622def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; 623 624let SchedRW = [WriteFLDC], Uses = [FPCW] in { 625def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; 626def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; 627def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; 628def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>; 629def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>; 630} // SchedRW 631 632// Floating point compares. 633let SchedRW = [WriteFCom], Uses = [FPCW] in { 634def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 635 [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; 636def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 637 [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>; 638def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 639 [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>; 640} // SchedRW 641} // Defs = [FPSW] 642 643let SchedRW = [WriteFCom] in { 644// CC = ST(0) cmp ST(i) 645let Defs = [EFLAGS, FPSW], Uses = [FPCW] in { 646def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 647 [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>, 648 Requires<[FPStackf32, HasCMov]>; 649def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 650 [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>, 651 Requires<[FPStackf64, HasCMov]>; 652def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 653 [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>, 654 Requires<[HasCMov]>; 655} 656 657let Defs = [FPSW], Uses = [ST0, FPCW] in { 658def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 659 (outs), (ins RSTi:$reg), "fucom\t$reg">; 660def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 661 (outs), (ins RSTi:$reg), "fucomp\t$reg">; 662def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 663 (outs), (ins), "fucompp">; 664} 665 666let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in { 667def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 668 (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">; 669def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 670 (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">; 671 672def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg), 673 "fcomi\t{$reg, %st|st, $reg}">; 674def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg), 675 "fcompi\t{$reg, %st|st, $reg}">; 676} 677} // SchedRW 678 679// Floating point flag ops. 680let SchedRW = [WriteALU] in { 681let Defs = [AX], Uses = [FPSW] in 682def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 683 (outs), (ins), "fnstsw\t{%ax|ax}", 684 [(set AX, (X86fp_stsw FPSW))]>; 685let Defs = [FPSW], Uses = [FPCW] in 686def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 687 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 688 [(X86fp_cwd_get16 addr:$dst)]>; 689} // SchedRW 690let Defs = [FPSW,FPCW], mayLoad = 1 in 691def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 692 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>, 693 Sched<[WriteLoad]>; 694 695// FPU control instructions 696let SchedRW = [WriteMicrocoded] in { 697let Defs = [FPSW] in { 698def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; 699def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">; 700def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">; 701 702// Clear exceptions 703def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; 704} // Defs = [FPSW] 705} // SchedRW 706 707// Operand-less floating-point instructions for the disassembler. 708def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>; 709 710let SchedRW = [WriteMicrocoded] in { 711let Defs = [FPSW] in { 712def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; 713def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>; 714def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>; 715def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>; 716def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>; 717def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>; 718def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>; 719def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>; 720def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>; 721def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>; 722def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>; 723def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>; 724def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; 725def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>; 726def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>; 727def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>; 728} // Defs = [FPSW] 729 730def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 731 "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB, 732 Requires<[HasFXSR]>; 733def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 734 "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>, 735 TB, Requires<[HasFXSR, In64BitMode]>; 736def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src), 737 "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>, 738 TB, Requires<[HasFXSR]>; 739def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), 740 "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>, 741 TB, Requires<[HasFXSR, In64BitMode]>; 742} // SchedRW 743 744//===----------------------------------------------------------------------===// 745// Non-Instruction Patterns 746//===----------------------------------------------------------------------===// 747 748// Required for RET of f32 / f64 / f80 values. 749def : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>; 750def : Pat<(X86fldf64 addr:$src), (LD_Fp64m addr:$src)>; 751def : Pat<(X86fldf80 addr:$src), (LD_Fp80m addr:$src)>; 752 753// Required for CALL which return f32 / f64 / f80 values. 754def : Pat<(X86fstf32 RFP32:$src, addr:$op), (ST_Fp32m addr:$op, RFP32:$src)>; 755def : Pat<(X86fstf32 RFP64:$src, addr:$op), (ST_Fp64m32 addr:$op, RFP64:$src)>; 756def : Pat<(X86fstf64 RFP64:$src, addr:$op), (ST_Fp64m addr:$op, RFP64:$src)>; 757def : Pat<(X86fstf32 RFP80:$src, addr:$op), (ST_Fp80m32 addr:$op, RFP80:$src)>; 758def : Pat<(X86fstf64 RFP80:$src, addr:$op), (ST_Fp80m64 addr:$op, RFP80:$src)>; 759def : Pat<(X86fstf80 RFP80:$src, addr:$op), (ST_FpP80m addr:$op, RFP80:$src)>; 760 761// Floating point constant -0.0 and -1.0 762def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 763def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 764def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 765def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 766def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 767def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 768 769// Used to conv. i64 to f64 since there isn't a SSE version. 770def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m64 addr:$src)>; 771 772// Used to conv. between f80 and i64 for i64 atomic loads. 773def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m80 addr:$src)>; 774def : Pat<(X86fist64 RFP80:$src, addr:$op), (IST_Fp64m80 addr:$op, RFP80:$src)>; 775 776// FP extensions map onto simple pseudo-value conversions if they are to/from 777// the FP stack. 778def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 779 Requires<[FPStackf32]>; 780def : Pat<(f80 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 781 Requires<[FPStackf32]>; 782def : Pat<(f80 (fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 783 Requires<[FPStackf64]>; 784 785// FP truncations map onto simple pseudo-value conversions if they are to/from 786// the FP stack. We have validated that only value-preserving truncations make 787// it through isel. 788def : Pat<(f32 (fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 789 Requires<[FPStackf32]>; 790def : Pat<(f32 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 791 Requires<[FPStackf32]>; 792def : Pat<(f64 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 793 Requires<[FPStackf64]>; 794