xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86InstrCompiler.td (revision e9e8876a4d6afc1ad5315faaa191b25121a813d7)
1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the various pseudo instructions used by the compiler,
10// as well as Pat patterns used during instruction selection.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Pattern Matching Support
16
17def GetLo32XForm : SDNodeXForm<imm, [{
18  // Transformation function: get the low 32 bits.
19  return getI32Imm((uint32_t)N->getZExtValue(), SDLoc(N));
20}]>;
21
22
23//===----------------------------------------------------------------------===//
24// Random Pseudo Instructions.
25
26// PIC base construction.  This expands to code that looks like this:
27//     call  $next_inst
28//     popl %destreg"
29let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP],
30    SchedRW = [WriteJump] in
31  def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
32                      "", []>;
33
34// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
35// a stack adjustment and the codegen must know that they may modify the stack
36// pointer before prolog-epilog rewriting occurs.
37// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
38// sub / add which can clobber EFLAGS.
39let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in {
40def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs),
41                           (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
42                           "#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>;
43def ADJCALLSTACKUP32   : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
44                           "#ADJCALLSTACKUP",
45                           [(X86callseq_end timm:$amt1, timm:$amt2)]>,
46                           Requires<[NotLP64]>;
47}
48def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
49       (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>;
50
51
52// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
53// a stack adjustment and the codegen must know that they may modify the stack
54// pointer before prolog-epilog rewriting occurs.
55// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
56// sub / add which can clobber EFLAGS.
57let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in {
58def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs),
59                           (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
60                           "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>;
61def ADJCALLSTACKUP64   : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
62                           "#ADJCALLSTACKUP",
63                           [(X86callseq_end timm:$amt1, timm:$amt2)]>,
64                           Requires<[IsLP64]>;
65}
66def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
67        (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>;
68
69let SchedRW = [WriteSystem] in {
70
71// x86-64 va_start lowering magic.
72let hasSideEffects = 1, Defs = [EFLAGS] in {
73def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
74                              (outs),
75                              (ins GR8:$al,
76                                   i32imm:$regsavefi, i32imm:$offset,
77                                   variable_ops),
78                              "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
79                              [(X86vastart_save_xmm_regs GR8:$al,
80                                                         timm:$regsavefi,
81                                                         timm:$offset),
82                               (implicit EFLAGS)]>;
83}
84
85let usesCustomInserter = 1, Defs = [EFLAGS] in {
86// The VAARG_64 and VAARG_X32 pseudo-instructions take the address of the
87// va_list, and place the address of the next argument into a register.
88let Defs = [EFLAGS] in {
89def VAARG_64 : I<0, Pseudo,
90                 (outs GR64:$dst),
91                 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92                 "#VAARG_64 $dst, $ap, $size, $mode, $align",
93                 [(set GR64:$dst,
94                    (X86vaarg64 addr:$ap, timm:$size, timm:$mode, timm:$align)),
95                  (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>;
96def VAARG_X32 : I<0, Pseudo,
97                 (outs GR32:$dst),
98                 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
99                 "#VAARG_X32 $dst, $ap, $size, $mode, $align",
100                 [(set GR32:$dst,
101                    (X86vaargx32 addr:$ap, timm:$size, timm:$mode, timm:$align)),
102                  (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>;
103}
104
105// When using segmented stacks these are lowered into instructions which first
106// check if the current stacklet has enough free memory. If it does, memory is
107// allocated by bumping the stack pointer. Otherwise memory is allocated from
108// the heap.
109
110let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
111def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
112                      "# variable sized alloca for segmented stacks",
113                      [(set GR32:$dst,
114                         (X86SegAlloca GR32:$size))]>,
115                    Requires<[NotLP64]>;
116
117let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
118def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
119                      "# variable sized alloca for segmented stacks",
120                      [(set GR64:$dst,
121                         (X86SegAlloca GR64:$size))]>,
122                    Requires<[In64BitMode]>;
123
124// To protect against stack clash, dynamic allocation should perform a memory
125// probe at each page.
126
127let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
128def PROBED_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
129                      "# variable sized alloca with probing",
130                      [(set GR32:$dst,
131                         (X86ProbedAlloca GR32:$size))]>,
132                    Requires<[NotLP64]>;
133
134let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
135def PROBED_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
136                      "# variable sized alloca with probing",
137                      [(set GR64:$dst,
138                         (X86ProbedAlloca GR64:$size))]>,
139                    Requires<[In64BitMode]>;
140}
141
142let hasNoSchedulingInfo = 1 in
143def STACKALLOC_W_PROBING : I<0, Pseudo, (outs), (ins i64imm:$stacksize),
144                             "# fixed size alloca with probing",
145                             []>;
146
147// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
148// targets.  These calls are needed to probe the stack when allocating more than
149// 4k bytes in one go. Touching the stack at 4K increments is necessary to
150// ensure that the guard pages used by the OS virtual memory manager are
151// allocated in correct sequence.
152// The main point of having separate instruction are extra unmodelled effects
153// (compared to ordinary calls) like stack pointer change.
154
155let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
156def WIN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size),
157                     "# dynamic stack allocation",
158                     [(X86WinAlloca GR32:$size)]>,
159                     Requires<[NotLP64]>;
160
161let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
162def WIN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size),
163                     "# dynamic stack allocation",
164                     [(X86WinAlloca GR64:$size)]>,
165                     Requires<[In64BitMode]>;
166} // SchedRW
167
168// These instructions XOR the frame pointer into a GPR. They are used in some
169// stack protection schemes. These are post-RA pseudos because we only know the
170// frame register after register allocation.
171let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in {
172  def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
173                  "xorl\t$$FP, $src", []>,
174                  Requires<[NotLP64]>, Sched<[WriteALU]>;
175  def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src),
176                  "xorq\t$$FP $src", []>,
177                  Requires<[In64BitMode]>, Sched<[WriteALU]>;
178}
179
180//===----------------------------------------------------------------------===//
181// EH Pseudo Instructions
182//
183let SchedRW = [WriteSystem] in {
184let isTerminator = 1, isReturn = 1, isBarrier = 1,
185    hasCtrlDep = 1, isCodeGenOnly = 1 in {
186def EH_RETURN   : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
187                    "ret\t#eh_return, addr: $addr",
188                    [(X86ehret GR32:$addr)]>, Sched<[WriteJumpLd]>;
189
190}
191
192let isTerminator = 1, isReturn = 1, isBarrier = 1,
193    hasCtrlDep = 1, isCodeGenOnly = 1 in {
194def EH_RETURN64   : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
195                     "ret\t#eh_return, addr: $addr",
196                     [(X86ehret GR64:$addr)]>, Sched<[WriteJumpLd]>;
197
198}
199
200let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,
201    isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1 in {
202  def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>;
203
204  // CATCHRET needs a custom inserter for SEH.
205  let usesCustomInserter = 1 in
206    def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from),
207                     "# CATCHRET",
208                     [(catchret bb:$dst, bb:$from)]>;
209}
210
211let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
212    usesCustomInserter = 1 in {
213  def EH_SjLj_SetJmp32  : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
214                            "#EH_SJLJ_SETJMP32",
215                            [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
216                          Requires<[Not64BitMode]>;
217  def EH_SjLj_SetJmp64  : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
218                            "#EH_SJLJ_SETJMP64",
219                            [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
220                          Requires<[In64BitMode]>;
221  let isTerminator = 1 in {
222  def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
223                            "#EH_SJLJ_LONGJMP32",
224                            [(X86eh_sjlj_longjmp addr:$buf)]>,
225                          Requires<[Not64BitMode]>;
226  def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
227                            "#EH_SJLJ_LONGJMP64",
228                            [(X86eh_sjlj_longjmp addr:$buf)]>,
229                          Requires<[In64BitMode]>;
230  }
231}
232
233let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
234  def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
235                        "#EH_SjLj_Setup\t$dst", []>;
236}
237} // SchedRW
238
239//===----------------------------------------------------------------------===//
240// Pseudo instructions used by unwind info.
241//
242let isPseudo = 1, SchedRW = [WriteSystem] in {
243  def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
244                            "#SEH_PushReg $reg", []>;
245  def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
246                            "#SEH_SaveReg $reg, $dst", []>;
247  def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
248                            "#SEH_SaveXMM $reg, $dst", []>;
249  def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
250                            "#SEH_StackAlloc $size", []>;
251  def SEH_StackAlign : I<0, Pseudo, (outs), (ins i32imm:$align),
252                            "#SEH_StackAlign $align", []>;
253  def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
254                            "#SEH_SetFrame $reg, $offset", []>;
255  def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
256                            "#SEH_PushFrame $mode", []>;
257  def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
258                            "#SEH_EndPrologue", []>;
259  def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
260                            "#SEH_Epilogue", []>;
261}
262
263//===----------------------------------------------------------------------===//
264// Pseudo instructions used by segmented stacks.
265//
266
267// This is lowered into a RET instruction by MCInstLower.  We need
268// this so that we don't have to have a MachineBasicBlock which ends
269// with a RET and also has successors.
270let isPseudo = 1, SchedRW = [WriteJumpLd] in {
271def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>;
272
273// This instruction is lowered to a RET followed by a MOV.  The two
274// instructions are not generated on a higher level since then the
275// verifier sees a MachineBasicBlock ending with a non-terminator.
276def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>;
277}
278
279//===----------------------------------------------------------------------===//
280// Alias Instructions
281//===----------------------------------------------------------------------===//
282
283// Alias instruction mapping movr0 to xor.
284// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
285let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
286    isPseudo = 1, isMoveImm = 1, AddedComplexity = 10 in
287def MOV32r0  : I<0, Pseudo, (outs GR32:$dst), (ins), "",
288                 [(set GR32:$dst, 0)]>, Sched<[WriteZero]>;
289
290// Other widths can also make use of the 32-bit xor, which may have a smaller
291// encoding and avoid partial register updates.
292let AddedComplexity = 10 in {
293def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
294def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
295def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>;
296}
297
298let Predicates = [OptForSize, Not64BitMode],
299    AddedComplexity = 10 in {
300  let SchedRW = [WriteALU] in {
301  // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC,
302  // which only require 3 bytes compared to MOV32ri which requires 5.
303  let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in {
304    def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
305                        [(set GR32:$dst, 1)]>;
306    def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
307                        [(set GR32:$dst, -1)]>;
308  }
309  } // SchedRW
310
311  // MOV16ri is 4 bytes, so the instructions above are smaller.
312  def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
313  def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
314}
315
316let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5,
317    SchedRW = [WriteALU] in {
318// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1.
319def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "",
320                       [(set GR32:$dst, i32immSExt8:$src)]>,
321                       Requires<[OptForMinSize, NotWin64WithoutFP]>;
322def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "",
323                       [(set GR64:$dst, i64immSExt8:$src)]>,
324                       Requires<[OptForMinSize, NotWin64WithoutFP]>;
325}
326
327// Materialize i64 constant where top 32-bits are zero. This could theoretically
328// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
329// that would make it more difficult to rematerialize.
330let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
331    isPseudo = 1, SchedRW = [WriteMove] in
332def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "",
333                  [(set GR64:$dst, i64immZExt32:$src)]>;
334
335// This 64-bit pseudo-move can also be used for labels in the x86-64 small code
336// model.
337def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [X86Wrapper]>;
338def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>;
339
340// Use sbb to materialize carry bit.
341let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteADC],
342    hasSideEffects = 0 in {
343// FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
344// However, Pat<> can't replicate the destination reg into the inputs of the
345// result.
346def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", []>;
347def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", []>;
348} // isCodeGenOnly
349
350//===----------------------------------------------------------------------===//
351// String Pseudo Instructions
352//
353let SchedRW = [WriteMicrocoded] in {
354let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
355def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins),
356                    "{rep;movsb (%esi), %es:(%edi)|rep movsb es:[edi], [esi]}",
357                    [(X86rep_movs i8)]>, REP, AdSize32,
358                   Requires<[NotLP64]>;
359def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins),
360                    "{rep;movsw (%esi), %es:(%edi)|rep movsw es:[edi], [esi]}",
361                    [(X86rep_movs i16)]>, REP, AdSize32, OpSize16,
362                   Requires<[NotLP64]>;
363def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins),
364                    "{rep;movsl (%esi), %es:(%edi)|rep movsd es:[edi], [esi]}",
365                    [(X86rep_movs i32)]>, REP, AdSize32, OpSize32,
366                   Requires<[NotLP64]>;
367def REP_MOVSQ_32 : RI<0xA5, RawFrm, (outs), (ins),
368                    "{rep;movsq (%esi), %es:(%edi)|rep movsq es:[edi], [esi]}",
369                    [(X86rep_movs i64)]>, REP, AdSize32,
370                   Requires<[NotLP64, In64BitMode]>;
371}
372
373let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
374def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins),
375                    "{rep;movsb (%rsi), %es:(%rdi)|rep movsb es:[rdi], [rsi]}",
376                    [(X86rep_movs i8)]>, REP, AdSize64,
377                   Requires<[IsLP64]>;
378def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins),
379                    "{rep;movsw (%rsi), %es:(%rdi)|rep movsw es:[rdi], [rsi]}",
380                    [(X86rep_movs i16)]>, REP, AdSize64, OpSize16,
381                   Requires<[IsLP64]>;
382def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins),
383                    "{rep;movsl (%rsi), %es:(%rdi)|rep movsdi es:[rdi], [rsi]}",
384                    [(X86rep_movs i32)]>, REP, AdSize64, OpSize32,
385                   Requires<[IsLP64]>;
386def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins),
387                    "{rep;movsq (%rsi), %es:(%rdi)|rep movsq es:[rdi], [rsi]}",
388                    [(X86rep_movs i64)]>, REP, AdSize64,
389                   Requires<[IsLP64]>;
390}
391
392// FIXME: Should use "(X86rep_stos AL)" as the pattern.
393let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
394  let Uses = [AL,ECX,EDI] in
395  def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins),
396                       "{rep;stosb %al, %es:(%edi)|rep stosb es:[edi], al}",
397                      [(X86rep_stos i8)]>, REP, AdSize32,
398                     Requires<[NotLP64]>;
399  let Uses = [AX,ECX,EDI] in
400  def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins),
401                      "{rep;stosw %ax, %es:(%edi)|rep stosw es:[edi], ax}",
402                      [(X86rep_stos i16)]>, REP, AdSize32, OpSize16,
403                     Requires<[NotLP64]>;
404  let Uses = [EAX,ECX,EDI] in
405  def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins),
406                      "{rep;stosl %eax, %es:(%edi)|rep stosd es:[edi], eax}",
407                      [(X86rep_stos i32)]>, REP, AdSize32, OpSize32,
408                     Requires<[NotLP64]>;
409  let Uses = [RAX,RCX,RDI] in
410  def REP_STOSQ_32 : RI<0xAB, RawFrm, (outs), (ins),
411                        "{rep;stosq %rax, %es:(%edi)|rep stosq es:[edi], rax}",
412                        [(X86rep_stos i64)]>, REP, AdSize32,
413                        Requires<[NotLP64, In64BitMode]>;
414}
415
416let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
417  let Uses = [AL,RCX,RDI] in
418  def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins),
419                       "{rep;stosb %al, %es:(%rdi)|rep stosb es:[rdi], al}",
420                       [(X86rep_stos i8)]>, REP, AdSize64,
421                       Requires<[IsLP64]>;
422  let Uses = [AX,RCX,RDI] in
423  def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins),
424                       "{rep;stosw %ax, %es:(%rdi)|rep stosw es:[rdi], ax}",
425                       [(X86rep_stos i16)]>, REP, AdSize64, OpSize16,
426                       Requires<[IsLP64]>;
427  let Uses = [RAX,RCX,RDI] in
428  def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins),
429                      "{rep;stosl %eax, %es:(%rdi)|rep stosd es:[rdi], eax}",
430                       [(X86rep_stos i32)]>, REP, AdSize64, OpSize32,
431                       Requires<[IsLP64]>;
432
433  let Uses = [RAX,RCX,RDI] in
434  def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins),
435                        "{rep;stosq %rax, %es:(%rdi)|rep stosq es:[rdi], rax}",
436                        [(X86rep_stos i64)]>, REP, AdSize64,
437                        Requires<[IsLP64]>;
438}
439} // SchedRW
440
441//===----------------------------------------------------------------------===//
442// Thread Local Storage Instructions
443//
444let SchedRW = [WriteSystem] in {
445
446// ELF TLS Support
447// All calls clobber the non-callee saved registers. ESP is marked as
448// a use to prevent stack-pointer assignments that appear immediately
449// before calls from potentially appearing dead.
450let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
451            ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
452            MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
453            XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
454            XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],
455    usesCustomInserter = 1, Uses = [ESP, SSP] in {
456def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
457                  "# TLS_addr32",
458                  [(X86tlsaddr tls32addr:$sym)]>,
459                  Requires<[Not64BitMode]>;
460def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
461                  "# TLS_base_addr32",
462                  [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
463                  Requires<[Not64BitMode]>;
464}
465
466// All calls clobber the non-callee saved registers. RSP is marked as
467// a use to prevent stack-pointer assignments that appear immediately
468// before calls from potentially appearing dead.
469let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
470            FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
471            ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
472            MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
473            XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
474            XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],
475    usesCustomInserter = 1, Uses = [RSP, SSP] in {
476def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
477                   "# TLS_addr64",
478                  [(X86tlsaddr tls64addr:$sym)]>,
479                  Requires<[In64BitMode, IsLP64]>;
480def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
481                   "# TLS_base_addr64",
482                  [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
483                  Requires<[In64BitMode, IsLP64]>;
484def TLS_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
485                   "# TLS_addrX32",
486                  [(X86tlsaddr tls32addr:$sym)]>,
487                  Requires<[In64BitMode, NotLP64]>;
488def TLS_base_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
489                   "# TLS_base_addrX32",
490                  [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
491                  Requires<[In64BitMode, NotLP64]>;
492}
493
494// Darwin TLS Support
495// For i386, the address of the thunk is passed on the stack, on return the
496// address of the variable is in %eax.  %ecx is trashed during the function
497// call.  All other registers are preserved.
498let Defs = [EAX, ECX, EFLAGS, DF],
499    Uses = [ESP, SSP],
500    usesCustomInserter = 1 in
501def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
502                "# TLSCall_32",
503                [(X86TLSCall addr:$sym)]>,
504                Requires<[Not64BitMode]>;
505
506// For x86_64, the address of the thunk is passed in %rdi, but the
507// pseudo directly use the symbol, so do not add an implicit use of
508// %rdi. The lowering will do the right thing with RDI.
509// On return the address of the variable is in %rax.  All other
510// registers are preserved.
511let Defs = [RAX, EFLAGS, DF],
512    Uses = [RSP, SSP],
513    usesCustomInserter = 1 in
514def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
515                  "# TLSCall_64",
516                  [(X86TLSCall addr:$sym)]>,
517                  Requires<[In64BitMode]>;
518} // SchedRW
519
520//===----------------------------------------------------------------------===//
521// Conditional Move Pseudo Instructions
522
523// CMOV* - Used to implement the SELECT DAG operation.  Expanded after
524// instruction selection into a branch sequence.
525multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {
526  def CMOV#NAME  : I<0, Pseudo,
527                    (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),
528                    "#CMOV_"#NAME#" PSEUDO!",
529                    [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, timm:$cond,
530                                                EFLAGS)))]>;
531}
532
533let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in {
534  // X86 doesn't have 8-bit conditional moves. Use a customInserter to
535  // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
536  // however that requires promoting the operands, and can induce additional
537  // i8 register pressure.
538  defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
539
540  let Predicates = [NoCMov] in {
541    defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
542    defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
543  } // Predicates = [NoCMov]
544
545  // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
546  // SSE1/SSE2.
547  let Predicates = [FPStackf32] in
548    defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;
549
550  let Predicates = [FPStackf64] in
551    defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;
552
553  defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
554
555  let Predicates = [HasMMX] in
556    defm _VR64   : CMOVrr_PSEUDO<VR64, x86mmx>;
557
558  let Predicates = [HasSSE1,NoAVX512] in
559    defm _FR32   : CMOVrr_PSEUDO<FR32, f32>;
560  let Predicates = [HasSSE2,NoAVX512] in
561    defm _FR64   : CMOVrr_PSEUDO<FR64, f64>;
562  let Predicates = [HasAVX512] in {
563    defm _FR32X  : CMOVrr_PSEUDO<FR32X, f32>;
564    defm _FR64X  : CMOVrr_PSEUDO<FR64X, f64>;
565  }
566  let Predicates = [NoVLX] in {
567    defm _VR128  : CMOVrr_PSEUDO<VR128, v2i64>;
568    defm _VR256  : CMOVrr_PSEUDO<VR256, v4i64>;
569  }
570  let Predicates = [HasVLX] in {
571    defm _VR128X : CMOVrr_PSEUDO<VR128X, v2i64>;
572    defm _VR256X : CMOVrr_PSEUDO<VR256X, v4i64>;
573  }
574  defm _VR512  : CMOVrr_PSEUDO<VR512, v8i64>;
575  defm _VK1    : CMOVrr_PSEUDO<VK1,  v1i1>;
576  defm _VK2    : CMOVrr_PSEUDO<VK2,  v2i1>;
577  defm _VK4    : CMOVrr_PSEUDO<VK4,  v4i1>;
578  defm _VK8    : CMOVrr_PSEUDO<VK8,  v8i1>;
579  defm _VK16   : CMOVrr_PSEUDO<VK16, v16i1>;
580  defm _VK32   : CMOVrr_PSEUDO<VK32, v32i1>;
581  defm _VK64   : CMOVrr_PSEUDO<VK64, v64i1>;
582} // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS]
583
584def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
585          (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;
586
587let Predicates = [NoVLX] in {
588  def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
589            (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;
590  def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
591            (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;
592  def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
593            (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;
594  def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
595            (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;
596  def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
597            (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;
598
599  def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
600            (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>;
601  def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
602            (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>;
603  def : Pat<(v8i32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
604            (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>;
605  def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
606            (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>;
607  def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
608            (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>;
609}
610let Predicates = [HasVLX] in {
611  def : Pat<(v16i8 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),
612            (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>;
613  def : Pat<(v8i16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),
614            (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>;
615  def : Pat<(v4i32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),
616            (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>;
617  def : Pat<(v4f32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),
618            (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>;
619  def : Pat<(v2f64 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)),
620            (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>;
621
622  def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
623            (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>;
624  def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
625            (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>;
626  def : Pat<(v8i32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
627            (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>;
628  def : Pat<(v8f32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
629            (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>;
630  def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
631            (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>;
632}
633
634def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
635          (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>;
636def : Pat<(v32i16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
637          (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>;
638def : Pat<(v16i32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
639          (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>;
640def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
641          (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>;
642def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
643          (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>;
644
645//===----------------------------------------------------------------------===//
646// Normal-Instructions-With-Lock-Prefix Pseudo Instructions
647//===----------------------------------------------------------------------===//
648
649// FIXME: Use normal instructions and add lock prefix dynamically.
650
651// Memory barriers
652
653let isCodeGenOnly = 1, Defs = [EFLAGS] in
654def OR32mi8Locked  : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$zero),
655                         "or{l}\t{$zero, $dst|$dst, $zero}", []>,
656                         Requires<[Not64BitMode]>, OpSize32, LOCK,
657                         Sched<[WriteALURMW]>;
658
659let hasSideEffects = 1 in
660def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
661                     "#MEMBARRIER",
662                     [(X86MemBarrier)]>, Sched<[WriteLoad]>;
663
664// RegOpc corresponds to the mr version of the instruction
665// ImmOpc corresponds to the mi version of the instruction
666// ImmOpc8 corresponds to the mi8 version of the instruction
667// ImmMod corresponds to the instruction format of the mi and mi8 versions
668multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
669                           Format ImmMod, SDNode Op, string mnemonic> {
670let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
671    SchedRW = [WriteALURMW] in {
672
673def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
674                  RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
675                  MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
676                  !strconcat(mnemonic, "{b}\t",
677                             "{$src2, $dst|$dst, $src2}"),
678                  [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK;
679
680def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
681                   RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
682                   MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
683                   !strconcat(mnemonic, "{w}\t",
684                              "{$src2, $dst|$dst, $src2}"),
685                   [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>,
686                   OpSize16, LOCK;
687
688def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
689                   RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
690                   MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
691                   !strconcat(mnemonic, "{l}\t",
692                              "{$src2, $dst|$dst, $src2}"),
693                   [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>,
694                   OpSize32, LOCK;
695
696def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
697                    RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
698                    MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
699                    !strconcat(mnemonic, "{q}\t",
700                               "{$src2, $dst|$dst, $src2}"),
701                    [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK;
702
703// NOTE: These are order specific, we want the mi8 forms to be listed
704// first so that they are slightly preferred to the mi forms.
705def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
706                      ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
707                      ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
708                      !strconcat(mnemonic, "{w}\t",
709                                 "{$src2, $dst|$dst, $src2}"),
710                      [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>,
711                      OpSize16, LOCK;
712
713def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
714                      ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
715                      ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
716                      !strconcat(mnemonic, "{l}\t",
717                                 "{$src2, $dst|$dst, $src2}"),
718                      [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>,
719                      OpSize32, LOCK;
720
721def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
722                       ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
723                       ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
724                       !strconcat(mnemonic, "{q}\t",
725                                  "{$src2, $dst|$dst, $src2}"),
726                       [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>,
727                       LOCK;
728
729def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
730                    ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
731                    ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
732                    !strconcat(mnemonic, "{b}\t",
733                               "{$src2, $dst|$dst, $src2}"),
734                    [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK;
735
736def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
737                      ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
738                      ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
739                      !strconcat(mnemonic, "{w}\t",
740                                 "{$src2, $dst|$dst, $src2}"),
741                      [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>,
742                      OpSize16, LOCK;
743
744def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
745                      ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
746                      ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
747                      !strconcat(mnemonic, "{l}\t",
748                                 "{$src2, $dst|$dst, $src2}"),
749                      [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>,
750                      OpSize32, LOCK;
751
752def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
753                          ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
754                          ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
755                          !strconcat(mnemonic, "{q}\t",
756                                     "{$src2, $dst|$dst, $src2}"),
757                          [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>,
758                          LOCK;
759}
760
761}
762
763defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">;
764defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">;
765defm LOCK_OR  : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">;
766defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">;
767defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">;
768
769def X86lock_add_nocf : PatFrag<(ops node:$lhs, node:$rhs),
770                               (X86lock_add node:$lhs, node:$rhs), [{
771  return hasNoCarryFlagUses(SDValue(N, 0));
772}]>;
773
774def X86lock_sub_nocf : PatFrag<(ops node:$lhs, node:$rhs),
775                               (X86lock_sub node:$lhs, node:$rhs), [{
776  return hasNoCarryFlagUses(SDValue(N, 0));
777}]>;
778
779let Predicates = [UseIncDec] in {
780  let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
781      SchedRW = [WriteALURMW]  in {
782    def LOCK_INC8m  : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
783                        "inc{b}\t$dst",
784                        [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i8 1)))]>,
785                        LOCK;
786    def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
787                        "inc{w}\t$dst",
788                        [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i16 1)))]>,
789                        OpSize16, LOCK;
790    def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
791                        "inc{l}\t$dst",
792                        [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i32 1)))]>,
793                        OpSize32, LOCK;
794    def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
795                         "inc{q}\t$dst",
796                         [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i64 1)))]>,
797                         LOCK;
798
799    def LOCK_DEC8m  : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
800                        "dec{b}\t$dst",
801                        [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i8 1)))]>,
802                        LOCK;
803    def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
804                        "dec{w}\t$dst",
805                        [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i16 1)))]>,
806                        OpSize16, LOCK;
807    def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
808                        "dec{l}\t$dst",
809                        [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i32 1)))]>,
810                        OpSize32, LOCK;
811    def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
812                         "dec{q}\t$dst",
813                         [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i64 1)))]>,
814                         LOCK;
815  }
816
817  // Additional patterns for -1 constant.
818  def : Pat<(X86lock_add addr:$dst, (i8  -1)), (LOCK_DEC8m  addr:$dst)>;
819  def : Pat<(X86lock_add addr:$dst, (i16 -1)), (LOCK_DEC16m addr:$dst)>;
820  def : Pat<(X86lock_add addr:$dst, (i32 -1)), (LOCK_DEC32m addr:$dst)>;
821  def : Pat<(X86lock_add addr:$dst, (i64 -1)), (LOCK_DEC64m addr:$dst)>;
822  def : Pat<(X86lock_sub addr:$dst, (i8  -1)), (LOCK_INC8m  addr:$dst)>;
823  def : Pat<(X86lock_sub addr:$dst, (i16 -1)), (LOCK_INC16m addr:$dst)>;
824  def : Pat<(X86lock_sub addr:$dst, (i32 -1)), (LOCK_INC32m addr:$dst)>;
825  def : Pat<(X86lock_sub addr:$dst, (i64 -1)), (LOCK_INC64m addr:$dst)>;
826}
827
828// Atomic compare and swap.
829multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
830                          string mnemonic, SDPatternOperator frag> {
831let isCodeGenOnly = 1, SchedRW = [WriteCMPXCHGRMW] in {
832  let Defs = [AL, EFLAGS], Uses = [AL] in
833  def NAME#8  : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
834                  !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
835                  [(frag addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
836  let Defs = [AX, EFLAGS], Uses = [AX] in
837  def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
838                  !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
839                  [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK;
840  let Defs = [EAX, EFLAGS], Uses = [EAX] in
841  def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
842                  !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
843                  [(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK;
844  let Defs = [RAX, EFLAGS], Uses = [RAX] in
845  def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
846                   !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
847                   [(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
848}
849}
850
851let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
852    Predicates = [HasCmpxchg8b], SchedRW = [WriteCMPXCHGRMW],
853    isCodeGenOnly = 1, usesCustomInserter = 1 in {
854def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
855                   "cmpxchg8b\t$ptr",
856                   [(X86cas8 addr:$ptr)]>, TB, LOCK;
857}
858
859let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
860    Predicates = [HasCmpxchg16b,In64BitMode], SchedRW = [WriteCMPXCHGRMW],
861    isCodeGenOnly = 1, mayLoad = 1, mayStore = 1, hasSideEffects = 0 in {
862def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr),
863                     "cmpxchg16b\t$ptr",
864                     []>, TB, LOCK;
865}
866
867// This pseudo must be used when the frame uses RBX as
868// the base pointer. Indeed, in such situation RBX is a reserved
869// register and the register allocator will ignore any use/def of
870// it. In other words, the register will not fix the clobbering of
871// RBX that will happen when setting the arguments for the instrucion.
872//
873// Unlike the actual related instruction, we mark that this one
874// defines RBX (instead of using RBX).
875// The rationale is that we will define RBX during the expansion of
876// the pseudo. The argument feeding RBX is rbx_input.
877//
878// The additional argument, $rbx_save, is a temporary register used to
879// save the value of RBX across the actual instruction.
880//
881// To make sure the register assigned to $rbx_save does not interfere with
882// the definition of the actual instruction, we use a definition $dst which
883// is tied to $rbx_save. That way, the live-range of $rbx_save spans across
884// the instruction and we are sure we will have a valid register to restore
885// the value of RBX.
886let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX],
887    Predicates = [HasCmpxchg16b,In64BitMode], SchedRW = [WriteCMPXCHGRMW],
888    isCodeGenOnly = 1, isPseudo = 1,
889    mayLoad = 1, mayStore = 1, hasSideEffects = 0,
890    Constraints = "$rbx_save = $dst" in {
891def LCMPXCHG16B_SAVE_RBX :
892    I<0, Pseudo, (outs GR64:$dst),
893      (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), "", []>;
894}
895
896// Pseudo instruction that doesn't read/write RBX. Will be turned into either
897// LCMPXCHG16B_SAVE_RBX or LCMPXCHG16B via a custom inserter.
898let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RCX, RDX],
899    Predicates = [HasCmpxchg16b,In64BitMode], SchedRW = [WriteCMPXCHGRMW],
900    isCodeGenOnly = 1, isPseudo = 1,
901    mayLoad = 1, mayStore = 1, hasSideEffects = 0,
902    usesCustomInserter = 1 in {
903def LCMPXCHG16B_NO_RBX :
904    I<0, Pseudo, (outs), (ins i128mem:$ptr, GR64:$rbx_input), "",
905      [(X86cas16 addr:$ptr, GR64:$rbx_input)]>;
906}
907
908// This pseudo must be used when the frame uses RBX/EBX as
909// the base pointer.
910// cf comment for LCMPXCHG16B_SAVE_RBX.
911let Defs = [EBX], Uses = [ECX, EAX],
912    Predicates = [HasMWAITX], SchedRW = [WriteSystem],
913    isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst" in {
914def MWAITX_SAVE_RBX :
915    I<0, Pseudo, (outs GR64:$dst),
916      (ins GR32:$ebx_input, GR64:$rbx_save),
917      "mwaitx",
918      []>;
919}
920
921// Pseudo mwaitx instruction to use for custom insertion.
922let Predicates = [HasMWAITX], SchedRW = [WriteSystem],
923    isCodeGenOnly = 1, isPseudo = 1,
924    usesCustomInserter = 1 in {
925def MWAITX :
926    I<0, Pseudo, (outs), (ins GR32:$ecx, GR32:$eax, GR32:$ebx),
927      "mwaitx",
928      [(int_x86_mwaitx GR32:$ecx, GR32:$eax, GR32:$ebx)]>;
929}
930
931
932defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>;
933
934// Atomic exchange and add
935multiclass ATOMIC_RMW_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
936                            string frag> {
937  let Constraints = "$val = $dst", Defs = [EFLAGS], mayLoad = 1, mayStore = 1,
938      isCodeGenOnly = 1, SchedRW = [WriteALURMW] in {
939    def NAME#8  : I<opc8, MRMSrcMem, (outs GR8:$dst),
940                    (ins GR8:$val, i8mem:$ptr),
941                    !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
942                    [(set GR8:$dst,
943                          (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>;
944    def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
945                    (ins GR16:$val, i16mem:$ptr),
946                    !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
947                    [(set
948                       GR16:$dst,
949                       (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>,
950                    OpSize16;
951    def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
952                    (ins GR32:$val, i32mem:$ptr),
953                    !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
954                    [(set
955                       GR32:$dst,
956                       (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>,
957                    OpSize32;
958    def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
959                     (ins GR64:$val, i64mem:$ptr),
960                     !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
961                     [(set
962                        GR64:$dst,
963                        (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>;
964  }
965}
966
967defm LXADD : ATOMIC_RMW_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK;
968
969/* The following multiclass tries to make sure that in code like
970 *    x.store (immediate op x.load(acquire), release)
971 * and
972 *    x.store (register op x.load(acquire), release)
973 * an operation directly on memory is generated instead of wasting a register.
974 * It is not automatic as atomic_store/load are only lowered to MOV instructions
975 * extremely late to prevent them from being accidentally reordered in the backend
976 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
977 */
978multiclass RELEASE_BINOP_MI<string Name, SDNode op> {
979  def : Pat<(atomic_store_8 addr:$dst,
980             (op (atomic_load_8 addr:$dst), (i8 imm:$src))),
981            (!cast<Instruction>(Name#"8mi") addr:$dst, imm:$src)>;
982  def : Pat<(atomic_store_16 addr:$dst,
983             (op (atomic_load_16 addr:$dst), (i16 imm:$src))),
984            (!cast<Instruction>(Name#"16mi") addr:$dst, imm:$src)>;
985  def : Pat<(atomic_store_32 addr:$dst,
986             (op (atomic_load_32 addr:$dst), (i32 imm:$src))),
987            (!cast<Instruction>(Name#"32mi") addr:$dst, imm:$src)>;
988  def : Pat<(atomic_store_64 addr:$dst,
989             (op (atomic_load_64 addr:$dst), (i64immSExt32:$src))),
990            (!cast<Instruction>(Name#"64mi32") addr:$dst, (i64immSExt32:$src))>;
991
992  def : Pat<(atomic_store_8 addr:$dst,
993             (op (atomic_load_8 addr:$dst), (i8 GR8:$src))),
994            (!cast<Instruction>(Name#"8mr") addr:$dst, GR8:$src)>;
995  def : Pat<(atomic_store_16 addr:$dst,
996             (op (atomic_load_16 addr:$dst), (i16 GR16:$src))),
997            (!cast<Instruction>(Name#"16mr") addr:$dst, GR16:$src)>;
998  def : Pat<(atomic_store_32 addr:$dst,
999             (op (atomic_load_32 addr:$dst), (i32 GR32:$src))),
1000            (!cast<Instruction>(Name#"32mr") addr:$dst, GR32:$src)>;
1001  def : Pat<(atomic_store_64 addr:$dst,
1002             (op (atomic_load_64 addr:$dst), (i64 GR64:$src))),
1003            (!cast<Instruction>(Name#"64mr") addr:$dst, GR64:$src)>;
1004}
1005defm : RELEASE_BINOP_MI<"ADD", add>;
1006defm : RELEASE_BINOP_MI<"AND", and>;
1007defm : RELEASE_BINOP_MI<"OR",  or>;
1008defm : RELEASE_BINOP_MI<"XOR", xor>;
1009defm : RELEASE_BINOP_MI<"SUB", sub>;
1010
1011// Atomic load + floating point patterns.
1012// FIXME: This could also handle SIMD operations with *ps and *pd instructions.
1013multiclass ATOMIC_LOAD_FP_BINOP_MI<string Name, SDNode op> {
1014  def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))),
1015            (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>,
1016            Requires<[UseSSE1]>;
1017  def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))),
1018            (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>,
1019            Requires<[UseAVX]>;
1020  def : Pat<(op FR32X:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))),
1021            (!cast<Instruction>("V"#Name#"SSZrm") FR32X:$src1, addr:$src2)>,
1022            Requires<[HasAVX512]>;
1023
1024  def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))),
1025            (!cast<Instruction>(Name#"SDrm") FR64:$src1, addr:$src2)>,
1026            Requires<[UseSSE1]>;
1027  def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))),
1028            (!cast<Instruction>("V"#Name#"SDrm") FR64:$src1, addr:$src2)>,
1029            Requires<[UseAVX]>;
1030  def : Pat<(op FR64X:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))),
1031            (!cast<Instruction>("V"#Name#"SDZrm") FR64X:$src1, addr:$src2)>,
1032            Requires<[HasAVX512]>;
1033}
1034defm : ATOMIC_LOAD_FP_BINOP_MI<"ADD", fadd>;
1035// FIXME: Add fsub, fmul, fdiv, ...
1036
1037multiclass RELEASE_UNOP<string Name, dag dag8, dag dag16, dag dag32,
1038                        dag dag64> {
1039  def : Pat<(atomic_store_8 addr:$dst, dag8),
1040            (!cast<Instruction>(Name#8m) addr:$dst)>;
1041  def : Pat<(atomic_store_16 addr:$dst, dag16),
1042            (!cast<Instruction>(Name#16m) addr:$dst)>;
1043  def : Pat<(atomic_store_32 addr:$dst, dag32),
1044            (!cast<Instruction>(Name#32m) addr:$dst)>;
1045  def : Pat<(atomic_store_64 addr:$dst, dag64),
1046            (!cast<Instruction>(Name#64m) addr:$dst)>;
1047}
1048
1049let Predicates = [UseIncDec] in {
1050  defm : RELEASE_UNOP<"INC",
1051      (add (atomic_load_8  addr:$dst), (i8 1)),
1052      (add (atomic_load_16 addr:$dst), (i16 1)),
1053      (add (atomic_load_32 addr:$dst), (i32 1)),
1054      (add (atomic_load_64 addr:$dst), (i64 1))>;
1055  defm : RELEASE_UNOP<"DEC",
1056      (add (atomic_load_8  addr:$dst), (i8 -1)),
1057      (add (atomic_load_16 addr:$dst), (i16 -1)),
1058      (add (atomic_load_32 addr:$dst), (i32 -1)),
1059      (add (atomic_load_64 addr:$dst), (i64 -1))>;
1060}
1061
1062defm : RELEASE_UNOP<"NEG",
1063    (ineg (i8 (atomic_load_8  addr:$dst))),
1064    (ineg (i16 (atomic_load_16 addr:$dst))),
1065    (ineg (i32 (atomic_load_32 addr:$dst))),
1066    (ineg (i64 (atomic_load_64 addr:$dst)))>;
1067defm : RELEASE_UNOP<"NOT",
1068    (not (i8 (atomic_load_8  addr:$dst))),
1069    (not (i16 (atomic_load_16 addr:$dst))),
1070    (not (i32 (atomic_load_32 addr:$dst))),
1071    (not (i64 (atomic_load_64 addr:$dst)))>;
1072
1073def : Pat<(atomic_store_8 addr:$dst, (i8 imm:$src)),
1074          (MOV8mi addr:$dst, imm:$src)>;
1075def : Pat<(atomic_store_16 addr:$dst, (i16 imm:$src)),
1076          (MOV16mi addr:$dst, imm:$src)>;
1077def : Pat<(atomic_store_32 addr:$dst, (i32 imm:$src)),
1078          (MOV32mi addr:$dst, imm:$src)>;
1079def : Pat<(atomic_store_64 addr:$dst, (i64immSExt32:$src)),
1080          (MOV64mi32 addr:$dst, i64immSExt32:$src)>;
1081
1082def : Pat<(atomic_store_8 addr:$dst, GR8:$src),
1083          (MOV8mr addr:$dst, GR8:$src)>;
1084def : Pat<(atomic_store_16 addr:$dst, GR16:$src),
1085          (MOV16mr addr:$dst, GR16:$src)>;
1086def : Pat<(atomic_store_32 addr:$dst, GR32:$src),
1087          (MOV32mr addr:$dst, GR32:$src)>;
1088def : Pat<(atomic_store_64 addr:$dst, GR64:$src),
1089          (MOV64mr addr:$dst, GR64:$src)>;
1090
1091def : Pat<(i8  (atomic_load_8 addr:$src)),  (MOV8rm addr:$src)>;
1092def : Pat<(i16 (atomic_load_16 addr:$src)), (MOV16rm addr:$src)>;
1093def : Pat<(i32 (atomic_load_32 addr:$src)), (MOV32rm addr:$src)>;
1094def : Pat<(i64 (atomic_load_64 addr:$src)), (MOV64rm addr:$src)>;
1095
1096// Floating point loads/stores.
1097def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))),
1098          (MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>;
1099def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))),
1100          (VMOVSSmr addr:$dst, FR32:$src)>, Requires<[UseAVX]>;
1101def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))),
1102          (VMOVSSZmr addr:$dst, FR32:$src)>, Requires<[HasAVX512]>;
1103
1104def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))),
1105          (MOVSDmr addr:$dst, FR64:$src)>, Requires<[UseSSE2]>;
1106def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))),
1107          (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[UseAVX]>;
1108def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))),
1109          (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[HasAVX512]>;
1110
1111def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))),
1112          (MOVSSrm_alt addr:$src)>, Requires<[UseSSE1]>;
1113def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))),
1114          (VMOVSSrm_alt addr:$src)>, Requires<[UseAVX]>;
1115def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))),
1116          (VMOVSSZrm_alt addr:$src)>, Requires<[HasAVX512]>;
1117
1118def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))),
1119          (MOVSDrm_alt addr:$src)>, Requires<[UseSSE2]>;
1120def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))),
1121          (VMOVSDrm_alt addr:$src)>, Requires<[UseAVX]>;
1122def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))),
1123          (VMOVSDZrm_alt addr:$src)>, Requires<[HasAVX512]>;
1124
1125//===----------------------------------------------------------------------===//
1126// DAG Pattern Matching Rules
1127//===----------------------------------------------------------------------===//
1128
1129// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves
1130// binary size compared to a regular MOV, but it introduces an unnecessary
1131// load, so is not suitable for regular or optsize functions.
1132let Predicates = [OptForMinSize] in {
1133def : Pat<(simple_store (i16 0), addr:$dst), (AND16mi8 addr:$dst, 0)>;
1134def : Pat<(simple_store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>;
1135def : Pat<(simple_store (i64 0), addr:$dst), (AND64mi8 addr:$dst, 0)>;
1136def : Pat<(simple_store (i16 -1), addr:$dst), (OR16mi8 addr:$dst, -1)>;
1137def : Pat<(simple_store (i32 -1), addr:$dst), (OR32mi8 addr:$dst, -1)>;
1138def : Pat<(simple_store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>;
1139}
1140
1141// In kernel code model, we can get the address of a label
1142// into a register with 'movq'.  FIXME: This is a hack, the 'imm' predicate of
1143// the MOV64ri32 should accept these.
1144def : Pat<(i64 (X86Wrapper tconstpool  :$dst)),
1145          (MOV64ri32 tconstpool  :$dst)>, Requires<[KernelCode]>;
1146def : Pat<(i64 (X86Wrapper tjumptable  :$dst)),
1147          (MOV64ri32 tjumptable  :$dst)>, Requires<[KernelCode]>;
1148def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1149          (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1150def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1151          (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1152def : Pat<(i64 (X86Wrapper mcsym:$dst)),
1153          (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>;
1154def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1155          (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1156
1157// If we have small model and -static mode, it is safe to store global addresses
1158// directly as immediates.  FIXME: This is really a hack, the 'imm' predicate
1159// for MOV64mi32 should handle this sort of thing.
1160def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1161          (MOV64mi32 addr:$dst, tconstpool:$src)>,
1162          Requires<[NearData, IsNotPIC]>;
1163def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1164          (MOV64mi32 addr:$dst, tjumptable:$src)>,
1165          Requires<[NearData, IsNotPIC]>;
1166def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1167          (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1168          Requires<[NearData, IsNotPIC]>;
1169def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1170          (MOV64mi32 addr:$dst, texternalsym:$src)>,
1171          Requires<[NearData, IsNotPIC]>;
1172def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst),
1173          (MOV64mi32 addr:$dst, mcsym:$src)>,
1174          Requires<[NearData, IsNotPIC]>;
1175def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1176          (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1177          Requires<[NearData, IsNotPIC]>;
1178
1179def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>;
1180def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;
1181
1182// Calls
1183
1184// tls has some funny stuff here...
1185// This corresponds to movabs $foo@tpoff, %rax
1186def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
1187          (MOV64ri32 tglobaltlsaddr :$dst)>;
1188// This corresponds to add $foo@tpoff, %rax
1189def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
1190          (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1191
1192
1193// Direct PC relative function call for small code model. 32-bit displacement
1194// sign extended to 64-bit.
1195def : Pat<(X86call (i64 tglobaladdr:$dst)),
1196          (CALL64pcrel32 tglobaladdr:$dst)>;
1197def : Pat<(X86call (i64 texternalsym:$dst)),
1198          (CALL64pcrel32 texternalsym:$dst)>;
1199
1200def : Pat<(X86call_rvmarker (timm:$sel), (i64 texternalsym:$dst)),
1201          (CALL64pcrel32_RVMARKER timm:$sel, texternalsym:$dst)>;
1202def : Pat<(X86call_rvmarker (timm:$sel), (i64 tglobaladdr:$dst)),
1203          (CALL64pcrel32_RVMARKER timm:$sel, tglobaladdr:$dst)>;
1204
1205
1206// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1207// can never use callee-saved registers. That is the purpose of the GR64_TC
1208// register classes.
1209//
1210// The only volatile register that is never used by the calling convention is
1211// %r11. This happens when calling a vararg function with 6 arguments.
1212//
1213// Match an X86tcret that uses less than 7 volatile registers.
1214def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1215                             (X86tcret node:$ptr, node:$off), [{
1216  // X86tcret args: (*chain, ptr, imm, regs..., glue)
1217  unsigned NumRegs = 0;
1218  for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1219    if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1220      return false;
1221  return true;
1222}]>;
1223
1224def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off),
1225          (TCRETURNri ptr_rc_tailcall:$dst, timm:$off)>,
1226          Requires<[Not64BitMode, NotUseIndirectThunkCalls]>;
1227
1228// FIXME: This is disabled for 32-bit PIC mode because the global base
1229// register which is part of the address mode may be assigned a
1230// callee-saved register.
1231def : Pat<(X86tcret (load addr:$dst), timm:$off),
1232          (TCRETURNmi addr:$dst, timm:$off)>,
1233          Requires<[Not64BitMode, IsNotPIC, NotUseIndirectThunkCalls]>;
1234
1235def : Pat<(X86tcret (i32 tglobaladdr:$dst), timm:$off),
1236          (TCRETURNdi tglobaladdr:$dst, timm:$off)>,
1237          Requires<[NotLP64]>;
1238
1239def : Pat<(X86tcret (i32 texternalsym:$dst), timm:$off),
1240          (TCRETURNdi texternalsym:$dst, timm:$off)>,
1241          Requires<[NotLP64]>;
1242
1243def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off),
1244          (TCRETURNri64 ptr_rc_tailcall:$dst, timm:$off)>,
1245          Requires<[In64BitMode, NotUseIndirectThunkCalls]>;
1246
1247// Don't fold loads into X86tcret requiring more than 6 regs.
1248// There wouldn't be enough scratch registers for base+index.
1249def : Pat<(X86tcret_6regs (load addr:$dst), timm:$off),
1250          (TCRETURNmi64 addr:$dst, timm:$off)>,
1251          Requires<[In64BitMode, NotUseIndirectThunkCalls]>;
1252
1253def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off),
1254          (INDIRECT_THUNK_TCRETURN64 ptr_rc_tailcall:$dst, timm:$off)>,
1255          Requires<[In64BitMode, UseIndirectThunkCalls]>;
1256
1257def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off),
1258          (INDIRECT_THUNK_TCRETURN32 ptr_rc_tailcall:$dst, timm:$off)>,
1259          Requires<[Not64BitMode, UseIndirectThunkCalls]>;
1260
1261def : Pat<(X86tcret (i64 tglobaladdr:$dst), timm:$off),
1262          (TCRETURNdi64 tglobaladdr:$dst, timm:$off)>,
1263          Requires<[IsLP64]>;
1264
1265def : Pat<(X86tcret (i64 texternalsym:$dst), timm:$off),
1266          (TCRETURNdi64 texternalsym:$dst, timm:$off)>,
1267          Requires<[IsLP64]>;
1268
1269// Normal calls, with various flavors of addresses.
1270def : Pat<(X86call (i32 tglobaladdr:$dst)),
1271          (CALLpcrel32 tglobaladdr:$dst)>;
1272def : Pat<(X86call (i32 texternalsym:$dst)),
1273          (CALLpcrel32 texternalsym:$dst)>;
1274def : Pat<(X86call (i32 imm:$dst)),
1275          (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1276
1277// Comparisons.
1278
1279// TEST R,R is smaller than CMP R,0
1280def : Pat<(X86cmp GR8:$src1, 0),
1281          (TEST8rr GR8:$src1, GR8:$src1)>;
1282def : Pat<(X86cmp GR16:$src1, 0),
1283          (TEST16rr GR16:$src1, GR16:$src1)>;
1284def : Pat<(X86cmp GR32:$src1, 0),
1285          (TEST32rr GR32:$src1, GR32:$src1)>;
1286def : Pat<(X86cmp GR64:$src1, 0),
1287          (TEST64rr GR64:$src1, GR64:$src1)>;
1288
1289// zextload bool -> zextload byte
1290// i1 stored in one byte in zero-extended form.
1291// Upper bits cleanup should be executed before Store.
1292def : Pat<(zextloadi8i1  addr:$src), (MOV8rm addr:$src)>;
1293def : Pat<(zextloadi16i1 addr:$src),
1294          (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1295def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1296def : Pat<(zextloadi64i1 addr:$src),
1297          (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1298
1299// extload bool -> extload byte
1300// When extloading from 16-bit and smaller memory locations into 64-bit
1301// registers, use zero-extending loads so that the entire 64-bit register is
1302// defined, avoiding partial-register updates.
1303
1304def : Pat<(extloadi8i1 addr:$src),   (MOV8rm      addr:$src)>;
1305def : Pat<(extloadi16i1 addr:$src),
1306          (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1307def : Pat<(extloadi32i1 addr:$src),  (MOVZX32rm8  addr:$src)>;
1308def : Pat<(extloadi16i8 addr:$src),
1309          (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1310def : Pat<(extloadi32i8 addr:$src),  (MOVZX32rm8  addr:$src)>;
1311def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1312
1313// For other extloads, use subregs, since the high contents of the register are
1314// defined after an extload.
1315// NOTE: The extloadi64i32 pattern needs to be first as it will try to form
1316// 32-bit loads for 4 byte aligned i8/i16 loads.
1317def : Pat<(extloadi64i32 addr:$src),
1318          (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1319def : Pat<(extloadi64i1 addr:$src),
1320          (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1321def : Pat<(extloadi64i8 addr:$src),
1322          (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1323def : Pat<(extloadi64i16 addr:$src),
1324          (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1325
1326// anyext. Define these to do an explicit zero-extend to
1327// avoid partial-register updates.
1328def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1329                                     (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1330def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8  GR8 :$src)>;
1331
1332// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1333def : Pat<(i32 (anyext GR16:$src)),
1334          (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1335
1336def : Pat<(i64 (anyext GR8 :$src)),
1337          (SUBREG_TO_REG (i64 0), (MOVZX32rr8  GR8  :$src), sub_32bit)>;
1338def : Pat<(i64 (anyext GR16:$src)),
1339          (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1340def : Pat<(i64 (anyext GR32:$src)),
1341          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>;
1342
1343// If this is an anyext of the remainder of an 8-bit sdivrem, use a MOVSX
1344// instead of a MOVZX. The sdivrem lowering will emit emit a MOVSX to move
1345// %ah to the lower byte of a register. By using a MOVSX here we allow a
1346// post-isel peephole to merge the two MOVSX instructions into one.
1347def anyext_sdiv : PatFrag<(ops node:$lhs), (anyext node:$lhs),[{
1348  return (N->getOperand(0).getOpcode() == ISD::SDIVREM &&
1349          N->getOperand(0).getResNo() == 1);
1350}]>;
1351def : Pat<(i32 (anyext_sdiv GR8:$src)), (MOVSX32rr8 GR8:$src)>;
1352
1353// Any instruction that defines a 32-bit result leaves the high half of the
1354// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1355// be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying
1356// anything about the upper 32 bits, they're probably just qualifying a
1357// CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit
1358// operation will zero-extend up to 64 bits.
1359def def32 : PatLeaf<(i32 GR32:$src), [{
1360  return N->getOpcode() != ISD::TRUNCATE &&
1361         N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1362         N->getOpcode() != ISD::CopyFromReg &&
1363         N->getOpcode() != ISD::AssertSext &&
1364         N->getOpcode() != ISD::AssertZext &&
1365         N->getOpcode() != ISD::AssertAlign &&
1366         N->getOpcode() != ISD::FREEZE;
1367}]>;
1368
1369// In the case of a 32-bit def that is known to implicitly zero-extend,
1370// we can use a SUBREG_TO_REG.
1371def : Pat<(i64 (zext def32:$src)),
1372          (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1373def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)),
1374          (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1375
1376//===----------------------------------------------------------------------===//
1377// Pattern match OR as ADD
1378//===----------------------------------------------------------------------===//
1379
1380// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1381// 3-addressified into an LEA instruction to avoid copies.  However, we also
1382// want to finally emit these instructions as an or at the end of the code
1383// generator to make the generated code easier to read.  To do this, we select
1384// into "disjoint bits" pseudo ops.
1385
1386// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1387def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1388  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1389    return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1390
1391  KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
1392  KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
1393  return (~Known0.Zero & ~Known1.Zero) == 0;
1394}]>;
1395
1396
1397// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1398// Try this before the selecting to OR.
1399let SchedRW = [WriteALU] in {
1400
1401let isConvertibleToThreeAddress = 1, isPseudo = 1,
1402    Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1403let isCommutable = 1 in {
1404def ADD8rr_DB   : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1405                    "", // orb/addb REG, REG
1406                    [(set GR8:$dst, (or_is_add GR8:$src1, GR8:$src2))]>;
1407def ADD16rr_DB  : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1408                    "", // orw/addw REG, REG
1409                    [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1410def ADD32rr_DB  : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1411                    "", // orl/addl REG, REG
1412                    [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1413def ADD64rr_DB  : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1414                    "", // orq/addq REG, REG
1415                    [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1416} // isCommutable
1417
1418// NOTE: These are order specific, we want the ri8 forms to be listed
1419// first so that they are slightly preferred to the ri forms.
1420
1421def ADD8ri_DB :   I<0, Pseudo,
1422                    (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1423                    "", // orb/addb REG, imm8
1424                    [(set GR8:$dst, (or_is_add GR8:$src1, imm:$src2))]>;
1425def ADD16ri8_DB : I<0, Pseudo,
1426                    (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1427                    "", // orw/addw REG, imm8
1428                    [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1429def ADD16ri_DB  : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1430                    "", // orw/addw REG, imm
1431                    [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1432
1433def ADD32ri8_DB : I<0, Pseudo,
1434                    (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1435                    "", // orl/addl REG, imm8
1436                    [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1437def ADD32ri_DB  : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1438                    "", // orl/addl REG, imm
1439                    [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1440
1441
1442def ADD64ri8_DB : I<0, Pseudo,
1443                    (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1444                    "", // orq/addq REG, imm8
1445                    [(set GR64:$dst, (or_is_add GR64:$src1,
1446                                                i64immSExt8:$src2))]>;
1447def ADD64ri32_DB : I<0, Pseudo,
1448                     (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1449                     "", // orq/addq REG, imm
1450                     [(set GR64:$dst, (or_is_add GR64:$src1,
1451                                                 i64immSExt32:$src2))]>;
1452}
1453} // AddedComplexity, SchedRW
1454
1455//===----------------------------------------------------------------------===//
1456// Pattern match SUB as XOR
1457//===----------------------------------------------------------------------===//
1458
1459// An immediate in the LHS of a subtract can't be encoded in the instruction.
1460// If there is no possibility of a borrow we can use an XOR instead of a SUB
1461// to enable the immediate to be folded.
1462// TODO: Move this to a DAG combine?
1463
1464def sub_is_xor : PatFrag<(ops node:$lhs, node:$rhs), (sub node:$lhs, node:$rhs),[{
1465  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
1466    KnownBits Known = CurDAG->computeKnownBits(N->getOperand(1));
1467
1468    // If all possible ones in the RHS are set in the LHS then there can't be
1469    // a borrow and we can use xor.
1470    return (~Known.Zero).isSubsetOf(CN->getAPIntValue());
1471  }
1472
1473  return false;
1474}]>;
1475
1476let AddedComplexity = 5 in {
1477def : Pat<(sub_is_xor imm:$src2, GR8:$src1),
1478          (XOR8ri GR8:$src1, imm:$src2)>;
1479def : Pat<(sub_is_xor i16immSExt8:$src2, GR16:$src1),
1480          (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1481def : Pat<(sub_is_xor imm:$src2, GR16:$src1),
1482          (XOR16ri GR16:$src1, imm:$src2)>;
1483def : Pat<(sub_is_xor i32immSExt8:$src2, GR32:$src1),
1484          (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1485def : Pat<(sub_is_xor imm:$src2, GR32:$src1),
1486          (XOR32ri GR32:$src1, imm:$src2)>;
1487def : Pat<(sub_is_xor i64immSExt8:$src2, GR64:$src1),
1488          (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1489def : Pat<(sub_is_xor i64immSExt32:$src2, GR64:$src1),
1490          (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1491}
1492
1493//===----------------------------------------------------------------------===//
1494// Some peepholes
1495//===----------------------------------------------------------------------===//
1496
1497// Odd encoding trick: -128 fits into an 8-bit immediate field while
1498// +128 doesn't, so in this special case use a sub instead of an add.
1499def : Pat<(add GR16:$src1, 128),
1500          (SUB16ri8 GR16:$src1, -128)>;
1501def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1502          (SUB16mi8 addr:$dst, -128)>;
1503
1504def : Pat<(add GR32:$src1, 128),
1505          (SUB32ri8 GR32:$src1, -128)>;
1506def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1507          (SUB32mi8 addr:$dst, -128)>;
1508
1509def : Pat<(add GR64:$src1, 128),
1510          (SUB64ri8 GR64:$src1, -128)>;
1511def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1512          (SUB64mi8 addr:$dst, -128)>;
1513
1514def : Pat<(X86add_flag_nocf GR16:$src1, 128),
1515          (SUB16ri8 GR16:$src1, -128)>;
1516def : Pat<(X86add_flag_nocf GR32:$src1, 128),
1517          (SUB32ri8 GR32:$src1, -128)>;
1518def : Pat<(X86add_flag_nocf GR64:$src1, 128),
1519          (SUB64ri8 GR64:$src1, -128)>;
1520
1521// The same trick applies for 32-bit immediate fields in 64-bit
1522// instructions.
1523def : Pat<(add GR64:$src1, 0x0000000080000000),
1524          (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1525def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst),
1526          (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1527
1528def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000),
1529          (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1530
1531// To avoid needing to materialize an immediate in a register, use a 32-bit and
1532// with implicit zero-extension instead of a 64-bit and if the immediate has at
1533// least 32 bits of leading zeros. If in addition the last 32 bits can be
1534// represented with a sign extension of a 8 bit constant, use that.
1535// This can also reduce instruction size by eliminating the need for the REX
1536// prefix.
1537
1538// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32.
1539let AddedComplexity = 1 in {
1540def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1541          (SUBREG_TO_REG
1542            (i64 0),
1543            (AND32ri8
1544              (EXTRACT_SUBREG GR64:$src, sub_32bit),
1545              (i32 (GetLo32XForm imm:$imm))),
1546            sub_32bit)>;
1547
1548def : Pat<(and GR64:$src, i64immZExt32:$imm),
1549          (SUBREG_TO_REG
1550            (i64 0),
1551            (AND32ri
1552              (EXTRACT_SUBREG GR64:$src, sub_32bit),
1553              (i32 (GetLo32XForm imm:$imm))),
1554            sub_32bit)>;
1555} // AddedComplexity = 1
1556
1557
1558// AddedComplexity is needed due to the increased complexity on the
1559// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all
1560// the MOVZX patterns keeps thems together in DAGIsel tables.
1561let AddedComplexity = 1 in {
1562// r & (2^16-1) ==> movz
1563def : Pat<(and GR32:$src1, 0xffff),
1564          (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1565// r & (2^8-1) ==> movz
1566def : Pat<(and GR32:$src1, 0xff),
1567          (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>;
1568// r & (2^8-1) ==> movz
1569def : Pat<(and GR16:$src1, 0xff),
1570           (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)),
1571             sub_16bit)>;
1572
1573// r & (2^32-1) ==> movz
1574def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1575          (SUBREG_TO_REG (i64 0),
1576                         (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1577                         sub_32bit)>;
1578// r & (2^16-1) ==> movz
1579def : Pat<(and GR64:$src, 0xffff),
1580          (SUBREG_TO_REG (i64 0),
1581                      (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1582                      sub_32bit)>;
1583// r & (2^8-1) ==> movz
1584def : Pat<(and GR64:$src, 0xff),
1585          (SUBREG_TO_REG (i64 0),
1586                         (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1587                         sub_32bit)>;
1588} // AddedComplexity = 1
1589
1590
1591// Try to use BTS/BTR/BTC for single bit operations on the upper 32-bits.
1592
1593def BTRXForm : SDNodeXForm<imm, [{
1594  // Transformation function: Find the lowest 0.
1595  return getI64Imm((uint8_t)N->getAPIntValue().countTrailingOnes(), SDLoc(N));
1596}]>;
1597
1598def BTCBTSXForm : SDNodeXForm<imm, [{
1599  // Transformation function: Find the lowest 1.
1600  return getI64Imm((uint8_t)N->getAPIntValue().countTrailingZeros(), SDLoc(N));
1601}]>;
1602
1603def BTRMask64 : ImmLeaf<i64, [{
1604  return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm);
1605}]>;
1606
1607def BTCBTSMask64 : ImmLeaf<i64, [{
1608  return !isInt<32>(Imm) && isPowerOf2_64(Imm);
1609}]>;
1610
1611// For now only do this for optsize.
1612let AddedComplexity = 1, Predicates=[OptForSize] in {
1613  def : Pat<(and GR64:$src1, BTRMask64:$mask),
1614            (BTR64ri8 GR64:$src1, (BTRXForm imm:$mask))>;
1615  def : Pat<(or GR64:$src1, BTCBTSMask64:$mask),
1616            (BTS64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>;
1617  def : Pat<(xor GR64:$src1, BTCBTSMask64:$mask),
1618            (BTC64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>;
1619}
1620
1621
1622// sext_inreg patterns
1623def : Pat<(sext_inreg GR32:$src, i16),
1624          (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1625def : Pat<(sext_inreg GR32:$src, i8),
1626          (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>;
1627
1628def : Pat<(sext_inreg GR16:$src, i8),
1629           (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)),
1630             sub_16bit)>;
1631
1632def : Pat<(sext_inreg GR64:$src, i32),
1633          (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1634def : Pat<(sext_inreg GR64:$src, i16),
1635          (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1636def : Pat<(sext_inreg GR64:$src, i8),
1637          (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1638
1639// sext, sext_load, zext, zext_load
1640def: Pat<(i16 (sext GR8:$src)),
1641          (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1642def: Pat<(sextloadi16i8 addr:$src),
1643          (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1644def: Pat<(i16 (zext GR8:$src)),
1645          (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1646def: Pat<(zextloadi16i8 addr:$src),
1647          (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1648
1649// trunc patterns
1650def : Pat<(i16 (trunc GR32:$src)),
1651          (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1652def : Pat<(i8 (trunc GR32:$src)),
1653          (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1654                          sub_8bit)>,
1655      Requires<[Not64BitMode]>;
1656def : Pat<(i8 (trunc GR16:$src)),
1657          (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1658                          sub_8bit)>,
1659      Requires<[Not64BitMode]>;
1660def : Pat<(i32 (trunc GR64:$src)),
1661          (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1662def : Pat<(i16 (trunc GR64:$src)),
1663          (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1664def : Pat<(i8 (trunc GR64:$src)),
1665          (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1666def : Pat<(i8 (trunc GR32:$src)),
1667          (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1668      Requires<[In64BitMode]>;
1669def : Pat<(i8 (trunc GR16:$src)),
1670          (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1671      Requires<[In64BitMode]>;
1672
1673def immff00_ffff  : ImmLeaf<i32, [{
1674  return Imm >= 0xff00 && Imm <= 0xffff;
1675}]>;
1676
1677// h-register tricks
1678def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1679          (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>,
1680      Requires<[Not64BitMode]>;
1681def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))),
1682          (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>,
1683      Requires<[Not64BitMode]>;
1684def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1685          (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>,
1686      Requires<[Not64BitMode]>;
1687def : Pat<(srl GR16:$src, (i8 8)),
1688          (EXTRACT_SUBREG
1689            (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
1690            sub_16bit)>;
1691def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1692          (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>;
1693def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1694          (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>;
1695def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1696          (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>;
1697def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)),
1698          (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>;
1699
1700// h-register tricks.
1701// For now, be conservative on x86-64 and use an h-register extract only if the
1702// value is immediately zero-extended or stored, which are somewhat common
1703// cases. This uses a bunch of code to prevent a register requiring a REX prefix
1704// from being allocated in the same instruction as the h register, as there's
1705// currently no way to describe this requirement to the register allocator.
1706
1707// h-register extract and zero-extend.
1708def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1709          (SUBREG_TO_REG
1710            (i64 0),
1711            (MOVZX32rr8_NOREX
1712              (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)),
1713            sub_32bit)>;
1714def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1715          (SUBREG_TO_REG
1716            (i64 0),
1717            (MOVZX32rr8_NOREX
1718              (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
1719            sub_32bit)>;
1720def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1721          (SUBREG_TO_REG
1722            (i64 0),
1723            (MOVZX32rr8_NOREX
1724              (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
1725            sub_32bit)>;
1726
1727// h-register extract and store.
1728def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1729          (MOV8mr_NOREX
1730            addr:$dst,
1731            (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>;
1732def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1733          (MOV8mr_NOREX
1734            addr:$dst,
1735            (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>,
1736      Requires<[In64BitMode]>;
1737def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1738          (MOV8mr_NOREX
1739            addr:$dst,
1740            (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>,
1741      Requires<[In64BitMode]>;
1742
1743// Special pattern to catch the last step of __builtin_parity handling. Our
1744// goal is to use an xor of an h-register with the corresponding l-register.
1745// The above patterns would handle this on non 64-bit targets, but for 64-bit
1746// we need to be more careful. We're using a NOREX instruction here in case
1747// register allocation fails to keep the two registers together. So we need to
1748// make sure we can't accidentally mix R8-R15 with an h-register.
1749def : Pat<(X86xor_flag (i8 (trunc GR32:$src)),
1750                       (i8 (trunc (srl_su GR32:$src, (i8 8))))),
1751          (XOR8rr_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit),
1752                        (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>;
1753
1754// (shl x, 1) ==> (add x, x)
1755// Note that if x is undef (immediate or otherwise), we could theoretically
1756// end up with the two uses of x getting different values, producing a result
1757// where the least significant bit is not 0. However, the probability of this
1758// happening is considered low enough that this is officially not a
1759// "real problem".
1760def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr  GR8 :$src1, GR8 :$src1)>;
1761def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1762def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1763def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1764
1765def shiftMask8 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{
1766  return isUnneededShiftMask(N, 3);
1767}]>;
1768
1769def shiftMask16 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{
1770  return isUnneededShiftMask(N, 4);
1771}]>;
1772
1773def shiftMask32 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{
1774  return isUnneededShiftMask(N, 5);
1775}]>;
1776
1777def shiftMask64 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{
1778  return isUnneededShiftMask(N, 6);
1779}]>;
1780
1781
1782// Shift amount is implicitly masked.
1783multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1784  // (shift x (and y, 31)) ==> (shift x, y)
1785  def : Pat<(frag GR8:$src1, (shiftMask32 CL)),
1786            (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1787  def : Pat<(frag GR16:$src1, (shiftMask32 CL)),
1788            (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1789  def : Pat<(frag GR32:$src1, (shiftMask32 CL)),
1790            (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1791  def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask32 CL)), addr:$dst),
1792            (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1793  def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask32 CL)), addr:$dst),
1794            (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1795  def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst),
1796            (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1797
1798  // (shift x (and y, 63)) ==> (shift x, y)
1799  def : Pat<(frag GR64:$src1, (shiftMask64 CL)),
1800            (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1801  def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst),
1802            (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1803}
1804
1805defm : MaskedShiftAmountPats<shl, "SHL">;
1806defm : MaskedShiftAmountPats<srl, "SHR">;
1807defm : MaskedShiftAmountPats<sra, "SAR">;
1808
1809// ROL/ROR instructions allow a stronger mask optimization than shift for 8- and
1810// 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount
1811// because over-rotating produces the same result. This is noted in the Intel
1812// docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation
1813// amount could affect EFLAGS results, but that does not matter because we are
1814// not tracking flags for these nodes.
1815multiclass MaskedRotateAmountPats<SDNode frag, string name> {
1816  // (rot x (and y, BitWidth - 1)) ==> (rot x, y)
1817  def : Pat<(frag GR8:$src1, (shiftMask8 CL)),
1818  (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1819  def : Pat<(frag GR16:$src1, (shiftMask16 CL)),
1820  (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1821  def : Pat<(frag GR32:$src1, (shiftMask32 CL)),
1822  (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1823  def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask8 CL)), addr:$dst),
1824  (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1825  def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask16 CL)), addr:$dst),
1826  (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1827  def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst),
1828  (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1829
1830  // (rot x (and y, 63)) ==> (rot x, y)
1831  def : Pat<(frag GR64:$src1, (shiftMask64 CL)),
1832  (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1833  def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst),
1834  (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1835}
1836
1837
1838defm : MaskedRotateAmountPats<rotl, "ROL">;
1839defm : MaskedRotateAmountPats<rotr, "ROR">;
1840
1841// Double "funnel" shift amount is implicitly masked.
1842// (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) (NOTE: modulo32)
1843def : Pat<(X86fshl GR16:$src1, GR16:$src2, (shiftMask32 CL)),
1844          (SHLD16rrCL GR16:$src1, GR16:$src2)>;
1845def : Pat<(X86fshr GR16:$src2, GR16:$src1, (shiftMask32 CL)),
1846          (SHRD16rrCL GR16:$src1, GR16:$src2)>;
1847
1848// (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y)
1849def : Pat<(fshl GR32:$src1, GR32:$src2, (shiftMask32 CL)),
1850          (SHLD32rrCL GR32:$src1, GR32:$src2)>;
1851def : Pat<(fshr GR32:$src2, GR32:$src1, (shiftMask32 CL)),
1852          (SHRD32rrCL GR32:$src1, GR32:$src2)>;
1853
1854// (fshl/fshr x (and y, 63)) ==> (fshl/fshr x, y)
1855def : Pat<(fshl GR64:$src1, GR64:$src2, (shiftMask64 CL)),
1856          (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1857def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)),
1858          (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1859
1860let Predicates = [HasBMI2] in {
1861  let AddedComplexity = 1 in {
1862    def : Pat<(sra GR32:$src1, (shiftMask32 GR8:$src2)),
1863              (SARX32rr GR32:$src1,
1864                        (INSERT_SUBREG
1865                          (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1866    def : Pat<(sra GR64:$src1, (shiftMask64 GR8:$src2)),
1867              (SARX64rr GR64:$src1,
1868                        (INSERT_SUBREG
1869                          (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1870
1871    def : Pat<(srl GR32:$src1, (shiftMask32 GR8:$src2)),
1872              (SHRX32rr GR32:$src1,
1873                        (INSERT_SUBREG
1874                          (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1875    def : Pat<(srl GR64:$src1, (shiftMask64 GR8:$src2)),
1876              (SHRX64rr GR64:$src1,
1877                        (INSERT_SUBREG
1878                          (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1879
1880    def : Pat<(shl GR32:$src1, (shiftMask32 GR8:$src2)),
1881              (SHLX32rr GR32:$src1,
1882                        (INSERT_SUBREG
1883                          (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1884    def : Pat<(shl GR64:$src1, (shiftMask64 GR8:$src2)),
1885              (SHLX64rr GR64:$src1,
1886                        (INSERT_SUBREG
1887                          (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1888  }
1889
1890  def : Pat<(sra (loadi32 addr:$src1), (shiftMask32 GR8:$src2)),
1891            (SARX32rm addr:$src1,
1892                      (INSERT_SUBREG
1893                        (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1894  def : Pat<(sra (loadi64 addr:$src1), (shiftMask64 GR8:$src2)),
1895            (SARX64rm addr:$src1,
1896                      (INSERT_SUBREG
1897                        (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1898
1899  def : Pat<(srl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)),
1900            (SHRX32rm addr:$src1,
1901                      (INSERT_SUBREG
1902                        (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1903  def : Pat<(srl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)),
1904            (SHRX64rm addr:$src1,
1905                      (INSERT_SUBREG
1906                        (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1907
1908  def : Pat<(shl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)),
1909            (SHLX32rm addr:$src1,
1910                      (INSERT_SUBREG
1911                        (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1912  def : Pat<(shl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)),
1913            (SHLX64rm addr:$src1,
1914                      (INSERT_SUBREG
1915                        (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1916}
1917
1918// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location.
1919multiclass one_bit_patterns<RegisterClass RC, ValueType VT, Instruction BTR,
1920                            Instruction BTS, Instruction BTC,
1921                            PatFrag ShiftMask> {
1922  def : Pat<(and RC:$src1, (rotl -2, GR8:$src2)),
1923            (BTR RC:$src1,
1924                 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1925  def : Pat<(or RC:$src1, (shl 1, GR8:$src2)),
1926            (BTS RC:$src1,
1927                 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1928  def : Pat<(xor RC:$src1, (shl 1, GR8:$src2)),
1929            (BTC RC:$src1,
1930                 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1931
1932  // Similar to above, but removing unneeded masking of the shift amount.
1933  def : Pat<(and RC:$src1, (rotl -2, (ShiftMask GR8:$src2))),
1934            (BTR RC:$src1,
1935                 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1936  def : Pat<(or RC:$src1, (shl 1, (ShiftMask GR8:$src2))),
1937            (BTS RC:$src1,
1938                (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1939  def : Pat<(xor RC:$src1, (shl 1, (ShiftMask GR8:$src2))),
1940            (BTC RC:$src1,
1941                (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1942}
1943
1944defm : one_bit_patterns<GR16, i16, BTR16rr, BTS16rr, BTC16rr, shiftMask16>;
1945defm : one_bit_patterns<GR32, i32, BTR32rr, BTS32rr, BTC32rr, shiftMask32>;
1946defm : one_bit_patterns<GR64, i64, BTR64rr, BTS64rr, BTC64rr, shiftMask64>;
1947
1948//===----------------------------------------------------------------------===//
1949// EFLAGS-defining Patterns
1950//===----------------------------------------------------------------------===//
1951
1952// add reg, reg
1953def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr  GR8 :$src1, GR8 :$src2)>;
1954def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1955def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1956def : Pat<(add GR64:$src1, GR64:$src2), (ADD64rr GR64:$src1, GR64:$src2)>;
1957
1958// add reg, mem
1959def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1960          (ADD8rm GR8:$src1, addr:$src2)>;
1961def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1962          (ADD16rm GR16:$src1, addr:$src2)>;
1963def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1964          (ADD32rm GR32:$src1, addr:$src2)>;
1965def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1966          (ADD64rm GR64:$src1, addr:$src2)>;
1967
1968// add reg, imm
1969def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri  GR8:$src1 , imm:$src2)>;
1970def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1971def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1972def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1973          (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1974def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1975          (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1976def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1977          (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1978def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1979          (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1980
1981// sub reg, reg
1982def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr  GR8 :$src1, GR8 :$src2)>;
1983def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1984def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1985def : Pat<(sub GR64:$src1, GR64:$src2), (SUB64rr GR64:$src1, GR64:$src2)>;
1986
1987// sub reg, mem
1988def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1989          (SUB8rm GR8:$src1, addr:$src2)>;
1990def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1991          (SUB16rm GR16:$src1, addr:$src2)>;
1992def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1993          (SUB32rm GR32:$src1, addr:$src2)>;
1994def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1995          (SUB64rm GR64:$src1, addr:$src2)>;
1996
1997// sub reg, imm
1998def : Pat<(sub GR8:$src1, imm:$src2),
1999          (SUB8ri GR8:$src1, imm:$src2)>;
2000def : Pat<(sub GR16:$src1, imm:$src2),
2001          (SUB16ri GR16:$src1, imm:$src2)>;
2002def : Pat<(sub GR32:$src1, imm:$src2),
2003          (SUB32ri GR32:$src1, imm:$src2)>;
2004def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
2005          (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
2006def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
2007          (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2008def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
2009          (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2010def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
2011          (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2012
2013// sub 0, reg
2014def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r  GR8 :$src)>;
2015def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
2016def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
2017def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
2018
2019// mul reg, reg
2020def : Pat<(mul GR16:$src1, GR16:$src2),
2021          (IMUL16rr GR16:$src1, GR16:$src2)>;
2022def : Pat<(mul GR32:$src1, GR32:$src2),
2023          (IMUL32rr GR32:$src1, GR32:$src2)>;
2024def : Pat<(mul GR64:$src1, GR64:$src2),
2025          (IMUL64rr GR64:$src1, GR64:$src2)>;
2026
2027// mul reg, mem
2028def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
2029          (IMUL16rm GR16:$src1, addr:$src2)>;
2030def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
2031          (IMUL32rm GR32:$src1, addr:$src2)>;
2032def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
2033          (IMUL64rm GR64:$src1, addr:$src2)>;
2034
2035// mul reg, imm
2036def : Pat<(mul GR16:$src1, imm:$src2),
2037          (IMUL16rri GR16:$src1, imm:$src2)>;
2038def : Pat<(mul GR32:$src1, imm:$src2),
2039          (IMUL32rri GR32:$src1, imm:$src2)>;
2040def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
2041          (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
2042def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
2043          (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
2044def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
2045          (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2046def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
2047          (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2048
2049// reg = mul mem, imm
2050def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
2051          (IMUL16rmi addr:$src1, imm:$src2)>;
2052def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
2053          (IMUL32rmi addr:$src1, imm:$src2)>;
2054def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
2055          (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
2056def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
2057          (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
2058def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
2059          (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2060def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
2061          (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2062
2063// Increment/Decrement reg.
2064// Do not make INC/DEC if it is slow
2065let Predicates = [UseIncDec] in {
2066  def : Pat<(add GR8:$src, 1),   (INC8r GR8:$src)>;
2067  def : Pat<(add GR16:$src, 1),  (INC16r GR16:$src)>;
2068  def : Pat<(add GR32:$src, 1),  (INC32r GR32:$src)>;
2069  def : Pat<(add GR64:$src, 1),  (INC64r GR64:$src)>;
2070  def : Pat<(add GR8:$src, -1),  (DEC8r GR8:$src)>;
2071  def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
2072  def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
2073  def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
2074
2075  def : Pat<(X86add_flag_nocf GR8:$src, -1),  (DEC8r GR8:$src)>;
2076  def : Pat<(X86add_flag_nocf GR16:$src, -1), (DEC16r GR16:$src)>;
2077  def : Pat<(X86add_flag_nocf GR32:$src, -1), (DEC32r GR32:$src)>;
2078  def : Pat<(X86add_flag_nocf GR64:$src, -1), (DEC64r GR64:$src)>;
2079  def : Pat<(X86sub_flag_nocf GR8:$src, -1),  (INC8r GR8:$src)>;
2080  def : Pat<(X86sub_flag_nocf GR16:$src, -1), (INC16r GR16:$src)>;
2081  def : Pat<(X86sub_flag_nocf GR32:$src, -1), (INC32r GR32:$src)>;
2082  def : Pat<(X86sub_flag_nocf GR64:$src, -1), (INC64r GR64:$src)>;
2083}
2084
2085// or reg/reg.
2086def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr  GR8 :$src1, GR8 :$src2)>;
2087def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
2088def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
2089def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
2090
2091// or reg/mem
2092def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
2093          (OR8rm GR8:$src1, addr:$src2)>;
2094def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
2095          (OR16rm GR16:$src1, addr:$src2)>;
2096def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
2097          (OR32rm GR32:$src1, addr:$src2)>;
2098def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
2099          (OR64rm GR64:$src1, addr:$src2)>;
2100
2101// or reg/imm
2102def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri  GR8 :$src1, imm:$src2)>;
2103def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
2104def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
2105def : Pat<(or GR16:$src1, i16immSExt8:$src2),
2106          (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
2107def : Pat<(or GR32:$src1, i32immSExt8:$src2),
2108          (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
2109def : Pat<(or GR64:$src1, i64immSExt8:$src2),
2110          (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2111def : Pat<(or GR64:$src1, i64immSExt32:$src2),
2112          (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2113
2114// xor reg/reg
2115def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr  GR8 :$src1, GR8 :$src2)>;
2116def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
2117def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
2118def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
2119
2120// xor reg/mem
2121def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
2122          (XOR8rm GR8:$src1, addr:$src2)>;
2123def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
2124          (XOR16rm GR16:$src1, addr:$src2)>;
2125def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
2126          (XOR32rm GR32:$src1, addr:$src2)>;
2127def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
2128          (XOR64rm GR64:$src1, addr:$src2)>;
2129
2130// xor reg/imm
2131def : Pat<(xor GR8:$src1, imm:$src2),
2132          (XOR8ri GR8:$src1, imm:$src2)>;
2133def : Pat<(xor GR16:$src1, imm:$src2),
2134          (XOR16ri GR16:$src1, imm:$src2)>;
2135def : Pat<(xor GR32:$src1, imm:$src2),
2136          (XOR32ri GR32:$src1, imm:$src2)>;
2137def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
2138          (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
2139def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
2140          (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
2141def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
2142          (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2143def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
2144          (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2145
2146// and reg/reg
2147def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr  GR8 :$src1, GR8 :$src2)>;
2148def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
2149def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
2150def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
2151
2152// and reg/mem
2153def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
2154          (AND8rm GR8:$src1, addr:$src2)>;
2155def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
2156          (AND16rm GR16:$src1, addr:$src2)>;
2157def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
2158          (AND32rm GR32:$src1, addr:$src2)>;
2159def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
2160          (AND64rm GR64:$src1, addr:$src2)>;
2161
2162// and reg/imm
2163def : Pat<(and GR8:$src1, imm:$src2),
2164          (AND8ri GR8:$src1, imm:$src2)>;
2165def : Pat<(and GR16:$src1, imm:$src2),
2166          (AND16ri GR16:$src1, imm:$src2)>;
2167def : Pat<(and GR32:$src1, imm:$src2),
2168          (AND32ri GR32:$src1, imm:$src2)>;
2169def : Pat<(and GR16:$src1, i16immSExt8:$src2),
2170          (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
2171def : Pat<(and GR32:$src1, i32immSExt8:$src2),
2172          (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
2173def : Pat<(and GR64:$src1, i64immSExt8:$src2),
2174          (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2175def : Pat<(and GR64:$src1, i64immSExt32:$src2),
2176          (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2177
2178// Bit scan instruction patterns to match explicit zero-undef behavior.
2179def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
2180def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
2181def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
2182def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
2183def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
2184def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
2185
2186// When HasMOVBE is enabled it is possible to get a non-legalized
2187// register-register 16 bit bswap. This maps it to a ROL instruction.
2188let Predicates = [HasMOVBE] in {
2189 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;
2190}
2191