1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the various pseudo instructions used by the compiler, 10// as well as Pat patterns used during instruction selection. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Pattern Matching Support 16 17def GetLo32XForm : SDNodeXForm<imm, [{ 18 // Transformation function: get the low 32 bits. 19 return getI32Imm((uint32_t)N->getZExtValue(), SDLoc(N)); 20}]>; 21 22 23//===----------------------------------------------------------------------===// 24// Random Pseudo Instructions. 25 26// PIC base construction. This expands to code that looks like this: 27// call $next_inst 28// popl %destreg" 29let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP], 30 SchedRW = [WriteJump] in 31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 32 "", []>; 33 34// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 35// a stack adjustment and the codegen must know that they may modify the stack 36// pointer before prolog-epilog rewriting occurs. 37// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 38// sub / add which can clobber EFLAGS. 39let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in { 40def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), 41 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 42 "#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>; 43def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 44 "#ADJCALLSTACKUP", 45 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 46 Requires<[NotLP64]>; 47} 48def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 49 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>; 50 51 52// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 53// a stack adjustment and the codegen must know that they may modify the stack 54// pointer before prolog-epilog rewriting occurs. 55// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 56// sub / add which can clobber EFLAGS. 57let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in { 58def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), 59 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 60 "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>; 61def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 62 "#ADJCALLSTACKUP", 63 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 64 Requires<[IsLP64]>; 65} 66def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 67 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>; 68 69let SchedRW = [WriteSystem] in { 70 71// x86-64 va_start lowering magic. 72let hasSideEffects = 1, mayStore = 1, Defs = [EFLAGS] in { 73def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 74 (outs), 75 (ins GR8:$al, i8mem:$regsavefi, variable_ops), 76 "#VASTART_SAVE_XMM_REGS $al, $regsavefi", 77 [(X86vastart_save_xmm_regs GR8:$al, addr:$regsavefi), 78 (implicit EFLAGS)]>; 79} 80 81let usesCustomInserter = 1, Defs = [EFLAGS] in { 82// The VAARG_64 and VAARG_X32 pseudo-instructions take the address of the 83// va_list, and place the address of the next argument into a register. 84let Defs = [EFLAGS] in { 85def VAARG_64 : I<0, Pseudo, 86 (outs GR64:$dst), 87 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 88 "#VAARG_64 $dst, $ap, $size, $mode, $align", 89 [(set GR64:$dst, 90 (X86vaarg64 addr:$ap, timm:$size, timm:$mode, timm:$align)), 91 (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>; 92def VAARG_X32 : I<0, Pseudo, 93 (outs GR32:$dst), 94 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 95 "#VAARG_X32 $dst, $ap, $size, $mode, $align", 96 [(set GR32:$dst, 97 (X86vaargx32 addr:$ap, timm:$size, timm:$mode, timm:$align)), 98 (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>; 99} 100 101// When using segmented stacks these are lowered into instructions which first 102// check if the current stacklet has enough free memory. If it does, memory is 103// allocated by bumping the stack pointer. Otherwise memory is allocated from 104// the heap. 105 106let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 107def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 108 "# variable sized alloca for segmented stacks", 109 [(set GR32:$dst, 110 (X86SegAlloca GR32:$size))]>, 111 Requires<[NotLP64]>; 112 113let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 114def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 115 "# variable sized alloca for segmented stacks", 116 [(set GR64:$dst, 117 (X86SegAlloca GR64:$size))]>, 118 Requires<[In64BitMode]>; 119 120// To protect against stack clash, dynamic allocation should perform a memory 121// probe at each page. 122 123let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 124def PROBED_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 125 "# variable sized alloca with probing", 126 [(set GR32:$dst, 127 (X86ProbedAlloca GR32:$size))]>, 128 Requires<[NotLP64]>; 129 130let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 131def PROBED_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 132 "# variable sized alloca with probing", 133 [(set GR64:$dst, 134 (X86ProbedAlloca GR64:$size))]>, 135 Requires<[In64BitMode]>; 136} 137 138let hasNoSchedulingInfo = 1 in 139def STACKALLOC_W_PROBING : I<0, Pseudo, (outs), (ins i64imm:$stacksize), 140 "# fixed size alloca with probing", 141 []>; 142 143// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 144// targets. These calls are needed to probe the stack when allocating more than 145// 4k bytes in one go. Touching the stack at 4K increments is necessary to 146// ensure that the guard pages used by the OS virtual memory manager are 147// allocated in correct sequence. 148// The main point of having separate instruction are extra unmodelled effects 149// (compared to ordinary calls) like stack pointer change. 150 151let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 152def DYN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size), 153 "# dynamic stack allocation", 154 [(X86DynAlloca GR32:$size)]>, 155 Requires<[NotLP64]>; 156 157let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 158def DYN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size), 159 "# dynamic stack allocation", 160 [(X86DynAlloca GR64:$size)]>, 161 Requires<[In64BitMode]>; 162} // SchedRW 163 164// These instructions XOR the frame pointer into a GPR. They are used in some 165// stack protection schemes. These are post-RA pseudos because we only know the 166// frame register after register allocation. 167let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in { 168 def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src), 169 "xorl\t$$FP, $src", []>, 170 Requires<[NotLP64]>, Sched<[WriteALU]>; 171 def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src), 172 "xorq\t$$FP $src", []>, 173 Requires<[In64BitMode]>, Sched<[WriteALU]>; 174} 175 176//===----------------------------------------------------------------------===// 177// EH Pseudo Instructions 178// 179let SchedRW = [WriteSystem] in { 180let isTerminator = 1, isReturn = 1, isBarrier = 1, 181 hasCtrlDep = 1, isCodeGenOnly = 1 in { 182def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 183 "ret\t#eh_return, addr: $addr", 184 [(X86ehret GR32:$addr)]>, Sched<[WriteJumpLd]>; 185 186} 187 188let isTerminator = 1, isReturn = 1, isBarrier = 1, 189 hasCtrlDep = 1, isCodeGenOnly = 1 in { 190def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 191 "ret\t#eh_return, addr: $addr", 192 [(X86ehret GR64:$addr)]>, Sched<[WriteJumpLd]>; 193 194} 195 196let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 197 isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1 in { 198 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>; 199 200 // CATCHRET needs a custom inserter for SEH. 201 let usesCustomInserter = 1 in 202 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), 203 "# CATCHRET", 204 [(catchret bb:$dst, bb:$from)]>; 205} 206 207let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 208 usesCustomInserter = 1 in { 209 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 210 "#EH_SJLJ_SETJMP32", 211 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 212 Requires<[Not64BitMode]>; 213 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 214 "#EH_SJLJ_SETJMP64", 215 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 216 Requires<[In64BitMode]>; 217 let isTerminator = 1 in { 218 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 219 "#EH_SJLJ_LONGJMP32", 220 [(X86eh_sjlj_longjmp addr:$buf)]>, 221 Requires<[Not64BitMode]>; 222 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 223 "#EH_SJLJ_LONGJMP64", 224 [(X86eh_sjlj_longjmp addr:$buf)]>, 225 Requires<[In64BitMode]>; 226 } 227} 228 229let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 230 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 231 "#EH_SjLj_Setup\t$dst", []>; 232} 233} // SchedRW 234 235//===----------------------------------------------------------------------===// 236// Pseudo instructions used by unwind info. 237// 238let isPseudo = 1, SchedRW = [WriteSystem] in { 239 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), 240 "#SEH_PushReg $reg", []>; 241 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 242 "#SEH_SaveReg $reg, $dst", []>; 243 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 244 "#SEH_SaveXMM $reg, $dst", []>; 245 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), 246 "#SEH_StackAlloc $size", []>; 247 def SEH_StackAlign : I<0, Pseudo, (outs), (ins i32imm:$align), 248 "#SEH_StackAlign $align", []>; 249 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), 250 "#SEH_SetFrame $reg, $offset", []>; 251 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), 252 "#SEH_PushFrame $mode", []>; 253 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), 254 "#SEH_EndPrologue", []>; 255 def SEH_Epilogue : I<0, Pseudo, (outs), (ins), 256 "#SEH_Epilogue", []>; 257} 258 259//===----------------------------------------------------------------------===// 260// Pseudo instructions used by KCFI. 261//===----------------------------------------------------------------------===// 262let 263 Defs = [R10, R11, EFLAGS] in { 264def KCFI_CHECK : PseudoI< 265 (outs), (ins GR64:$ptr, i32imm:$type), []>, Sched<[]>; 266} 267 268//===----------------------------------------------------------------------===// 269// Pseudo instructions used by address sanitizer. 270//===----------------------------------------------------------------------===// 271let 272 Defs = [R10, R11, EFLAGS] in { 273def ASAN_CHECK_MEMACCESS : PseudoI< 274 (outs), (ins GR64PLTSafe:$addr, i32imm:$accessinfo), 275 [(int_asan_check_memaccess GR64PLTSafe:$addr, (i32 timm:$accessinfo))]>, 276 Sched<[]>; 277} 278 279//===----------------------------------------------------------------------===// 280// Pseudo instructions used by segmented stacks. 281// 282 283// This is lowered into a RET instruction by MCInstLower. We need 284// this so that we don't have to have a MachineBasicBlock which ends 285// with a RET and also has successors. 286let isPseudo = 1, SchedRW = [WriteJumpLd] in { 287def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>; 288 289// This instruction is lowered to a RET followed by a MOV. The two 290// instructions are not generated on a higher level since then the 291// verifier sees a MachineBasicBlock ending with a non-terminator. 292def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>; 293} 294 295//===----------------------------------------------------------------------===// 296// Alias Instructions 297//===----------------------------------------------------------------------===// 298 299// Alias instruction mapping movr0 to xor. 300// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 301let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 302 isPseudo = 1, isMoveImm = 1, AddedComplexity = 10 in 303def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 304 [(set GR32:$dst, 0)]>, Sched<[WriteZero]>; 305 306// Other widths can also make use of the 32-bit xor, which may have a smaller 307// encoding and avoid partial register updates. 308let AddedComplexity = 10 in { 309def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 310def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 311def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>; 312} 313 314let Predicates = [OptForSize, Not64BitMode], 315 AddedComplexity = 10 in { 316 let SchedRW = [WriteALU] in { 317 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, 318 // which only require 3 bytes compared to MOV32ri which requires 5. 319 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { 320 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 321 [(set GR32:$dst, 1)]>; 322 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 323 [(set GR32:$dst, -1)]>; 324 } 325 } // SchedRW 326 327 // MOV16ri is 4 bytes, so the instructions above are smaller. 328 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; 329 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; 330} 331 332let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5, 333 SchedRW = [WriteALU] in { 334// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1. 335def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "", 336 [(set GR32:$dst, i32immSExt8:$src)]>, 337 Requires<[OptForMinSize, NotWin64WithoutFP]>; 338def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", 339 [(set GR64:$dst, i64immSExt8:$src)]>, 340 Requires<[OptForMinSize, NotWin64WithoutFP]>; 341} 342 343// Materialize i64 constant where top 32-bits are zero. This could theoretically 344// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 345// that would make it more difficult to rematerialize. 346let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 347 isPseudo = 1, SchedRW = [WriteMove] in 348def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "", 349 [(set GR64:$dst, i64immZExt32:$src)]>; 350 351// This 64-bit pseudo-move can also be used for labels in the x86-64 small code 352// model. 353def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [X86Wrapper]>; 354def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>; 355 356// Use sbb to materialize carry bit. 357let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteADC], 358 hasSideEffects = 0 in { 359// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 360// However, Pat<> can't replicate the destination reg into the inputs of the 361// result. 362def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", []>; 363def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", []>; 364} // isCodeGenOnly 365 366//===----------------------------------------------------------------------===// 367// String Pseudo Instructions 368// 369let SchedRW = [WriteMicrocoded] in { 370let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 371def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), 372 "{rep;movsb (%esi), %es:(%edi)|rep movsb es:[edi], [esi]}", 373 [(X86rep_movs i8)]>, REP, AdSize32, 374 Requires<[NotLP64]>; 375def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), 376 "{rep;movsw (%esi), %es:(%edi)|rep movsw es:[edi], [esi]}", 377 [(X86rep_movs i16)]>, REP, AdSize32, OpSize16, 378 Requires<[NotLP64]>; 379def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), 380 "{rep;movsl (%esi), %es:(%edi)|rep movsd es:[edi], [esi]}", 381 [(X86rep_movs i32)]>, REP, AdSize32, OpSize32, 382 Requires<[NotLP64]>; 383def REP_MOVSQ_32 : RI<0xA5, RawFrm, (outs), (ins), 384 "{rep;movsq (%esi), %es:(%edi)|rep movsq es:[edi], [esi]}", 385 [(X86rep_movs i64)]>, REP, AdSize32, 386 Requires<[NotLP64, In64BitMode]>; 387} 388 389let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 390def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), 391 "{rep;movsb (%rsi), %es:(%rdi)|rep movsb es:[rdi], [rsi]}", 392 [(X86rep_movs i8)]>, REP, AdSize64, 393 Requires<[IsLP64]>; 394def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), 395 "{rep;movsw (%rsi), %es:(%rdi)|rep movsw es:[rdi], [rsi]}", 396 [(X86rep_movs i16)]>, REP, AdSize64, OpSize16, 397 Requires<[IsLP64]>; 398def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), 399 "{rep;movsl (%rsi), %es:(%rdi)|rep movsdi es:[rdi], [rsi]}", 400 [(X86rep_movs i32)]>, REP, AdSize64, OpSize32, 401 Requires<[IsLP64]>; 402def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), 403 "{rep;movsq (%rsi), %es:(%rdi)|rep movsq es:[rdi], [rsi]}", 404 [(X86rep_movs i64)]>, REP, AdSize64, 405 Requires<[IsLP64]>; 406} 407 408// FIXME: Should use "(X86rep_stos AL)" as the pattern. 409let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 410 let Uses = [AL,ECX,EDI] in 411 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), 412 "{rep;stosb %al, %es:(%edi)|rep stosb es:[edi], al}", 413 [(X86rep_stos i8)]>, REP, AdSize32, 414 Requires<[NotLP64]>; 415 let Uses = [AX,ECX,EDI] in 416 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), 417 "{rep;stosw %ax, %es:(%edi)|rep stosw es:[edi], ax}", 418 [(X86rep_stos i16)]>, REP, AdSize32, OpSize16, 419 Requires<[NotLP64]>; 420 let Uses = [EAX,ECX,EDI] in 421 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), 422 "{rep;stosl %eax, %es:(%edi)|rep stosd es:[edi], eax}", 423 [(X86rep_stos i32)]>, REP, AdSize32, OpSize32, 424 Requires<[NotLP64]>; 425 let Uses = [RAX,RCX,RDI] in 426 def REP_STOSQ_32 : RI<0xAB, RawFrm, (outs), (ins), 427 "{rep;stosq %rax, %es:(%edi)|rep stosq es:[edi], rax}", 428 [(X86rep_stos i64)]>, REP, AdSize32, 429 Requires<[NotLP64, In64BitMode]>; 430} 431 432let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 433 let Uses = [AL,RCX,RDI] in 434 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), 435 "{rep;stosb %al, %es:(%rdi)|rep stosb es:[rdi], al}", 436 [(X86rep_stos i8)]>, REP, AdSize64, 437 Requires<[IsLP64]>; 438 let Uses = [AX,RCX,RDI] in 439 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), 440 "{rep;stosw %ax, %es:(%rdi)|rep stosw es:[rdi], ax}", 441 [(X86rep_stos i16)]>, REP, AdSize64, OpSize16, 442 Requires<[IsLP64]>; 443 let Uses = [RAX,RCX,RDI] in 444 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), 445 "{rep;stosl %eax, %es:(%rdi)|rep stosd es:[rdi], eax}", 446 [(X86rep_stos i32)]>, REP, AdSize64, OpSize32, 447 Requires<[IsLP64]>; 448 449 let Uses = [RAX,RCX,RDI] in 450 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), 451 "{rep;stosq %rax, %es:(%rdi)|rep stosq es:[rdi], rax}", 452 [(X86rep_stos i64)]>, REP, AdSize64, 453 Requires<[IsLP64]>; 454} 455} // SchedRW 456 457//===----------------------------------------------------------------------===// 458// Thread Local Storage Instructions 459// 460let SchedRW = [WriteSystem] in { 461 462// ELF TLS Support 463// All calls clobber the non-callee saved registers. ESP is marked as 464// a use to prevent stack-pointer assignments that appear immediately 465// before calls from potentially appearing dead. 466let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 467 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 468 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 469 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 470 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 471 usesCustomInserter = 1, Uses = [ESP, SSP] in { 472def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 473 "# TLS_addr32", 474 [(X86tlsaddr tls32addr:$sym)]>, 475 Requires<[Not64BitMode]>; 476def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 477 "# TLS_base_addr32", 478 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 479 Requires<[Not64BitMode]>; 480} 481 482// All calls clobber the non-callee saved registers. RSP is marked as 483// a use to prevent stack-pointer assignments that appear immediately 484// before calls from potentially appearing dead. 485let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 486 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 487 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 488 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 489 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 490 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 491 usesCustomInserter = 1, Uses = [RSP, SSP] in { 492def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 493 "# TLS_addr64", 494 [(X86tlsaddr tls64addr:$sym)]>, 495 Requires<[In64BitMode, IsLP64]>; 496def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 497 "# TLS_base_addr64", 498 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 499 Requires<[In64BitMode, IsLP64]>; 500def TLS_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 501 "# TLS_addrX32", 502 [(X86tlsaddr tls32addr:$sym)]>, 503 Requires<[In64BitMode, NotLP64]>; 504def TLS_base_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 505 "# TLS_base_addrX32", 506 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 507 Requires<[In64BitMode, NotLP64]>; 508} 509 510// Darwin TLS Support 511// For i386, the address of the thunk is passed on the stack, on return the 512// address of the variable is in %eax. %ecx is trashed during the function 513// call. All other registers are preserved. 514let Defs = [EAX, ECX, EFLAGS, DF], 515 Uses = [ESP, SSP], 516 usesCustomInserter = 1 in 517def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 518 "# TLSCall_32", 519 [(X86TLSCall addr:$sym)]>, 520 Requires<[Not64BitMode]>; 521 522// For x86_64, the address of the thunk is passed in %rdi, but the 523// pseudo directly use the symbol, so do not add an implicit use of 524// %rdi. The lowering will do the right thing with RDI. 525// On return the address of the variable is in %rax. All other 526// registers are preserved. 527let Defs = [RAX, EFLAGS, DF], 528 Uses = [RSP, SSP], 529 usesCustomInserter = 1 in 530def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 531 "# TLSCall_64", 532 [(X86TLSCall addr:$sym)]>, 533 Requires<[In64BitMode]>; 534} // SchedRW 535 536//===----------------------------------------------------------------------===// 537// Conditional Move Pseudo Instructions 538 539// CMOV* - Used to implement the SELECT DAG operation. Expanded after 540// instruction selection into a branch sequence. 541multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> { 542 def CMOV#NAME : I<0, Pseudo, 543 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), 544 "#CMOV_"#NAME#" PSEUDO!", 545 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, timm:$cond, 546 EFLAGS)))]>; 547} 548 549let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in { 550 // X86 doesn't have 8-bit conditional moves. Use a customInserter to 551 // emit control flow. An alternative to this is to mark i8 SELECT as Promote, 552 // however that requires promoting the operands, and can induce additional 553 // i8 register pressure. 554 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>; 555 556 let Predicates = [NoCMOV] in { 557 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>; 558 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>; 559 } // Predicates = [NoCMOV] 560 561 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 562 // SSE1/SSE2. 563 let Predicates = [FPStackf32] in 564 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>; 565 566 let Predicates = [FPStackf64] in 567 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>; 568 569 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>; 570 571 let Predicates = [HasMMX] in 572 defm _VR64 : CMOVrr_PSEUDO<VR64, x86mmx>; 573 574 let Predicates = [HasSSE1,NoAVX512] in 575 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 576 let Predicates = [HasSSE2,NoAVX512] in { 577 defm _FR16 : CMOVrr_PSEUDO<FR16, f16>; 578 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>; 579 } 580 let Predicates = [HasAVX512] in { 581 defm _FR16X : CMOVrr_PSEUDO<FR16X, f16>; 582 defm _FR32X : CMOVrr_PSEUDO<FR32X, f32>; 583 defm _FR64X : CMOVrr_PSEUDO<FR64X, f64>; 584 } 585 let Predicates = [NoVLX] in { 586 defm _VR128 : CMOVrr_PSEUDO<VR128, v2i64>; 587 defm _VR256 : CMOVrr_PSEUDO<VR256, v4i64>; 588 } 589 let Predicates = [HasVLX] in { 590 defm _VR128X : CMOVrr_PSEUDO<VR128X, v2i64>; 591 defm _VR256X : CMOVrr_PSEUDO<VR256X, v4i64>; 592 } 593 defm _VR512 : CMOVrr_PSEUDO<VR512, v8i64>; 594 defm _VK1 : CMOVrr_PSEUDO<VK1, v1i1>; 595 defm _VK2 : CMOVrr_PSEUDO<VK2, v2i1>; 596 defm _VK4 : CMOVrr_PSEUDO<VK4, v4i1>; 597 defm _VK8 : CMOVrr_PSEUDO<VK8, v8i1>; 598 defm _VK16 : CMOVrr_PSEUDO<VK16, v16i1>; 599 defm _VK32 : CMOVrr_PSEUDO<VK32, v32i1>; 600 defm _VK64 : CMOVrr_PSEUDO<VK64, v64i1>; 601} // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] 602 603def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 604 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 605 606let Predicates = [NoVLX] in { 607 def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 608 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 609 def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 610 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 611 def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 612 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 613 def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 614 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 615 def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 616 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 617 618 def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 619 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 620 def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 621 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 622 def : Pat<(v8i32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 623 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 624 def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 625 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 626 def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 627 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 628} 629let Predicates = [HasVLX] in { 630 def : Pat<(v16i8 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 631 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 632 def : Pat<(v8i16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 633 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 634 def : Pat<(v8f16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 635 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 636 def : Pat<(v4i32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 637 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 638 def : Pat<(v4f32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 639 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 640 def : Pat<(v2f64 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 641 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 642 643 def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 644 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 645 def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 646 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 647 def : Pat<(v16f16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 648 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 649 def : Pat<(v8i32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 650 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 651 def : Pat<(v8f32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 652 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 653 def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 654 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 655} 656 657def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 658 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 659def : Pat<(v32i16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 660 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 661def : Pat<(v32f16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 662 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 663def : Pat<(v16i32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 664 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 665def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 666 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 667def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 668 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 669 670//===----------------------------------------------------------------------===// 671// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 672//===----------------------------------------------------------------------===// 673 674// FIXME: Use normal instructions and add lock prefix dynamically. 675 676// Memory barriers 677 678let isCodeGenOnly = 1, Defs = [EFLAGS] in 679def OR32mi8Locked : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$zero), 680 "or{l}\t{$zero, $dst|$dst, $zero}", []>, 681 Requires<[Not64BitMode]>, OpSize32, LOCK, 682 Sched<[WriteALURMW]>; 683 684// RegOpc corresponds to the mr version of the instruction 685// ImmOpc corresponds to the mi version of the instruction 686// ImmOpc8 corresponds to the mi8 version of the instruction 687// ImmMod corresponds to the instruction format of the mi and mi8 versions 688multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 689 Format ImmMod, SDNode Op, string mnemonic> { 690let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 691 SchedRW = [WriteALURMW] in { 692 693def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 694 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 695 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 696 !strconcat(mnemonic, "{b}\t", 697 "{$src2, $dst|$dst, $src2}"), 698 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK; 699 700def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 701 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 702 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 703 !strconcat(mnemonic, "{w}\t", 704 "{$src2, $dst|$dst, $src2}"), 705 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>, 706 OpSize16, LOCK; 707 708def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 709 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 710 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 711 !strconcat(mnemonic, "{l}\t", 712 "{$src2, $dst|$dst, $src2}"), 713 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>, 714 OpSize32, LOCK; 715 716def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 717 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 718 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 719 !strconcat(mnemonic, "{q}\t", 720 "{$src2, $dst|$dst, $src2}"), 721 [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK; 722 723// NOTE: These are order specific, we want the mi8 forms to be listed 724// first so that they are slightly preferred to the mi forms. 725def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 726 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 727 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 728 !strconcat(mnemonic, "{w}\t", 729 "{$src2, $dst|$dst, $src2}"), 730 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>, 731 OpSize16, LOCK; 732 733def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 734 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 735 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 736 !strconcat(mnemonic, "{l}\t", 737 "{$src2, $dst|$dst, $src2}"), 738 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>, 739 OpSize32, LOCK; 740 741def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 742 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 743 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 744 !strconcat(mnemonic, "{q}\t", 745 "{$src2, $dst|$dst, $src2}"), 746 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>, 747 LOCK; 748 749def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 750 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 751 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 752 !strconcat(mnemonic, "{b}\t", 753 "{$src2, $dst|$dst, $src2}"), 754 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK; 755 756def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 757 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 758 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 759 !strconcat(mnemonic, "{w}\t", 760 "{$src2, $dst|$dst, $src2}"), 761 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>, 762 OpSize16, LOCK; 763 764def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 765 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 766 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 767 !strconcat(mnemonic, "{l}\t", 768 "{$src2, $dst|$dst, $src2}"), 769 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>, 770 OpSize32, LOCK; 771 772def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 773 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 774 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 775 !strconcat(mnemonic, "{q}\t", 776 "{$src2, $dst|$dst, $src2}"), 777 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>, 778 LOCK; 779} 780 781} 782 783defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">; 784defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">; 785defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">; 786defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; 787defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; 788 789let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 790 SchedRW = [WriteALURMW] in { 791 let Predicates = [UseIncDec] in { 792 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), 793 "inc{b}\t$dst", 794 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i8 1)))]>, 795 LOCK; 796 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), 797 "inc{w}\t$dst", 798 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i16 1)))]>, 799 OpSize16, LOCK; 800 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), 801 "inc{l}\t$dst", 802 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i32 1)))]>, 803 OpSize32, LOCK; 804 805 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), 806 "dec{b}\t$dst", 807 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i8 1)))]>, 808 LOCK; 809 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), 810 "dec{w}\t$dst", 811 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i16 1)))]>, 812 OpSize16, LOCK; 813 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), 814 "dec{l}\t$dst", 815 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i32 1)))]>, 816 OpSize32, LOCK; 817 } 818 819 let Predicates = [UseIncDec, In64BitMode] in { 820 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), 821 "inc{q}\t$dst", 822 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i64 1)))]>, 823 LOCK; 824 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), 825 "dec{q}\t$dst", 826 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i64 1)))]>, 827 LOCK; 828 } 829} 830 831let Predicates = [UseIncDec] in { 832 // Additional patterns for -1 constant. 833 def : Pat<(X86lock_add addr:$dst, (i8 -1)), (LOCK_DEC8m addr:$dst)>; 834 def : Pat<(X86lock_add addr:$dst, (i16 -1)), (LOCK_DEC16m addr:$dst)>; 835 def : Pat<(X86lock_add addr:$dst, (i32 -1)), (LOCK_DEC32m addr:$dst)>; 836 def : Pat<(X86lock_sub addr:$dst, (i8 -1)), (LOCK_INC8m addr:$dst)>; 837 def : Pat<(X86lock_sub addr:$dst, (i16 -1)), (LOCK_INC16m addr:$dst)>; 838 def : Pat<(X86lock_sub addr:$dst, (i32 -1)), (LOCK_INC32m addr:$dst)>; 839} 840 841let Predicates = [UseIncDec, In64BitMode] in { 842 // Additional patterns for -1 constant. 843 def : Pat<(X86lock_add addr:$dst, (i64 -1)), (LOCK_DEC64m addr:$dst)>; 844 def : Pat<(X86lock_sub addr:$dst, (i64 -1)), (LOCK_INC64m addr:$dst)>; 845} 846 847// Atomic bit test. 848def X86LBTest : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisPtrTy<1>, 849 SDTCisVT<2, i8>, SDTCisVT<3, i32>]>; 850def x86bts : SDNode<"X86ISD::LBTS", X86LBTest, 851 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 852def x86btc : SDNode<"X86ISD::LBTC", X86LBTest, 853 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 854def x86btr : SDNode<"X86ISD::LBTR", X86LBTest, 855 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 856 857def X86LBTestRM : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>, 858 SDTCisInt<2>]>; 859 860def x86_rm_bts : SDNode<"X86ISD::LBTS_RM", X86LBTestRM, 861 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 862def x86_rm_btc : SDNode<"X86ISD::LBTC_RM", X86LBTestRM, 863 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 864def x86_rm_btr : SDNode<"X86ISD::LBTR_RM", X86LBTestRM, 865 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 866 867 868multiclass ATOMIC_LOGIC_OP<Format Form, string s> { 869 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 870 SchedRW = [WriteBitTestSetRegRMW] in { 871 def 16m : Ii8<0xBA, Form, (outs), (ins i16mem:$src1, i8imm:$src2), 872 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"), 873 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 16)))]>, 874 OpSize16, TB, LOCK; 875 def 32m : Ii8<0xBA, Form, (outs), (ins i32mem:$src1, i8imm:$src2), 876 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"), 877 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 32)))]>, 878 OpSize32, TB, LOCK; 879 def 64m : RIi8<0xBA, Form, (outs), (ins i64mem:$src1, i8imm:$src2), 880 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"), 881 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 64)))]>, 882 TB, LOCK; 883 } 884} 885 886multiclass ATOMIC_LOGIC_OP_RM<bits<8> Opc8, string s> { 887 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 888 SchedRW = [WriteBitTestSetRegRMW] in { 889 def 16rm : I<Opc8, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 890 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"), 891 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR16:$src2))]>, 892 OpSize16, TB, LOCK; 893 def 32rm : I<Opc8, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 894 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"), 895 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR32:$src2))]>, 896 OpSize32, TB, LOCK; 897 def 64rm : RI<Opc8, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 898 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"), 899 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR64:$src2))]>, 900 TB, LOCK; 901 } 902} 903 904 905defm LOCK_BTS : ATOMIC_LOGIC_OP<MRM5m, "bts">; 906defm LOCK_BTC : ATOMIC_LOGIC_OP<MRM7m, "btc">; 907defm LOCK_BTR : ATOMIC_LOGIC_OP<MRM6m, "btr">; 908 909defm LOCK_BTS_RM : ATOMIC_LOGIC_OP_RM<0xAB, "bts">; 910defm LOCK_BTC_RM : ATOMIC_LOGIC_OP_RM<0xBB, "btc">; 911defm LOCK_BTR_RM : ATOMIC_LOGIC_OP_RM<0xB3, "btr">; 912 913// Atomic compare and swap. 914multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 915 string mnemonic, SDPatternOperator frag> { 916let isCodeGenOnly = 1, SchedRW = [WriteCMPXCHGRMW] in { 917 let Defs = [AL, EFLAGS], Uses = [AL] in 918 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 919 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 920 [(frag addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; 921 let Defs = [AX, EFLAGS], Uses = [AX] in 922 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 923 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 924 [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK; 925 let Defs = [EAX, EFLAGS], Uses = [EAX] in 926 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 927 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 928 [(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK; 929 let Defs = [RAX, EFLAGS], Uses = [RAX] in 930 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 931 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 932 [(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK; 933} 934} 935 936let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 937 Predicates = [HasCX8], SchedRW = [WriteCMPXCHGRMW], 938 isCodeGenOnly = 1, usesCustomInserter = 1 in { 939def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr), 940 "cmpxchg8b\t$ptr", 941 [(X86cas8 addr:$ptr)]>, TB, LOCK; 942} 943 944let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 945 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 946 isCodeGenOnly = 1, mayLoad = 1, mayStore = 1, hasSideEffects = 0 in { 947def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr), 948 "cmpxchg16b\t$ptr", 949 []>, TB, LOCK; 950} 951 952// This pseudo must be used when the frame uses RBX as 953// the base pointer. Indeed, in such situation RBX is a reserved 954// register and the register allocator will ignore any use/def of 955// it. In other words, the register will not fix the clobbering of 956// RBX that will happen when setting the arguments for the instrucion. 957// 958// Unlike the actual related instruction, we mark that this one 959// defines RBX (instead of using RBX). 960// The rationale is that we will define RBX during the expansion of 961// the pseudo. The argument feeding RBX is rbx_input. 962// 963// The additional argument, $rbx_save, is a temporary register used to 964// save the value of RBX across the actual instruction. 965// 966// To make sure the register assigned to $rbx_save does not interfere with 967// the definition of the actual instruction, we use a definition $dst which 968// is tied to $rbx_save. That way, the live-range of $rbx_save spans across 969// the instruction and we are sure we will have a valid register to restore 970// the value of RBX. 971let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX], 972 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 973 isCodeGenOnly = 1, isPseudo = 1, 974 mayLoad = 1, mayStore = 1, hasSideEffects = 0, 975 Constraints = "$rbx_save = $dst" in { 976def LCMPXCHG16B_SAVE_RBX : 977 I<0, Pseudo, (outs GR64:$dst), 978 (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), "", []>; 979} 980 981// Pseudo instruction that doesn't read/write RBX. Will be turned into either 982// LCMPXCHG16B_SAVE_RBX or LCMPXCHG16B via a custom inserter. 983let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RCX, RDX], 984 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 985 isCodeGenOnly = 1, isPseudo = 1, 986 mayLoad = 1, mayStore = 1, hasSideEffects = 0, 987 usesCustomInserter = 1 in { 988def LCMPXCHG16B_NO_RBX : 989 I<0, Pseudo, (outs), (ins i128mem:$ptr, GR64:$rbx_input), "", 990 [(X86cas16 addr:$ptr, GR64:$rbx_input)]>; 991} 992 993// This pseudo must be used when the frame uses RBX/EBX as 994// the base pointer. 995// cf comment for LCMPXCHG16B_SAVE_RBX. 996let Defs = [EBX], Uses = [ECX, EAX], 997 Predicates = [HasMWAITX], SchedRW = [WriteSystem], 998 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst" in { 999def MWAITX_SAVE_RBX : 1000 I<0, Pseudo, (outs GR64:$dst), 1001 (ins GR32:$ebx_input, GR64:$rbx_save), 1002 "mwaitx", 1003 []>; 1004} 1005 1006// Pseudo mwaitx instruction to use for custom insertion. 1007let Predicates = [HasMWAITX], SchedRW = [WriteSystem], 1008 isCodeGenOnly = 1, isPseudo = 1, 1009 usesCustomInserter = 1 in { 1010def MWAITX : 1011 I<0, Pseudo, (outs), (ins GR32:$ecx, GR32:$eax, GR32:$ebx), 1012 "mwaitx", 1013 [(int_x86_mwaitx GR32:$ecx, GR32:$eax, GR32:$ebx)]>; 1014} 1015 1016 1017defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>; 1018 1019// Atomic exchange and add 1020multiclass ATOMIC_RMW_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 1021 string frag> { 1022 let Constraints = "$val = $dst", Defs = [EFLAGS], mayLoad = 1, mayStore = 1, 1023 isCodeGenOnly = 1, SchedRW = [WriteALURMW] in { 1024 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 1025 (ins GR8:$val, i8mem:$ptr), 1026 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 1027 [(set GR8:$dst, 1028 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>; 1029 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 1030 (ins GR16:$val, i16mem:$ptr), 1031 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 1032 [(set 1033 GR16:$dst, 1034 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, 1035 OpSize16; 1036 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 1037 (ins GR32:$val, i32mem:$ptr), 1038 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 1039 [(set 1040 GR32:$dst, 1041 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, 1042 OpSize32; 1043 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 1044 (ins GR64:$val, i64mem:$ptr), 1045 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 1046 [(set 1047 GR64:$dst, 1048 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; 1049 } 1050} 1051 1052defm LXADD : ATOMIC_RMW_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK; 1053 1054/* The following multiclass tries to make sure that in code like 1055 * x.store (immediate op x.load(acquire), release) 1056 * and 1057 * x.store (register op x.load(acquire), release) 1058 * an operation directly on memory is generated instead of wasting a register. 1059 * It is not automatic as atomic_store/load are only lowered to MOV instructions 1060 * extremely late to prevent them from being accidentally reordered in the backend 1061 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) 1062 */ 1063multiclass RELEASE_BINOP_MI<string Name, SDNode op> { 1064 def : Pat<(atomic_store_8 (op (atomic_load_8 addr:$dst), (i8 imm:$src)), 1065 addr:$dst), 1066 (!cast<Instruction>(Name#"8mi") addr:$dst, imm:$src)>; 1067 def : Pat<(atomic_store_16 (op (atomic_load_16 addr:$dst), (i16 imm:$src)), 1068 addr:$dst), 1069 (!cast<Instruction>(Name#"16mi") addr:$dst, imm:$src)>; 1070 def : Pat<(atomic_store_32 (op (atomic_load_32 addr:$dst), (i32 imm:$src)), 1071 addr:$dst), 1072 (!cast<Instruction>(Name#"32mi") addr:$dst, imm:$src)>; 1073 def : Pat<(atomic_store_64 (op (atomic_load_64 addr:$dst), (i64immSExt32:$src)), 1074 addr:$dst), 1075 (!cast<Instruction>(Name#"64mi32") addr:$dst, (i64immSExt32:$src))>; 1076 def : Pat<(atomic_store_8 (op (atomic_load_8 addr:$dst), (i8 GR8:$src)), addr:$dst), 1077 (!cast<Instruction>(Name#"8mr") addr:$dst, GR8:$src)>; 1078 def : Pat<(atomic_store_16 (op (atomic_load_16 addr:$dst), (i16 GR16:$src)), 1079 addr:$dst), 1080 (!cast<Instruction>(Name#"16mr") addr:$dst, GR16:$src)>; 1081 def : Pat<(atomic_store_32 (op (atomic_load_32 addr:$dst), (i32 GR32:$src)), 1082 addr:$dst), 1083 (!cast<Instruction>(Name#"32mr") addr:$dst, GR32:$src)>; 1084 def : Pat<(atomic_store_64 (op (atomic_load_64 addr:$dst), (i64 GR64:$src)), 1085 addr:$dst), 1086 (!cast<Instruction>(Name#"64mr") addr:$dst, GR64:$src)>; 1087} 1088defm : RELEASE_BINOP_MI<"ADD", add>; 1089defm : RELEASE_BINOP_MI<"AND", and>; 1090defm : RELEASE_BINOP_MI<"OR", or>; 1091defm : RELEASE_BINOP_MI<"XOR", xor>; 1092defm : RELEASE_BINOP_MI<"SUB", sub>; 1093 1094// Atomic load + floating point patterns. 1095// FIXME: This could also handle SIMD operations with *ps and *pd instructions. 1096multiclass ATOMIC_LOAD_FP_BINOP_MI<string Name, SDNode op> { 1097 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1098 (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>, 1099 Requires<[UseSSE1]>; 1100 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1101 (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>, 1102 Requires<[UseAVX]>; 1103 def : Pat<(op FR32X:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1104 (!cast<Instruction>("V"#Name#"SSZrm") FR32X:$src1, addr:$src2)>, 1105 Requires<[HasAVX512]>; 1106 1107 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1108 (!cast<Instruction>(Name#"SDrm") FR64:$src1, addr:$src2)>, 1109 Requires<[UseSSE1]>; 1110 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1111 (!cast<Instruction>("V"#Name#"SDrm") FR64:$src1, addr:$src2)>, 1112 Requires<[UseAVX]>; 1113 def : Pat<(op FR64X:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1114 (!cast<Instruction>("V"#Name#"SDZrm") FR64X:$src1, addr:$src2)>, 1115 Requires<[HasAVX512]>; 1116} 1117defm : ATOMIC_LOAD_FP_BINOP_MI<"ADD", fadd>; 1118// FIXME: Add fsub, fmul, fdiv, ... 1119 1120multiclass RELEASE_UNOP<string Name, dag dag8, dag dag16, dag dag32, 1121 dag dag64> { 1122 def : Pat<(atomic_store_8 dag8, addr:$dst), 1123 (!cast<Instruction>(Name#8m) addr:$dst)>; 1124 def : Pat<(atomic_store_16 dag16, addr:$dst), 1125 (!cast<Instruction>(Name#16m) addr:$dst)>; 1126 def : Pat<(atomic_store_32 dag32, addr:$dst), 1127 (!cast<Instruction>(Name#32m) addr:$dst)>; 1128 def : Pat<(atomic_store_64 dag64, addr:$dst), 1129 (!cast<Instruction>(Name#64m) addr:$dst)>; 1130} 1131 1132let Predicates = [UseIncDec] in { 1133 defm : RELEASE_UNOP<"INC", 1134 (add (atomic_load_8 addr:$dst), (i8 1)), 1135 (add (atomic_load_16 addr:$dst), (i16 1)), 1136 (add (atomic_load_32 addr:$dst), (i32 1)), 1137 (add (atomic_load_64 addr:$dst), (i64 1))>; 1138 defm : RELEASE_UNOP<"DEC", 1139 (add (atomic_load_8 addr:$dst), (i8 -1)), 1140 (add (atomic_load_16 addr:$dst), (i16 -1)), 1141 (add (atomic_load_32 addr:$dst), (i32 -1)), 1142 (add (atomic_load_64 addr:$dst), (i64 -1))>; 1143} 1144 1145defm : RELEASE_UNOP<"NEG", 1146 (ineg (i8 (atomic_load_8 addr:$dst))), 1147 (ineg (i16 (atomic_load_16 addr:$dst))), 1148 (ineg (i32 (atomic_load_32 addr:$dst))), 1149 (ineg (i64 (atomic_load_64 addr:$dst)))>; 1150defm : RELEASE_UNOP<"NOT", 1151 (not (i8 (atomic_load_8 addr:$dst))), 1152 (not (i16 (atomic_load_16 addr:$dst))), 1153 (not (i32 (atomic_load_32 addr:$dst))), 1154 (not (i64 (atomic_load_64 addr:$dst)))>; 1155 1156def : Pat<(atomic_store_8 (i8 imm:$src), addr:$dst), 1157 (MOV8mi addr:$dst, imm:$src)>; 1158def : Pat<(atomic_store_16 (i16 imm:$src), addr:$dst), 1159 (MOV16mi addr:$dst, imm:$src)>; 1160def : Pat<(atomic_store_32 (i32 imm:$src), addr:$dst), 1161 (MOV32mi addr:$dst, imm:$src)>; 1162def : Pat<(atomic_store_64 (i64immSExt32:$src), addr:$dst), 1163 (MOV64mi32 addr:$dst, i64immSExt32:$src)>; 1164 1165def : Pat<(atomic_store_8 GR8:$src, addr:$dst), 1166 (MOV8mr addr:$dst, GR8:$src)>; 1167def : Pat<(atomic_store_16 GR16:$src, addr:$dst), 1168 (MOV16mr addr:$dst, GR16:$src)>; 1169def : Pat<(atomic_store_32 GR32:$src, addr:$dst), 1170 (MOV32mr addr:$dst, GR32:$src)>; 1171def : Pat<(atomic_store_64 GR64:$src, addr:$dst), 1172 (MOV64mr addr:$dst, GR64:$src)>; 1173 1174def : Pat<(i8 (atomic_load_8 addr:$src)), (MOV8rm addr:$src)>; 1175def : Pat<(i16 (atomic_load_16 addr:$src)), (MOV16rm addr:$src)>; 1176def : Pat<(i32 (atomic_load_32 addr:$src)), (MOV32rm addr:$src)>; 1177def : Pat<(i64 (atomic_load_64 addr:$src)), (MOV64rm addr:$src)>; 1178 1179// Floating point loads/stores. 1180def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst), 1181 (MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>; 1182def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst), 1183 (VMOVSSmr addr:$dst, FR32:$src)>, Requires<[UseAVX]>; 1184def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst), 1185 (VMOVSSZmr addr:$dst, FR32:$src)>, Requires<[HasAVX512]>; 1186 1187def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst), 1188 (MOVSDmr addr:$dst, FR64:$src)>, Requires<[UseSSE2]>; 1189def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst), 1190 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[UseAVX]>; 1191def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst), 1192 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[HasAVX512]>; 1193 1194def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1195 (MOVSSrm_alt addr:$src)>, Requires<[UseSSE1]>; 1196def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1197 (VMOVSSrm_alt addr:$src)>, Requires<[UseAVX]>; 1198def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1199 (VMOVSSZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1200 1201def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1202 (MOVSDrm_alt addr:$src)>, Requires<[UseSSE2]>; 1203def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1204 (VMOVSDrm_alt addr:$src)>, Requires<[UseAVX]>; 1205def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1206 (VMOVSDZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1207 1208//===----------------------------------------------------------------------===// 1209// DAG Pattern Matching Rules 1210//===----------------------------------------------------------------------===// 1211 1212// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves 1213// binary size compared to a regular MOV, but it introduces an unnecessary 1214// load, so is not suitable for regular or optsize functions. 1215let Predicates = [OptForMinSize] in { 1216def : Pat<(simple_store (i16 0), addr:$dst), (AND16mi addr:$dst, 0)>; 1217def : Pat<(simple_store (i32 0), addr:$dst), (AND32mi addr:$dst, 0)>; 1218def : Pat<(simple_store (i64 0), addr:$dst), (AND64mi32 addr:$dst, 0)>; 1219def : Pat<(simple_store (i16 -1), addr:$dst), (OR16mi addr:$dst, -1)>; 1220def : Pat<(simple_store (i32 -1), addr:$dst), (OR32mi addr:$dst, -1)>; 1221def : Pat<(simple_store (i64 -1), addr:$dst), (OR64mi32 addr:$dst, -1)>; 1222} 1223 1224// In kernel code model, we can get the address of a label 1225// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 1226// the MOV64ri32 should accept these. 1227def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 1228 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 1229def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 1230 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 1231def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 1232 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 1233def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 1234 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 1235def : Pat<(i64 (X86Wrapper mcsym:$dst)), 1236 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; 1237def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 1238 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 1239 1240// If we have small model and -static mode, it is safe to store global addresses 1241// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 1242// for MOV64mi32 should handle this sort of thing. 1243def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 1244 (MOV64mi32 addr:$dst, tconstpool:$src)>, 1245 Requires<[NearData, IsNotPIC]>; 1246def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 1247 (MOV64mi32 addr:$dst, tjumptable:$src)>, 1248 Requires<[NearData, IsNotPIC]>; 1249def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1250 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 1251 Requires<[NearData, IsNotPIC]>; 1252def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 1253 (MOV64mi32 addr:$dst, texternalsym:$src)>, 1254 Requires<[NearData, IsNotPIC]>; 1255def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), 1256 (MOV64mi32 addr:$dst, mcsym:$src)>, 1257 Requires<[NearData, IsNotPIC]>; 1258def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 1259 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 1260 Requires<[NearData, IsNotPIC]>; 1261 1262def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; 1263def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; 1264 1265// Calls 1266 1267// tls has some funny stuff here... 1268// This corresponds to movabs $foo@tpoff, %rax 1269def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 1270 (MOV64ri32 tglobaltlsaddr :$dst)>; 1271// This corresponds to add $foo@tpoff, %rax 1272def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 1273 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 1274 1275 1276// Direct PC relative function call for small code model. 32-bit displacement 1277// sign extended to 64-bit. 1278def : Pat<(X86call (i64 tglobaladdr:$dst)), 1279 (CALL64pcrel32 tglobaladdr:$dst)>; 1280def : Pat<(X86call (i64 texternalsym:$dst)), 1281 (CALL64pcrel32 texternalsym:$dst)>; 1282 1283def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 texternalsym:$dst)), 1284 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, texternalsym:$dst)>; 1285def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 tglobaladdr:$dst)), 1286 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, tglobaladdr:$dst)>; 1287 1288 1289// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1290// can never use callee-saved registers. That is the purpose of the GR64_TC 1291// register classes. 1292// 1293// The only volatile register that is never used by the calling convention is 1294// %r11. This happens when calling a vararg function with 6 arguments. 1295// 1296// Match an X86tcret that uses less than 7 volatile registers. 1297def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1298 (TCRETURNri ptr_rc_tailcall:$dst, timm:$off)>, 1299 Requires<[Not64BitMode, NotUseIndirectThunkCalls]>; 1300 1301// FIXME: This is disabled for 32-bit PIC mode because the global base 1302// register which is part of the address mode may be assigned a 1303// callee-saved register. 1304// Similar to X86tcret_6regs, here we only have 1 register left 1305def : Pat<(X86tcret_1reg (load addr:$dst), timm:$off), 1306 (TCRETURNmi addr:$dst, timm:$off)>, 1307 Requires<[Not64BitMode, IsNotPIC, NotUseIndirectThunkCalls]>; 1308 1309def : Pat<(X86tcret (i32 tglobaladdr:$dst), timm:$off), 1310 (TCRETURNdi tglobaladdr:$dst, timm:$off)>, 1311 Requires<[NotLP64]>; 1312 1313def : Pat<(X86tcret (i32 texternalsym:$dst), timm:$off), 1314 (TCRETURNdi texternalsym:$dst, timm:$off)>, 1315 Requires<[NotLP64]>; 1316 1317def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1318 (TCRETURNri64 ptr_rc_tailcall:$dst, timm:$off)>, 1319 Requires<[In64BitMode, NotUseIndirectThunkCalls]>; 1320 1321// Don't fold loads into X86tcret requiring more than 6 regs. 1322// There wouldn't be enough scratch registers for base+index. 1323def : Pat<(X86tcret_6regs (load addr:$dst), timm:$off), 1324 (TCRETURNmi64 addr:$dst, timm:$off)>, 1325 Requires<[In64BitMode, NotUseIndirectThunkCalls]>; 1326 1327def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1328 (INDIRECT_THUNK_TCRETURN64 ptr_rc_tailcall:$dst, timm:$off)>, 1329 Requires<[In64BitMode, UseIndirectThunkCalls]>; 1330 1331def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1332 (INDIRECT_THUNK_TCRETURN32 ptr_rc_tailcall:$dst, timm:$off)>, 1333 Requires<[Not64BitMode, UseIndirectThunkCalls]>; 1334 1335def : Pat<(X86tcret (i64 tglobaladdr:$dst), timm:$off), 1336 (TCRETURNdi64 tglobaladdr:$dst, timm:$off)>, 1337 Requires<[IsLP64]>; 1338 1339def : Pat<(X86tcret (i64 texternalsym:$dst), timm:$off), 1340 (TCRETURNdi64 texternalsym:$dst, timm:$off)>, 1341 Requires<[IsLP64]>; 1342 1343// Normal calls, with various flavors of addresses. 1344def : Pat<(X86call (i32 tglobaladdr:$dst)), 1345 (CALLpcrel32 tglobaladdr:$dst)>; 1346def : Pat<(X86call (i32 texternalsym:$dst)), 1347 (CALLpcrel32 texternalsym:$dst)>; 1348def : Pat<(X86call (i32 imm:$dst)), 1349 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1350 1351// Comparisons. 1352 1353// TEST R,R is smaller than CMP R,0 1354def : Pat<(X86cmp GR8:$src1, 0), 1355 (TEST8rr GR8:$src1, GR8:$src1)>; 1356def : Pat<(X86cmp GR16:$src1, 0), 1357 (TEST16rr GR16:$src1, GR16:$src1)>; 1358def : Pat<(X86cmp GR32:$src1, 0), 1359 (TEST32rr GR32:$src1, GR32:$src1)>; 1360def : Pat<(X86cmp GR64:$src1, 0), 1361 (TEST64rr GR64:$src1, GR64:$src1)>; 1362 1363// zextload bool -> zextload byte 1364// i1 stored in one byte in zero-extended form. 1365// Upper bits cleanup should be executed before Store. 1366def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1367def : Pat<(zextloadi16i1 addr:$src), 1368 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1369def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1370def : Pat<(zextloadi64i1 addr:$src), 1371 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1372 1373// extload bool -> extload byte 1374// When extloading from 16-bit and smaller memory locations into 64-bit 1375// registers, use zero-extending loads so that the entire 64-bit register is 1376// defined, avoiding partial-register updates. 1377 1378def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1379def : Pat<(extloadi16i1 addr:$src), 1380 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1381def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1382def : Pat<(extloadi16i8 addr:$src), 1383 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1384def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1385def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1386 1387// For other extloads, use subregs, since the high contents of the register are 1388// defined after an extload. 1389// NOTE: The extloadi64i32 pattern needs to be first as it will try to form 1390// 32-bit loads for 4 byte aligned i8/i16 loads. 1391def : Pat<(extloadi64i32 addr:$src), 1392 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1393def : Pat<(extloadi64i1 addr:$src), 1394 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1395def : Pat<(extloadi64i8 addr:$src), 1396 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1397def : Pat<(extloadi64i16 addr:$src), 1398 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1399 1400// anyext. Define these to do an explicit zero-extend to 1401// avoid partial-register updates. 1402def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1403 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1404def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1405 1406// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1407def : Pat<(i32 (anyext GR16:$src)), 1408 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1409 1410def : Pat<(i64 (anyext GR8 :$src)), 1411 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1412def : Pat<(i64 (anyext GR16:$src)), 1413 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1414def : Pat<(i64 (anyext GR32:$src)), 1415 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>; 1416 1417def : Pat<(i32 (anyext_sdiv GR8:$src)), (MOVSX32rr8 GR8:$src)>; 1418 1419// In the case of a 32-bit def that is known to implicitly zero-extend, 1420// we can use a SUBREG_TO_REG. 1421def : Pat<(i64 (zext def32:$src)), 1422 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1423def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)), 1424 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1425 1426//===----------------------------------------------------------------------===// 1427// Pattern match OR as ADD 1428//===----------------------------------------------------------------------===// 1429 1430// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1431// 3-addressified into an LEA instruction to avoid copies. However, we also 1432// want to finally emit these instructions as an or at the end of the code 1433// generator to make the generated code easier to read. To do this, we select 1434// into "disjoint bits" pseudo ops. 1435 1436// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1437// Try this before the selecting to OR. 1438let SchedRW = [WriteALU] in { 1439 1440let isConvertibleToThreeAddress = 1, isPseudo = 1, 1441 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1442let isCommutable = 1 in { 1443def ADD8rr_DB : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), 1444 "", // orb/addb REG, REG 1445 [(set GR8:$dst, (or_is_add GR8:$src1, GR8:$src2))]>; 1446def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1447 "", // orw/addw REG, REG 1448 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1449def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1450 "", // orl/addl REG, REG 1451 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1452def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1453 "", // orq/addq REG, REG 1454 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1455} // isCommutable 1456 1457def ADD8ri_DB : I<0, Pseudo, 1458 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), 1459 "", // orb/addb REG, imm8 1460 [(set GR8:$dst, (or_is_add GR8:$src1, imm:$src2))]>; 1461def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1462 "", // orw/addw REG, imm 1463 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1464def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1465 "", // orl/addl REG, imm 1466 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1467def ADD64ri32_DB : I<0, Pseudo, 1468 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1469 "", // orq/addq REG, imm 1470 [(set GR64:$dst, (or_is_add GR64:$src1, 1471 i64immSExt32:$src2))]>; 1472} 1473} // AddedComplexity, SchedRW 1474 1475//===----------------------------------------------------------------------===// 1476// Pattern match XOR as ADD 1477//===----------------------------------------------------------------------===// 1478 1479// Prefer to pattern match XOR with min_signed_value as ADD at isel time. 1480// ADD can be 3-addressified into an LEA instruction to avoid copies. 1481let AddedComplexity = 5 in { 1482def : Pat<(xor GR8:$src1, -128), 1483 (ADD8ri GR8:$src1, -128)>; 1484def : Pat<(xor GR16:$src1, -32768), 1485 (ADD16ri GR16:$src1, -32768)>; 1486def : Pat<(xor GR32:$src1, -2147483648), 1487 (ADD32ri GR32:$src1, -2147483648)>; 1488} 1489 1490//===----------------------------------------------------------------------===// 1491// Some peepholes 1492//===----------------------------------------------------------------------===// 1493 1494// Odd encoding trick: -128 fits into an 8-bit immediate field while 1495// +128 doesn't, so in this special case use a sub instead of an add. 1496def : Pat<(add GR16:$src1, 128), 1497 (SUB16ri GR16:$src1, -128)>; 1498def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1499 (SUB16mi addr:$dst, -128)>; 1500 1501def : Pat<(add GR32:$src1, 128), 1502 (SUB32ri GR32:$src1, -128)>; 1503def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1504 (SUB32mi addr:$dst, -128)>; 1505 1506def : Pat<(add GR64:$src1, 128), 1507 (SUB64ri32 GR64:$src1, -128)>; 1508def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1509 (SUB64mi32 addr:$dst, -128)>; 1510 1511def : Pat<(X86add_flag_nocf GR16:$src1, 128), 1512 (SUB16ri GR16:$src1, -128)>; 1513def : Pat<(X86add_flag_nocf GR32:$src1, 128), 1514 (SUB32ri GR32:$src1, -128)>; 1515def : Pat<(X86add_flag_nocf GR64:$src1, 128), 1516 (SUB64ri32 GR64:$src1, -128)>; 1517 1518// Depositing value to 8/16 bit subreg: 1519def : Pat<(or (and GR64:$dst, -256), 1520 (i64 (zextloadi8 addr:$src))), 1521 (INSERT_SUBREG (i64 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>; 1522 1523def : Pat<(or (and GR32:$dst, -256), 1524 (i32 (zextloadi8 addr:$src))), 1525 (INSERT_SUBREG (i32 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>; 1526 1527def : Pat<(or (and GR64:$dst, -65536), 1528 (i64 (zextloadi16 addr:$src))), 1529 (INSERT_SUBREG (i64 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit)>; 1530 1531def : Pat<(or (and GR32:$dst, -65536), 1532 (i32 (zextloadi16 addr:$src))), 1533 (INSERT_SUBREG (i32 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit)>; 1534 1535// The same trick applies for 32-bit immediate fields in 64-bit 1536// instructions. 1537def : Pat<(add GR64:$src1, 0x0000000080000000), 1538 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1539def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst), 1540 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1541def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000), 1542 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1543 1544// To avoid needing to materialize an immediate in a register, use a 32-bit and 1545// with implicit zero-extension instead of a 64-bit and if the immediate has at 1546// least 32 bits of leading zeros. If in addition the last 32 bits can be 1547// represented with a sign extension of a 8 bit constant, use that. 1548// This can also reduce instruction size by eliminating the need for the REX 1549// prefix. 1550 1551// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. 1552let AddedComplexity = 1 in { 1553 let Predicates = [NoNDD] in { 1554 def : Pat<(and GR64:$src, i64immZExt32:$imm), 1555 (SUBREG_TO_REG 1556 (i64 0), 1557 (AND32ri 1558 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1559 (i32 (GetLo32XForm imm:$imm))), 1560 sub_32bit)>; 1561 } 1562 let Predicates = [HasNDD] in { 1563 def : Pat<(and GR64:$src, i64immZExt32:$imm), 1564 (SUBREG_TO_REG 1565 (i64 0), 1566 (AND32ri_ND 1567 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1568 (i32 (GetLo32XForm imm:$imm))), 1569 sub_32bit)>; 1570 } 1571} // AddedComplexity = 1 1572 1573 1574// AddedComplexity is needed due to the increased complexity on the 1575// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all 1576// the MOVZX patterns keeps thems together in DAGIsel tables. 1577let AddedComplexity = 1 in { 1578// r & (2^16-1) ==> movz 1579def : Pat<(and GR32:$src1, 0xffff), 1580 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1581// r & (2^8-1) ==> movz 1582def : Pat<(and GR32:$src1, 0xff), 1583 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>; 1584// r & (2^8-1) ==> movz 1585def : Pat<(and GR16:$src1, 0xff), 1586 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)), 1587 sub_16bit)>; 1588 1589// r & (2^32-1) ==> movz 1590def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1591 (SUBREG_TO_REG (i64 0), 1592 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1593 sub_32bit)>; 1594// r & (2^16-1) ==> movz 1595def : Pat<(and GR64:$src, 0xffff), 1596 (SUBREG_TO_REG (i64 0), 1597 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1598 sub_32bit)>; 1599// r & (2^8-1) ==> movz 1600def : Pat<(and GR64:$src, 0xff), 1601 (SUBREG_TO_REG (i64 0), 1602 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1603 sub_32bit)>; 1604} // AddedComplexity = 1 1605 1606 1607// Try to use BTS/BTR/BTC for single bit operations on the upper 32-bits. 1608 1609def BTRXForm : SDNodeXForm<imm, [{ 1610 // Transformation function: Find the lowest 0. 1611 return getI64Imm((uint8_t)N->getAPIntValue().countr_one(), SDLoc(N)); 1612}]>; 1613 1614def BTCBTSXForm : SDNodeXForm<imm, [{ 1615 // Transformation function: Find the lowest 1. 1616 return getI64Imm((uint8_t)N->getAPIntValue().countr_zero(), SDLoc(N)); 1617}]>; 1618 1619def BTRMask64 : ImmLeaf<i64, [{ 1620 return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm); 1621}]>; 1622 1623def BTCBTSMask64 : ImmLeaf<i64, [{ 1624 return !isInt<32>(Imm) && isPowerOf2_64(Imm); 1625}]>; 1626 1627// For now only do this for optsize. 1628let AddedComplexity = 1, Predicates=[OptForSize] in { 1629 def : Pat<(and GR64:$src1, BTRMask64:$mask), 1630 (BTR64ri8 GR64:$src1, (BTRXForm imm:$mask))>; 1631 def : Pat<(or GR64:$src1, BTCBTSMask64:$mask), 1632 (BTS64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1633 def : Pat<(xor GR64:$src1, BTCBTSMask64:$mask), 1634 (BTC64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1635} 1636 1637 1638// sext_inreg patterns 1639def : Pat<(sext_inreg GR32:$src, i16), 1640 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1641def : Pat<(sext_inreg GR32:$src, i8), 1642 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>; 1643 1644def : Pat<(sext_inreg GR16:$src, i8), 1645 (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)), 1646 sub_16bit)>; 1647 1648def : Pat<(sext_inreg GR64:$src, i32), 1649 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1650def : Pat<(sext_inreg GR64:$src, i16), 1651 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1652def : Pat<(sext_inreg GR64:$src, i8), 1653 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1654 1655// sext, sext_load, zext, zext_load 1656def: Pat<(i16 (sext GR8:$src)), 1657 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1658def: Pat<(sextloadi16i8 addr:$src), 1659 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1660def: Pat<(i16 (zext GR8:$src)), 1661 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1662def: Pat<(zextloadi16i8 addr:$src), 1663 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1664 1665// trunc patterns 1666def : Pat<(i16 (trunc GR32:$src)), 1667 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1668def : Pat<(i8 (trunc GR32:$src)), 1669 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1670 sub_8bit)>, 1671 Requires<[Not64BitMode]>; 1672def : Pat<(i8 (trunc GR16:$src)), 1673 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1674 sub_8bit)>, 1675 Requires<[Not64BitMode]>; 1676def : Pat<(i32 (trunc GR64:$src)), 1677 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1678def : Pat<(i16 (trunc GR64:$src)), 1679 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1680def : Pat<(i8 (trunc GR64:$src)), 1681 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1682def : Pat<(i8 (trunc GR32:$src)), 1683 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1684 Requires<[In64BitMode]>; 1685def : Pat<(i8 (trunc GR16:$src)), 1686 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1687 Requires<[In64BitMode]>; 1688 1689def immff00_ffff : ImmLeaf<i32, [{ 1690 return Imm >= 0xff00 && Imm <= 0xffff; 1691}]>; 1692 1693// h-register tricks 1694def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1695 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1696 Requires<[Not64BitMode]>; 1697def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))), 1698 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1699 Requires<[Not64BitMode]>; 1700def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1701 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>, 1702 Requires<[Not64BitMode]>; 1703def : Pat<(srl GR16:$src, (i8 8)), 1704 (EXTRACT_SUBREG 1705 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1706 sub_16bit)>; 1707def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1708 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1709def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1710 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1711def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1712 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1713def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)), 1714 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1715 1716// h-register tricks. 1717// For now, be conservative on x86-64 and use an h-register extract only if the 1718// value is immediately zero-extended or stored, which are somewhat common 1719// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1720// from being allocated in the same instruction as the h register, as there's 1721// currently no way to describe this requirement to the register allocator. 1722 1723// h-register extract and zero-extend. 1724def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1725 (SUBREG_TO_REG 1726 (i64 0), 1727 (MOVZX32rr8_NOREX 1728 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), 1729 sub_32bit)>; 1730def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1731 (SUBREG_TO_REG 1732 (i64 0), 1733 (MOVZX32rr8_NOREX 1734 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1735 sub_32bit)>; 1736def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1737 (SUBREG_TO_REG 1738 (i64 0), 1739 (MOVZX32rr8_NOREX 1740 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1741 sub_32bit)>; 1742 1743// h-register extract and store. 1744def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1745 (MOV8mr_NOREX 1746 addr:$dst, 1747 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>; 1748def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1749 (MOV8mr_NOREX 1750 addr:$dst, 1751 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, 1752 Requires<[In64BitMode]>; 1753def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1754 (MOV8mr_NOREX 1755 addr:$dst, 1756 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, 1757 Requires<[In64BitMode]>; 1758 1759// Special pattern to catch the last step of __builtin_parity handling. Our 1760// goal is to use an xor of an h-register with the corresponding l-register. 1761// The above patterns would handle this on non 64-bit targets, but for 64-bit 1762// we need to be more careful. We're using a NOREX instruction here in case 1763// register allocation fails to keep the two registers together. So we need to 1764// make sure we can't accidentally mix R8-R15 with an h-register. 1765def : Pat<(X86xor_flag (i8 (trunc GR32:$src)), 1766 (i8 (trunc (srl_su GR32:$src, (i8 8))))), 1767 (XOR8rr_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit), 1768 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1769 1770// (shl x, 1) ==> (add x, x) 1771// Note that if x is undef (immediate or otherwise), we could theoretically 1772// end up with the two uses of x getting different values, producing a result 1773// where the least significant bit is not 0. However, the probability of this 1774// happening is considered low enough that this is officially not a 1775// "real problem". 1776let Predicates = [NoNDD] in { 1777 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1778 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1779 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1780 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1781} 1782let Predicates = [HasNDD] in { 1783 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr_ND GR8 :$src1, GR8 :$src1)>; 1784 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr_ND GR16:$src1, GR16:$src1)>; 1785 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr_ND GR32:$src1, GR32:$src1)>; 1786 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr_ND GR64:$src1, GR64:$src1)>; 1787} 1788 1789// Shift amount is implicitly masked. 1790multiclass MaskedShiftAmountPats<SDNode frag> { 1791 // (shift x (and y, 31)) ==> (shift x, y) 1792 // (shift x (and y, 63)) ==> (shift x, y) 1793 let Predicates = [NoNDD] in { 1794 def : Pat<(frag GR8:$src1, (shiftMask32 CL)), 1795 (!cast<Instruction>(NAME # "8rCL") GR8:$src1)>; 1796 def : Pat<(frag GR16:$src1, (shiftMask32 CL)), 1797 (!cast<Instruction>(NAME # "16rCL") GR16:$src1)>; 1798 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1799 (!cast<Instruction>(NAME # "32rCL") GR32:$src1)>; 1800 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1801 (!cast<Instruction>(NAME # "64rCL") GR64:$src1)>; 1802 } 1803 let Predicates = [HasNDD] in { 1804 def : Pat<(frag GR8:$src1, (shiftMask32 CL)), 1805 (!cast<Instruction>(NAME # "8rCL_ND") GR8:$src1)>; 1806 def : Pat<(frag GR16:$src1, (shiftMask32 CL)), 1807 (!cast<Instruction>(NAME # "16rCL_ND") GR16:$src1)>; 1808 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1809 (!cast<Instruction>(NAME # "32rCL_ND") GR32:$src1)>; 1810 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1811 (!cast<Instruction>(NAME # "64rCL_ND") GR64:$src1)>; 1812 } 1813 1814 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask32 CL)), addr:$dst), 1815 (!cast<Instruction>(NAME # "8mCL") addr:$dst)>; 1816 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask32 CL)), addr:$dst), 1817 (!cast<Instruction>(NAME # "16mCL") addr:$dst)>; 1818 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1819 (!cast<Instruction>(NAME # "32mCL") addr:$dst)>; 1820 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1821 (!cast<Instruction>(NAME # "64mCL") addr:$dst)>; 1822 1823 let Predicates = [HasNDD] in { 1824 def : Pat<(frag (loadi8 addr:$src), (shiftMask32 CL)), 1825 (!cast<Instruction>(NAME # "8mCL_ND") addr:$src)>; 1826 def : Pat<(frag (loadi16 addr:$src), (shiftMask32 CL)), 1827 (!cast<Instruction>(NAME # "16mCL_ND") addr:$src)>; 1828 def : Pat<(frag (loadi32 addr:$src), (shiftMask32 CL)), 1829 (!cast<Instruction>(NAME # "32mCL_ND") addr:$src)>; 1830 def : Pat<(frag (loadi64 addr:$src), (shiftMask64 CL)), 1831 (!cast<Instruction>(NAME # "64mCL_ND") addr:$src)>; 1832 } 1833} 1834 1835defm SHL : MaskedShiftAmountPats<shl>; 1836defm SHR : MaskedShiftAmountPats<srl>; 1837defm SAR : MaskedShiftAmountPats<sra>; 1838 1839// ROL/ROR instructions allow a stronger mask optimization than shift for 8- and 1840// 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount 1841// because over-rotating produces the same result. This is noted in the Intel 1842// docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation 1843// amount could affect EFLAGS results, but that does not matter because we are 1844// not tracking flags for these nodes. 1845multiclass MaskedRotateAmountPats<SDNode frag> { 1846 // (rot x (and y, BitWidth - 1)) ==> (rot x, y) 1847 let Predicates = [NoNDD] in { 1848 def : Pat<(frag GR8:$src1, (shiftMask8 CL)), 1849 (!cast<Instruction>(NAME # "8rCL") GR8:$src1)>; 1850 def : Pat<(frag GR16:$src1, (shiftMask16 CL)), 1851 (!cast<Instruction>(NAME # "16rCL") GR16:$src1)>; 1852 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1853 (!cast<Instruction>(NAME # "32rCL") GR32:$src1)>; 1854 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1855 (!cast<Instruction>(NAME # "64rCL") GR64:$src1)>; 1856 } 1857 let Predicates = [HasNDD] in { 1858 def : Pat<(frag GR8:$src1, (shiftMask8 CL)), 1859 (!cast<Instruction>(NAME # "8rCL_ND") GR8:$src1)>; 1860 def : Pat<(frag GR16:$src1, (shiftMask16 CL)), 1861 (!cast<Instruction>(NAME # "16rCL_ND") GR16:$src1)>; 1862 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1863 (!cast<Instruction>(NAME # "32rCL_ND") GR32:$src1)>; 1864 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1865 (!cast<Instruction>(NAME # "64rCL_ND") GR64:$src1)>; 1866 } 1867 1868 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask8 CL)), addr:$dst), 1869 (!cast<Instruction>(NAME # "8mCL") addr:$dst)>; 1870 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask16 CL)), addr:$dst), 1871 (!cast<Instruction>(NAME # "16mCL") addr:$dst)>; 1872 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1873 (!cast<Instruction>(NAME # "32mCL") addr:$dst)>; 1874 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1875 (!cast<Instruction>(NAME # "64mCL") addr:$dst)>; 1876 1877 let Predicates = [HasNDD] in { 1878 def : Pat<(frag (loadi8 addr:$src), (shiftMask8 CL)), 1879 (!cast<Instruction>(NAME # "8mCL_ND") addr:$src)>; 1880 def : Pat<(frag (loadi16 addr:$src), (shiftMask16 CL)), 1881 (!cast<Instruction>(NAME # "16mCL_ND") addr:$src)>; 1882 def : Pat<(frag (loadi32 addr:$src), (shiftMask32 CL)), 1883 (!cast<Instruction>(NAME # "32mCL_ND") addr:$src)>; 1884 def : Pat<(frag (loadi64 addr:$src), (shiftMask64 CL)), 1885 (!cast<Instruction>(NAME # "64mCL_ND") addr:$src)>; 1886 } 1887} 1888 1889defm ROL : MaskedRotateAmountPats<rotl>; 1890defm ROR : MaskedRotateAmountPats<rotr>; 1891 1892multiclass MaskedShlrdAmountPats<string suffix, Predicate p> { 1893 let Predicates = [p] in { 1894 // Double "funnel" shift amount is implicitly masked. 1895 // (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) (NOTE: modulo32) 1896 def : Pat<(X86fshl GR16:$src1, GR16:$src2, (shiftMask32 CL)), 1897 (!cast<Instruction>(SHLD16rrCL#suffix) GR16:$src1, GR16:$src2)>; 1898 def : Pat<(X86fshr GR16:$src2, GR16:$src1, (shiftMask32 CL)), 1899 (!cast<Instruction>(SHRD16rrCL#suffix) GR16:$src1, GR16:$src2)>; 1900 1901 // (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) 1902 def : Pat<(fshl GR32:$src1, GR32:$src2, (shiftMask32 CL)), 1903 (!cast<Instruction>(SHLD32rrCL#suffix) GR32:$src1, GR32:$src2)>; 1904 def : Pat<(fshr GR32:$src2, GR32:$src1, (shiftMask32 CL)), 1905 (!cast<Instruction>(SHRD32rrCL#suffix) GR32:$src1, GR32:$src2)>; 1906 1907 // (fshl/fshr x (and y, 63)) ==> (fshl/fshr x, y) 1908 def : Pat<(fshl GR64:$src1, GR64:$src2, (shiftMask64 CL)), 1909 (!cast<Instruction>(SHLD64rrCL#suffix) GR64:$src1, GR64:$src2)>; 1910 def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)), 1911 (!cast<Instruction>(SHRD64rrCL#suffix) GR64:$src1, GR64:$src2)>; 1912 } 1913} 1914 1915defm : MaskedShlrdAmountPats<"", NoNDD>; 1916defm : MaskedShlrdAmountPats<"_ND", HasNDD>; 1917 1918// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location. 1919multiclass OneBitPats<RegisterClass rc, ValueType vt, Instruction btr, 1920 Instruction bts, Instruction btc, PatFrag mask> { 1921 def : Pat<(and rc:$src1, (rotl -2, GR8:$src2)), 1922 (btr rc:$src1, 1923 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1924 def : Pat<(or rc:$src1, (shl 1, GR8:$src2)), 1925 (bts rc:$src1, 1926 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1927 def : Pat<(xor rc:$src1, (shl 1, GR8:$src2)), 1928 (btc rc:$src1, 1929 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1930 1931 // Similar to above, but removing unneeded masking of the shift amount. 1932 def : Pat<(and rc:$src1, (rotl -2, (mask GR8:$src2))), 1933 (btr rc:$src1, 1934 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1935 def : Pat<(or rc:$src1, (shl 1, (mask GR8:$src2))), 1936 (bts rc:$src1, 1937 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1938 def : Pat<(xor rc:$src1, (shl 1, (mask GR8:$src2))), 1939 (btc rc:$src1, 1940 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1941} 1942 1943defm : OneBitPats<GR16, i16, BTR16rr, BTS16rr, BTC16rr, shiftMask16>; 1944defm : OneBitPats<GR32, i32, BTR32rr, BTS32rr, BTC32rr, shiftMask32>; 1945defm : OneBitPats<GR64, i64, BTR64rr, BTS64rr, BTC64rr, shiftMask64>; 1946 1947//===----------------------------------------------------------------------===// 1948// EFLAGS-defining Patterns 1949//===----------------------------------------------------------------------===// 1950 1951multiclass EFLAGSDefiningPats<string suffix, Predicate p> { 1952 let Predicates = [p] in { 1953 // add reg, reg 1954 def : Pat<(add GR8 :$src1, GR8 :$src2), (!cast<Instruction>(ADD8rr#suffix) GR8 :$src1, GR8 :$src2)>; 1955 def : Pat<(add GR16:$src1, GR16:$src2), (!cast<Instruction>(ADD16rr#suffix) GR16:$src1, GR16:$src2)>; 1956 def : Pat<(add GR32:$src1, GR32:$src2), (!cast<Instruction>(ADD32rr#suffix) GR32:$src1, GR32:$src2)>; 1957 def : Pat<(add GR64:$src1, GR64:$src2), (!cast<Instruction>(ADD64rr#suffix) GR64:$src1, GR64:$src2)>; 1958 1959 // add reg, mem 1960 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1961 (!cast<Instruction>(ADD8rm#suffix) GR8:$src1, addr:$src2)>; 1962 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1963 (!cast<Instruction>(ADD16rm#suffix) GR16:$src1, addr:$src2)>; 1964 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1965 (!cast<Instruction>(ADD32rm#suffix) GR32:$src1, addr:$src2)>; 1966 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1967 (!cast<Instruction>(ADD64rm#suffix) GR64:$src1, addr:$src2)>; 1968 1969 // add reg, imm 1970 def : Pat<(add GR8 :$src1, imm:$src2), (!cast<Instruction>(ADD8ri#suffix) GR8:$src1 , imm:$src2)>; 1971 def : Pat<(add GR16:$src1, imm:$src2), (!cast<Instruction>(ADD16ri#suffix) GR16:$src1, imm:$src2)>; 1972 def : Pat<(add GR32:$src1, imm:$src2), (!cast<Instruction>(ADD32ri#suffix) GR32:$src1, imm:$src2)>; 1973 def : Pat<(add GR64:$src1, i64immSExt32:$src2), (!cast<Instruction>(ADD64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 1974 1975 // sub reg, reg 1976 def : Pat<(sub GR8 :$src1, GR8 :$src2), (!cast<Instruction>(SUB8rr#suffix) GR8 :$src1, GR8 :$src2)>; 1977 def : Pat<(sub GR16:$src1, GR16:$src2), (!cast<Instruction>(SUB16rr#suffix) GR16:$src1, GR16:$src2)>; 1978 def : Pat<(sub GR32:$src1, GR32:$src2), (!cast<Instruction>(SUB32rr#suffix) GR32:$src1, GR32:$src2)>; 1979 def : Pat<(sub GR64:$src1, GR64:$src2), (!cast<Instruction>(SUB64rr#suffix) GR64:$src1, GR64:$src2)>; 1980 1981 // sub reg, mem 1982 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1983 (!cast<Instruction>(SUB8rm#suffix) GR8:$src1, addr:$src2)>; 1984 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1985 (!cast<Instruction>(SUB16rm#suffix) GR16:$src1, addr:$src2)>; 1986 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1987 (!cast<Instruction>(SUB32rm#suffix) GR32:$src1, addr:$src2)>; 1988 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1989 (!cast<Instruction>(SUB64rm#suffix) GR64:$src1, addr:$src2)>; 1990 1991 // sub reg, imm 1992 def : Pat<(sub GR8:$src1, imm:$src2), 1993 (!cast<Instruction>(SUB8ri#suffix) GR8:$src1, imm:$src2)>; 1994 def : Pat<(sub GR16:$src1, imm:$src2), 1995 (!cast<Instruction>(SUB16ri#suffix) GR16:$src1, imm:$src2)>; 1996 def : Pat<(sub GR32:$src1, imm:$src2), 1997 (!cast<Instruction>(SUB32ri#suffix) GR32:$src1, imm:$src2)>; 1998 def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 1999 (!cast<Instruction>(SUB64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2000 2001 // sub 0, reg 2002 def : Pat<(X86sub_flag 0, GR8 :$src), (!cast<Instruction>(NEG8r#suffix) GR8 :$src)>; 2003 def : Pat<(X86sub_flag 0, GR16:$src), (!cast<Instruction>(NEG16r#suffix) GR16:$src)>; 2004 def : Pat<(X86sub_flag 0, GR32:$src), (!cast<Instruction>(NEG32r#suffix) GR32:$src)>; 2005 def : Pat<(X86sub_flag 0, GR64:$src), (!cast<Instruction>(NEG64r#suffix) GR64:$src)>; 2006 2007 // mul reg, reg 2008 def : Pat<(mul GR16:$src1, GR16:$src2), 2009 (!cast<Instruction>(IMUL16rr#suffix) GR16:$src1, GR16:$src2)>; 2010 def : Pat<(mul GR32:$src1, GR32:$src2), 2011 (!cast<Instruction>(IMUL32rr#suffix) GR32:$src1, GR32:$src2)>; 2012 def : Pat<(mul GR64:$src1, GR64:$src2), 2013 (!cast<Instruction>(IMUL64rr#suffix) GR64:$src1, GR64:$src2)>; 2014 2015 // mul reg, mem 2016 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 2017 (!cast<Instruction>(IMUL16rm#suffix) GR16:$src1, addr:$src2)>; 2018 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 2019 (!cast<Instruction>(IMUL32rm#suffix) GR32:$src1, addr:$src2)>; 2020 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 2021 (!cast<Instruction>(IMUL64rm#suffix) GR64:$src1, addr:$src2)>; 2022 2023 // or reg/reg. 2024 def : Pat<(or GR8 :$src1, GR8 :$src2), (!cast<Instruction>(OR8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2025 def : Pat<(or GR16:$src1, GR16:$src2), (!cast<Instruction>(OR16rr#suffix) GR16:$src1, GR16:$src2)>; 2026 def : Pat<(or GR32:$src1, GR32:$src2), (!cast<Instruction>(OR32rr#suffix) GR32:$src1, GR32:$src2)>; 2027 def : Pat<(or GR64:$src1, GR64:$src2), (!cast<Instruction>(OR64rr#suffix) GR64:$src1, GR64:$src2)>; 2028 2029 // or reg/mem 2030 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 2031 (!cast<Instruction>(OR8rm#suffix) GR8:$src1, addr:$src2)>; 2032 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 2033 (!cast<Instruction>(OR16rm#suffix) GR16:$src1, addr:$src2)>; 2034 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 2035 (!cast<Instruction>(OR32rm#suffix) GR32:$src1, addr:$src2)>; 2036 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 2037 (!cast<Instruction>(OR64rm#suffix) GR64:$src1, addr:$src2)>; 2038 2039 // or reg/imm 2040 def : Pat<(or GR8:$src1 , imm:$src2), (!cast<Instruction>(OR8ri#suffix) GR8 :$src1, imm:$src2)>; 2041 def : Pat<(or GR16:$src1, imm:$src2), (!cast<Instruction>(OR16ri#suffix) GR16:$src1, imm:$src2)>; 2042 def : Pat<(or GR32:$src1, imm:$src2), (!cast<Instruction>(OR32ri#suffix) GR32:$src1, imm:$src2)>; 2043 def : Pat<(or GR64:$src1, i64immSExt32:$src2), 2044 (!cast<Instruction>(OR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2045 2046 // xor reg/reg 2047 def : Pat<(xor GR8 :$src1, GR8 :$src2), (!cast<Instruction>(XOR8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2048 def : Pat<(xor GR16:$src1, GR16:$src2), (!cast<Instruction>(XOR16rr#suffix) GR16:$src1, GR16:$src2)>; 2049 def : Pat<(xor GR32:$src1, GR32:$src2), (!cast<Instruction>(XOR32rr#suffix) GR32:$src1, GR32:$src2)>; 2050 def : Pat<(xor GR64:$src1, GR64:$src2), (!cast<Instruction>(XOR64rr#suffix) GR64:$src1, GR64:$src2)>; 2051 2052 // xor reg/mem 2053 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 2054 (!cast<Instruction>(XOR8rm#suffix) GR8:$src1, addr:$src2)>; 2055 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 2056 (!cast<Instruction>(XOR16rm#suffix) GR16:$src1, addr:$src2)>; 2057 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 2058 (!cast<Instruction>(XOR32rm#suffix) GR32:$src1, addr:$src2)>; 2059 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 2060 (!cast<Instruction>(XOR64rm#suffix) GR64:$src1, addr:$src2)>; 2061 2062 // xor reg/imm 2063 def : Pat<(xor GR8:$src1, imm:$src2), 2064 (!cast<Instruction>(XOR8ri#suffix) GR8:$src1, imm:$src2)>; 2065 def : Pat<(xor GR16:$src1, imm:$src2), 2066 (!cast<Instruction>(XOR16ri#suffix) GR16:$src1, imm:$src2)>; 2067 def : Pat<(xor GR32:$src1, imm:$src2), 2068 (!cast<Instruction>(XOR32ri#suffix) GR32:$src1, imm:$src2)>; 2069 def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 2070 (!cast<Instruction>(XOR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2071 2072 // and reg/reg 2073 def : Pat<(and GR8 :$src1, GR8 :$src2), (!cast<Instruction>(AND8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2074 def : Pat<(and GR16:$src1, GR16:$src2), (!cast<Instruction>(AND16rr#suffix) GR16:$src1, GR16:$src2)>; 2075 def : Pat<(and GR32:$src1, GR32:$src2), (!cast<Instruction>(AND32rr#suffix) GR32:$src1, GR32:$src2)>; 2076 def : Pat<(and GR64:$src1, GR64:$src2), (!cast<Instruction>(AND64rr#suffix) GR64:$src1, GR64:$src2)>; 2077 2078 // and reg/mem 2079 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 2080 (!cast<Instruction>(AND8rm#suffix) GR8:$src1, addr:$src2)>; 2081 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 2082 (!cast<Instruction>(AND16rm#suffix) GR16:$src1, addr:$src2)>; 2083 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 2084 (!cast<Instruction>(AND32rm#suffix) GR32:$src1, addr:$src2)>; 2085 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 2086 (!cast<Instruction>(AND64rm#suffix) GR64:$src1, addr:$src2)>; 2087 2088 // and reg/imm 2089 def : Pat<(and GR8:$src1, imm:$src2), 2090 (!cast<Instruction>(AND8ri#suffix) GR8:$src1, imm:$src2)>; 2091 def : Pat<(and GR16:$src1, imm:$src2), 2092 (!cast<Instruction>(AND16ri#suffix) GR16:$src1, imm:$src2)>; 2093 def : Pat<(and GR32:$src1, imm:$src2), 2094 (!cast<Instruction>(AND32ri#suffix) GR32:$src1, imm:$src2)>; 2095 def : Pat<(and GR64:$src1, i64immSExt32:$src2), 2096 (!cast<Instruction>(AND64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2097 } 2098 2099 // Increment/Decrement reg. 2100 // Do not make INC/DEC if it is slow 2101 let Predicates = [UseIncDec, p] in { 2102 def : Pat<(add GR8:$src, 1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>; 2103 def : Pat<(add GR16:$src, 1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>; 2104 def : Pat<(add GR32:$src, 1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>; 2105 def : Pat<(add GR64:$src, 1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>; 2106 def : Pat<(add GR8:$src, -1), (!cast<Instruction>(DEC8r#suffix) GR8:$src)>; 2107 def : Pat<(add GR16:$src, -1), (!cast<Instruction>(DEC16r#suffix) GR16:$src)>; 2108 def : Pat<(add GR32:$src, -1), (!cast<Instruction>(DEC32r#suffix) GR32:$src)>; 2109 def : Pat<(add GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>; 2110 2111 def : Pat<(X86add_flag_nocf GR8:$src, -1), (!cast<Instruction>(DEC8r#suffix) GR8:$src)>; 2112 def : Pat<(X86add_flag_nocf GR16:$src, -1), (!cast<Instruction>(DEC16r#suffix) GR16:$src)>; 2113 def : Pat<(X86add_flag_nocf GR32:$src, -1), (!cast<Instruction>(DEC32r#suffix) GR32:$src)>; 2114 def : Pat<(X86add_flag_nocf GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>; 2115 def : Pat<(X86sub_flag_nocf GR8:$src, -1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>; 2116 def : Pat<(X86sub_flag_nocf GR16:$src, -1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>; 2117 def : Pat<(X86sub_flag_nocf GR32:$src, -1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>; 2118 def : Pat<(X86sub_flag_nocf GR64:$src, -1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>; 2119 } 2120} 2121 2122defm : EFLAGSDefiningPats<"", NoNDD>; 2123defm : EFLAGSDefiningPats<"_ND", HasNDD>; 2124 2125// mul reg, imm 2126def : Pat<(mul GR16:$src1, imm:$src2), 2127 (IMUL16rri GR16:$src1, imm:$src2)>; 2128def : Pat<(mul GR32:$src1, imm:$src2), 2129 (IMUL32rri GR32:$src1, imm:$src2)>; 2130def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 2131 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 2132 2133// reg = mul mem, imm 2134def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 2135 (IMUL16rmi addr:$src1, imm:$src2)>; 2136def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 2137 (IMUL32rmi addr:$src1, imm:$src2)>; 2138def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 2139 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 2140 2141// Bit scan instruction patterns to match explicit zero-undef behavior. 2142def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 2143def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 2144def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 2145def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 2146def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 2147def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 2148 2149// When HasMOVBE is enabled it is possible to get a non-legalized 2150// register-register 16 bit bswap. This maps it to a ROL instruction. 2151let Predicates = [HasMOVBE] in { 2152 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; 2153} 2154