1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the various pseudo instructions used by the compiler, 10// as well as Pat patterns used during instruction selection. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Pattern Matching Support 16 17def GetLo32XForm : SDNodeXForm<imm, [{ 18 // Transformation function: get the low 32 bits. 19 return getI32Imm((uint32_t)N->getZExtValue(), SDLoc(N)); 20}]>; 21 22 23//===----------------------------------------------------------------------===// 24// Random Pseudo Instructions. 25 26// PIC base construction. This expands to code that looks like this: 27// call $next_inst 28// popl %destreg" 29let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP], 30 SchedRW = [WriteJump] in 31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 32 "", []>; 33 34// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 35// a stack adjustment and the codegen must know that they may modify the stack 36// pointer before prolog-epilog rewriting occurs. 37// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 38// sub / add which can clobber EFLAGS. 39let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in { 40def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), 41 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 42 "#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>; 43def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 44 "#ADJCALLSTACKUP", 45 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 46 Requires<[NotLP64]>; 47} 48def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 49 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>; 50 51 52// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 53// a stack adjustment and the codegen must know that they may modify the stack 54// pointer before prolog-epilog rewriting occurs. 55// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 56// sub / add which can clobber EFLAGS. 57let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in { 58def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), 59 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 60 "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>; 61def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 62 "#ADJCALLSTACKUP", 63 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 64 Requires<[IsLP64]>; 65} 66def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 67 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>; 68 69let SchedRW = [WriteSystem] in { 70 71// x86-64 va_start lowering magic. 72let hasSideEffects = 1, mayStore = 1, Defs = [EFLAGS] in { 73def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 74 (outs), 75 (ins GR8:$al, i8mem:$regsavefi, variable_ops), 76 "#VASTART_SAVE_XMM_REGS $al, $regsavefi", 77 [(X86vastart_save_xmm_regs GR8:$al, addr:$regsavefi), 78 (implicit EFLAGS)]>; 79} 80 81let usesCustomInserter = 1, Defs = [EFLAGS] in { 82// The VAARG_64 and VAARG_X32 pseudo-instructions take the address of the 83// va_list, and place the address of the next argument into a register. 84let Defs = [EFLAGS] in { 85def VAARG_64 : I<0, Pseudo, 86 (outs GR64:$dst), 87 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 88 "#VAARG_64 $dst, $ap, $size, $mode, $align", 89 [(set GR64:$dst, 90 (X86vaarg64 addr:$ap, timm:$size, timm:$mode, timm:$align)), 91 (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>; 92def VAARG_X32 : I<0, Pseudo, 93 (outs GR32:$dst), 94 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 95 "#VAARG_X32 $dst, $ap, $size, $mode, $align", 96 [(set GR32:$dst, 97 (X86vaargx32 addr:$ap, timm:$size, timm:$mode, timm:$align)), 98 (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>; 99} 100 101// When using segmented stacks these are lowered into instructions which first 102// check if the current stacklet has enough free memory. If it does, memory is 103// allocated by bumping the stack pointer. Otherwise memory is allocated from 104// the heap. 105 106let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 107def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 108 "# variable sized alloca for segmented stacks", 109 [(set GR32:$dst, 110 (X86SegAlloca GR32:$size))]>, 111 Requires<[NotLP64]>; 112 113let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 114def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 115 "# variable sized alloca for segmented stacks", 116 [(set GR64:$dst, 117 (X86SegAlloca GR64:$size))]>, 118 Requires<[In64BitMode]>; 119 120// To protect against stack clash, dynamic allocation should perform a memory 121// probe at each page. 122 123let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 124def PROBED_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 125 "# variable sized alloca with probing", 126 [(set GR32:$dst, 127 (X86ProbedAlloca GR32:$size))]>, 128 Requires<[NotLP64]>; 129 130let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 131def PROBED_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 132 "# variable sized alloca with probing", 133 [(set GR64:$dst, 134 (X86ProbedAlloca GR64:$size))]>, 135 Requires<[In64BitMode]>; 136} 137 138let hasNoSchedulingInfo = 1 in 139def STACKALLOC_W_PROBING : I<0, Pseudo, (outs), (ins i64imm:$stacksize), 140 "# fixed size alloca with probing", 141 []>; 142 143// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 144// targets. These calls are needed to probe the stack when allocating more than 145// 4k bytes in one go. Touching the stack at 4K increments is necessary to 146// ensure that the guard pages used by the OS virtual memory manager are 147// allocated in correct sequence. 148// The main point of having separate instruction are extra unmodelled effects 149// (compared to ordinary calls) like stack pointer change. 150 151let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 152def DYN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size), 153 "# dynamic stack allocation", 154 [(X86DynAlloca GR32:$size)]>, 155 Requires<[NotLP64]>; 156 157let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 158def DYN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size), 159 "# dynamic stack allocation", 160 [(X86DynAlloca GR64:$size)]>, 161 Requires<[In64BitMode]>; 162} // SchedRW 163 164// These instructions XOR the frame pointer into a GPR. They are used in some 165// stack protection schemes. These are post-RA pseudos because we only know the 166// frame register after register allocation. 167let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in { 168 def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src), 169 "xorl\t$$FP, $src", []>, 170 Requires<[NotLP64]>, Sched<[WriteALU]>; 171 def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src), 172 "xorq\t$$FP $src", []>, 173 Requires<[In64BitMode]>, Sched<[WriteALU]>; 174} 175 176//===----------------------------------------------------------------------===// 177// EH Pseudo Instructions 178// 179let SchedRW = [WriteSystem] in { 180let isTerminator = 1, isReturn = 1, isBarrier = 1, 181 hasCtrlDep = 1, isCodeGenOnly = 1 in { 182def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 183 "ret\t#eh_return, addr: $addr", 184 [(X86ehret GR32:$addr)]>, Sched<[WriteJumpLd]>; 185 186} 187 188let isTerminator = 1, isReturn = 1, isBarrier = 1, 189 hasCtrlDep = 1, isCodeGenOnly = 1 in { 190def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 191 "ret\t#eh_return, addr: $addr", 192 [(X86ehret GR64:$addr)]>, Sched<[WriteJumpLd]>; 193 194} 195 196let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 197 isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1 in { 198 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>; 199 200 // CATCHRET needs a custom inserter for SEH. 201 let usesCustomInserter = 1 in 202 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), 203 "# CATCHRET", 204 [(catchret bb:$dst, bb:$from)]>; 205} 206 207let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 208 usesCustomInserter = 1 in { 209 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 210 "#EH_SJLJ_SETJMP32", 211 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 212 Requires<[Not64BitMode]>; 213 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 214 "#EH_SJLJ_SETJMP64", 215 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 216 Requires<[In64BitMode]>; 217 let isTerminator = 1 in { 218 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 219 "#EH_SJLJ_LONGJMP32", 220 [(X86eh_sjlj_longjmp addr:$buf)]>, 221 Requires<[Not64BitMode]>; 222 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 223 "#EH_SJLJ_LONGJMP64", 224 [(X86eh_sjlj_longjmp addr:$buf)]>, 225 Requires<[In64BitMode]>; 226 } 227} 228 229let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 230 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 231 "#EH_SjLj_Setup\t$dst", []>; 232} 233} // SchedRW 234 235//===----------------------------------------------------------------------===// 236// Pseudo instructions used by unwind info. 237// 238let isPseudo = 1, SchedRW = [WriteSystem] in { 239 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), 240 "#SEH_PushReg $reg", []>; 241 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 242 "#SEH_SaveReg $reg, $dst", []>; 243 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 244 "#SEH_SaveXMM $reg, $dst", []>; 245 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), 246 "#SEH_StackAlloc $size", []>; 247 def SEH_StackAlign : I<0, Pseudo, (outs), (ins i32imm:$align), 248 "#SEH_StackAlign $align", []>; 249 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), 250 "#SEH_SetFrame $reg, $offset", []>; 251 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), 252 "#SEH_PushFrame $mode", []>; 253 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), 254 "#SEH_EndPrologue", []>; 255 def SEH_Epilogue : I<0, Pseudo, (outs), (ins), 256 "#SEH_Epilogue", []>; 257} 258 259//===----------------------------------------------------------------------===// 260// Pseudo instructions used by KCFI. 261//===----------------------------------------------------------------------===// 262let 263 Defs = [R10, R11, EFLAGS] in { 264def KCFI_CHECK : PseudoI< 265 (outs), (ins GR64:$ptr, i32imm:$type), []>, Sched<[]>; 266} 267 268//===----------------------------------------------------------------------===// 269// Pseudo instructions used by address sanitizer. 270//===----------------------------------------------------------------------===// 271let 272 Defs = [R10, R11, EFLAGS] in { 273def ASAN_CHECK_MEMACCESS : PseudoI< 274 (outs), (ins GR64PLTSafe:$addr, i32imm:$accessinfo), 275 [(int_asan_check_memaccess GR64PLTSafe:$addr, (i32 timm:$accessinfo))]>, 276 Sched<[]>; 277} 278 279//===----------------------------------------------------------------------===// 280// Pseudo instructions used by segmented stacks. 281// 282 283// This is lowered into a RET instruction by MCInstLower. We need 284// this so that we don't have to have a MachineBasicBlock which ends 285// with a RET and also has successors. 286let isPseudo = 1, SchedRW = [WriteJumpLd] in { 287def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>; 288 289// This instruction is lowered to a RET followed by a MOV. The two 290// instructions are not generated on a higher level since then the 291// verifier sees a MachineBasicBlock ending with a non-terminator. 292def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>; 293} 294 295//===----------------------------------------------------------------------===// 296// Alias Instructions 297//===----------------------------------------------------------------------===// 298 299// Alias instruction mapping movr0 to xor. 300// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 301let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 302 isPseudo = 1, isMoveImm = 1, AddedComplexity = 10 in 303def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 304 [(set GR32:$dst, 0)]>, Sched<[WriteZero]>; 305 306// Other widths can also make use of the 32-bit xor, which may have a smaller 307// encoding and avoid partial register updates. 308let AddedComplexity = 10 in { 309def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 310def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 311def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>; 312} 313 314let Predicates = [OptForSize, Not64BitMode], 315 AddedComplexity = 10 in { 316 let SchedRW = [WriteALU] in { 317 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, 318 // which only require 3 bytes compared to MOV32ri which requires 5. 319 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { 320 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 321 [(set GR32:$dst, 1)]>; 322 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 323 [(set GR32:$dst, -1)]>; 324 } 325 } // SchedRW 326 327 // MOV16ri is 4 bytes, so the instructions above are smaller. 328 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; 329 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; 330} 331 332let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5, 333 SchedRW = [WriteALU] in { 334// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1. 335def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "", 336 [(set GR32:$dst, i32immSExt8:$src)]>, 337 Requires<[OptForMinSize, NotWin64WithoutFP]>; 338def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", 339 [(set GR64:$dst, i64immSExt8:$src)]>, 340 Requires<[OptForMinSize, NotWin64WithoutFP]>; 341} 342 343// Materialize i64 constant where top 32-bits are zero. This could theoretically 344// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 345// that would make it more difficult to rematerialize. 346let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 347 isPseudo = 1, SchedRW = [WriteMove] in 348def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "", 349 [(set GR64:$dst, i64immZExt32:$src)]>; 350 351// This 64-bit pseudo-move can also be used for labels in the x86-64 small code 352// model. 353def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [X86Wrapper]>; 354def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>; 355 356// Use sbb to materialize carry bit. 357let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteADC], 358 hasSideEffects = 0 in { 359// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 360// However, Pat<> can't replicate the destination reg into the inputs of the 361// result. 362def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", []>; 363def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", []>; 364} // isCodeGenOnly 365 366//===----------------------------------------------------------------------===// 367// String Pseudo Instructions 368// 369let SchedRW = [WriteMicrocoded] in { 370let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 371def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), 372 "{rep;movsb (%esi), %es:(%edi)|rep movsb es:[edi], [esi]}", 373 [(X86rep_movs i8)]>, REP, AdSize32, 374 Requires<[NotLP64]>; 375def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), 376 "{rep;movsw (%esi), %es:(%edi)|rep movsw es:[edi], [esi]}", 377 [(X86rep_movs i16)]>, REP, AdSize32, OpSize16, 378 Requires<[NotLP64]>; 379def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), 380 "{rep;movsl (%esi), %es:(%edi)|rep movsd es:[edi], [esi]}", 381 [(X86rep_movs i32)]>, REP, AdSize32, OpSize32, 382 Requires<[NotLP64]>; 383def REP_MOVSQ_32 : RI<0xA5, RawFrm, (outs), (ins), 384 "{rep;movsq (%esi), %es:(%edi)|rep movsq es:[edi], [esi]}", 385 [(X86rep_movs i64)]>, REP, AdSize32, 386 Requires<[NotLP64, In64BitMode]>; 387} 388 389let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 390def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), 391 "{rep;movsb (%rsi), %es:(%rdi)|rep movsb es:[rdi], [rsi]}", 392 [(X86rep_movs i8)]>, REP, AdSize64, 393 Requires<[IsLP64]>; 394def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), 395 "{rep;movsw (%rsi), %es:(%rdi)|rep movsw es:[rdi], [rsi]}", 396 [(X86rep_movs i16)]>, REP, AdSize64, OpSize16, 397 Requires<[IsLP64]>; 398def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), 399 "{rep;movsl (%rsi), %es:(%rdi)|rep movsdi es:[rdi], [rsi]}", 400 [(X86rep_movs i32)]>, REP, AdSize64, OpSize32, 401 Requires<[IsLP64]>; 402def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), 403 "{rep;movsq (%rsi), %es:(%rdi)|rep movsq es:[rdi], [rsi]}", 404 [(X86rep_movs i64)]>, REP, AdSize64, 405 Requires<[IsLP64]>; 406} 407 408// FIXME: Should use "(X86rep_stos AL)" as the pattern. 409let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 410 let Uses = [AL,ECX,EDI] in 411 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), 412 "{rep;stosb %al, %es:(%edi)|rep stosb es:[edi], al}", 413 [(X86rep_stos i8)]>, REP, AdSize32, 414 Requires<[NotLP64]>; 415 let Uses = [AX,ECX,EDI] in 416 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), 417 "{rep;stosw %ax, %es:(%edi)|rep stosw es:[edi], ax}", 418 [(X86rep_stos i16)]>, REP, AdSize32, OpSize16, 419 Requires<[NotLP64]>; 420 let Uses = [EAX,ECX,EDI] in 421 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), 422 "{rep;stosl %eax, %es:(%edi)|rep stosd es:[edi], eax}", 423 [(X86rep_stos i32)]>, REP, AdSize32, OpSize32, 424 Requires<[NotLP64]>; 425 let Uses = [RAX,RCX,RDI] in 426 def REP_STOSQ_32 : RI<0xAB, RawFrm, (outs), (ins), 427 "{rep;stosq %rax, %es:(%edi)|rep stosq es:[edi], rax}", 428 [(X86rep_stos i64)]>, REP, AdSize32, 429 Requires<[NotLP64, In64BitMode]>; 430} 431 432let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 433 let Uses = [AL,RCX,RDI] in 434 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), 435 "{rep;stosb %al, %es:(%rdi)|rep stosb es:[rdi], al}", 436 [(X86rep_stos i8)]>, REP, AdSize64, 437 Requires<[IsLP64]>; 438 let Uses = [AX,RCX,RDI] in 439 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), 440 "{rep;stosw %ax, %es:(%rdi)|rep stosw es:[rdi], ax}", 441 [(X86rep_stos i16)]>, REP, AdSize64, OpSize16, 442 Requires<[IsLP64]>; 443 let Uses = [RAX,RCX,RDI] in 444 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), 445 "{rep;stosl %eax, %es:(%rdi)|rep stosd es:[rdi], eax}", 446 [(X86rep_stos i32)]>, REP, AdSize64, OpSize32, 447 Requires<[IsLP64]>; 448 449 let Uses = [RAX,RCX,RDI] in 450 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), 451 "{rep;stosq %rax, %es:(%rdi)|rep stosq es:[rdi], rax}", 452 [(X86rep_stos i64)]>, REP, AdSize64, 453 Requires<[IsLP64]>; 454} 455} // SchedRW 456 457//===----------------------------------------------------------------------===// 458// Thread Local Storage Instructions 459// 460let SchedRW = [WriteSystem] in { 461 462// ELF TLS Support 463// All calls clobber the non-callee saved registers. ESP is marked as 464// a use to prevent stack-pointer assignments that appear immediately 465// before calls from potentially appearing dead. 466let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 467 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 468 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 469 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 470 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 471 usesCustomInserter = 1, Uses = [ESP, SSP] in { 472def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 473 "# TLS_addr32", 474 [(X86tlsaddr tls32addr:$sym)]>, 475 Requires<[Not64BitMode]>; 476def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 477 "# TLS_base_addr32", 478 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 479 Requires<[Not64BitMode]>; 480} 481 482// All calls clobber the non-callee saved registers. RSP is marked as 483// a use to prevent stack-pointer assignments that appear immediately 484// before calls from potentially appearing dead. 485let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 486 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 487 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 488 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 489 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 490 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 491 usesCustomInserter = 1, Uses = [RSP, SSP] in { 492def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 493 "# TLS_addr64", 494 [(X86tlsaddr tls64addr:$sym)]>, 495 Requires<[In64BitMode, IsLP64]>; 496def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 497 "# TLS_base_addr64", 498 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 499 Requires<[In64BitMode, IsLP64]>; 500def TLS_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 501 "# TLS_addrX32", 502 [(X86tlsaddr tls32addr:$sym)]>, 503 Requires<[In64BitMode, NotLP64]>; 504def TLS_base_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 505 "# TLS_base_addrX32", 506 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 507 Requires<[In64BitMode, NotLP64]>; 508} 509 510// Darwin TLS Support 511// For i386, the address of the thunk is passed on the stack, on return the 512// address of the variable is in %eax. %ecx is trashed during the function 513// call. All other registers are preserved. 514let Defs = [EAX, ECX, EFLAGS, DF], 515 Uses = [ESP, SSP], 516 usesCustomInserter = 1 in 517def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 518 "# TLSCall_32", 519 [(X86TLSCall addr:$sym)]>, 520 Requires<[Not64BitMode]>; 521 522// For x86_64, the address of the thunk is passed in %rdi, but the 523// pseudo directly use the symbol, so do not add an implicit use of 524// %rdi. The lowering will do the right thing with RDI. 525// On return the address of the variable is in %rax. All other 526// registers are preserved. 527let Defs = [RAX, EFLAGS, DF], 528 Uses = [RSP, SSP], 529 usesCustomInserter = 1 in 530def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 531 "# TLSCall_64", 532 [(X86TLSCall addr:$sym)]>, 533 Requires<[In64BitMode]>; 534} // SchedRW 535 536//===----------------------------------------------------------------------===// 537// Conditional Move Pseudo Instructions 538 539// CMOV* - Used to implement the SELECT DAG operation. Expanded after 540// instruction selection into a branch sequence. 541multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> { 542 def CMOV#NAME : I<0, Pseudo, 543 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), 544 "#CMOV_"#NAME#" PSEUDO!", 545 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, timm:$cond, 546 EFLAGS)))]>; 547} 548 549let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in { 550 // X86 doesn't have 8-bit conditional moves. Use a customInserter to 551 // emit control flow. An alternative to this is to mark i8 SELECT as Promote, 552 // however that requires promoting the operands, and can induce additional 553 // i8 register pressure. 554 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>; 555 556 let Predicates = [NoCMOV] in { 557 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>; 558 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>; 559 } // Predicates = [NoCMOV] 560 561 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 562 // SSE1/SSE2. 563 let Predicates = [FPStackf32] in 564 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>; 565 566 let Predicates = [FPStackf64] in 567 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>; 568 569 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>; 570 571 let Predicates = [HasMMX] in 572 defm _VR64 : CMOVrr_PSEUDO<VR64, x86mmx>; 573 574 let Predicates = [HasSSE1,NoAVX512] in 575 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 576 let Predicates = [HasSSE2,NoAVX512] in { 577 defm _FR16 : CMOVrr_PSEUDO<FR16, f16>; 578 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>; 579 } 580 let Predicates = [HasAVX512] in { 581 defm _FR16X : CMOVrr_PSEUDO<FR16X, f16>; 582 defm _FR32X : CMOVrr_PSEUDO<FR32X, f32>; 583 defm _FR64X : CMOVrr_PSEUDO<FR64X, f64>; 584 } 585 let Predicates = [NoVLX] in { 586 defm _VR128 : CMOVrr_PSEUDO<VR128, v2i64>; 587 defm _VR256 : CMOVrr_PSEUDO<VR256, v4i64>; 588 } 589 let Predicates = [HasVLX] in { 590 defm _VR128X : CMOVrr_PSEUDO<VR128X, v2i64>; 591 defm _VR256X : CMOVrr_PSEUDO<VR256X, v4i64>; 592 } 593 defm _VR512 : CMOVrr_PSEUDO<VR512, v8i64>; 594 defm _VK1 : CMOVrr_PSEUDO<VK1, v1i1>; 595 defm _VK2 : CMOVrr_PSEUDO<VK2, v2i1>; 596 defm _VK4 : CMOVrr_PSEUDO<VK4, v4i1>; 597 defm _VK8 : CMOVrr_PSEUDO<VK8, v8i1>; 598 defm _VK16 : CMOVrr_PSEUDO<VK16, v16i1>; 599 defm _VK32 : CMOVrr_PSEUDO<VK32, v32i1>; 600 defm _VK64 : CMOVrr_PSEUDO<VK64, v64i1>; 601} // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] 602 603def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 604 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 605 606let Predicates = [NoVLX] in { 607 def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 608 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 609 def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 610 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 611 def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 612 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 613 def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 614 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 615 def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 616 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 617 618 def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 619 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 620 def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 621 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 622 def : Pat<(v8i32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 623 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 624 def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 625 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 626 def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 627 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 628} 629let Predicates = [HasVLX] in { 630 def : Pat<(v16i8 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 631 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 632 def : Pat<(v8i16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 633 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 634 def : Pat<(v8f16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 635 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 636 def : Pat<(v4i32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 637 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 638 def : Pat<(v4f32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 639 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 640 def : Pat<(v2f64 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 641 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 642 643 def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 644 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 645 def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 646 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 647 def : Pat<(v16f16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 648 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 649 def : Pat<(v8i32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 650 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 651 def : Pat<(v8f32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 652 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 653 def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 654 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 655} 656 657def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 658 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 659def : Pat<(v32i16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 660 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 661def : Pat<(v32f16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 662 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 663def : Pat<(v16i32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 664 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 665def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 666 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 667def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 668 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 669 670//===----------------------------------------------------------------------===// 671// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 672//===----------------------------------------------------------------------===// 673 674// FIXME: Use normal instructions and add lock prefix dynamically. 675 676// Memory barriers 677 678let isCodeGenOnly = 1, Defs = [EFLAGS] in 679def OR32mi8Locked : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$zero), 680 "or{l}\t{$zero, $dst|$dst, $zero}", []>, 681 Requires<[Not64BitMode]>, OpSize32, LOCK, 682 Sched<[WriteALURMW]>; 683 684// RegOpc corresponds to the mr version of the instruction 685// ImmOpc corresponds to the mi version of the instruction 686// ImmOpc8 corresponds to the mi8 version of the instruction 687// ImmMod corresponds to the instruction format of the mi and mi8 versions 688multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 689 Format ImmMod, SDNode Op, string mnemonic> { 690let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 691 SchedRW = [WriteALURMW] in { 692 693def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 694 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 695 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 696 !strconcat(mnemonic, "{b}\t", 697 "{$src2, $dst|$dst, $src2}"), 698 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK; 699 700def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 701 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 702 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 703 !strconcat(mnemonic, "{w}\t", 704 "{$src2, $dst|$dst, $src2}"), 705 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>, 706 OpSize16, LOCK; 707 708def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 709 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 710 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 711 !strconcat(mnemonic, "{l}\t", 712 "{$src2, $dst|$dst, $src2}"), 713 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>, 714 OpSize32, LOCK; 715 716def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 717 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 718 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 719 !strconcat(mnemonic, "{q}\t", 720 "{$src2, $dst|$dst, $src2}"), 721 [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK; 722 723// NOTE: These are order specific, we want the mi8 forms to be listed 724// first so that they are slightly preferred to the mi forms. 725def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 726 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 727 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 728 !strconcat(mnemonic, "{w}\t", 729 "{$src2, $dst|$dst, $src2}"), 730 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>, 731 OpSize16, LOCK; 732 733def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 734 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 735 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 736 !strconcat(mnemonic, "{l}\t", 737 "{$src2, $dst|$dst, $src2}"), 738 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>, 739 OpSize32, LOCK; 740 741def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 742 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 743 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 744 !strconcat(mnemonic, "{q}\t", 745 "{$src2, $dst|$dst, $src2}"), 746 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>, 747 LOCK; 748 749def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 750 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 751 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 752 !strconcat(mnemonic, "{b}\t", 753 "{$src2, $dst|$dst, $src2}"), 754 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK; 755 756def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 757 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 758 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 759 !strconcat(mnemonic, "{w}\t", 760 "{$src2, $dst|$dst, $src2}"), 761 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>, 762 OpSize16, LOCK; 763 764def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 765 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 766 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 767 !strconcat(mnemonic, "{l}\t", 768 "{$src2, $dst|$dst, $src2}"), 769 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>, 770 OpSize32, LOCK; 771 772def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 773 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 774 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 775 !strconcat(mnemonic, "{q}\t", 776 "{$src2, $dst|$dst, $src2}"), 777 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>, 778 LOCK; 779} 780 781} 782 783defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">; 784defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">; 785defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">; 786defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; 787defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; 788 789def X86lock_add_nocf : PatFrag<(ops node:$lhs, node:$rhs), 790 (X86lock_add node:$lhs, node:$rhs), [{ 791 return hasNoCarryFlagUses(SDValue(N, 0)); 792}]>; 793 794def X86lock_sub_nocf : PatFrag<(ops node:$lhs, node:$rhs), 795 (X86lock_sub node:$lhs, node:$rhs), [{ 796 return hasNoCarryFlagUses(SDValue(N, 0)); 797}]>; 798 799let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 800 SchedRW = [WriteALURMW] in { 801 let Predicates = [UseIncDec] in { 802 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), 803 "inc{b}\t$dst", 804 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i8 1)))]>, 805 LOCK; 806 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), 807 "inc{w}\t$dst", 808 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i16 1)))]>, 809 OpSize16, LOCK; 810 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), 811 "inc{l}\t$dst", 812 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i32 1)))]>, 813 OpSize32, LOCK; 814 815 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), 816 "dec{b}\t$dst", 817 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i8 1)))]>, 818 LOCK; 819 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), 820 "dec{w}\t$dst", 821 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i16 1)))]>, 822 OpSize16, LOCK; 823 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), 824 "dec{l}\t$dst", 825 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i32 1)))]>, 826 OpSize32, LOCK; 827 } 828 829 let Predicates = [UseIncDec, In64BitMode] in { 830 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), 831 "inc{q}\t$dst", 832 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i64 1)))]>, 833 LOCK; 834 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), 835 "dec{q}\t$dst", 836 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i64 1)))]>, 837 LOCK; 838 } 839} 840 841let Predicates = [UseIncDec] in { 842 // Additional patterns for -1 constant. 843 def : Pat<(X86lock_add addr:$dst, (i8 -1)), (LOCK_DEC8m addr:$dst)>; 844 def : Pat<(X86lock_add addr:$dst, (i16 -1)), (LOCK_DEC16m addr:$dst)>; 845 def : Pat<(X86lock_add addr:$dst, (i32 -1)), (LOCK_DEC32m addr:$dst)>; 846 def : Pat<(X86lock_sub addr:$dst, (i8 -1)), (LOCK_INC8m addr:$dst)>; 847 def : Pat<(X86lock_sub addr:$dst, (i16 -1)), (LOCK_INC16m addr:$dst)>; 848 def : Pat<(X86lock_sub addr:$dst, (i32 -1)), (LOCK_INC32m addr:$dst)>; 849} 850 851let Predicates = [UseIncDec, In64BitMode] in { 852 // Additional patterns for -1 constant. 853 def : Pat<(X86lock_add addr:$dst, (i64 -1)), (LOCK_DEC64m addr:$dst)>; 854 def : Pat<(X86lock_sub addr:$dst, (i64 -1)), (LOCK_INC64m addr:$dst)>; 855} 856 857// Atomic bit test. 858def X86LBTest : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisPtrTy<1>, 859 SDTCisVT<2, i8>, SDTCisVT<3, i32>]>; 860def x86bts : SDNode<"X86ISD::LBTS", X86LBTest, 861 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 862def x86btc : SDNode<"X86ISD::LBTC", X86LBTest, 863 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 864def x86btr : SDNode<"X86ISD::LBTR", X86LBTest, 865 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 866 867def X86LBTestRM : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>, 868 SDTCisInt<2>]>; 869 870def x86_rm_bts : SDNode<"X86ISD::LBTS_RM", X86LBTestRM, 871 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 872def x86_rm_btc : SDNode<"X86ISD::LBTC_RM", X86LBTestRM, 873 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 874def x86_rm_btr : SDNode<"X86ISD::LBTR_RM", X86LBTestRM, 875 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 876 877 878multiclass ATOMIC_LOGIC_OP<Format Form, string s> { 879 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 880 SchedRW = [WriteBitTestSetRegRMW] in { 881 def 16m : Ii8<0xBA, Form, (outs), (ins i16mem:$src1, i8imm:$src2), 882 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"), 883 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 16)))]>, 884 OpSize16, TB, LOCK; 885 def 32m : Ii8<0xBA, Form, (outs), (ins i32mem:$src1, i8imm:$src2), 886 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"), 887 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 32)))]>, 888 OpSize32, TB, LOCK; 889 def 64m : RIi8<0xBA, Form, (outs), (ins i64mem:$src1, i8imm:$src2), 890 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"), 891 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 64)))]>, 892 TB, LOCK; 893 } 894} 895 896multiclass ATOMIC_LOGIC_OP_RM<bits<8> Opc8, string s> { 897 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 898 SchedRW = [WriteBitTestSetRegRMW] in { 899 def 16rm : I<Opc8, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 900 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"), 901 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR16:$src2))]>, 902 OpSize16, TB, LOCK; 903 def 32rm : I<Opc8, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 904 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"), 905 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR32:$src2))]>, 906 OpSize32, TB, LOCK; 907 def 64rm : RI<Opc8, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 908 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"), 909 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR64:$src2))]>, 910 TB, LOCK; 911 } 912} 913 914 915defm LOCK_BTS : ATOMIC_LOGIC_OP<MRM5m, "bts">; 916defm LOCK_BTC : ATOMIC_LOGIC_OP<MRM7m, "btc">; 917defm LOCK_BTR : ATOMIC_LOGIC_OP<MRM6m, "btr">; 918 919defm LOCK_BTS_RM : ATOMIC_LOGIC_OP_RM<0xAB, "bts">; 920defm LOCK_BTC_RM : ATOMIC_LOGIC_OP_RM<0xBB, "btc">; 921defm LOCK_BTR_RM : ATOMIC_LOGIC_OP_RM<0xB3, "btr">; 922 923// Atomic compare and swap. 924multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 925 string mnemonic, SDPatternOperator frag> { 926let isCodeGenOnly = 1, SchedRW = [WriteCMPXCHGRMW] in { 927 let Defs = [AL, EFLAGS], Uses = [AL] in 928 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 929 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 930 [(frag addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; 931 let Defs = [AX, EFLAGS], Uses = [AX] in 932 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 933 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 934 [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK; 935 let Defs = [EAX, EFLAGS], Uses = [EAX] in 936 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 937 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 938 [(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK; 939 let Defs = [RAX, EFLAGS], Uses = [RAX] in 940 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 941 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 942 [(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK; 943} 944} 945 946let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 947 Predicates = [HasCX8], SchedRW = [WriteCMPXCHGRMW], 948 isCodeGenOnly = 1, usesCustomInserter = 1 in { 949def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr), 950 "cmpxchg8b\t$ptr", 951 [(X86cas8 addr:$ptr)]>, TB, LOCK; 952} 953 954let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 955 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 956 isCodeGenOnly = 1, mayLoad = 1, mayStore = 1, hasSideEffects = 0 in { 957def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr), 958 "cmpxchg16b\t$ptr", 959 []>, TB, LOCK; 960} 961 962// This pseudo must be used when the frame uses RBX as 963// the base pointer. Indeed, in such situation RBX is a reserved 964// register and the register allocator will ignore any use/def of 965// it. In other words, the register will not fix the clobbering of 966// RBX that will happen when setting the arguments for the instrucion. 967// 968// Unlike the actual related instruction, we mark that this one 969// defines RBX (instead of using RBX). 970// The rationale is that we will define RBX during the expansion of 971// the pseudo. The argument feeding RBX is rbx_input. 972// 973// The additional argument, $rbx_save, is a temporary register used to 974// save the value of RBX across the actual instruction. 975// 976// To make sure the register assigned to $rbx_save does not interfere with 977// the definition of the actual instruction, we use a definition $dst which 978// is tied to $rbx_save. That way, the live-range of $rbx_save spans across 979// the instruction and we are sure we will have a valid register to restore 980// the value of RBX. 981let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX], 982 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 983 isCodeGenOnly = 1, isPseudo = 1, 984 mayLoad = 1, mayStore = 1, hasSideEffects = 0, 985 Constraints = "$rbx_save = $dst" in { 986def LCMPXCHG16B_SAVE_RBX : 987 I<0, Pseudo, (outs GR64:$dst), 988 (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), "", []>; 989} 990 991// Pseudo instruction that doesn't read/write RBX. Will be turned into either 992// LCMPXCHG16B_SAVE_RBX or LCMPXCHG16B via a custom inserter. 993let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RCX, RDX], 994 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 995 isCodeGenOnly = 1, isPseudo = 1, 996 mayLoad = 1, mayStore = 1, hasSideEffects = 0, 997 usesCustomInserter = 1 in { 998def LCMPXCHG16B_NO_RBX : 999 I<0, Pseudo, (outs), (ins i128mem:$ptr, GR64:$rbx_input), "", 1000 [(X86cas16 addr:$ptr, GR64:$rbx_input)]>; 1001} 1002 1003// This pseudo must be used when the frame uses RBX/EBX as 1004// the base pointer. 1005// cf comment for LCMPXCHG16B_SAVE_RBX. 1006let Defs = [EBX], Uses = [ECX, EAX], 1007 Predicates = [HasMWAITX], SchedRW = [WriteSystem], 1008 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst" in { 1009def MWAITX_SAVE_RBX : 1010 I<0, Pseudo, (outs GR64:$dst), 1011 (ins GR32:$ebx_input, GR64:$rbx_save), 1012 "mwaitx", 1013 []>; 1014} 1015 1016// Pseudo mwaitx instruction to use for custom insertion. 1017let Predicates = [HasMWAITX], SchedRW = [WriteSystem], 1018 isCodeGenOnly = 1, isPseudo = 1, 1019 usesCustomInserter = 1 in { 1020def MWAITX : 1021 I<0, Pseudo, (outs), (ins GR32:$ecx, GR32:$eax, GR32:$ebx), 1022 "mwaitx", 1023 [(int_x86_mwaitx GR32:$ecx, GR32:$eax, GR32:$ebx)]>; 1024} 1025 1026 1027defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>; 1028 1029// Atomic exchange and add 1030multiclass ATOMIC_RMW_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 1031 string frag> { 1032 let Constraints = "$val = $dst", Defs = [EFLAGS], mayLoad = 1, mayStore = 1, 1033 isCodeGenOnly = 1, SchedRW = [WriteALURMW] in { 1034 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 1035 (ins GR8:$val, i8mem:$ptr), 1036 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 1037 [(set GR8:$dst, 1038 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>; 1039 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 1040 (ins GR16:$val, i16mem:$ptr), 1041 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 1042 [(set 1043 GR16:$dst, 1044 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, 1045 OpSize16; 1046 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 1047 (ins GR32:$val, i32mem:$ptr), 1048 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 1049 [(set 1050 GR32:$dst, 1051 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, 1052 OpSize32; 1053 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 1054 (ins GR64:$val, i64mem:$ptr), 1055 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 1056 [(set 1057 GR64:$dst, 1058 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; 1059 } 1060} 1061 1062defm LXADD : ATOMIC_RMW_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK; 1063 1064/* The following multiclass tries to make sure that in code like 1065 * x.store (immediate op x.load(acquire), release) 1066 * and 1067 * x.store (register op x.load(acquire), release) 1068 * an operation directly on memory is generated instead of wasting a register. 1069 * It is not automatic as atomic_store/load are only lowered to MOV instructions 1070 * extremely late to prevent them from being accidentally reordered in the backend 1071 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) 1072 */ 1073multiclass RELEASE_BINOP_MI<string Name, SDNode op> { 1074 def : Pat<(atomic_store_8 addr:$dst, 1075 (op (atomic_load_8 addr:$dst), (i8 imm:$src))), 1076 (!cast<Instruction>(Name#"8mi") addr:$dst, imm:$src)>; 1077 def : Pat<(atomic_store_16 addr:$dst, 1078 (op (atomic_load_16 addr:$dst), (i16 imm:$src))), 1079 (!cast<Instruction>(Name#"16mi") addr:$dst, imm:$src)>; 1080 def : Pat<(atomic_store_32 addr:$dst, 1081 (op (atomic_load_32 addr:$dst), (i32 imm:$src))), 1082 (!cast<Instruction>(Name#"32mi") addr:$dst, imm:$src)>; 1083 def : Pat<(atomic_store_64 addr:$dst, 1084 (op (atomic_load_64 addr:$dst), (i64immSExt32:$src))), 1085 (!cast<Instruction>(Name#"64mi32") addr:$dst, (i64immSExt32:$src))>; 1086 1087 def : Pat<(atomic_store_8 addr:$dst, 1088 (op (atomic_load_8 addr:$dst), (i8 GR8:$src))), 1089 (!cast<Instruction>(Name#"8mr") addr:$dst, GR8:$src)>; 1090 def : Pat<(atomic_store_16 addr:$dst, 1091 (op (atomic_load_16 addr:$dst), (i16 GR16:$src))), 1092 (!cast<Instruction>(Name#"16mr") addr:$dst, GR16:$src)>; 1093 def : Pat<(atomic_store_32 addr:$dst, 1094 (op (atomic_load_32 addr:$dst), (i32 GR32:$src))), 1095 (!cast<Instruction>(Name#"32mr") addr:$dst, GR32:$src)>; 1096 def : Pat<(atomic_store_64 addr:$dst, 1097 (op (atomic_load_64 addr:$dst), (i64 GR64:$src))), 1098 (!cast<Instruction>(Name#"64mr") addr:$dst, GR64:$src)>; 1099} 1100defm : RELEASE_BINOP_MI<"ADD", add>; 1101defm : RELEASE_BINOP_MI<"AND", and>; 1102defm : RELEASE_BINOP_MI<"OR", or>; 1103defm : RELEASE_BINOP_MI<"XOR", xor>; 1104defm : RELEASE_BINOP_MI<"SUB", sub>; 1105 1106// Atomic load + floating point patterns. 1107// FIXME: This could also handle SIMD operations with *ps and *pd instructions. 1108multiclass ATOMIC_LOAD_FP_BINOP_MI<string Name, SDNode op> { 1109 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1110 (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>, 1111 Requires<[UseSSE1]>; 1112 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1113 (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>, 1114 Requires<[UseAVX]>; 1115 def : Pat<(op FR32X:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1116 (!cast<Instruction>("V"#Name#"SSZrm") FR32X:$src1, addr:$src2)>, 1117 Requires<[HasAVX512]>; 1118 1119 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1120 (!cast<Instruction>(Name#"SDrm") FR64:$src1, addr:$src2)>, 1121 Requires<[UseSSE1]>; 1122 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1123 (!cast<Instruction>("V"#Name#"SDrm") FR64:$src1, addr:$src2)>, 1124 Requires<[UseAVX]>; 1125 def : Pat<(op FR64X:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1126 (!cast<Instruction>("V"#Name#"SDZrm") FR64X:$src1, addr:$src2)>, 1127 Requires<[HasAVX512]>; 1128} 1129defm : ATOMIC_LOAD_FP_BINOP_MI<"ADD", fadd>; 1130// FIXME: Add fsub, fmul, fdiv, ... 1131 1132multiclass RELEASE_UNOP<string Name, dag dag8, dag dag16, dag dag32, 1133 dag dag64> { 1134 def : Pat<(atomic_store_8 addr:$dst, dag8), 1135 (!cast<Instruction>(Name#8m) addr:$dst)>; 1136 def : Pat<(atomic_store_16 addr:$dst, dag16), 1137 (!cast<Instruction>(Name#16m) addr:$dst)>; 1138 def : Pat<(atomic_store_32 addr:$dst, dag32), 1139 (!cast<Instruction>(Name#32m) addr:$dst)>; 1140 def : Pat<(atomic_store_64 addr:$dst, dag64), 1141 (!cast<Instruction>(Name#64m) addr:$dst)>; 1142} 1143 1144let Predicates = [UseIncDec] in { 1145 defm : RELEASE_UNOP<"INC", 1146 (add (atomic_load_8 addr:$dst), (i8 1)), 1147 (add (atomic_load_16 addr:$dst), (i16 1)), 1148 (add (atomic_load_32 addr:$dst), (i32 1)), 1149 (add (atomic_load_64 addr:$dst), (i64 1))>; 1150 defm : RELEASE_UNOP<"DEC", 1151 (add (atomic_load_8 addr:$dst), (i8 -1)), 1152 (add (atomic_load_16 addr:$dst), (i16 -1)), 1153 (add (atomic_load_32 addr:$dst), (i32 -1)), 1154 (add (atomic_load_64 addr:$dst), (i64 -1))>; 1155} 1156 1157defm : RELEASE_UNOP<"NEG", 1158 (ineg (i8 (atomic_load_8 addr:$dst))), 1159 (ineg (i16 (atomic_load_16 addr:$dst))), 1160 (ineg (i32 (atomic_load_32 addr:$dst))), 1161 (ineg (i64 (atomic_load_64 addr:$dst)))>; 1162defm : RELEASE_UNOP<"NOT", 1163 (not (i8 (atomic_load_8 addr:$dst))), 1164 (not (i16 (atomic_load_16 addr:$dst))), 1165 (not (i32 (atomic_load_32 addr:$dst))), 1166 (not (i64 (atomic_load_64 addr:$dst)))>; 1167 1168def : Pat<(atomic_store_8 addr:$dst, (i8 imm:$src)), 1169 (MOV8mi addr:$dst, imm:$src)>; 1170def : Pat<(atomic_store_16 addr:$dst, (i16 imm:$src)), 1171 (MOV16mi addr:$dst, imm:$src)>; 1172def : Pat<(atomic_store_32 addr:$dst, (i32 imm:$src)), 1173 (MOV32mi addr:$dst, imm:$src)>; 1174def : Pat<(atomic_store_64 addr:$dst, (i64immSExt32:$src)), 1175 (MOV64mi32 addr:$dst, i64immSExt32:$src)>; 1176 1177def : Pat<(atomic_store_8 addr:$dst, GR8:$src), 1178 (MOV8mr addr:$dst, GR8:$src)>; 1179def : Pat<(atomic_store_16 addr:$dst, GR16:$src), 1180 (MOV16mr addr:$dst, GR16:$src)>; 1181def : Pat<(atomic_store_32 addr:$dst, GR32:$src), 1182 (MOV32mr addr:$dst, GR32:$src)>; 1183def : Pat<(atomic_store_64 addr:$dst, GR64:$src), 1184 (MOV64mr addr:$dst, GR64:$src)>; 1185 1186def : Pat<(i8 (atomic_load_8 addr:$src)), (MOV8rm addr:$src)>; 1187def : Pat<(i16 (atomic_load_16 addr:$src)), (MOV16rm addr:$src)>; 1188def : Pat<(i32 (atomic_load_32 addr:$src)), (MOV32rm addr:$src)>; 1189def : Pat<(i64 (atomic_load_64 addr:$src)), (MOV64rm addr:$src)>; 1190 1191// Floating point loads/stores. 1192def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1193 (MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>; 1194def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1195 (VMOVSSmr addr:$dst, FR32:$src)>, Requires<[UseAVX]>; 1196def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1197 (VMOVSSZmr addr:$dst, FR32:$src)>, Requires<[HasAVX512]>; 1198 1199def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))), 1200 (MOVSDmr addr:$dst, FR64:$src)>, Requires<[UseSSE2]>; 1201def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))), 1202 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[UseAVX]>; 1203def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))), 1204 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[HasAVX512]>; 1205 1206def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1207 (MOVSSrm_alt addr:$src)>, Requires<[UseSSE1]>; 1208def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1209 (VMOVSSrm_alt addr:$src)>, Requires<[UseAVX]>; 1210def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1211 (VMOVSSZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1212 1213def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1214 (MOVSDrm_alt addr:$src)>, Requires<[UseSSE2]>; 1215def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1216 (VMOVSDrm_alt addr:$src)>, Requires<[UseAVX]>; 1217def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1218 (VMOVSDZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1219 1220//===----------------------------------------------------------------------===// 1221// DAG Pattern Matching Rules 1222//===----------------------------------------------------------------------===// 1223 1224// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves 1225// binary size compared to a regular MOV, but it introduces an unnecessary 1226// load, so is not suitable for regular or optsize functions. 1227let Predicates = [OptForMinSize] in { 1228def : Pat<(simple_store (i16 0), addr:$dst), (AND16mi8 addr:$dst, 0)>; 1229def : Pat<(simple_store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>; 1230def : Pat<(simple_store (i64 0), addr:$dst), (AND64mi8 addr:$dst, 0)>; 1231def : Pat<(simple_store (i16 -1), addr:$dst), (OR16mi8 addr:$dst, -1)>; 1232def : Pat<(simple_store (i32 -1), addr:$dst), (OR32mi8 addr:$dst, -1)>; 1233def : Pat<(simple_store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>; 1234} 1235 1236// In kernel code model, we can get the address of a label 1237// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 1238// the MOV64ri32 should accept these. 1239def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 1240 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 1241def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 1242 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 1243def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 1244 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 1245def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 1246 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 1247def : Pat<(i64 (X86Wrapper mcsym:$dst)), 1248 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; 1249def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 1250 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 1251 1252// If we have small model and -static mode, it is safe to store global addresses 1253// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 1254// for MOV64mi32 should handle this sort of thing. 1255def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 1256 (MOV64mi32 addr:$dst, tconstpool:$src)>, 1257 Requires<[NearData, IsNotPIC]>; 1258def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 1259 (MOV64mi32 addr:$dst, tjumptable:$src)>, 1260 Requires<[NearData, IsNotPIC]>; 1261def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1262 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 1263 Requires<[NearData, IsNotPIC]>; 1264def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 1265 (MOV64mi32 addr:$dst, texternalsym:$src)>, 1266 Requires<[NearData, IsNotPIC]>; 1267def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), 1268 (MOV64mi32 addr:$dst, mcsym:$src)>, 1269 Requires<[NearData, IsNotPIC]>; 1270def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 1271 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 1272 Requires<[NearData, IsNotPIC]>; 1273 1274def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; 1275def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; 1276 1277// Calls 1278 1279// tls has some funny stuff here... 1280// This corresponds to movabs $foo@tpoff, %rax 1281def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 1282 (MOV64ri32 tglobaltlsaddr :$dst)>; 1283// This corresponds to add $foo@tpoff, %rax 1284def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 1285 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 1286 1287 1288// Direct PC relative function call for small code model. 32-bit displacement 1289// sign extended to 64-bit. 1290def : Pat<(X86call (i64 tglobaladdr:$dst)), 1291 (CALL64pcrel32 tglobaladdr:$dst)>; 1292def : Pat<(X86call (i64 texternalsym:$dst)), 1293 (CALL64pcrel32 texternalsym:$dst)>; 1294 1295def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 texternalsym:$dst)), 1296 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, texternalsym:$dst)>; 1297def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 tglobaladdr:$dst)), 1298 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, tglobaladdr:$dst)>; 1299 1300 1301// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1302// can never use callee-saved registers. That is the purpose of the GR64_TC 1303// register classes. 1304// 1305// The only volatile register that is never used by the calling convention is 1306// %r11. This happens when calling a vararg function with 6 arguments. 1307// 1308// Match an X86tcret that uses less than 7 volatile registers. 1309def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 1310 (X86tcret node:$ptr, node:$off), [{ 1311 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1312 unsigned NumRegs = 0; 1313 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1314 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 1315 return false; 1316 return true; 1317}]>; 1318 1319def X86tcret_1reg : PatFrag<(ops node:$ptr, node:$off), 1320 (X86tcret node:$ptr, node:$off), [{ 1321 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1322 unsigned NumRegs = 1; 1323 const SDValue& BasePtr = cast<LoadSDNode>(N->getOperand(1))->getBasePtr(); 1324 if (isa<FrameIndexSDNode>(BasePtr)) 1325 NumRegs = 3; 1326 else if (BasePtr->getNumOperands() && isa<GlobalAddressSDNode>(BasePtr->getOperand(0))) 1327 NumRegs = 3; 1328 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1329 if (isa<RegisterSDNode>(N->getOperand(i)) && ( NumRegs-- == 0)) 1330 return false; 1331 return true; 1332}]>; 1333 1334def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1335 (TCRETURNri ptr_rc_tailcall:$dst, timm:$off)>, 1336 Requires<[Not64BitMode, NotUseIndirectThunkCalls]>; 1337 1338// FIXME: This is disabled for 32-bit PIC mode because the global base 1339// register which is part of the address mode may be assigned a 1340// callee-saved register. 1341// Similar to X86tcret_6regs, here we only have 1 register left 1342def : Pat<(X86tcret_1reg (load addr:$dst), timm:$off), 1343 (TCRETURNmi addr:$dst, timm:$off)>, 1344 Requires<[Not64BitMode, IsNotPIC, NotUseIndirectThunkCalls]>; 1345 1346def : Pat<(X86tcret (i32 tglobaladdr:$dst), timm:$off), 1347 (TCRETURNdi tglobaladdr:$dst, timm:$off)>, 1348 Requires<[NotLP64]>; 1349 1350def : Pat<(X86tcret (i32 texternalsym:$dst), timm:$off), 1351 (TCRETURNdi texternalsym:$dst, timm:$off)>, 1352 Requires<[NotLP64]>; 1353 1354def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1355 (TCRETURNri64 ptr_rc_tailcall:$dst, timm:$off)>, 1356 Requires<[In64BitMode, NotUseIndirectThunkCalls]>; 1357 1358// Don't fold loads into X86tcret requiring more than 6 regs. 1359// There wouldn't be enough scratch registers for base+index. 1360def : Pat<(X86tcret_6regs (load addr:$dst), timm:$off), 1361 (TCRETURNmi64 addr:$dst, timm:$off)>, 1362 Requires<[In64BitMode, NotUseIndirectThunkCalls]>; 1363 1364def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1365 (INDIRECT_THUNK_TCRETURN64 ptr_rc_tailcall:$dst, timm:$off)>, 1366 Requires<[In64BitMode, UseIndirectThunkCalls]>; 1367 1368def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1369 (INDIRECT_THUNK_TCRETURN32 ptr_rc_tailcall:$dst, timm:$off)>, 1370 Requires<[Not64BitMode, UseIndirectThunkCalls]>; 1371 1372def : Pat<(X86tcret (i64 tglobaladdr:$dst), timm:$off), 1373 (TCRETURNdi64 tglobaladdr:$dst, timm:$off)>, 1374 Requires<[IsLP64]>; 1375 1376def : Pat<(X86tcret (i64 texternalsym:$dst), timm:$off), 1377 (TCRETURNdi64 texternalsym:$dst, timm:$off)>, 1378 Requires<[IsLP64]>; 1379 1380// Normal calls, with various flavors of addresses. 1381def : Pat<(X86call (i32 tglobaladdr:$dst)), 1382 (CALLpcrel32 tglobaladdr:$dst)>; 1383def : Pat<(X86call (i32 texternalsym:$dst)), 1384 (CALLpcrel32 texternalsym:$dst)>; 1385def : Pat<(X86call (i32 imm:$dst)), 1386 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1387 1388// Comparisons. 1389 1390// TEST R,R is smaller than CMP R,0 1391def : Pat<(X86cmp GR8:$src1, 0), 1392 (TEST8rr GR8:$src1, GR8:$src1)>; 1393def : Pat<(X86cmp GR16:$src1, 0), 1394 (TEST16rr GR16:$src1, GR16:$src1)>; 1395def : Pat<(X86cmp GR32:$src1, 0), 1396 (TEST32rr GR32:$src1, GR32:$src1)>; 1397def : Pat<(X86cmp GR64:$src1, 0), 1398 (TEST64rr GR64:$src1, GR64:$src1)>; 1399 1400// zextload bool -> zextload byte 1401// i1 stored in one byte in zero-extended form. 1402// Upper bits cleanup should be executed before Store. 1403def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1404def : Pat<(zextloadi16i1 addr:$src), 1405 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1406def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1407def : Pat<(zextloadi64i1 addr:$src), 1408 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1409 1410// extload bool -> extload byte 1411// When extloading from 16-bit and smaller memory locations into 64-bit 1412// registers, use zero-extending loads so that the entire 64-bit register is 1413// defined, avoiding partial-register updates. 1414 1415def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1416def : Pat<(extloadi16i1 addr:$src), 1417 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1418def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1419def : Pat<(extloadi16i8 addr:$src), 1420 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1421def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1422def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1423 1424// For other extloads, use subregs, since the high contents of the register are 1425// defined after an extload. 1426// NOTE: The extloadi64i32 pattern needs to be first as it will try to form 1427// 32-bit loads for 4 byte aligned i8/i16 loads. 1428def : Pat<(extloadi64i32 addr:$src), 1429 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1430def : Pat<(extloadi64i1 addr:$src), 1431 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1432def : Pat<(extloadi64i8 addr:$src), 1433 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1434def : Pat<(extloadi64i16 addr:$src), 1435 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1436 1437// anyext. Define these to do an explicit zero-extend to 1438// avoid partial-register updates. 1439def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1440 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1441def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1442 1443// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1444def : Pat<(i32 (anyext GR16:$src)), 1445 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1446 1447def : Pat<(i64 (anyext GR8 :$src)), 1448 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1449def : Pat<(i64 (anyext GR16:$src)), 1450 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1451def : Pat<(i64 (anyext GR32:$src)), 1452 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>; 1453 1454// If this is an anyext of the remainder of an 8-bit sdivrem, use a MOVSX 1455// instead of a MOVZX. The sdivrem lowering will emit emit a MOVSX to move 1456// %ah to the lower byte of a register. By using a MOVSX here we allow a 1457// post-isel peephole to merge the two MOVSX instructions into one. 1458def anyext_sdiv : PatFrag<(ops node:$lhs), (anyext node:$lhs),[{ 1459 return (N->getOperand(0).getOpcode() == ISD::SDIVREM && 1460 N->getOperand(0).getResNo() == 1); 1461}]>; 1462def : Pat<(i32 (anyext_sdiv GR8:$src)), (MOVSX32rr8 GR8:$src)>; 1463 1464// Any instruction that defines a 32-bit result leaves the high half of the 1465// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1466// be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying 1467// anything about the upper 32 bits, they're probably just qualifying a 1468// CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit 1469// operation will zero-extend up to 64 bits. 1470def def32 : PatLeaf<(i32 GR32:$src), [{ 1471 return N->getOpcode() != ISD::TRUNCATE && 1472 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1473 N->getOpcode() != ISD::CopyFromReg && 1474 N->getOpcode() != ISD::AssertSext && 1475 N->getOpcode() != ISD::AssertZext && 1476 N->getOpcode() != ISD::AssertAlign && 1477 N->getOpcode() != ISD::FREEZE; 1478}]>; 1479 1480// In the case of a 32-bit def that is known to implicitly zero-extend, 1481// we can use a SUBREG_TO_REG. 1482def : Pat<(i64 (zext def32:$src)), 1483 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1484def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)), 1485 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1486 1487//===----------------------------------------------------------------------===// 1488// Pattern match OR as ADD 1489//===----------------------------------------------------------------------===// 1490 1491// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1492// 3-addressified into an LEA instruction to avoid copies. However, we also 1493// want to finally emit these instructions as an or at the end of the code 1494// generator to make the generated code easier to read. To do this, we select 1495// into "disjoint bits" pseudo ops. 1496 1497// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1498def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1499 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1500 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1501 1502 KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0); 1503 KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0); 1504 return (~Known0.Zero & ~Known1.Zero) == 0; 1505}]>; 1506 1507 1508// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1509// Try this before the selecting to OR. 1510let SchedRW = [WriteALU] in { 1511 1512let isConvertibleToThreeAddress = 1, isPseudo = 1, 1513 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1514let isCommutable = 1 in { 1515def ADD8rr_DB : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), 1516 "", // orb/addb REG, REG 1517 [(set GR8:$dst, (or_is_add GR8:$src1, GR8:$src2))]>; 1518def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1519 "", // orw/addw REG, REG 1520 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1521def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1522 "", // orl/addl REG, REG 1523 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1524def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1525 "", // orq/addq REG, REG 1526 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1527} // isCommutable 1528 1529// NOTE: These are order specific, we want the ri8 forms to be listed 1530// first so that they are slightly preferred to the ri forms. 1531 1532def ADD8ri_DB : I<0, Pseudo, 1533 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), 1534 "", // orb/addb REG, imm8 1535 [(set GR8:$dst, (or_is_add GR8:$src1, imm:$src2))]>; 1536def ADD16ri8_DB : I<0, Pseudo, 1537 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1538 "", // orw/addw REG, imm8 1539 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1540def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1541 "", // orw/addw REG, imm 1542 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1543 1544def ADD32ri8_DB : I<0, Pseudo, 1545 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1546 "", // orl/addl REG, imm8 1547 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1548def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1549 "", // orl/addl REG, imm 1550 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1551 1552 1553def ADD64ri8_DB : I<0, Pseudo, 1554 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1555 "", // orq/addq REG, imm8 1556 [(set GR64:$dst, (or_is_add GR64:$src1, 1557 i64immSExt8:$src2))]>; 1558def ADD64ri32_DB : I<0, Pseudo, 1559 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1560 "", // orq/addq REG, imm 1561 [(set GR64:$dst, (or_is_add GR64:$src1, 1562 i64immSExt32:$src2))]>; 1563} 1564} // AddedComplexity, SchedRW 1565 1566//===----------------------------------------------------------------------===// 1567// Pattern match XOR as ADD 1568//===----------------------------------------------------------------------===// 1569 1570// Prefer to pattern match XOR with min_signed_value as ADD at isel time. 1571// ADD can be 3-addressified into an LEA instruction to avoid copies. 1572let AddedComplexity = 5 in { 1573def : Pat<(xor GR8:$src1, -128), 1574 (ADD8ri GR8:$src1, -128)>; 1575def : Pat<(xor GR16:$src1, -32768), 1576 (ADD16ri GR16:$src1, -32768)>; 1577def : Pat<(xor GR32:$src1, -2147483648), 1578 (ADD32ri GR32:$src1, -2147483648)>; 1579} 1580 1581//===----------------------------------------------------------------------===// 1582// Some peepholes 1583//===----------------------------------------------------------------------===// 1584 1585// Odd encoding trick: -128 fits into an 8-bit immediate field while 1586// +128 doesn't, so in this special case use a sub instead of an add. 1587def : Pat<(add GR16:$src1, 128), 1588 (SUB16ri8 GR16:$src1, -128)>; 1589def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1590 (SUB16mi8 addr:$dst, -128)>; 1591 1592def : Pat<(add GR32:$src1, 128), 1593 (SUB32ri8 GR32:$src1, -128)>; 1594def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1595 (SUB32mi8 addr:$dst, -128)>; 1596 1597def : Pat<(add GR64:$src1, 128), 1598 (SUB64ri8 GR64:$src1, -128)>; 1599def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1600 (SUB64mi8 addr:$dst, -128)>; 1601 1602def : Pat<(X86add_flag_nocf GR16:$src1, 128), 1603 (SUB16ri8 GR16:$src1, -128)>; 1604def : Pat<(X86add_flag_nocf GR32:$src1, 128), 1605 (SUB32ri8 GR32:$src1, -128)>; 1606def : Pat<(X86add_flag_nocf GR64:$src1, 128), 1607 (SUB64ri8 GR64:$src1, -128)>; 1608 1609// The same trick applies for 32-bit immediate fields in 64-bit 1610// instructions. 1611def : Pat<(add GR64:$src1, 0x0000000080000000), 1612 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1613def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst), 1614 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1615 1616def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000), 1617 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1618 1619// To avoid needing to materialize an immediate in a register, use a 32-bit and 1620// with implicit zero-extension instead of a 64-bit and if the immediate has at 1621// least 32 bits of leading zeros. If in addition the last 32 bits can be 1622// represented with a sign extension of a 8 bit constant, use that. 1623// This can also reduce instruction size by eliminating the need for the REX 1624// prefix. 1625 1626// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. 1627let AddedComplexity = 1 in { 1628def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1629 (SUBREG_TO_REG 1630 (i64 0), 1631 (AND32ri8 1632 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1633 (i32 (GetLo32XForm imm:$imm))), 1634 sub_32bit)>; 1635 1636def : Pat<(and GR64:$src, i64immZExt32:$imm), 1637 (SUBREG_TO_REG 1638 (i64 0), 1639 (AND32ri 1640 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1641 (i32 (GetLo32XForm imm:$imm))), 1642 sub_32bit)>; 1643} // AddedComplexity = 1 1644 1645 1646// AddedComplexity is needed due to the increased complexity on the 1647// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all 1648// the MOVZX patterns keeps thems together in DAGIsel tables. 1649let AddedComplexity = 1 in { 1650// r & (2^16-1) ==> movz 1651def : Pat<(and GR32:$src1, 0xffff), 1652 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1653// r & (2^8-1) ==> movz 1654def : Pat<(and GR32:$src1, 0xff), 1655 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>; 1656// r & (2^8-1) ==> movz 1657def : Pat<(and GR16:$src1, 0xff), 1658 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)), 1659 sub_16bit)>; 1660 1661// r & (2^32-1) ==> movz 1662def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1663 (SUBREG_TO_REG (i64 0), 1664 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1665 sub_32bit)>; 1666// r & (2^16-1) ==> movz 1667def : Pat<(and GR64:$src, 0xffff), 1668 (SUBREG_TO_REG (i64 0), 1669 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1670 sub_32bit)>; 1671// r & (2^8-1) ==> movz 1672def : Pat<(and GR64:$src, 0xff), 1673 (SUBREG_TO_REG (i64 0), 1674 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1675 sub_32bit)>; 1676} // AddedComplexity = 1 1677 1678 1679// Try to use BTS/BTR/BTC for single bit operations on the upper 32-bits. 1680 1681def BTRXForm : SDNodeXForm<imm, [{ 1682 // Transformation function: Find the lowest 0. 1683 return getI64Imm((uint8_t)N->getAPIntValue().countTrailingOnes(), SDLoc(N)); 1684}]>; 1685 1686def BTCBTSXForm : SDNodeXForm<imm, [{ 1687 // Transformation function: Find the lowest 1. 1688 return getI64Imm((uint8_t)N->getAPIntValue().countTrailingZeros(), SDLoc(N)); 1689}]>; 1690 1691def BTRMask64 : ImmLeaf<i64, [{ 1692 return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm); 1693}]>; 1694 1695def BTCBTSMask64 : ImmLeaf<i64, [{ 1696 return !isInt<32>(Imm) && isPowerOf2_64(Imm); 1697}]>; 1698 1699// For now only do this for optsize. 1700let AddedComplexity = 1, Predicates=[OptForSize] in { 1701 def : Pat<(and GR64:$src1, BTRMask64:$mask), 1702 (BTR64ri8 GR64:$src1, (BTRXForm imm:$mask))>; 1703 def : Pat<(or GR64:$src1, BTCBTSMask64:$mask), 1704 (BTS64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1705 def : Pat<(xor GR64:$src1, BTCBTSMask64:$mask), 1706 (BTC64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1707} 1708 1709 1710// sext_inreg patterns 1711def : Pat<(sext_inreg GR32:$src, i16), 1712 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1713def : Pat<(sext_inreg GR32:$src, i8), 1714 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>; 1715 1716def : Pat<(sext_inreg GR16:$src, i8), 1717 (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)), 1718 sub_16bit)>; 1719 1720def : Pat<(sext_inreg GR64:$src, i32), 1721 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1722def : Pat<(sext_inreg GR64:$src, i16), 1723 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1724def : Pat<(sext_inreg GR64:$src, i8), 1725 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1726 1727// sext, sext_load, zext, zext_load 1728def: Pat<(i16 (sext GR8:$src)), 1729 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1730def: Pat<(sextloadi16i8 addr:$src), 1731 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1732def: Pat<(i16 (zext GR8:$src)), 1733 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1734def: Pat<(zextloadi16i8 addr:$src), 1735 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1736 1737// trunc patterns 1738def : Pat<(i16 (trunc GR32:$src)), 1739 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1740def : Pat<(i8 (trunc GR32:$src)), 1741 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1742 sub_8bit)>, 1743 Requires<[Not64BitMode]>; 1744def : Pat<(i8 (trunc GR16:$src)), 1745 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1746 sub_8bit)>, 1747 Requires<[Not64BitMode]>; 1748def : Pat<(i32 (trunc GR64:$src)), 1749 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1750def : Pat<(i16 (trunc GR64:$src)), 1751 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1752def : Pat<(i8 (trunc GR64:$src)), 1753 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1754def : Pat<(i8 (trunc GR32:$src)), 1755 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1756 Requires<[In64BitMode]>; 1757def : Pat<(i8 (trunc GR16:$src)), 1758 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1759 Requires<[In64BitMode]>; 1760 1761def immff00_ffff : ImmLeaf<i32, [{ 1762 return Imm >= 0xff00 && Imm <= 0xffff; 1763}]>; 1764 1765// h-register tricks 1766def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1767 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1768 Requires<[Not64BitMode]>; 1769def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))), 1770 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1771 Requires<[Not64BitMode]>; 1772def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1773 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>, 1774 Requires<[Not64BitMode]>; 1775def : Pat<(srl GR16:$src, (i8 8)), 1776 (EXTRACT_SUBREG 1777 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1778 sub_16bit)>; 1779def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1780 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1781def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1782 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1783def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1784 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1785def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)), 1786 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1787 1788// h-register tricks. 1789// For now, be conservative on x86-64 and use an h-register extract only if the 1790// value is immediately zero-extended or stored, which are somewhat common 1791// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1792// from being allocated in the same instruction as the h register, as there's 1793// currently no way to describe this requirement to the register allocator. 1794 1795// h-register extract and zero-extend. 1796def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1797 (SUBREG_TO_REG 1798 (i64 0), 1799 (MOVZX32rr8_NOREX 1800 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), 1801 sub_32bit)>; 1802def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1803 (SUBREG_TO_REG 1804 (i64 0), 1805 (MOVZX32rr8_NOREX 1806 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1807 sub_32bit)>; 1808def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1809 (SUBREG_TO_REG 1810 (i64 0), 1811 (MOVZX32rr8_NOREX 1812 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1813 sub_32bit)>; 1814 1815// h-register extract and store. 1816def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1817 (MOV8mr_NOREX 1818 addr:$dst, 1819 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>; 1820def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1821 (MOV8mr_NOREX 1822 addr:$dst, 1823 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, 1824 Requires<[In64BitMode]>; 1825def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1826 (MOV8mr_NOREX 1827 addr:$dst, 1828 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, 1829 Requires<[In64BitMode]>; 1830 1831// Special pattern to catch the last step of __builtin_parity handling. Our 1832// goal is to use an xor of an h-register with the corresponding l-register. 1833// The above patterns would handle this on non 64-bit targets, but for 64-bit 1834// we need to be more careful. We're using a NOREX instruction here in case 1835// register allocation fails to keep the two registers together. So we need to 1836// make sure we can't accidentally mix R8-R15 with an h-register. 1837def : Pat<(X86xor_flag (i8 (trunc GR32:$src)), 1838 (i8 (trunc (srl_su GR32:$src, (i8 8))))), 1839 (XOR8rr_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit), 1840 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1841 1842// (shl x, 1) ==> (add x, x) 1843// Note that if x is undef (immediate or otherwise), we could theoretically 1844// end up with the two uses of x getting different values, producing a result 1845// where the least significant bit is not 0. However, the probability of this 1846// happening is considered low enough that this is officially not a 1847// "real problem". 1848def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1849def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1850def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1851def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1852 1853def shiftMask8 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1854 return isUnneededShiftMask(N, 3); 1855}]>; 1856 1857def shiftMask16 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1858 return isUnneededShiftMask(N, 4); 1859}]>; 1860 1861def shiftMask32 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1862 return isUnneededShiftMask(N, 5); 1863}]>; 1864 1865def shiftMask64 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1866 return isUnneededShiftMask(N, 6); 1867}]>; 1868 1869 1870// Shift amount is implicitly masked. 1871multiclass MaskedShiftAmountPats<SDNode frag, string name> { 1872 // (shift x (and y, 31)) ==> (shift x, y) 1873 def : Pat<(frag GR8:$src1, (shiftMask32 CL)), 1874 (!cast<Instruction>(name # "8rCL") GR8:$src1)>; 1875 def : Pat<(frag GR16:$src1, (shiftMask32 CL)), 1876 (!cast<Instruction>(name # "16rCL") GR16:$src1)>; 1877 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1878 (!cast<Instruction>(name # "32rCL") GR32:$src1)>; 1879 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask32 CL)), addr:$dst), 1880 (!cast<Instruction>(name # "8mCL") addr:$dst)>; 1881 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask32 CL)), addr:$dst), 1882 (!cast<Instruction>(name # "16mCL") addr:$dst)>; 1883 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1884 (!cast<Instruction>(name # "32mCL") addr:$dst)>; 1885 1886 // (shift x (and y, 63)) ==> (shift x, y) 1887 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1888 (!cast<Instruction>(name # "64rCL") GR64:$src1)>; 1889 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1890 (!cast<Instruction>(name # "64mCL") addr:$dst)>; 1891} 1892 1893defm : MaskedShiftAmountPats<shl, "SHL">; 1894defm : MaskedShiftAmountPats<srl, "SHR">; 1895defm : MaskedShiftAmountPats<sra, "SAR">; 1896 1897// ROL/ROR instructions allow a stronger mask optimization than shift for 8- and 1898// 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount 1899// because over-rotating produces the same result. This is noted in the Intel 1900// docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation 1901// amount could affect EFLAGS results, but that does not matter because we are 1902// not tracking flags for these nodes. 1903multiclass MaskedRotateAmountPats<SDNode frag, string name> { 1904 // (rot x (and y, BitWidth - 1)) ==> (rot x, y) 1905 def : Pat<(frag GR8:$src1, (shiftMask8 CL)), 1906 (!cast<Instruction>(name # "8rCL") GR8:$src1)>; 1907 def : Pat<(frag GR16:$src1, (shiftMask16 CL)), 1908 (!cast<Instruction>(name # "16rCL") GR16:$src1)>; 1909 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1910 (!cast<Instruction>(name # "32rCL") GR32:$src1)>; 1911 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask8 CL)), addr:$dst), 1912 (!cast<Instruction>(name # "8mCL") addr:$dst)>; 1913 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask16 CL)), addr:$dst), 1914 (!cast<Instruction>(name # "16mCL") addr:$dst)>; 1915 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1916 (!cast<Instruction>(name # "32mCL") addr:$dst)>; 1917 1918 // (rot x (and y, 63)) ==> (rot x, y) 1919 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1920 (!cast<Instruction>(name # "64rCL") GR64:$src1)>; 1921 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1922 (!cast<Instruction>(name # "64mCL") addr:$dst)>; 1923} 1924 1925 1926defm : MaskedRotateAmountPats<rotl, "ROL">; 1927defm : MaskedRotateAmountPats<rotr, "ROR">; 1928 1929// Double "funnel" shift amount is implicitly masked. 1930// (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) (NOTE: modulo32) 1931def : Pat<(X86fshl GR16:$src1, GR16:$src2, (shiftMask32 CL)), 1932 (SHLD16rrCL GR16:$src1, GR16:$src2)>; 1933def : Pat<(X86fshr GR16:$src2, GR16:$src1, (shiftMask32 CL)), 1934 (SHRD16rrCL GR16:$src1, GR16:$src2)>; 1935 1936// (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) 1937def : Pat<(fshl GR32:$src1, GR32:$src2, (shiftMask32 CL)), 1938 (SHLD32rrCL GR32:$src1, GR32:$src2)>; 1939def : Pat<(fshr GR32:$src2, GR32:$src1, (shiftMask32 CL)), 1940 (SHRD32rrCL GR32:$src1, GR32:$src2)>; 1941 1942// (fshl/fshr x (and y, 63)) ==> (fshl/fshr x, y) 1943def : Pat<(fshl GR64:$src1, GR64:$src2, (shiftMask64 CL)), 1944 (SHLD64rrCL GR64:$src1, GR64:$src2)>; 1945def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)), 1946 (SHRD64rrCL GR64:$src1, GR64:$src2)>; 1947 1948let Predicates = [HasBMI2] in { 1949 let AddedComplexity = 1 in { 1950 def : Pat<(sra GR32:$src1, (shiftMask32 GR8:$src2)), 1951 (SARX32rr GR32:$src1, 1952 (INSERT_SUBREG 1953 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1954 def : Pat<(sra GR64:$src1, (shiftMask64 GR8:$src2)), 1955 (SARX64rr GR64:$src1, 1956 (INSERT_SUBREG 1957 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1958 1959 def : Pat<(srl GR32:$src1, (shiftMask32 GR8:$src2)), 1960 (SHRX32rr GR32:$src1, 1961 (INSERT_SUBREG 1962 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1963 def : Pat<(srl GR64:$src1, (shiftMask64 GR8:$src2)), 1964 (SHRX64rr GR64:$src1, 1965 (INSERT_SUBREG 1966 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1967 1968 def : Pat<(shl GR32:$src1, (shiftMask32 GR8:$src2)), 1969 (SHLX32rr GR32:$src1, 1970 (INSERT_SUBREG 1971 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1972 def : Pat<(shl GR64:$src1, (shiftMask64 GR8:$src2)), 1973 (SHLX64rr GR64:$src1, 1974 (INSERT_SUBREG 1975 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1976 } 1977 1978 def : Pat<(sra (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), 1979 (SARX32rm addr:$src1, 1980 (INSERT_SUBREG 1981 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1982 def : Pat<(sra (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), 1983 (SARX64rm addr:$src1, 1984 (INSERT_SUBREG 1985 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1986 1987 def : Pat<(srl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), 1988 (SHRX32rm addr:$src1, 1989 (INSERT_SUBREG 1990 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1991 def : Pat<(srl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), 1992 (SHRX64rm addr:$src1, 1993 (INSERT_SUBREG 1994 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1995 1996 def : Pat<(shl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), 1997 (SHLX32rm addr:$src1, 1998 (INSERT_SUBREG 1999 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 2000 def : Pat<(shl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), 2001 (SHLX64rm addr:$src1, 2002 (INSERT_SUBREG 2003 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 2004} 2005 2006// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location. 2007multiclass one_bit_patterns<RegisterClass RC, ValueType VT, Instruction BTR, 2008 Instruction BTS, Instruction BTC, 2009 PatFrag ShiftMask> { 2010 def : Pat<(and RC:$src1, (rotl -2, GR8:$src2)), 2011 (BTR RC:$src1, 2012 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 2013 def : Pat<(or RC:$src1, (shl 1, GR8:$src2)), 2014 (BTS RC:$src1, 2015 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 2016 def : Pat<(xor RC:$src1, (shl 1, GR8:$src2)), 2017 (BTC RC:$src1, 2018 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 2019 2020 // Similar to above, but removing unneeded masking of the shift amount. 2021 def : Pat<(and RC:$src1, (rotl -2, (ShiftMask GR8:$src2))), 2022 (BTR RC:$src1, 2023 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 2024 def : Pat<(or RC:$src1, (shl 1, (ShiftMask GR8:$src2))), 2025 (BTS RC:$src1, 2026 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 2027 def : Pat<(xor RC:$src1, (shl 1, (ShiftMask GR8:$src2))), 2028 (BTC RC:$src1, 2029 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 2030} 2031 2032defm : one_bit_patterns<GR16, i16, BTR16rr, BTS16rr, BTC16rr, shiftMask16>; 2033defm : one_bit_patterns<GR32, i32, BTR32rr, BTS32rr, BTC32rr, shiftMask32>; 2034defm : one_bit_patterns<GR64, i64, BTR64rr, BTS64rr, BTC64rr, shiftMask64>; 2035 2036//===----------------------------------------------------------------------===// 2037// EFLAGS-defining Patterns 2038//===----------------------------------------------------------------------===// 2039 2040// add reg, reg 2041def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 2042def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 2043def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 2044def : Pat<(add GR64:$src1, GR64:$src2), (ADD64rr GR64:$src1, GR64:$src2)>; 2045 2046// add reg, mem 2047def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 2048 (ADD8rm GR8:$src1, addr:$src2)>; 2049def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 2050 (ADD16rm GR16:$src1, addr:$src2)>; 2051def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 2052 (ADD32rm GR32:$src1, addr:$src2)>; 2053def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 2054 (ADD64rm GR64:$src1, addr:$src2)>; 2055 2056// add reg, imm 2057def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 2058def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 2059def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 2060def : Pat<(add GR16:$src1, i16immSExt8:$src2), 2061 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 2062def : Pat<(add GR32:$src1, i32immSExt8:$src2), 2063 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 2064def : Pat<(add GR64:$src1, i64immSExt8:$src2), 2065 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 2066def : Pat<(add GR64:$src1, i64immSExt32:$src2), 2067 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 2068 2069// sub reg, reg 2070def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 2071def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 2072def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 2073def : Pat<(sub GR64:$src1, GR64:$src2), (SUB64rr GR64:$src1, GR64:$src2)>; 2074 2075// sub reg, mem 2076def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 2077 (SUB8rm GR8:$src1, addr:$src2)>; 2078def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 2079 (SUB16rm GR16:$src1, addr:$src2)>; 2080def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 2081 (SUB32rm GR32:$src1, addr:$src2)>; 2082def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 2083 (SUB64rm GR64:$src1, addr:$src2)>; 2084 2085// sub reg, imm 2086def : Pat<(sub GR8:$src1, imm:$src2), 2087 (SUB8ri GR8:$src1, imm:$src2)>; 2088def : Pat<(sub GR16:$src1, imm:$src2), 2089 (SUB16ri GR16:$src1, imm:$src2)>; 2090def : Pat<(sub GR32:$src1, imm:$src2), 2091 (SUB32ri GR32:$src1, imm:$src2)>; 2092def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 2093 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 2094def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 2095 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 2096def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 2097 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 2098def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 2099 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 2100 2101// sub 0, reg 2102def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; 2103def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; 2104def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; 2105def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; 2106 2107// mul reg, reg 2108def : Pat<(mul GR16:$src1, GR16:$src2), 2109 (IMUL16rr GR16:$src1, GR16:$src2)>; 2110def : Pat<(mul GR32:$src1, GR32:$src2), 2111 (IMUL32rr GR32:$src1, GR32:$src2)>; 2112def : Pat<(mul GR64:$src1, GR64:$src2), 2113 (IMUL64rr GR64:$src1, GR64:$src2)>; 2114 2115// mul reg, mem 2116def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 2117 (IMUL16rm GR16:$src1, addr:$src2)>; 2118def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 2119 (IMUL32rm GR32:$src1, addr:$src2)>; 2120def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 2121 (IMUL64rm GR64:$src1, addr:$src2)>; 2122 2123// mul reg, imm 2124def : Pat<(mul GR16:$src1, imm:$src2), 2125 (IMUL16rri GR16:$src1, imm:$src2)>; 2126def : Pat<(mul GR32:$src1, imm:$src2), 2127 (IMUL32rri GR32:$src1, imm:$src2)>; 2128def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 2129 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 2130def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 2131 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 2132def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 2133 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 2134def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 2135 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 2136 2137// reg = mul mem, imm 2138def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 2139 (IMUL16rmi addr:$src1, imm:$src2)>; 2140def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 2141 (IMUL32rmi addr:$src1, imm:$src2)>; 2142def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 2143 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 2144def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 2145 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 2146def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 2147 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 2148def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 2149 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 2150 2151// Increment/Decrement reg. 2152// Do not make INC/DEC if it is slow 2153let Predicates = [UseIncDec] in { 2154 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>; 2155 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>; 2156 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>; 2157 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 2158 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>; 2159 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>; 2160 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>; 2161 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 2162 2163 def : Pat<(X86add_flag_nocf GR8:$src, -1), (DEC8r GR8:$src)>; 2164 def : Pat<(X86add_flag_nocf GR16:$src, -1), (DEC16r GR16:$src)>; 2165 def : Pat<(X86add_flag_nocf GR32:$src, -1), (DEC32r GR32:$src)>; 2166 def : Pat<(X86add_flag_nocf GR64:$src, -1), (DEC64r GR64:$src)>; 2167 def : Pat<(X86sub_flag_nocf GR8:$src, -1), (INC8r GR8:$src)>; 2168 def : Pat<(X86sub_flag_nocf GR16:$src, -1), (INC16r GR16:$src)>; 2169 def : Pat<(X86sub_flag_nocf GR32:$src, -1), (INC32r GR32:$src)>; 2170 def : Pat<(X86sub_flag_nocf GR64:$src, -1), (INC64r GR64:$src)>; 2171} 2172 2173// or reg/reg. 2174def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 2175def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 2176def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 2177def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 2178 2179// or reg/mem 2180def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 2181 (OR8rm GR8:$src1, addr:$src2)>; 2182def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 2183 (OR16rm GR16:$src1, addr:$src2)>; 2184def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 2185 (OR32rm GR32:$src1, addr:$src2)>; 2186def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 2187 (OR64rm GR64:$src1, addr:$src2)>; 2188 2189// or reg/imm 2190def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 2191def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 2192def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 2193def : Pat<(or GR16:$src1, i16immSExt8:$src2), 2194 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 2195def : Pat<(or GR32:$src1, i32immSExt8:$src2), 2196 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 2197def : Pat<(or GR64:$src1, i64immSExt8:$src2), 2198 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 2199def : Pat<(or GR64:$src1, i64immSExt32:$src2), 2200 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 2201 2202// xor reg/reg 2203def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 2204def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 2205def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 2206def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 2207 2208// xor reg/mem 2209def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 2210 (XOR8rm GR8:$src1, addr:$src2)>; 2211def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 2212 (XOR16rm GR16:$src1, addr:$src2)>; 2213def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 2214 (XOR32rm GR32:$src1, addr:$src2)>; 2215def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 2216 (XOR64rm GR64:$src1, addr:$src2)>; 2217 2218// xor reg/imm 2219def : Pat<(xor GR8:$src1, imm:$src2), 2220 (XOR8ri GR8:$src1, imm:$src2)>; 2221def : Pat<(xor GR16:$src1, imm:$src2), 2222 (XOR16ri GR16:$src1, imm:$src2)>; 2223def : Pat<(xor GR32:$src1, imm:$src2), 2224 (XOR32ri GR32:$src1, imm:$src2)>; 2225def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 2226 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 2227def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 2228 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 2229def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 2230 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 2231def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 2232 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 2233 2234// and reg/reg 2235def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 2236def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 2237def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 2238def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 2239 2240// and reg/mem 2241def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 2242 (AND8rm GR8:$src1, addr:$src2)>; 2243def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 2244 (AND16rm GR16:$src1, addr:$src2)>; 2245def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 2246 (AND32rm GR32:$src1, addr:$src2)>; 2247def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 2248 (AND64rm GR64:$src1, addr:$src2)>; 2249 2250// and reg/imm 2251def : Pat<(and GR8:$src1, imm:$src2), 2252 (AND8ri GR8:$src1, imm:$src2)>; 2253def : Pat<(and GR16:$src1, imm:$src2), 2254 (AND16ri GR16:$src1, imm:$src2)>; 2255def : Pat<(and GR32:$src1, imm:$src2), 2256 (AND32ri GR32:$src1, imm:$src2)>; 2257def : Pat<(and GR16:$src1, i16immSExt8:$src2), 2258 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 2259def : Pat<(and GR32:$src1, i32immSExt8:$src2), 2260 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 2261def : Pat<(and GR64:$src1, i64immSExt8:$src2), 2262 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 2263def : Pat<(and GR64:$src1, i64immSExt32:$src2), 2264 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 2265 2266// Bit scan instruction patterns to match explicit zero-undef behavior. 2267def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 2268def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 2269def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 2270def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 2271def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 2272def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 2273 2274// When HasMOVBE is enabled it is possible to get a non-legalized 2275// register-register 16 bit bswap. This maps it to a ROL instruction. 2276let Predicates = [HasMOVBE] in { 2277 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; 2278} 2279