1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the various pseudo instructions used by the compiler, 10// as well as Pat patterns used during instruction selection. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Pattern Matching Support 16 17def GetLo32XForm : SDNodeXForm<imm, [{ 18 // Transformation function: get the low 32 bits. 19 return getI32Imm((uint32_t)N->getZExtValue(), SDLoc(N)); 20}]>; 21 22 23//===----------------------------------------------------------------------===// 24// Random Pseudo Instructions. 25 26// PIC base construction. This expands to code that looks like this: 27// call $next_inst 28// popl %destreg" 29let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP], 30 SchedRW = [WriteJump] in 31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 32 "", []>; 33 34// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 35// a stack adjustment and the codegen must know that they may modify the stack 36// pointer before prolog-epilog rewriting occurs. 37// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 38// sub / add which can clobber EFLAGS. 39let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in { 40def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), 41 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 42 "#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>; 43def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 44 "#ADJCALLSTACKUP", 45 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 46 Requires<[NotLP64]>; 47} 48def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 49 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>; 50 51 52// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 53// a stack adjustment and the codegen must know that they may modify the stack 54// pointer before prolog-epilog rewriting occurs. 55// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 56// sub / add which can clobber EFLAGS. 57let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in { 58def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), 59 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 60 "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>; 61def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 62 "#ADJCALLSTACKUP", 63 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 64 Requires<[IsLP64]>; 65} 66def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 67 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>; 68 69let SchedRW = [WriteSystem] in { 70 71// x86-64 va_start lowering magic. 72let hasSideEffects = 1, mayStore = 1, Defs = [EFLAGS] in { 73def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 74 (outs), 75 (ins GR8:$al, i8mem:$regsavefi, variable_ops), 76 "#VASTART_SAVE_XMM_REGS $al, $regsavefi", 77 [(X86vastart_save_xmm_regs GR8:$al, addr:$regsavefi), 78 (implicit EFLAGS)]>; 79} 80 81let usesCustomInserter = 1, Defs = [EFLAGS] in { 82// The VAARG_64 and VAARG_X32 pseudo-instructions take the address of the 83// va_list, and place the address of the next argument into a register. 84let Defs = [EFLAGS] in { 85def VAARG_64 : I<0, Pseudo, 86 (outs GR64:$dst), 87 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 88 "#VAARG_64 $dst, $ap, $size, $mode, $align", 89 [(set GR64:$dst, 90 (X86vaarg64 addr:$ap, timm:$size, timm:$mode, timm:$align)), 91 (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>; 92def VAARG_X32 : I<0, Pseudo, 93 (outs GR32:$dst), 94 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 95 "#VAARG_X32 $dst, $ap, $size, $mode, $align", 96 [(set GR32:$dst, 97 (X86vaargx32 addr:$ap, timm:$size, timm:$mode, timm:$align)), 98 (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>; 99} 100 101// When using segmented stacks these are lowered into instructions which first 102// check if the current stacklet has enough free memory. If it does, memory is 103// allocated by bumping the stack pointer. Otherwise memory is allocated from 104// the heap. 105 106let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 107def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 108 "# variable sized alloca for segmented stacks", 109 [(set GR32:$dst, 110 (X86SegAlloca GR32:$size))]>, 111 Requires<[NotLP64]>; 112 113let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 114def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 115 "# variable sized alloca for segmented stacks", 116 [(set GR64:$dst, 117 (X86SegAlloca GR64:$size))]>, 118 Requires<[In64BitMode]>; 119 120// To protect against stack clash, dynamic allocation should perform a memory 121// probe at each page. 122 123let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 124def PROBED_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 125 "# variable sized alloca with probing", 126 [(set GR32:$dst, 127 (X86ProbedAlloca GR32:$size))]>, 128 Requires<[NotLP64]>; 129 130let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 131def PROBED_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 132 "# variable sized alloca with probing", 133 [(set GR64:$dst, 134 (X86ProbedAlloca GR64:$size))]>, 135 Requires<[In64BitMode]>; 136} 137 138let hasNoSchedulingInfo = 1 in 139def STACKALLOC_W_PROBING : I<0, Pseudo, (outs), (ins i64imm:$stacksize), 140 "# fixed size alloca with probing", 141 []>; 142 143// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 144// targets. These calls are needed to probe the stack when allocating more than 145// 4k bytes in one go. Touching the stack at 4K increments is necessary to 146// ensure that the guard pages used by the OS virtual memory manager are 147// allocated in correct sequence. 148// The main point of having separate instruction are extra unmodelled effects 149// (compared to ordinary calls) like stack pointer change. 150 151let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 152def DYN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size), 153 "# dynamic stack allocation", 154 [(X86DynAlloca GR32:$size)]>, 155 Requires<[NotLP64]>; 156 157let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 158def DYN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size), 159 "# dynamic stack allocation", 160 [(X86DynAlloca GR64:$size)]>, 161 Requires<[In64BitMode]>; 162} // SchedRW 163 164// These instructions XOR the frame pointer into a GPR. They are used in some 165// stack protection schemes. These are post-RA pseudos because we only know the 166// frame register after register allocation. 167let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in { 168 def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src), 169 "xorl\t$$FP, $src", []>, 170 Requires<[NotLP64]>, Sched<[WriteALU]>; 171 def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src), 172 "xorq\t$$FP $src", []>, 173 Requires<[In64BitMode]>, Sched<[WriteALU]>; 174} 175 176//===----------------------------------------------------------------------===// 177// EH Pseudo Instructions 178// 179let SchedRW = [WriteSystem] in { 180let isTerminator = 1, isReturn = 1, isBarrier = 1, 181 hasCtrlDep = 1, isCodeGenOnly = 1 in { 182def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 183 "ret\t#eh_return, addr: $addr", 184 [(X86ehret GR32:$addr)]>, Sched<[WriteJumpLd]>; 185 186} 187 188let isTerminator = 1, isReturn = 1, isBarrier = 1, 189 hasCtrlDep = 1, isCodeGenOnly = 1 in { 190def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 191 "ret\t#eh_return, addr: $addr", 192 [(X86ehret GR64:$addr)]>, Sched<[WriteJumpLd]>; 193 194} 195 196let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 197 isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1 in { 198 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", 199 [(cleanupret bb)]>; 200 201 // CATCHRET needs a custom inserter for SEH. 202 let usesCustomInserter = 1 in 203 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), 204 "# CATCHRET", 205 [(catchret bb:$dst, bb:$from)]>; 206} 207 208let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 209 usesCustomInserter = 1 in { 210 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 211 "#EH_SJLJ_SETJMP32", 212 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 213 Requires<[Not64BitMode]>; 214 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 215 "#EH_SJLJ_SETJMP64", 216 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 217 Requires<[In64BitMode]>; 218 let isTerminator = 1 in { 219 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 220 "#EH_SJLJ_LONGJMP32", 221 [(X86eh_sjlj_longjmp addr:$buf)]>, 222 Requires<[Not64BitMode]>; 223 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 224 "#EH_SJLJ_LONGJMP64", 225 [(X86eh_sjlj_longjmp addr:$buf)]>, 226 Requires<[In64BitMode]>; 227 } 228} 229 230let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 231 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 232 "#EH_SjLj_Setup\t$dst", []>; 233} 234} // SchedRW 235 236//===----------------------------------------------------------------------===// 237// Pseudo instructions used by unwind info. 238// 239let isPseudo = 1, SchedRW = [WriteSystem] in { 240 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), 241 "#SEH_PushReg $reg", []>; 242 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 243 "#SEH_SaveReg $reg, $dst", []>; 244 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 245 "#SEH_SaveXMM $reg, $dst", []>; 246 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), 247 "#SEH_StackAlloc $size", []>; 248 def SEH_StackAlign : I<0, Pseudo, (outs), (ins i32imm:$align), 249 "#SEH_StackAlign $align", []>; 250 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), 251 "#SEH_SetFrame $reg, $offset", []>; 252 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), 253 "#SEH_PushFrame $mode", []>; 254 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), 255 "#SEH_EndPrologue", []>; 256 def SEH_Epilogue : I<0, Pseudo, (outs), (ins), 257 "#SEH_Epilogue", []>; 258} 259 260//===----------------------------------------------------------------------===// 261// Pseudo instructions used by KCFI. 262//===----------------------------------------------------------------------===// 263let 264 Defs = [R10, R11, EFLAGS] in { 265def KCFI_CHECK : PseudoI< 266 (outs), (ins GR64:$ptr, i32imm:$type), []>, Sched<[]>; 267} 268 269//===----------------------------------------------------------------------===// 270// Pseudo instructions used by address sanitizer. 271//===----------------------------------------------------------------------===// 272let 273 Defs = [R10, R11, EFLAGS] in { 274def ASAN_CHECK_MEMACCESS : PseudoI< 275 (outs), (ins GR64PLTSafe:$addr, i32imm:$accessinfo), 276 [(int_asan_check_memaccess GR64PLTSafe:$addr, (i32 timm:$accessinfo))]>, 277 Sched<[]>; 278} 279 280//===----------------------------------------------------------------------===// 281// Pseudo instructions used by segmented stacks. 282// 283 284// This is lowered into a RET instruction by MCInstLower. We need 285// this so that we don't have to have a MachineBasicBlock which ends 286// with a RET and also has successors. 287let isPseudo = 1, SchedRW = [WriteJumpLd] in { 288def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>; 289 290// This instruction is lowered to a RET followed by a MOV. The two 291// instructions are not generated on a higher level since then the 292// verifier sees a MachineBasicBlock ending with a non-terminator. 293def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>; 294} 295 296//===----------------------------------------------------------------------===// 297// Alias Instructions 298//===----------------------------------------------------------------------===// 299 300// Alias instruction mapping movr0 to xor. 301// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 302let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 303 isPseudo = 1, isMoveImm = 1, AddedComplexity = 10 in 304def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 305 [(set GR32:$dst, 0)]>, Sched<[WriteZero]>; 306 307// Other widths can also make use of the 32-bit xor, which may have a smaller 308// encoding and avoid partial register updates. 309let AddedComplexity = 10 in { 310def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 311def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 312def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>; 313} 314 315let Predicates = [OptForSize, Not64BitMode], 316 AddedComplexity = 10 in { 317 let SchedRW = [WriteALU] in { 318 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, 319 // which only require 3 bytes compared to MOV32ri which requires 5. 320 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { 321 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 322 [(set GR32:$dst, 1)]>; 323 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 324 [(set GR32:$dst, -1)]>; 325 } 326 } // SchedRW 327 328 // MOV16ri is 4 bytes, so the instructions above are smaller. 329 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; 330 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; 331} 332 333let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5, 334 SchedRW = [WriteALU] in { 335// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1. 336def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "", 337 [(set GR32:$dst, i32immSExt8:$src)]>, 338 Requires<[OptForMinSize, NotWin64WithoutFP]>; 339def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", 340 [(set GR64:$dst, i64immSExt8:$src)]>, 341 Requires<[OptForMinSize, NotWin64WithoutFP]>; 342} 343 344// Materialize i64 constant where top 32-bits are zero. This could theoretically 345// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 346// that would make it more difficult to rematerialize. 347let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 348 isPseudo = 1, SchedRW = [WriteMove] in 349def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "", 350 [(set GR64:$dst, i64immZExt32:$src)]>; 351 352// This 64-bit pseudo-move can also be used for labels in the x86-64 small code 353// model. 354def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [X86Wrapper]>; 355def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>; 356 357// Use sbb to materialize carry bit. 358let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteADC], 359 hasSideEffects = 0 in { 360// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 361// However, Pat<> can't replicate the destination reg into the inputs of the 362// result. 363def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", []>; 364def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", []>; 365} // isCodeGenOnly 366 367//===----------------------------------------------------------------------===// 368// String Pseudo Instructions 369// 370let SchedRW = [WriteMicrocoded] in { 371let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 372def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), 373 "{rep;movsb (%esi), %es:(%edi)|rep movsb es:[edi], [esi]}", 374 [(X86rep_movs i8)]>, REP, AdSize32, 375 Requires<[NotLP64]>; 376def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), 377 "{rep;movsw (%esi), %es:(%edi)|rep movsw es:[edi], [esi]}", 378 [(X86rep_movs i16)]>, REP, AdSize32, OpSize16, 379 Requires<[NotLP64]>; 380def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), 381 "{rep;movsl (%esi), %es:(%edi)|rep movsd es:[edi], [esi]}", 382 [(X86rep_movs i32)]>, REP, AdSize32, OpSize32, 383 Requires<[NotLP64]>; 384def REP_MOVSQ_32 : RI<0xA5, RawFrm, (outs), (ins), 385 "{rep;movsq (%esi), %es:(%edi)|rep movsq es:[edi], [esi]}", 386 [(X86rep_movs i64)]>, REP, AdSize32, 387 Requires<[NotLP64, In64BitMode]>; 388} 389 390let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 391def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), 392 "{rep;movsb (%rsi), %es:(%rdi)|rep movsb es:[rdi], [rsi]}", 393 [(X86rep_movs i8)]>, REP, AdSize64, 394 Requires<[IsLP64]>; 395def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), 396 "{rep;movsw (%rsi), %es:(%rdi)|rep movsw es:[rdi], [rsi]}", 397 [(X86rep_movs i16)]>, REP, AdSize64, OpSize16, 398 Requires<[IsLP64]>; 399def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), 400 "{rep;movsl (%rsi), %es:(%rdi)|rep movsdi es:[rdi], [rsi]}", 401 [(X86rep_movs i32)]>, REP, AdSize64, OpSize32, 402 Requires<[IsLP64]>; 403def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), 404 "{rep;movsq (%rsi), %es:(%rdi)|rep movsq es:[rdi], [rsi]}", 405 [(X86rep_movs i64)]>, REP, AdSize64, 406 Requires<[IsLP64]>; 407} 408 409// FIXME: Should use "(X86rep_stos AL)" as the pattern. 410let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 411 let Uses = [AL,ECX,EDI] in 412 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), 413 "{rep;stosb %al, %es:(%edi)|rep stosb es:[edi], al}", 414 [(X86rep_stos i8)]>, REP, AdSize32, 415 Requires<[NotLP64]>; 416 let Uses = [AX,ECX,EDI] in 417 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), 418 "{rep;stosw %ax, %es:(%edi)|rep stosw es:[edi], ax}", 419 [(X86rep_stos i16)]>, REP, AdSize32, OpSize16, 420 Requires<[NotLP64]>; 421 let Uses = [EAX,ECX,EDI] in 422 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), 423 "{rep;stosl %eax, %es:(%edi)|rep stosd es:[edi], eax}", 424 [(X86rep_stos i32)]>, REP, AdSize32, OpSize32, 425 Requires<[NotLP64]>; 426 let Uses = [RAX,RCX,RDI] in 427 def REP_STOSQ_32 : RI<0xAB, RawFrm, (outs), (ins), 428 "{rep;stosq %rax, %es:(%edi)|rep stosq es:[edi], rax}", 429 [(X86rep_stos i64)]>, REP, AdSize32, 430 Requires<[NotLP64, In64BitMode]>; 431} 432 433let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 434 let Uses = [AL,RCX,RDI] in 435 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), 436 "{rep;stosb %al, %es:(%rdi)|rep stosb es:[rdi], al}", 437 [(X86rep_stos i8)]>, REP, AdSize64, 438 Requires<[IsLP64]>; 439 let Uses = [AX,RCX,RDI] in 440 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), 441 "{rep;stosw %ax, %es:(%rdi)|rep stosw es:[rdi], ax}", 442 [(X86rep_stos i16)]>, REP, AdSize64, OpSize16, 443 Requires<[IsLP64]>; 444 let Uses = [RAX,RCX,RDI] in 445 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), 446 "{rep;stosl %eax, %es:(%rdi)|rep stosd es:[rdi], eax}", 447 [(X86rep_stos i32)]>, REP, AdSize64, OpSize32, 448 Requires<[IsLP64]>; 449 450 let Uses = [RAX,RCX,RDI] in 451 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), 452 "{rep;stosq %rax, %es:(%rdi)|rep stosq es:[rdi], rax}", 453 [(X86rep_stos i64)]>, REP, AdSize64, 454 Requires<[IsLP64]>; 455} 456} // SchedRW 457 458//===----------------------------------------------------------------------===// 459// Thread Local Storage Instructions 460// 461let SchedRW = [WriteSystem] in { 462 463// ELF TLS Support 464// All calls clobber the non-callee saved registers. ESP is marked as 465// a use to prevent stack-pointer assignments that appear immediately 466// before calls from potentially appearing dead. 467let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 468 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 469 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 470 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 471 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 472 usesCustomInserter = 1, Uses = [ESP, SSP] in { 473def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 474 "# TLS_addr32", 475 [(X86tlsaddr tls32addr:$sym)]>, 476 Requires<[Not64BitMode]>; 477def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 478 "# TLS_base_addr32", 479 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 480 Requires<[Not64BitMode]>; 481} 482 483// All calls clobber the non-callee saved registers. RSP is marked as 484// a use to prevent stack-pointer assignments that appear immediately 485// before calls from potentially appearing dead. 486let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 487 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 488 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 489 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 490 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 491 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 492 usesCustomInserter = 1, Uses = [RSP, SSP] in { 493def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 494 "# TLS_addr64", 495 [(X86tlsaddr tls64addr:$sym)]>, 496 Requires<[In64BitMode, IsLP64]>; 497def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 498 "# TLS_base_addr64", 499 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 500 Requires<[In64BitMode, IsLP64]>; 501def TLS_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 502 "# TLS_addrX32", 503 [(X86tlsaddr tls32addr:$sym)]>, 504 Requires<[In64BitMode, NotLP64]>; 505def TLS_base_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 506 "# TLS_base_addrX32", 507 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 508 Requires<[In64BitMode, NotLP64]>; 509} 510 511// TLSDESC only clobbers EAX and EFLAGS. ESP is marked as a use to prevent 512// stack-pointer assignments that appear immediately before calls from 513// potentially appearing dead. 514let Defs = [EAX, EFLAGS], usesCustomInserter = 1, Uses = [RSP, SSP] in { 515 def TLS_desc32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 516 "# TLS_desc32", [(X86tlsdesc tls32addr:$sym)]>; 517 def TLS_desc64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 518 "# TLS_desc64", [(X86tlsdesc tls64addr:$sym)]>; 519} 520 521// Darwin TLS Support 522// For i386, the address of the thunk is passed on the stack, on return the 523// address of the variable is in %eax. %ecx is trashed during the function 524// call. All other registers are preserved. 525let Defs = [EAX, ECX, EFLAGS, DF], 526 Uses = [ESP, SSP], 527 usesCustomInserter = 1 in 528def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 529 "# TLSCall_32", 530 [(X86TLSCall addr:$sym)]>, 531 Requires<[Not64BitMode]>; 532 533// For x86_64, the address of the thunk is passed in %rdi, but the 534// pseudo directly use the symbol, so do not add an implicit use of 535// %rdi. The lowering will do the right thing with RDI. 536// On return the address of the variable is in %rax. All other 537// registers are preserved. 538let Defs = [RAX, EFLAGS, DF], 539 Uses = [RSP, SSP], 540 usesCustomInserter = 1 in 541def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 542 "# TLSCall_64", 543 [(X86TLSCall addr:$sym)]>, 544 Requires<[In64BitMode]>; 545} // SchedRW 546 547//===----------------------------------------------------------------------===// 548// Conditional Move Pseudo Instructions 549 550// CMOV* - Used to implement the SELECT DAG operation. Expanded after 551// instruction selection into a branch sequence. 552multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> { 553 def CMOV#NAME : I<0, Pseudo, 554 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), 555 "#CMOV_"#NAME#" PSEUDO!", 556 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, timm:$cond, 557 EFLAGS)))]>; 558} 559 560let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in { 561 // X86 doesn't have 8-bit conditional moves. Use a customInserter to 562 // emit control flow. An alternative to this is to mark i8 SELECT as Promote, 563 // however that requires promoting the operands, and can induce additional 564 // i8 register pressure. 565 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>; 566 567 let Predicates = [NoCMOV] in { 568 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>; 569 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>; 570 } // Predicates = [NoCMOV] 571 572 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 573 // SSE1/SSE2. 574 let Predicates = [FPStackf32] in 575 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>; 576 577 let Predicates = [FPStackf64] in 578 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>; 579 580 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>; 581 582 let Predicates = [HasMMX] in 583 defm _VR64 : CMOVrr_PSEUDO<VR64, x86mmx>; 584 585 let Predicates = [HasSSE1,NoAVX512] in 586 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 587 let Predicates = [HasSSE2,NoAVX512] in { 588 defm _FR16 : CMOVrr_PSEUDO<FR16, f16>; 589 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>; 590 } 591 let Predicates = [HasAVX512] in { 592 defm _FR16X : CMOVrr_PSEUDO<FR16X, f16>; 593 defm _FR32X : CMOVrr_PSEUDO<FR32X, f32>; 594 defm _FR64X : CMOVrr_PSEUDO<FR64X, f64>; 595 } 596 let Predicates = [NoVLX] in { 597 defm _VR128 : CMOVrr_PSEUDO<VR128, v2i64>; 598 defm _VR256 : CMOVrr_PSEUDO<VR256, v4i64>; 599 } 600 let Predicates = [HasVLX] in { 601 defm _VR128X : CMOVrr_PSEUDO<VR128X, v2i64>; 602 defm _VR256X : CMOVrr_PSEUDO<VR256X, v4i64>; 603 } 604 defm _VR512 : CMOVrr_PSEUDO<VR512, v8i64>; 605 defm _VK1 : CMOVrr_PSEUDO<VK1, v1i1>; 606 defm _VK2 : CMOVrr_PSEUDO<VK2, v2i1>; 607 defm _VK4 : CMOVrr_PSEUDO<VK4, v4i1>; 608 defm _VK8 : CMOVrr_PSEUDO<VK8, v8i1>; 609 defm _VK16 : CMOVrr_PSEUDO<VK16, v16i1>; 610 defm _VK32 : CMOVrr_PSEUDO<VK32, v32i1>; 611 defm _VK64 : CMOVrr_PSEUDO<VK64, v64i1>; 612} // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] 613 614def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 615 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 616 617let Predicates = [NoVLX] in { 618 def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 619 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 620 def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 621 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 622 def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 623 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 624 def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 625 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 626 def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 627 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 628 629 def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 630 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 631 def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 632 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 633 def : Pat<(v8i32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 634 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 635 def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 636 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 637 def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 638 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 639} 640let Predicates = [HasVLX] in { 641 def : Pat<(v16i8 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 642 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 643 def : Pat<(v8i16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 644 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 645 def : Pat<(v8f16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 646 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 647 def : Pat<(v4i32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 648 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 649 def : Pat<(v4f32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 650 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 651 def : Pat<(v2f64 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 652 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 653 654 def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 655 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 656 def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 657 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 658 def : Pat<(v16f16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 659 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 660 def : Pat<(v8i32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 661 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 662 def : Pat<(v8f32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 663 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 664 def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 665 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 666} 667 668def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 669 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 670def : Pat<(v32i16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 671 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 672def : Pat<(v32f16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 673 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 674def : Pat<(v16i32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 675 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 676def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 677 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 678def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 679 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 680 681//===----------------------------------------------------------------------===// 682// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 683//===----------------------------------------------------------------------===// 684 685// FIXME: Use normal instructions and add lock prefix dynamically. 686 687// Memory barriers 688 689let isCodeGenOnly = 1, Defs = [EFLAGS] in 690def OR32mi8Locked : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$zero), 691 "or{l}\t{$zero, $dst|$dst, $zero}", []>, 692 Requires<[Not64BitMode]>, OpSize32, LOCK, 693 Sched<[WriteALURMW]>; 694 695// RegOpc corresponds to the mr version of the instruction 696// ImmOpc corresponds to the mi version of the instruction 697// ImmOpc8 corresponds to the mi8 version of the instruction 698// ImmMod corresponds to the instruction format of the mi and mi8 versions 699multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 700 Format ImmMod, SDNode Op, string mnemonic> { 701let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 702 SchedRW = [WriteALURMW] in { 703 704def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 705 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 706 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 707 !strconcat(mnemonic, "{b}\t", 708 "{$src2, $dst|$dst, $src2}"), 709 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK; 710 711def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 712 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 713 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 714 !strconcat(mnemonic, "{w}\t", 715 "{$src2, $dst|$dst, $src2}"), 716 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>, 717 OpSize16, LOCK; 718 719def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 720 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 721 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 722 !strconcat(mnemonic, "{l}\t", 723 "{$src2, $dst|$dst, $src2}"), 724 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>, 725 OpSize32, LOCK; 726 727def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 728 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 729 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 730 !strconcat(mnemonic, "{q}\t", 731 "{$src2, $dst|$dst, $src2}"), 732 [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK; 733 734// NOTE: These are order specific, we want the mi8 forms to be listed 735// first so that they are slightly preferred to the mi forms. 736def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 737 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 738 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 739 !strconcat(mnemonic, "{w}\t", 740 "{$src2, $dst|$dst, $src2}"), 741 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>, 742 OpSize16, LOCK; 743 744def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 745 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 746 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 747 !strconcat(mnemonic, "{l}\t", 748 "{$src2, $dst|$dst, $src2}"), 749 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>, 750 OpSize32, LOCK; 751 752def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 753 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 754 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 755 !strconcat(mnemonic, "{q}\t", 756 "{$src2, $dst|$dst, $src2}"), 757 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>, 758 LOCK; 759 760def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 761 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 762 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 763 !strconcat(mnemonic, "{b}\t", 764 "{$src2, $dst|$dst, $src2}"), 765 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK; 766 767def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 768 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 769 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 770 !strconcat(mnemonic, "{w}\t", 771 "{$src2, $dst|$dst, $src2}"), 772 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>, 773 OpSize16, LOCK; 774 775def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 776 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 777 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 778 !strconcat(mnemonic, "{l}\t", 779 "{$src2, $dst|$dst, $src2}"), 780 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>, 781 OpSize32, LOCK; 782 783def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 784 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 785 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 786 !strconcat(mnemonic, "{q}\t", 787 "{$src2, $dst|$dst, $src2}"), 788 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>, 789 LOCK; 790} 791 792} 793 794defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">; 795defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">; 796defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">; 797defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; 798defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; 799 800let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 801 SchedRW = [WriteALURMW] in { 802 let Predicates = [UseIncDec] in { 803 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), 804 "inc{b}\t$dst", 805 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i8 1)))]>, 806 LOCK; 807 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), 808 "inc{w}\t$dst", 809 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i16 1)))]>, 810 OpSize16, LOCK; 811 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), 812 "inc{l}\t$dst", 813 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i32 1)))]>, 814 OpSize32, LOCK; 815 816 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), 817 "dec{b}\t$dst", 818 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i8 1)))]>, 819 LOCK; 820 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), 821 "dec{w}\t$dst", 822 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i16 1)))]>, 823 OpSize16, LOCK; 824 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), 825 "dec{l}\t$dst", 826 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i32 1)))]>, 827 OpSize32, LOCK; 828 } 829 830 let Predicates = [UseIncDec, In64BitMode] in { 831 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), 832 "inc{q}\t$dst", 833 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i64 1)))]>, 834 LOCK; 835 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), 836 "dec{q}\t$dst", 837 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i64 1)))]>, 838 LOCK; 839 } 840} 841 842let Predicates = [UseIncDec] in { 843 // Additional patterns for -1 constant. 844 def : Pat<(X86lock_add addr:$dst, (i8 -1)), (LOCK_DEC8m addr:$dst)>; 845 def : Pat<(X86lock_add addr:$dst, (i16 -1)), (LOCK_DEC16m addr:$dst)>; 846 def : Pat<(X86lock_add addr:$dst, (i32 -1)), (LOCK_DEC32m addr:$dst)>; 847 def : Pat<(X86lock_sub addr:$dst, (i8 -1)), (LOCK_INC8m addr:$dst)>; 848 def : Pat<(X86lock_sub addr:$dst, (i16 -1)), (LOCK_INC16m addr:$dst)>; 849 def : Pat<(X86lock_sub addr:$dst, (i32 -1)), (LOCK_INC32m addr:$dst)>; 850} 851 852let Predicates = [UseIncDec, In64BitMode] in { 853 // Additional patterns for -1 constant. 854 def : Pat<(X86lock_add addr:$dst, (i64 -1)), (LOCK_DEC64m addr:$dst)>; 855 def : Pat<(X86lock_sub addr:$dst, (i64 -1)), (LOCK_INC64m addr:$dst)>; 856} 857 858// Atomic bit test. 859def X86LBTest : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisPtrTy<1>, 860 SDTCisVT<2, i8>, SDTCisVT<3, i32>]>; 861def x86bts : SDNode<"X86ISD::LBTS", X86LBTest, 862 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 863def x86btc : SDNode<"X86ISD::LBTC", X86LBTest, 864 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 865def x86btr : SDNode<"X86ISD::LBTR", X86LBTest, 866 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 867 868def X86LBTestRM : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>, 869 SDTCisInt<2>]>; 870 871def x86_rm_bts : SDNode<"X86ISD::LBTS_RM", X86LBTestRM, 872 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 873def x86_rm_btc : SDNode<"X86ISD::LBTC_RM", X86LBTestRM, 874 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 875def x86_rm_btr : SDNode<"X86ISD::LBTR_RM", X86LBTestRM, 876 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 877 878 879multiclass ATOMIC_LOGIC_OP<Format Form, string s> { 880 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 881 SchedRW = [WriteBitTestSetRegRMW] in { 882 def 16m : Ii8<0xBA, Form, (outs), (ins i16mem:$src1, i8imm:$src2), 883 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"), 884 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 16)))]>, 885 OpSize16, TB, LOCK; 886 def 32m : Ii8<0xBA, Form, (outs), (ins i32mem:$src1, i8imm:$src2), 887 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"), 888 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 32)))]>, 889 OpSize32, TB, LOCK; 890 def 64m : RIi8<0xBA, Form, (outs), (ins i64mem:$src1, i8imm:$src2), 891 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"), 892 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 64)))]>, 893 TB, LOCK; 894 } 895} 896 897multiclass ATOMIC_LOGIC_OP_RM<bits<8> Opc8, string s> { 898 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 899 SchedRW = [WriteBitTestSetRegRMW] in { 900 def 16rm : I<Opc8, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 901 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"), 902 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR16:$src2))]>, 903 OpSize16, TB, LOCK; 904 def 32rm : I<Opc8, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 905 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"), 906 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR32:$src2))]>, 907 OpSize32, TB, LOCK; 908 def 64rm : RI<Opc8, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 909 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"), 910 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR64:$src2))]>, 911 TB, LOCK; 912 } 913} 914 915 916defm LOCK_BTS : ATOMIC_LOGIC_OP<MRM5m, "bts">; 917defm LOCK_BTC : ATOMIC_LOGIC_OP<MRM7m, "btc">; 918defm LOCK_BTR : ATOMIC_LOGIC_OP<MRM6m, "btr">; 919 920defm LOCK_BTS_RM : ATOMIC_LOGIC_OP_RM<0xAB, "bts">; 921defm LOCK_BTC_RM : ATOMIC_LOGIC_OP_RM<0xBB, "btc">; 922defm LOCK_BTR_RM : ATOMIC_LOGIC_OP_RM<0xB3, "btr">; 923 924// Atomic compare and swap. 925multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 926 string mnemonic, SDPatternOperator frag> { 927let isCodeGenOnly = 1, SchedRW = [WriteCMPXCHGRMW] in { 928 let Defs = [AL, EFLAGS], Uses = [AL] in 929 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 930 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 931 [(frag addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; 932 let Defs = [AX, EFLAGS], Uses = [AX] in 933 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 934 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 935 [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK; 936 let Defs = [EAX, EFLAGS], Uses = [EAX] in 937 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 938 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 939 [(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK; 940 let Defs = [RAX, EFLAGS], Uses = [RAX] in 941 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 942 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 943 [(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK; 944} 945} 946 947let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 948 Predicates = [HasCX8], SchedRW = [WriteCMPXCHGRMW], 949 isCodeGenOnly = 1, usesCustomInserter = 1 in { 950def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr), 951 "cmpxchg8b\t$ptr", 952 [(X86cas8 addr:$ptr)]>, TB, LOCK; 953} 954 955let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 956 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 957 isCodeGenOnly = 1, mayLoad = 1, mayStore = 1, hasSideEffects = 0 in { 958def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr), 959 "cmpxchg16b\t$ptr", 960 []>, TB, LOCK; 961} 962 963// This pseudo must be used when the frame uses RBX as 964// the base pointer. Indeed, in such situation RBX is a reserved 965// register and the register allocator will ignore any use/def of 966// it. In other words, the register will not fix the clobbering of 967// RBX that will happen when setting the arguments for the instrucion. 968// 969// Unlike the actual related instruction, we mark that this one 970// defines RBX (instead of using RBX). 971// The rationale is that we will define RBX during the expansion of 972// the pseudo. The argument feeding RBX is rbx_input. 973// 974// The additional argument, $rbx_save, is a temporary register used to 975// save the value of RBX across the actual instruction. 976// 977// To make sure the register assigned to $rbx_save does not interfere with 978// the definition of the actual instruction, we use a definition $dst which 979// is tied to $rbx_save. That way, the live-range of $rbx_save spans across 980// the instruction and we are sure we will have a valid register to restore 981// the value of RBX. 982let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX], 983 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 984 isCodeGenOnly = 1, isPseudo = 1, 985 mayLoad = 1, mayStore = 1, hasSideEffects = 0, 986 Constraints = "$rbx_save = $dst" in { 987def LCMPXCHG16B_SAVE_RBX : 988 I<0, Pseudo, (outs GR64:$dst), 989 (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), "", []>; 990} 991 992// Pseudo instruction that doesn't read/write RBX. Will be turned into either 993// LCMPXCHG16B_SAVE_RBX or LCMPXCHG16B via a custom inserter. 994let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RCX, RDX], 995 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 996 isCodeGenOnly = 1, isPseudo = 1, 997 mayLoad = 1, mayStore = 1, hasSideEffects = 0, 998 usesCustomInserter = 1 in { 999def LCMPXCHG16B_NO_RBX : 1000 I<0, Pseudo, (outs), (ins i128mem:$ptr, GR64:$rbx_input), "", 1001 [(X86cas16 addr:$ptr, GR64:$rbx_input)]>; 1002} 1003 1004// This pseudo must be used when the frame uses RBX/EBX as 1005// the base pointer. 1006// cf comment for LCMPXCHG16B_SAVE_RBX. 1007let Defs = [EBX], Uses = [ECX, EAX], 1008 Predicates = [HasMWAITX], SchedRW = [WriteSystem], 1009 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst" in { 1010def MWAITX_SAVE_RBX : 1011 I<0, Pseudo, (outs GR64:$dst), 1012 (ins GR32:$ebx_input, GR64:$rbx_save), 1013 "mwaitx", 1014 []>; 1015} 1016 1017// Pseudo mwaitx instruction to use for custom insertion. 1018let Predicates = [HasMWAITX], SchedRW = [WriteSystem], 1019 isCodeGenOnly = 1, isPseudo = 1, 1020 usesCustomInserter = 1 in { 1021def MWAITX : 1022 I<0, Pseudo, (outs), (ins GR32:$ecx, GR32:$eax, GR32:$ebx), 1023 "mwaitx", 1024 [(int_x86_mwaitx GR32:$ecx, GR32:$eax, GR32:$ebx)]>; 1025} 1026 1027 1028defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>; 1029 1030// Atomic exchange and add 1031multiclass ATOMIC_RMW_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 1032 string frag> { 1033 let Constraints = "$val = $dst", Defs = [EFLAGS], mayLoad = 1, mayStore = 1, 1034 isCodeGenOnly = 1, SchedRW = [WriteALURMW] in { 1035 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 1036 (ins GR8:$val, i8mem:$ptr), 1037 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 1038 [(set GR8:$dst, 1039 (!cast<PatFrag>(frag # "_i8") addr:$ptr, GR8:$val))]>; 1040 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 1041 (ins GR16:$val, i16mem:$ptr), 1042 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 1043 [(set 1044 GR16:$dst, 1045 (!cast<PatFrag>(frag # "_i16") addr:$ptr, GR16:$val))]>, 1046 OpSize16; 1047 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 1048 (ins GR32:$val, i32mem:$ptr), 1049 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 1050 [(set 1051 GR32:$dst, 1052 (!cast<PatFrag>(frag # "_i32") addr:$ptr, GR32:$val))]>, 1053 OpSize32; 1054 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 1055 (ins GR64:$val, i64mem:$ptr), 1056 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 1057 [(set 1058 GR64:$dst, 1059 (!cast<PatFrag>(frag # "_i64") addr:$ptr, GR64:$val))]>; 1060 } 1061} 1062 1063defm LXADD : ATOMIC_RMW_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK; 1064 1065/* The following multiclass tries to make sure that in code like 1066 * x.store (immediate op x.load(acquire), release) 1067 * and 1068 * x.store (register op x.load(acquire), release) 1069 * an operation directly on memory is generated instead of wasting a register. 1070 * It is not automatic as atomic_store/load are only lowered to MOV instructions 1071 * extremely late to prevent them from being accidentally reordered in the backend 1072 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) 1073 */ 1074multiclass RELEASE_BINOP_MI<string Name, SDNode op> { 1075 def : Pat<(atomic_store_8 (op (atomic_load_8 addr:$dst), (i8 imm:$src)), 1076 addr:$dst), 1077 (!cast<Instruction>(Name#"8mi") addr:$dst, imm:$src)>; 1078 def : Pat<(atomic_store_16 (op (atomic_load_16 addr:$dst), (i16 imm:$src)), 1079 addr:$dst), 1080 (!cast<Instruction>(Name#"16mi") addr:$dst, imm:$src)>; 1081 def : Pat<(atomic_store_32 (op (atomic_load_32 addr:$dst), (i32 imm:$src)), 1082 addr:$dst), 1083 (!cast<Instruction>(Name#"32mi") addr:$dst, imm:$src)>; 1084 def : Pat<(atomic_store_64 (op (atomic_load_64 addr:$dst), (i64immSExt32:$src)), 1085 addr:$dst), 1086 (!cast<Instruction>(Name#"64mi32") addr:$dst, (i64immSExt32:$src))>; 1087 def : Pat<(atomic_store_8 (op (atomic_load_8 addr:$dst), (i8 GR8:$src)), addr:$dst), 1088 (!cast<Instruction>(Name#"8mr") addr:$dst, GR8:$src)>; 1089 def : Pat<(atomic_store_16 (op (atomic_load_16 addr:$dst), (i16 GR16:$src)), 1090 addr:$dst), 1091 (!cast<Instruction>(Name#"16mr") addr:$dst, GR16:$src)>; 1092 def : Pat<(atomic_store_32 (op (atomic_load_32 addr:$dst), (i32 GR32:$src)), 1093 addr:$dst), 1094 (!cast<Instruction>(Name#"32mr") addr:$dst, GR32:$src)>; 1095 def : Pat<(atomic_store_64 (op (atomic_load_64 addr:$dst), (i64 GR64:$src)), 1096 addr:$dst), 1097 (!cast<Instruction>(Name#"64mr") addr:$dst, GR64:$src)>; 1098} 1099defm : RELEASE_BINOP_MI<"ADD", add>; 1100defm : RELEASE_BINOP_MI<"AND", and>; 1101defm : RELEASE_BINOP_MI<"OR", or>; 1102defm : RELEASE_BINOP_MI<"XOR", xor>; 1103defm : RELEASE_BINOP_MI<"SUB", sub>; 1104 1105// Atomic load + floating point patterns. 1106// FIXME: This could also handle SIMD operations with *ps and *pd instructions. 1107multiclass ATOMIC_LOAD_FP_BINOP_MI<string Name, SDNode op> { 1108 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1109 (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>, 1110 Requires<[UseSSE1]>; 1111 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1112 (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>, 1113 Requires<[UseAVX]>; 1114 def : Pat<(op FR32X:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1115 (!cast<Instruction>("V"#Name#"SSZrm") FR32X:$src1, addr:$src2)>, 1116 Requires<[HasAVX512]>; 1117 1118 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1119 (!cast<Instruction>(Name#"SDrm") FR64:$src1, addr:$src2)>, 1120 Requires<[UseSSE1]>; 1121 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1122 (!cast<Instruction>("V"#Name#"SDrm") FR64:$src1, addr:$src2)>, 1123 Requires<[UseAVX]>; 1124 def : Pat<(op FR64X:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1125 (!cast<Instruction>("V"#Name#"SDZrm") FR64X:$src1, addr:$src2)>, 1126 Requires<[HasAVX512]>; 1127} 1128defm : ATOMIC_LOAD_FP_BINOP_MI<"ADD", fadd>; 1129defm : ATOMIC_LOAD_FP_BINOP_MI<"SUB", fsub>; 1130defm : ATOMIC_LOAD_FP_BINOP_MI<"MUL", fmul>; 1131defm : ATOMIC_LOAD_FP_BINOP_MI<"DIV", fdiv>; 1132 1133multiclass RELEASE_UNOP<string Name, dag dag8, dag dag16, dag dag32, 1134 dag dag64> { 1135 def : Pat<(atomic_store_8 dag8, addr:$dst), 1136 (!cast<Instruction>(Name#8m) addr:$dst)>; 1137 def : Pat<(atomic_store_16 dag16, addr:$dst), 1138 (!cast<Instruction>(Name#16m) addr:$dst)>; 1139 def : Pat<(atomic_store_32 dag32, addr:$dst), 1140 (!cast<Instruction>(Name#32m) addr:$dst)>; 1141 def : Pat<(atomic_store_64 dag64, addr:$dst), 1142 (!cast<Instruction>(Name#64m) addr:$dst)>; 1143} 1144 1145let Predicates = [UseIncDec] in { 1146 defm : RELEASE_UNOP<"INC", 1147 (add (atomic_load_8 addr:$dst), (i8 1)), 1148 (add (atomic_load_16 addr:$dst), (i16 1)), 1149 (add (atomic_load_32 addr:$dst), (i32 1)), 1150 (add (atomic_load_64 addr:$dst), (i64 1))>; 1151 defm : RELEASE_UNOP<"DEC", 1152 (add (atomic_load_8 addr:$dst), (i8 -1)), 1153 (add (atomic_load_16 addr:$dst), (i16 -1)), 1154 (add (atomic_load_32 addr:$dst), (i32 -1)), 1155 (add (atomic_load_64 addr:$dst), (i64 -1))>; 1156} 1157 1158defm : RELEASE_UNOP<"NEG", 1159 (ineg (i8 (atomic_load_8 addr:$dst))), 1160 (ineg (i16 (atomic_load_16 addr:$dst))), 1161 (ineg (i32 (atomic_load_32 addr:$dst))), 1162 (ineg (i64 (atomic_load_64 addr:$dst)))>; 1163defm : RELEASE_UNOP<"NOT", 1164 (not (i8 (atomic_load_8 addr:$dst))), 1165 (not (i16 (atomic_load_16 addr:$dst))), 1166 (not (i32 (atomic_load_32 addr:$dst))), 1167 (not (i64 (atomic_load_64 addr:$dst)))>; 1168 1169def : Pat<(atomic_store_8 (i8 imm:$src), addr:$dst), 1170 (MOV8mi addr:$dst, imm:$src)>; 1171def : Pat<(atomic_store_16 (i16 imm:$src), addr:$dst), 1172 (MOV16mi addr:$dst, imm:$src)>; 1173def : Pat<(atomic_store_32 (i32 imm:$src), addr:$dst), 1174 (MOV32mi addr:$dst, imm:$src)>; 1175def : Pat<(atomic_store_64 (i64immSExt32:$src), addr:$dst), 1176 (MOV64mi32 addr:$dst, i64immSExt32:$src)>; 1177 1178def : Pat<(atomic_store_8 GR8:$src, addr:$dst), 1179 (MOV8mr addr:$dst, GR8:$src)>; 1180def : Pat<(atomic_store_16 GR16:$src, addr:$dst), 1181 (MOV16mr addr:$dst, GR16:$src)>; 1182def : Pat<(atomic_store_32 GR32:$src, addr:$dst), 1183 (MOV32mr addr:$dst, GR32:$src)>; 1184def : Pat<(atomic_store_64 GR64:$src, addr:$dst), 1185 (MOV64mr addr:$dst, GR64:$src)>; 1186 1187def : Pat<(i8 (atomic_load_8 addr:$src)), (MOV8rm addr:$src)>; 1188def : Pat<(i16 (atomic_load_16 addr:$src)), (MOV16rm addr:$src)>; 1189def : Pat<(i32 (atomic_load_32 addr:$src)), (MOV32rm addr:$src)>; 1190def : Pat<(i64 (atomic_load_64 addr:$src)), (MOV64rm addr:$src)>; 1191 1192// Floating point loads/stores. 1193def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst), 1194 (MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>; 1195def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst), 1196 (VMOVSSmr addr:$dst, FR32:$src)>, Requires<[UseAVX]>; 1197def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst), 1198 (VMOVSSZmr addr:$dst, FR32:$src)>, Requires<[HasAVX512]>; 1199 1200def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst), 1201 (MOVSDmr addr:$dst, FR64:$src)>, Requires<[UseSSE2]>; 1202def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst), 1203 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[UseAVX]>; 1204def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst), 1205 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[HasAVX512]>; 1206 1207def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1208 (MOVSSrm_alt addr:$src)>, Requires<[UseSSE1]>; 1209def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1210 (VMOVSSrm_alt addr:$src)>, Requires<[UseAVX]>; 1211def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1212 (VMOVSSZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1213 1214def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1215 (MOVSDrm_alt addr:$src)>, Requires<[UseSSE2]>; 1216def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1217 (VMOVSDrm_alt addr:$src)>, Requires<[UseAVX]>; 1218def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1219 (VMOVSDZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1220 1221//===----------------------------------------------------------------------===// 1222// DAG Pattern Matching Rules 1223//===----------------------------------------------------------------------===// 1224 1225// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves 1226// binary size compared to a regular MOV, but it introduces an unnecessary 1227// load, so is not suitable for regular or optsize functions. 1228let Predicates = [OptForMinSize] in { 1229def : Pat<(simple_store (i16 0), addr:$dst), (AND16mi addr:$dst, 0)>; 1230def : Pat<(simple_store (i32 0), addr:$dst), (AND32mi addr:$dst, 0)>; 1231def : Pat<(simple_store (i64 0), addr:$dst), (AND64mi32 addr:$dst, 0)>; 1232def : Pat<(simple_store (i16 -1), addr:$dst), (OR16mi addr:$dst, -1)>; 1233def : Pat<(simple_store (i32 -1), addr:$dst), (OR32mi addr:$dst, -1)>; 1234def : Pat<(simple_store (i64 -1), addr:$dst), (OR64mi32 addr:$dst, -1)>; 1235} 1236 1237// In kernel code model, we can get the address of a label 1238// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 1239// the MOV64ri32 should accept these. 1240def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 1241 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 1242def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 1243 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 1244def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 1245 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 1246def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 1247 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 1248def : Pat<(i64 (X86Wrapper mcsym:$dst)), 1249 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; 1250def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 1251 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 1252 1253// If we have small model and -static mode, it is safe to store global addresses 1254// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 1255// for MOV64mi32 should handle this sort of thing. 1256def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 1257 (MOV64mi32 addr:$dst, tconstpool:$src)>, 1258 Requires<[NearData, IsNotPIC]>; 1259def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 1260 (MOV64mi32 addr:$dst, tjumptable:$src)>, 1261 Requires<[NearData, IsNotPIC]>; 1262def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1263 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 1264 Requires<[NearData, IsNotPIC]>; 1265def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 1266 (MOV64mi32 addr:$dst, texternalsym:$src)>, 1267 Requires<[NearData, IsNotPIC]>; 1268def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), 1269 (MOV64mi32 addr:$dst, mcsym:$src)>, 1270 Requires<[NearData, IsNotPIC]>; 1271def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 1272 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 1273 Requires<[NearData, IsNotPIC]>; 1274 1275def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; 1276def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; 1277 1278// Calls 1279 1280// tls has some funny stuff here... 1281// This corresponds to movabs $foo@tpoff, %rax 1282def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 1283 (MOV64ri32 tglobaltlsaddr :$dst)>; 1284// This corresponds to add $foo@tpoff, %rax 1285def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 1286 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 1287 1288 1289// Direct PC relative function call for small code model. 32-bit displacement 1290// sign extended to 64-bit. 1291def : Pat<(X86call (i64 tglobaladdr:$dst)), 1292 (CALL64pcrel32 tglobaladdr:$dst)>; 1293def : Pat<(X86call (i64 texternalsym:$dst)), 1294 (CALL64pcrel32 texternalsym:$dst)>; 1295 1296def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 texternalsym:$dst)), 1297 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, texternalsym:$dst)>; 1298def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 tglobaladdr:$dst)), 1299 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, tglobaladdr:$dst)>; 1300 1301 1302// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1303// can never use callee-saved registers. That is the purpose of the GR64_TC 1304// register classes. 1305// 1306// The only volatile register that is never used by the calling convention is 1307// %r11. This happens when calling a vararg function with 6 arguments. 1308// 1309// Match an X86tcret that uses less than 7 volatile registers. 1310def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1311 (TCRETURNri ptr_rc_tailcall:$dst, timm:$off)>, 1312 Requires<[Not64BitMode, NotUseIndirectThunkCalls]>; 1313 1314// FIXME: This is disabled for 32-bit PIC mode because the global base 1315// register which is part of the address mode may be assigned a 1316// callee-saved register. 1317// Similar to X86tcret_6regs, here we only have 1 register left 1318def : Pat<(X86tcret_1reg (load addr:$dst), timm:$off), 1319 (TCRETURNmi addr:$dst, timm:$off)>, 1320 Requires<[Not64BitMode, IsNotPIC, NotUseIndirectThunkCalls]>; 1321 1322def : Pat<(X86tcret (i32 tglobaladdr:$dst), timm:$off), 1323 (TCRETURNdi tglobaladdr:$dst, timm:$off)>, 1324 Requires<[NotLP64]>; 1325 1326def : Pat<(X86tcret (i32 texternalsym:$dst), timm:$off), 1327 (TCRETURNdi texternalsym:$dst, timm:$off)>, 1328 Requires<[NotLP64]>; 1329 1330def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1331 (TCRETURNri64 ptr_rc_tailcall:$dst, timm:$off)>, 1332 Requires<[In64BitMode, NotUseIndirectThunkCalls]>; 1333 1334// Don't fold loads into X86tcret requiring more than 6 regs. 1335// There wouldn't be enough scratch registers for base+index. 1336def : Pat<(X86tcret_6regs (load addr:$dst), timm:$off), 1337 (TCRETURNmi64 addr:$dst, timm:$off)>, 1338 Requires<[In64BitMode, NotUseIndirectThunkCalls]>; 1339 1340def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1341 (INDIRECT_THUNK_TCRETURN64 ptr_rc_tailcall:$dst, timm:$off)>, 1342 Requires<[In64BitMode, UseIndirectThunkCalls]>; 1343 1344def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1345 (INDIRECT_THUNK_TCRETURN32 ptr_rc_tailcall:$dst, timm:$off)>, 1346 Requires<[Not64BitMode, UseIndirectThunkCalls]>; 1347 1348def : Pat<(X86tcret (i64 tglobaladdr:$dst), timm:$off), 1349 (TCRETURNdi64 tglobaladdr:$dst, timm:$off)>, 1350 Requires<[IsLP64]>; 1351 1352def : Pat<(X86tcret (i64 texternalsym:$dst), timm:$off), 1353 (TCRETURNdi64 texternalsym:$dst, timm:$off)>, 1354 Requires<[IsLP64]>; 1355 1356// Normal calls, with various flavors of addresses. 1357def : Pat<(X86call (i32 tglobaladdr:$dst)), 1358 (CALLpcrel32 tglobaladdr:$dst)>; 1359def : Pat<(X86call (i32 texternalsym:$dst)), 1360 (CALLpcrel32 texternalsym:$dst)>; 1361def : Pat<(X86call (i32 imm:$dst)), 1362 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1363 1364// Comparisons. 1365 1366// TEST R,R is smaller than CMP R,0 1367def : Pat<(X86cmp GR8:$src1, 0), 1368 (TEST8rr GR8:$src1, GR8:$src1)>; 1369def : Pat<(X86cmp GR16:$src1, 0), 1370 (TEST16rr GR16:$src1, GR16:$src1)>; 1371def : Pat<(X86cmp GR32:$src1, 0), 1372 (TEST32rr GR32:$src1, GR32:$src1)>; 1373def : Pat<(X86cmp GR64:$src1, 0), 1374 (TEST64rr GR64:$src1, GR64:$src1)>; 1375 1376// zextload bool -> zextload byte 1377// i1 stored in one byte in zero-extended form. 1378// Upper bits cleanup should be executed before Store. 1379def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1380def : Pat<(zextloadi16i1 addr:$src), 1381 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1382def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1383def : Pat<(zextloadi64i1 addr:$src), 1384 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1385 1386// extload bool -> extload byte 1387// When extloading from 16-bit and smaller memory locations into 64-bit 1388// registers, use zero-extending loads so that the entire 64-bit register is 1389// defined, avoiding partial-register updates. 1390 1391def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1392def : Pat<(extloadi16i1 addr:$src), 1393 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1394def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1395def : Pat<(extloadi16i8 addr:$src), 1396 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1397def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1398def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1399 1400// For other extloads, use subregs, since the high contents of the register are 1401// defined after an extload. 1402// NOTE: The extloadi64i32 pattern needs to be first as it will try to form 1403// 32-bit loads for 4 byte aligned i8/i16 loads. 1404def : Pat<(extloadi64i32 addr:$src), 1405 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1406def : Pat<(extloadi64i1 addr:$src), 1407 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1408def : Pat<(extloadi64i8 addr:$src), 1409 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1410def : Pat<(extloadi64i16 addr:$src), 1411 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1412 1413// anyext. Define these to do an explicit zero-extend to 1414// avoid partial-register updates. 1415def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1416 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1417def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1418 1419// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1420def : Pat<(i32 (anyext GR16:$src)), 1421 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1422 1423def : Pat<(i64 (anyext GR8 :$src)), 1424 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1425def : Pat<(i64 (anyext GR16:$src)), 1426 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1427def : Pat<(i64 (anyext GR32:$src)), 1428 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>; 1429 1430def : Pat<(i32 (anyext_sdiv GR8:$src)), (MOVSX32rr8 GR8:$src)>; 1431 1432// In the case of a 32-bit def that is known to implicitly zero-extend, 1433// we can use a SUBREG_TO_REG. 1434def : Pat<(i64 (zext def32:$src)), 1435 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1436def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)), 1437 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1438 1439//===----------------------------------------------------------------------===// 1440// Pattern match OR as ADD 1441//===----------------------------------------------------------------------===// 1442 1443// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1444// 3-addressified into an LEA instruction to avoid copies. However, we also 1445// want to finally emit these instructions as an or at the end of the code 1446// generator to make the generated code easier to read. To do this, we select 1447// into "disjoint bits" pseudo ops. 1448 1449// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1450// Try this before the selecting to OR. 1451let SchedRW = [WriteALU] in { 1452 1453let isConvertibleToThreeAddress = 1, isPseudo = 1, 1454 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1455let isCommutable = 1 in { 1456def ADD8rr_DB : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), 1457 "", // orb/addb REG, REG 1458 [(set GR8:$dst, (or_is_add GR8:$src1, GR8:$src2))]>; 1459def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1460 "", // orw/addw REG, REG 1461 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1462def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1463 "", // orl/addl REG, REG 1464 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1465def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1466 "", // orq/addq REG, REG 1467 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1468} // isCommutable 1469 1470def ADD8ri_DB : I<0, Pseudo, 1471 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), 1472 "", // orb/addb REG, imm8 1473 [(set GR8:$dst, (or_is_add GR8:$src1, imm:$src2))]>; 1474def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1475 "", // orw/addw REG, imm 1476 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1477def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1478 "", // orl/addl REG, imm 1479 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1480def ADD64ri32_DB : I<0, Pseudo, 1481 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1482 "", // orq/addq REG, imm 1483 [(set GR64:$dst, (or_is_add GR64:$src1, 1484 i64immSExt32:$src2))]>; 1485} 1486} // AddedComplexity, SchedRW 1487 1488//===----------------------------------------------------------------------===// 1489// Pattern match XOR as ADD 1490//===----------------------------------------------------------------------===// 1491 1492// Prefer to pattern match XOR with min_signed_value as ADD at isel time. 1493// ADD can be 3-addressified into an LEA instruction to avoid copies. 1494let AddedComplexity = 5 in { 1495def : Pat<(xor GR8:$src1, -128), 1496 (ADD8ri GR8:$src1, -128)>; 1497def : Pat<(xor GR16:$src1, -32768), 1498 (ADD16ri GR16:$src1, -32768)>; 1499def : Pat<(xor GR32:$src1, -2147483648), 1500 (ADD32ri GR32:$src1, -2147483648)>; 1501} 1502 1503//===----------------------------------------------------------------------===// 1504// Some peepholes 1505//===----------------------------------------------------------------------===// 1506 1507// Odd encoding trick: -128 fits into an 8-bit immediate field while 1508// +128 doesn't, so in this special case use a sub instead of an add. 1509let Predicates = [NoNDD] in { 1510 def : Pat<(add GR16:$src1, 128), 1511 (SUB16ri GR16:$src1, -128)>; 1512 def : Pat<(add GR32:$src1, 128), 1513 (SUB32ri GR32:$src1, -128)>; 1514 def : Pat<(add GR64:$src1, 128), 1515 (SUB64ri32 GR64:$src1, -128)>; 1516 1517 def : Pat<(X86add_flag_nocf GR16:$src1, 128), 1518 (SUB16ri GR16:$src1, -128)>; 1519 def : Pat<(X86add_flag_nocf GR32:$src1, 128), 1520 (SUB32ri GR32:$src1, -128)>; 1521 def : Pat<(X86add_flag_nocf GR64:$src1, 128), 1522 (SUB64ri32 GR64:$src1, -128)>; 1523} 1524let Predicates = [HasNDD] in { 1525 def : Pat<(add GR16:$src1, 128), 1526 (SUB16ri_ND GR16:$src1, -128)>; 1527 def : Pat<(add GR32:$src1, 128), 1528 (SUB32ri_ND GR32:$src1, -128)>; 1529 def : Pat<(add GR64:$src1, 128), 1530 (SUB64ri32_ND GR64:$src1, -128)>; 1531 1532 def : Pat<(X86add_flag_nocf GR16:$src1, 128), 1533 (SUB16ri_ND GR16:$src1, -128)>; 1534 def : Pat<(X86add_flag_nocf GR32:$src1, 128), 1535 (SUB32ri_ND GR32:$src1, -128)>; 1536 def : Pat<(X86add_flag_nocf GR64:$src1, 128), 1537 (SUB64ri32_ND GR64:$src1, -128)>; 1538} 1539def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1540 (SUB16mi addr:$dst, -128)>; 1541def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1542 (SUB32mi addr:$dst, -128)>; 1543def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1544 (SUB64mi32 addr:$dst, -128)>; 1545let Predicates = [HasNDD] in { 1546 def : Pat<(add (loadi16 addr:$src), 128), 1547 (SUB16mi_ND addr:$src, -128)>; 1548 def : Pat<(add (loadi32 addr:$src), 128), 1549 (SUB32mi_ND addr:$src, -128)>; 1550 def : Pat<(add (loadi64 addr:$src), 128), 1551 (SUB64mi32_ND addr:$src, -128)>; 1552} 1553 1554// The same trick applies for 32-bit immediate fields in 64-bit 1555// instructions. 1556let Predicates = [NoNDD] in { 1557 def : Pat<(add GR64:$src1, 0x0000000080000000), 1558 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1559 def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000), 1560 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1561} 1562let Predicates = [HasNDD] in { 1563 def : Pat<(add GR64:$src1, 0x0000000080000000), 1564 (SUB64ri32_ND GR64:$src1, 0xffffffff80000000)>; 1565 def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000), 1566 (SUB64ri32_ND GR64:$src1, 0xffffffff80000000)>; 1567} 1568def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst), 1569 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1570let Predicates = [HasNDD] in { 1571 def : Pat<(add(loadi64 addr:$src), 0x0000000080000000), 1572 (SUB64mi32_ND addr:$src, 0xffffffff80000000)>; 1573} 1574 1575// Depositing value to 8/16 bit subreg: 1576def : Pat<(or (and GR64:$dst, -256), 1577 (i64 (zextloadi8 addr:$src))), 1578 (INSERT_SUBREG (i64 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>; 1579 1580def : Pat<(or (and GR32:$dst, -256), 1581 (i32 (zextloadi8 addr:$src))), 1582 (INSERT_SUBREG (i32 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>; 1583 1584def : Pat<(or (and GR64:$dst, -65536), 1585 (i64 (zextloadi16 addr:$src))), 1586 (INSERT_SUBREG (i64 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit)>; 1587 1588def : Pat<(or (and GR32:$dst, -65536), 1589 (i32 (zextloadi16 addr:$src))), 1590 (INSERT_SUBREG (i32 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit)>; 1591 1592// To avoid needing to materialize an immediate in a register, use a 32-bit and 1593// with implicit zero-extension instead of a 64-bit and if the immediate has at 1594// least 32 bits of leading zeros. If in addition the last 32 bits can be 1595// represented with a sign extension of a 8 bit constant, use that. 1596// This can also reduce instruction size by eliminating the need for the REX 1597// prefix. 1598 1599// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. 1600let AddedComplexity = 1 in { 1601 let Predicates = [NoNDD] in { 1602 def : Pat<(and GR64:$src, i64immZExt32:$imm), 1603 (SUBREG_TO_REG 1604 (i64 0), 1605 (AND32ri 1606 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1607 (i32 (GetLo32XForm imm:$imm))), 1608 sub_32bit)>; 1609 } 1610 let Predicates = [HasNDD] in { 1611 def : Pat<(and GR64:$src, i64immZExt32:$imm), 1612 (SUBREG_TO_REG 1613 (i64 0), 1614 (AND32ri_ND 1615 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1616 (i32 (GetLo32XForm imm:$imm))), 1617 sub_32bit)>; 1618 } 1619} // AddedComplexity = 1 1620 1621 1622// AddedComplexity is needed due to the increased complexity on the 1623// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all 1624// the MOVZX patterns keeps thems together in DAGIsel tables. 1625let AddedComplexity = 1 in { 1626// r & (2^16-1) ==> movz 1627def : Pat<(and GR32:$src1, 0xffff), 1628 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1629// r & (2^8-1) ==> movz 1630def : Pat<(and GR32:$src1, 0xff), 1631 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>; 1632// r & (2^8-1) ==> movz 1633def : Pat<(and GR16:$src1, 0xff), 1634 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)), 1635 sub_16bit)>; 1636 1637// r & (2^32-1) ==> movz 1638def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1639 (SUBREG_TO_REG (i64 0), 1640 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1641 sub_32bit)>; 1642// r & (2^16-1) ==> movz 1643def : Pat<(and GR64:$src, 0xffff), 1644 (SUBREG_TO_REG (i64 0), 1645 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1646 sub_32bit)>; 1647// r & (2^8-1) ==> movz 1648def : Pat<(and GR64:$src, 0xff), 1649 (SUBREG_TO_REG (i64 0), 1650 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1651 sub_32bit)>; 1652} // AddedComplexity = 1 1653 1654 1655// Try to use BTS/BTR/BTC for single bit operations on the upper 32-bits. 1656 1657def BTRXForm : SDNodeXForm<imm, [{ 1658 // Transformation function: Find the lowest 0. 1659 return getI64Imm((uint8_t)N->getAPIntValue().countr_one(), SDLoc(N)); 1660}]>; 1661 1662def BTCBTSXForm : SDNodeXForm<imm, [{ 1663 // Transformation function: Find the lowest 1. 1664 return getI64Imm((uint8_t)N->getAPIntValue().countr_zero(), SDLoc(N)); 1665}]>; 1666 1667def BTRMask64 : ImmLeaf<i64, [{ 1668 return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm); 1669}]>; 1670 1671def BTCBTSMask64 : ImmLeaf<i64, [{ 1672 return !isInt<32>(Imm) && isPowerOf2_64(Imm); 1673}]>; 1674 1675// For now only do this for optsize. 1676let AddedComplexity = 1, Predicates=[OptForSize] in { 1677 def : Pat<(and GR64:$src1, BTRMask64:$mask), 1678 (BTR64ri8 GR64:$src1, (BTRXForm imm:$mask))>; 1679 def : Pat<(or GR64:$src1, BTCBTSMask64:$mask), 1680 (BTS64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1681 def : Pat<(xor GR64:$src1, BTCBTSMask64:$mask), 1682 (BTC64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1683} 1684 1685 1686// sext_inreg patterns 1687def : Pat<(sext_inreg GR32:$src, i16), 1688 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1689def : Pat<(sext_inreg GR32:$src, i8), 1690 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>; 1691 1692def : Pat<(sext_inreg GR16:$src, i8), 1693 (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)), 1694 sub_16bit)>; 1695 1696def : Pat<(sext_inreg GR64:$src, i32), 1697 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1698def : Pat<(sext_inreg GR64:$src, i16), 1699 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1700def : Pat<(sext_inreg GR64:$src, i8), 1701 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1702 1703// sext, sext_load, zext, zext_load 1704def: Pat<(i16 (sext GR8:$src)), 1705 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1706def: Pat<(sextloadi16i8 addr:$src), 1707 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1708def: Pat<(i16 (zext GR8:$src)), 1709 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1710def: Pat<(zextloadi16i8 addr:$src), 1711 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1712 1713// trunc patterns 1714def : Pat<(i16 (trunc GR32:$src)), 1715 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1716def : Pat<(i8 (trunc GR32:$src)), 1717 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1718 sub_8bit)>, 1719 Requires<[Not64BitMode]>; 1720def : Pat<(i8 (trunc GR16:$src)), 1721 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1722 sub_8bit)>, 1723 Requires<[Not64BitMode]>; 1724def : Pat<(i32 (trunc GR64:$src)), 1725 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1726def : Pat<(i16 (trunc GR64:$src)), 1727 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1728def : Pat<(i8 (trunc GR64:$src)), 1729 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1730def : Pat<(i8 (trunc GR32:$src)), 1731 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1732 Requires<[In64BitMode]>; 1733def : Pat<(i8 (trunc GR16:$src)), 1734 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1735 Requires<[In64BitMode]>; 1736 1737def immff00_ffff : ImmLeaf<i32, [{ 1738 return Imm >= 0xff00 && Imm <= 0xffff; 1739}]>; 1740 1741// h-register tricks 1742def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1743 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1744 Requires<[Not64BitMode]>; 1745def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))), 1746 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1747 Requires<[Not64BitMode]>; 1748def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1749 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>, 1750 Requires<[Not64BitMode]>; 1751def : Pat<(srl GR16:$src, (i8 8)), 1752 (EXTRACT_SUBREG 1753 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1754 sub_16bit)>; 1755def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1756 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1757def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1758 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1759def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1760 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1761def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)), 1762 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1763 1764// h-register tricks. 1765// For now, be conservative on x86-64 and use an h-register extract only if the 1766// value is immediately zero-extended or stored, which are somewhat common 1767// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1768// from being allocated in the same instruction as the h register, as there's 1769// currently no way to describe this requirement to the register allocator. 1770 1771// h-register extract and zero-extend. 1772def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1773 (SUBREG_TO_REG 1774 (i64 0), 1775 (MOVZX32rr8_NOREX 1776 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), 1777 sub_32bit)>; 1778def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1779 (SUBREG_TO_REG 1780 (i64 0), 1781 (MOVZX32rr8_NOREX 1782 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1783 sub_32bit)>; 1784def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1785 (SUBREG_TO_REG 1786 (i64 0), 1787 (MOVZX32rr8_NOREX 1788 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1789 sub_32bit)>; 1790 1791// h-register extract and store. 1792def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1793 (MOV8mr_NOREX 1794 addr:$dst, 1795 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>; 1796def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1797 (MOV8mr_NOREX 1798 addr:$dst, 1799 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, 1800 Requires<[In64BitMode]>; 1801def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1802 (MOV8mr_NOREX 1803 addr:$dst, 1804 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, 1805 Requires<[In64BitMode]>; 1806 1807// Special pattern to catch the last step of __builtin_parity handling. Our 1808// goal is to use an xor of an h-register with the corresponding l-register. 1809// The above patterns would handle this on non 64-bit targets, but for 64-bit 1810// we need to be more careful. We're using a NOREX instruction here in case 1811// register allocation fails to keep the two registers together. So we need to 1812// make sure we can't accidentally mix R8-R15 with an h-register. 1813def : Pat<(X86xor_flag (i8 (trunc GR32:$src)), 1814 (i8 (trunc (srl_su GR32:$src, (i8 8))))), 1815 (XOR8rr_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit), 1816 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1817 1818// (shl x, 1) ==> (add x, x) 1819// Note that if x is undef (immediate or otherwise), we could theoretically 1820// end up with the two uses of x getting different values, producing a result 1821// where the least significant bit is not 0. However, the probability of this 1822// happening is considered low enough that this is officially not a 1823// "real problem". 1824let Predicates = [NoNDD] in { 1825 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1826 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1827 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1828 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1829} 1830let Predicates = [HasNDD] in { 1831 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr_ND GR8 :$src1, GR8 :$src1)>; 1832 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr_ND GR16:$src1, GR16:$src1)>; 1833 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr_ND GR32:$src1, GR32:$src1)>; 1834 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr_ND GR64:$src1, GR64:$src1)>; 1835} 1836 1837// Shift amount is implicitly masked. 1838multiclass MaskedShiftAmountPats<SDNode frag> { 1839 // (shift x (and y, 31)) ==> (shift x, y) 1840 // (shift x (and y, 63)) ==> (shift x, y) 1841 let Predicates = [NoNDD] in { 1842 def : Pat<(frag GR8:$src1, (shiftMask32 CL)), 1843 (!cast<Instruction>(NAME # "8rCL") GR8:$src1)>; 1844 def : Pat<(frag GR16:$src1, (shiftMask32 CL)), 1845 (!cast<Instruction>(NAME # "16rCL") GR16:$src1)>; 1846 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1847 (!cast<Instruction>(NAME # "32rCL") GR32:$src1)>; 1848 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1849 (!cast<Instruction>(NAME # "64rCL") GR64:$src1)>; 1850 } 1851 let Predicates = [HasNDD] in { 1852 def : Pat<(frag GR8:$src1, (shiftMask32 CL)), 1853 (!cast<Instruction>(NAME # "8rCL_ND") GR8:$src1)>; 1854 def : Pat<(frag GR16:$src1, (shiftMask32 CL)), 1855 (!cast<Instruction>(NAME # "16rCL_ND") GR16:$src1)>; 1856 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1857 (!cast<Instruction>(NAME # "32rCL_ND") GR32:$src1)>; 1858 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1859 (!cast<Instruction>(NAME # "64rCL_ND") GR64:$src1)>; 1860 } 1861 1862 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask32 CL)), addr:$dst), 1863 (!cast<Instruction>(NAME # "8mCL") addr:$dst)>; 1864 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask32 CL)), addr:$dst), 1865 (!cast<Instruction>(NAME # "16mCL") addr:$dst)>; 1866 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1867 (!cast<Instruction>(NAME # "32mCL") addr:$dst)>; 1868 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1869 (!cast<Instruction>(NAME # "64mCL") addr:$dst)>; 1870 1871 let Predicates = [HasNDD] in { 1872 def : Pat<(frag (loadi8 addr:$src), (shiftMask32 CL)), 1873 (!cast<Instruction>(NAME # "8mCL_ND") addr:$src)>; 1874 def : Pat<(frag (loadi16 addr:$src), (shiftMask32 CL)), 1875 (!cast<Instruction>(NAME # "16mCL_ND") addr:$src)>; 1876 def : Pat<(frag (loadi32 addr:$src), (shiftMask32 CL)), 1877 (!cast<Instruction>(NAME # "32mCL_ND") addr:$src)>; 1878 def : Pat<(frag (loadi64 addr:$src), (shiftMask64 CL)), 1879 (!cast<Instruction>(NAME # "64mCL_ND") addr:$src)>; 1880 } 1881} 1882 1883defm SHL : MaskedShiftAmountPats<shl>; 1884defm SHR : MaskedShiftAmountPats<srl>; 1885defm SAR : MaskedShiftAmountPats<sra>; 1886 1887// ROL/ROR instructions allow a stronger mask optimization than shift for 8- and 1888// 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount 1889// because over-rotating produces the same result. This is noted in the Intel 1890// docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation 1891// amount could affect EFLAGS results, but that does not matter because we are 1892// not tracking flags for these nodes. 1893multiclass MaskedRotateAmountPats<SDNode frag> { 1894 // (rot x (and y, BitWidth - 1)) ==> (rot x, y) 1895 let Predicates = [NoNDD] in { 1896 def : Pat<(frag GR8:$src1, (shiftMask8 CL)), 1897 (!cast<Instruction>(NAME # "8rCL") GR8:$src1)>; 1898 def : Pat<(frag GR16:$src1, (shiftMask16 CL)), 1899 (!cast<Instruction>(NAME # "16rCL") GR16:$src1)>; 1900 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1901 (!cast<Instruction>(NAME # "32rCL") GR32:$src1)>; 1902 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1903 (!cast<Instruction>(NAME # "64rCL") GR64:$src1)>; 1904 } 1905 let Predicates = [HasNDD] in { 1906 def : Pat<(frag GR8:$src1, (shiftMask8 CL)), 1907 (!cast<Instruction>(NAME # "8rCL_ND") GR8:$src1)>; 1908 def : Pat<(frag GR16:$src1, (shiftMask16 CL)), 1909 (!cast<Instruction>(NAME # "16rCL_ND") GR16:$src1)>; 1910 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1911 (!cast<Instruction>(NAME # "32rCL_ND") GR32:$src1)>; 1912 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1913 (!cast<Instruction>(NAME # "64rCL_ND") GR64:$src1)>; 1914 } 1915 1916 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask8 CL)), addr:$dst), 1917 (!cast<Instruction>(NAME # "8mCL") addr:$dst)>; 1918 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask16 CL)), addr:$dst), 1919 (!cast<Instruction>(NAME # "16mCL") addr:$dst)>; 1920 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1921 (!cast<Instruction>(NAME # "32mCL") addr:$dst)>; 1922 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1923 (!cast<Instruction>(NAME # "64mCL") addr:$dst)>; 1924 1925 let Predicates = [HasNDD] in { 1926 def : Pat<(frag (loadi8 addr:$src), (shiftMask8 CL)), 1927 (!cast<Instruction>(NAME # "8mCL_ND") addr:$src)>; 1928 def : Pat<(frag (loadi16 addr:$src), (shiftMask16 CL)), 1929 (!cast<Instruction>(NAME # "16mCL_ND") addr:$src)>; 1930 def : Pat<(frag (loadi32 addr:$src), (shiftMask32 CL)), 1931 (!cast<Instruction>(NAME # "32mCL_ND") addr:$src)>; 1932 def : Pat<(frag (loadi64 addr:$src), (shiftMask64 CL)), 1933 (!cast<Instruction>(NAME # "64mCL_ND") addr:$src)>; 1934 } 1935} 1936 1937defm ROL : MaskedRotateAmountPats<rotl>; 1938defm ROR : MaskedRotateAmountPats<rotr>; 1939 1940multiclass MaskedShlrdAmountPats<string suffix, Predicate p> { 1941 let Predicates = [p] in { 1942 // Double "funnel" shift amount is implicitly masked. 1943 // (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) (NOTE: modulo32) 1944 def : Pat<(X86fshl GR16:$src1, GR16:$src2, (shiftMask32 CL)), 1945 (!cast<Instruction>(SHLD16rrCL#suffix) GR16:$src1, GR16:$src2)>; 1946 def : Pat<(X86fshr GR16:$src2, GR16:$src1, (shiftMask32 CL)), 1947 (!cast<Instruction>(SHRD16rrCL#suffix) GR16:$src1, GR16:$src2)>; 1948 1949 // (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) 1950 def : Pat<(fshl GR32:$src1, GR32:$src2, (shiftMask32 CL)), 1951 (!cast<Instruction>(SHLD32rrCL#suffix) GR32:$src1, GR32:$src2)>; 1952 def : Pat<(fshr GR32:$src2, GR32:$src1, (shiftMask32 CL)), 1953 (!cast<Instruction>(SHRD32rrCL#suffix) GR32:$src1, GR32:$src2)>; 1954 1955 // (fshl/fshr x (and y, 63)) ==> (fshl/fshr x, y) 1956 def : Pat<(fshl GR64:$src1, GR64:$src2, (shiftMask64 CL)), 1957 (!cast<Instruction>(SHLD64rrCL#suffix) GR64:$src1, GR64:$src2)>; 1958 def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)), 1959 (!cast<Instruction>(SHRD64rrCL#suffix) GR64:$src1, GR64:$src2)>; 1960 } 1961} 1962 1963defm : MaskedShlrdAmountPats<"", NoNDD>; 1964defm : MaskedShlrdAmountPats<"_ND", HasNDD>; 1965 1966// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location. 1967multiclass OneBitPats<RegisterClass rc, ValueType vt, Instruction btr, 1968 Instruction bts, Instruction btc, PatFrag mask> { 1969 def : Pat<(and rc:$src1, (rotl -2, GR8:$src2)), 1970 (btr rc:$src1, 1971 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1972 def : Pat<(or rc:$src1, (shl 1, GR8:$src2)), 1973 (bts rc:$src1, 1974 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1975 def : Pat<(xor rc:$src1, (shl 1, GR8:$src2)), 1976 (btc rc:$src1, 1977 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1978 1979 // Similar to above, but removing unneeded masking of the shift amount. 1980 def : Pat<(and rc:$src1, (rotl -2, (mask GR8:$src2))), 1981 (btr rc:$src1, 1982 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1983 def : Pat<(or rc:$src1, (shl 1, (mask GR8:$src2))), 1984 (bts rc:$src1, 1985 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1986 def : Pat<(xor rc:$src1, (shl 1, (mask GR8:$src2))), 1987 (btc rc:$src1, 1988 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1989} 1990 1991defm : OneBitPats<GR16, i16, BTR16rr, BTS16rr, BTC16rr, shiftMask16>; 1992defm : OneBitPats<GR32, i32, BTR32rr, BTS32rr, BTC32rr, shiftMask32>; 1993defm : OneBitPats<GR64, i64, BTR64rr, BTS64rr, BTC64rr, shiftMask64>; 1994 1995//===----------------------------------------------------------------------===// 1996// EFLAGS-defining Patterns 1997//===----------------------------------------------------------------------===// 1998 1999multiclass EFLAGSDefiningPats<string suffix, Predicate p> { 2000 let Predicates = [p] in { 2001 // add reg, reg 2002 def : Pat<(add GR8 :$src1, GR8 :$src2), (!cast<Instruction>(ADD8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2003 def : Pat<(add GR16:$src1, GR16:$src2), (!cast<Instruction>(ADD16rr#suffix) GR16:$src1, GR16:$src2)>; 2004 def : Pat<(add GR32:$src1, GR32:$src2), (!cast<Instruction>(ADD32rr#suffix) GR32:$src1, GR32:$src2)>; 2005 def : Pat<(add GR64:$src1, GR64:$src2), (!cast<Instruction>(ADD64rr#suffix) GR64:$src1, GR64:$src2)>; 2006 2007 // add reg, mem 2008 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 2009 (!cast<Instruction>(ADD8rm#suffix) GR8:$src1, addr:$src2)>; 2010 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 2011 (!cast<Instruction>(ADD16rm#suffix) GR16:$src1, addr:$src2)>; 2012 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 2013 (!cast<Instruction>(ADD32rm#suffix) GR32:$src1, addr:$src2)>; 2014 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 2015 (!cast<Instruction>(ADD64rm#suffix) GR64:$src1, addr:$src2)>; 2016 2017 // add reg, imm 2018 def : Pat<(add GR8 :$src1, imm:$src2), (!cast<Instruction>(ADD8ri#suffix) GR8:$src1 , imm:$src2)>; 2019 def : Pat<(add GR16:$src1, imm:$src2), (!cast<Instruction>(ADD16ri#suffix) GR16:$src1, imm:$src2)>; 2020 def : Pat<(add GR32:$src1, imm:$src2), (!cast<Instruction>(ADD32ri#suffix) GR32:$src1, imm:$src2)>; 2021 def : Pat<(add GR64:$src1, i64immSExt32:$src2), (!cast<Instruction>(ADD64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2022 2023 // sub reg, reg 2024 def : Pat<(sub GR8 :$src1, GR8 :$src2), (!cast<Instruction>(SUB8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2025 def : Pat<(sub GR16:$src1, GR16:$src2), (!cast<Instruction>(SUB16rr#suffix) GR16:$src1, GR16:$src2)>; 2026 def : Pat<(sub GR32:$src1, GR32:$src2), (!cast<Instruction>(SUB32rr#suffix) GR32:$src1, GR32:$src2)>; 2027 def : Pat<(sub GR64:$src1, GR64:$src2), (!cast<Instruction>(SUB64rr#suffix) GR64:$src1, GR64:$src2)>; 2028 2029 // sub reg, mem 2030 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 2031 (!cast<Instruction>(SUB8rm#suffix) GR8:$src1, addr:$src2)>; 2032 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 2033 (!cast<Instruction>(SUB16rm#suffix) GR16:$src1, addr:$src2)>; 2034 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 2035 (!cast<Instruction>(SUB32rm#suffix) GR32:$src1, addr:$src2)>; 2036 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 2037 (!cast<Instruction>(SUB64rm#suffix) GR64:$src1, addr:$src2)>; 2038 2039 // sub reg, imm 2040 def : Pat<(sub GR8:$src1, imm:$src2), 2041 (!cast<Instruction>(SUB8ri#suffix) GR8:$src1, imm:$src2)>; 2042 def : Pat<(sub GR16:$src1, imm:$src2), 2043 (!cast<Instruction>(SUB16ri#suffix) GR16:$src1, imm:$src2)>; 2044 def : Pat<(sub GR32:$src1, imm:$src2), 2045 (!cast<Instruction>(SUB32ri#suffix) GR32:$src1, imm:$src2)>; 2046 def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 2047 (!cast<Instruction>(SUB64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2048 2049 // sub 0, reg 2050 def : Pat<(X86sub_flag 0, GR8 :$src), (!cast<Instruction>(NEG8r#suffix) GR8 :$src)>; 2051 def : Pat<(X86sub_flag 0, GR16:$src), (!cast<Instruction>(NEG16r#suffix) GR16:$src)>; 2052 def : Pat<(X86sub_flag 0, GR32:$src), (!cast<Instruction>(NEG32r#suffix) GR32:$src)>; 2053 def : Pat<(X86sub_flag 0, GR64:$src), (!cast<Instruction>(NEG64r#suffix) GR64:$src)>; 2054 2055 // mul reg, reg 2056 def : Pat<(mul GR16:$src1, GR16:$src2), 2057 (!cast<Instruction>(IMUL16rr#suffix) GR16:$src1, GR16:$src2)>; 2058 def : Pat<(mul GR32:$src1, GR32:$src2), 2059 (!cast<Instruction>(IMUL32rr#suffix) GR32:$src1, GR32:$src2)>; 2060 def : Pat<(mul GR64:$src1, GR64:$src2), 2061 (!cast<Instruction>(IMUL64rr#suffix) GR64:$src1, GR64:$src2)>; 2062 2063 // mul reg, mem 2064 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 2065 (!cast<Instruction>(IMUL16rm#suffix) GR16:$src1, addr:$src2)>; 2066 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 2067 (!cast<Instruction>(IMUL32rm#suffix) GR32:$src1, addr:$src2)>; 2068 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 2069 (!cast<Instruction>(IMUL64rm#suffix) GR64:$src1, addr:$src2)>; 2070 2071 // or reg/reg. 2072 def : Pat<(or GR8 :$src1, GR8 :$src2), (!cast<Instruction>(OR8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2073 def : Pat<(or GR16:$src1, GR16:$src2), (!cast<Instruction>(OR16rr#suffix) GR16:$src1, GR16:$src2)>; 2074 def : Pat<(or GR32:$src1, GR32:$src2), (!cast<Instruction>(OR32rr#suffix) GR32:$src1, GR32:$src2)>; 2075 def : Pat<(or GR64:$src1, GR64:$src2), (!cast<Instruction>(OR64rr#suffix) GR64:$src1, GR64:$src2)>; 2076 2077 // or reg/mem 2078 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 2079 (!cast<Instruction>(OR8rm#suffix) GR8:$src1, addr:$src2)>; 2080 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 2081 (!cast<Instruction>(OR16rm#suffix) GR16:$src1, addr:$src2)>; 2082 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 2083 (!cast<Instruction>(OR32rm#suffix) GR32:$src1, addr:$src2)>; 2084 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 2085 (!cast<Instruction>(OR64rm#suffix) GR64:$src1, addr:$src2)>; 2086 2087 // or reg/imm 2088 def : Pat<(or GR8:$src1 , imm:$src2), (!cast<Instruction>(OR8ri#suffix) GR8 :$src1, imm:$src2)>; 2089 def : Pat<(or GR16:$src1, imm:$src2), (!cast<Instruction>(OR16ri#suffix) GR16:$src1, imm:$src2)>; 2090 def : Pat<(or GR32:$src1, imm:$src2), (!cast<Instruction>(OR32ri#suffix) GR32:$src1, imm:$src2)>; 2091 def : Pat<(or GR64:$src1, i64immSExt32:$src2), 2092 (!cast<Instruction>(OR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2093 2094 // xor reg/reg 2095 def : Pat<(xor GR8 :$src1, GR8 :$src2), (!cast<Instruction>(XOR8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2096 def : Pat<(xor GR16:$src1, GR16:$src2), (!cast<Instruction>(XOR16rr#suffix) GR16:$src1, GR16:$src2)>; 2097 def : Pat<(xor GR32:$src1, GR32:$src2), (!cast<Instruction>(XOR32rr#suffix) GR32:$src1, GR32:$src2)>; 2098 def : Pat<(xor GR64:$src1, GR64:$src2), (!cast<Instruction>(XOR64rr#suffix) GR64:$src1, GR64:$src2)>; 2099 2100 // xor reg/mem 2101 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 2102 (!cast<Instruction>(XOR8rm#suffix) GR8:$src1, addr:$src2)>; 2103 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 2104 (!cast<Instruction>(XOR16rm#suffix) GR16:$src1, addr:$src2)>; 2105 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 2106 (!cast<Instruction>(XOR32rm#suffix) GR32:$src1, addr:$src2)>; 2107 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 2108 (!cast<Instruction>(XOR64rm#suffix) GR64:$src1, addr:$src2)>; 2109 2110 // xor reg/imm 2111 def : Pat<(xor GR8:$src1, imm:$src2), 2112 (!cast<Instruction>(XOR8ri#suffix) GR8:$src1, imm:$src2)>; 2113 def : Pat<(xor GR16:$src1, imm:$src2), 2114 (!cast<Instruction>(XOR16ri#suffix) GR16:$src1, imm:$src2)>; 2115 def : Pat<(xor GR32:$src1, imm:$src2), 2116 (!cast<Instruction>(XOR32ri#suffix) GR32:$src1, imm:$src2)>; 2117 def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 2118 (!cast<Instruction>(XOR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2119 2120 // and reg/reg 2121 def : Pat<(and GR8 :$src1, GR8 :$src2), (!cast<Instruction>(AND8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2122 def : Pat<(and GR16:$src1, GR16:$src2), (!cast<Instruction>(AND16rr#suffix) GR16:$src1, GR16:$src2)>; 2123 def : Pat<(and GR32:$src1, GR32:$src2), (!cast<Instruction>(AND32rr#suffix) GR32:$src1, GR32:$src2)>; 2124 def : Pat<(and GR64:$src1, GR64:$src2), (!cast<Instruction>(AND64rr#suffix) GR64:$src1, GR64:$src2)>; 2125 2126 // and reg/mem 2127 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 2128 (!cast<Instruction>(AND8rm#suffix) GR8:$src1, addr:$src2)>; 2129 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 2130 (!cast<Instruction>(AND16rm#suffix) GR16:$src1, addr:$src2)>; 2131 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 2132 (!cast<Instruction>(AND32rm#suffix) GR32:$src1, addr:$src2)>; 2133 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 2134 (!cast<Instruction>(AND64rm#suffix) GR64:$src1, addr:$src2)>; 2135 2136 // and reg/imm 2137 def : Pat<(and GR8:$src1, imm:$src2), 2138 (!cast<Instruction>(AND8ri#suffix) GR8:$src1, imm:$src2)>; 2139 def : Pat<(and GR16:$src1, imm:$src2), 2140 (!cast<Instruction>(AND16ri#suffix) GR16:$src1, imm:$src2)>; 2141 def : Pat<(and GR32:$src1, imm:$src2), 2142 (!cast<Instruction>(AND32ri#suffix) GR32:$src1, imm:$src2)>; 2143 def : Pat<(and GR64:$src1, i64immSExt32:$src2), 2144 (!cast<Instruction>(AND64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2145 } 2146 2147 // Increment/Decrement reg. 2148 // Do not make INC/DEC if it is slow 2149 let Predicates = [UseIncDec, p] in { 2150 def : Pat<(add GR8:$src, 1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>; 2151 def : Pat<(add GR16:$src, 1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>; 2152 def : Pat<(add GR32:$src, 1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>; 2153 def : Pat<(add GR64:$src, 1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>; 2154 def : Pat<(add GR8:$src, -1), (!cast<Instruction>(DEC8r#suffix) GR8:$src)>; 2155 def : Pat<(add GR16:$src, -1), (!cast<Instruction>(DEC16r#suffix) GR16:$src)>; 2156 def : Pat<(add GR32:$src, -1), (!cast<Instruction>(DEC32r#suffix) GR32:$src)>; 2157 def : Pat<(add GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>; 2158 2159 def : Pat<(X86add_flag_nocf GR8:$src, -1), (!cast<Instruction>(DEC8r#suffix) GR8:$src)>; 2160 def : Pat<(X86add_flag_nocf GR16:$src, -1), (!cast<Instruction>(DEC16r#suffix) GR16:$src)>; 2161 def : Pat<(X86add_flag_nocf GR32:$src, -1), (!cast<Instruction>(DEC32r#suffix) GR32:$src)>; 2162 def : Pat<(X86add_flag_nocf GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>; 2163 def : Pat<(X86sub_flag_nocf GR8:$src, -1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>; 2164 def : Pat<(X86sub_flag_nocf GR16:$src, -1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>; 2165 def : Pat<(X86sub_flag_nocf GR32:$src, -1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>; 2166 def : Pat<(X86sub_flag_nocf GR64:$src, -1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>; 2167 2168 def : Pat<(or_is_add GR8:$src, 1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>; 2169 def : Pat<(or_is_add GR16:$src, 1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>; 2170 def : Pat<(or_is_add GR32:$src, 1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>; 2171 def : Pat<(or_is_add GR64:$src, 1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>; 2172 } 2173} 2174 2175defm : EFLAGSDefiningPats<"", NoNDD>; 2176defm : EFLAGSDefiningPats<"_ND", HasNDD>; 2177 2178// mul reg, imm 2179def : Pat<(mul GR16:$src1, imm:$src2), 2180 (IMUL16rri GR16:$src1, imm:$src2)>; 2181def : Pat<(mul GR32:$src1, imm:$src2), 2182 (IMUL32rri GR32:$src1, imm:$src2)>; 2183def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 2184 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 2185 2186// reg = mul mem, imm 2187def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 2188 (IMUL16rmi addr:$src1, imm:$src2)>; 2189def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 2190 (IMUL32rmi addr:$src1, imm:$src2)>; 2191def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 2192 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 2193 2194// Bit scan instruction patterns to match explicit zero-undef behavior. 2195def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 2196def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 2197def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 2198def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 2199def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 2200def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 2201 2202// When HasMOVBE is enabled it is possible to get a non-legalized 2203// register-register 16 bit bswap. This maps it to a ROL instruction. 2204let Predicates = [HasMOVBE] in { 2205 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; 2206} 2207