1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the various pseudo instructions used by the compiler, 10// as well as Pat patterns used during instruction selection. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Pattern Matching Support 16 17def GetLo32XForm : SDNodeXForm<imm, [{ 18 // Transformation function: get the low 32 bits. 19 return getI32Imm((uint32_t)N->getZExtValue(), SDLoc(N)); 20}]>; 21 22 23//===----------------------------------------------------------------------===// 24// Random Pseudo Instructions. 25 26// PIC base construction. This expands to code that looks like this: 27// call $next_inst 28// popl %destreg" 29let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP], 30 SchedRW = [WriteJump] in 31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 32 "", []>; 33 34// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 35// a stack adjustment and the codegen must know that they may modify the stack 36// pointer before prolog-epilog rewriting occurs. 37// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 38// sub / add which can clobber EFLAGS. 39let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in { 40def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), 41 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 42 "#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>; 43def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 44 "#ADJCALLSTACKUP", 45 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 46 Requires<[NotLP64]>; 47} 48def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 49 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>; 50 51 52// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 53// a stack adjustment and the codegen must know that they may modify the stack 54// pointer before prolog-epilog rewriting occurs. 55// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 56// sub / add which can clobber EFLAGS. 57let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in { 58def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), 59 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 60 "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>; 61def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 62 "#ADJCALLSTACKUP", 63 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 64 Requires<[IsLP64]>; 65} 66def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 67 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>; 68 69let SchedRW = [WriteSystem] in { 70 71// x86-64 va_start lowering magic. 72let usesCustomInserter = 1, Defs = [EFLAGS] in { 73def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 74 (outs), 75 (ins GR8:$al, 76 i64imm:$regsavefi, i64imm:$offset, 77 variable_ops), 78 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", 79 [(X86vastart_save_xmm_regs GR8:$al, 80 imm:$regsavefi, 81 imm:$offset), 82 (implicit EFLAGS)]>; 83 84// The VAARG_64 pseudo-instruction takes the address of the va_list, 85// and places the address of the next argument into a register. 86let Defs = [EFLAGS] in 87def VAARG_64 : I<0, Pseudo, 88 (outs GR64:$dst), 89 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 90 "#VAARG_64 $dst, $ap, $size, $mode, $align", 91 [(set GR64:$dst, 92 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), 93 (implicit EFLAGS)]>; 94 95 96// When using segmented stacks these are lowered into instructions which first 97// check if the current stacklet has enough free memory. If it does, memory is 98// allocated by bumping the stack pointer. Otherwise memory is allocated from 99// the heap. 100 101let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 102def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 103 "# variable sized alloca for segmented stacks", 104 [(set GR32:$dst, 105 (X86SegAlloca GR32:$size))]>, 106 Requires<[NotLP64]>; 107 108let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 109def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 110 "# variable sized alloca for segmented stacks", 111 [(set GR64:$dst, 112 (X86SegAlloca GR64:$size))]>, 113 Requires<[In64BitMode]>; 114} 115 116// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 117// targets. These calls are needed to probe the stack when allocating more than 118// 4k bytes in one go. Touching the stack at 4K increments is necessary to 119// ensure that the guard pages used by the OS virtual memory manager are 120// allocated in correct sequence. 121// The main point of having separate instruction are extra unmodelled effects 122// (compared to ordinary calls) like stack pointer change. 123 124let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 125def WIN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size), 126 "# dynamic stack allocation", 127 [(X86WinAlloca GR32:$size)]>, 128 Requires<[NotLP64]>; 129 130let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 131def WIN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size), 132 "# dynamic stack allocation", 133 [(X86WinAlloca GR64:$size)]>, 134 Requires<[In64BitMode]>; 135} // SchedRW 136 137// These instructions XOR the frame pointer into a GPR. They are used in some 138// stack protection schemes. These are post-RA pseudos because we only know the 139// frame register after register allocation. 140let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in { 141 def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src), 142 "xorl\t$$FP, $src", []>, 143 Requires<[NotLP64]>, Sched<[WriteALU]>; 144 def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src), 145 "xorq\t$$FP $src", []>, 146 Requires<[In64BitMode]>, Sched<[WriteALU]>; 147} 148 149//===----------------------------------------------------------------------===// 150// EH Pseudo Instructions 151// 152let SchedRW = [WriteSystem] in { 153let isTerminator = 1, isReturn = 1, isBarrier = 1, 154 hasCtrlDep = 1, isCodeGenOnly = 1 in { 155def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 156 "ret\t#eh_return, addr: $addr", 157 [(X86ehret GR32:$addr)]>, Sched<[WriteJumpLd]>; 158 159} 160 161let isTerminator = 1, isReturn = 1, isBarrier = 1, 162 hasCtrlDep = 1, isCodeGenOnly = 1 in { 163def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 164 "ret\t#eh_return, addr: $addr", 165 [(X86ehret GR64:$addr)]>, Sched<[WriteJumpLd]>; 166 167} 168 169let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 170 isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1 in { 171 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>; 172 173 // CATCHRET needs a custom inserter for SEH. 174 let usesCustomInserter = 1 in 175 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), 176 "# CATCHRET", 177 [(catchret bb:$dst, bb:$from)]>; 178} 179 180let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1, 181 usesCustomInserter = 1 in 182def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>; 183 184// This instruction is responsible for re-establishing stack pointers after an 185// exception has been caught and we are rejoining normal control flow in the 186// parent function or funclet. It generally sets ESP and EBP, and optionally 187// ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us 188// elsewhere. 189let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in 190def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>; 191 192let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 193 usesCustomInserter = 1 in { 194 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 195 "#EH_SJLJ_SETJMP32", 196 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 197 Requires<[Not64BitMode]>; 198 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 199 "#EH_SJLJ_SETJMP64", 200 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 201 Requires<[In64BitMode]>; 202 let isTerminator = 1 in { 203 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 204 "#EH_SJLJ_LONGJMP32", 205 [(X86eh_sjlj_longjmp addr:$buf)]>, 206 Requires<[Not64BitMode]>; 207 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 208 "#EH_SJLJ_LONGJMP64", 209 [(X86eh_sjlj_longjmp addr:$buf)]>, 210 Requires<[In64BitMode]>; 211 } 212} 213 214let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 215 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 216 "#EH_SjLj_Setup\t$dst", []>; 217} 218} // SchedRW 219 220//===----------------------------------------------------------------------===// 221// Pseudo instructions used by unwind info. 222// 223let isPseudo = 1, SchedRW = [WriteSystem] in { 224 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), 225 "#SEH_PushReg $reg", []>; 226 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 227 "#SEH_SaveReg $reg, $dst", []>; 228 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 229 "#SEH_SaveXMM $reg, $dst", []>; 230 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), 231 "#SEH_StackAlloc $size", []>; 232 def SEH_StackAlign : I<0, Pseudo, (outs), (ins i32imm:$align), 233 "#SEH_StackAlign $align", []>; 234 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), 235 "#SEH_SetFrame $reg, $offset", []>; 236 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), 237 "#SEH_PushFrame $mode", []>; 238 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), 239 "#SEH_EndPrologue", []>; 240 def SEH_Epilogue : I<0, Pseudo, (outs), (ins), 241 "#SEH_Epilogue", []>; 242} 243 244//===----------------------------------------------------------------------===// 245// Pseudo instructions used by segmented stacks. 246// 247 248// This is lowered into a RET instruction by MCInstLower. We need 249// this so that we don't have to have a MachineBasicBlock which ends 250// with a RET and also has successors. 251let isPseudo = 1, SchedRW = [WriteJumpLd] in { 252def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>; 253 254// This instruction is lowered to a RET followed by a MOV. The two 255// instructions are not generated on a higher level since then the 256// verifier sees a MachineBasicBlock ending with a non-terminator. 257def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>; 258} 259 260//===----------------------------------------------------------------------===// 261// Alias Instructions 262//===----------------------------------------------------------------------===// 263 264// Alias instruction mapping movr0 to xor. 265// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 266let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 267 isPseudo = 1, isMoveImm = 1, AddedComplexity = 10 in 268def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 269 [(set GR32:$dst, 0)]>, Sched<[WriteZero]>; 270 271// Other widths can also make use of the 32-bit xor, which may have a smaller 272// encoding and avoid partial register updates. 273let AddedComplexity = 10 in { 274def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 275def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 276def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>; 277} 278 279let Predicates = [OptForSize, Not64BitMode], 280 AddedComplexity = 10 in { 281 let SchedRW = [WriteALU] in { 282 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, 283 // which only require 3 bytes compared to MOV32ri which requires 5. 284 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { 285 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 286 [(set GR32:$dst, 1)]>; 287 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 288 [(set GR32:$dst, -1)]>; 289 } 290 } // SchedRW 291 292 // MOV16ri is 4 bytes, so the instructions above are smaller. 293 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; 294 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; 295} 296 297let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5, 298 SchedRW = [WriteALU] in { 299// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1. 300def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "", 301 [(set GR32:$dst, i32immSExt8:$src)]>, 302 Requires<[OptForMinSize, NotWin64WithoutFP]>; 303def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", 304 [(set GR64:$dst, i64immSExt8:$src)]>, 305 Requires<[OptForMinSize, NotWin64WithoutFP]>; 306} 307 308// Materialize i64 constant where top 32-bits are zero. This could theoretically 309// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 310// that would make it more difficult to rematerialize. 311let isReMaterializable = 1, isAsCheapAsAMove = 1, 312 isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteMove] in 313def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "", []>; 314 315// This 64-bit pseudo-move can be used for both a 64-bit constant that is 316// actually the zero-extension of a 32-bit constant and for labels in the 317// x86-64 small code model. 318def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>; 319 320def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>; 321 322// Use sbb to materialize carry bit. 323let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in { 324// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 325// However, Pat<> can't replicate the destination reg into the inputs of the 326// result. 327def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "", 328 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 329def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "", 330 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 331def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", 332 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 333def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", 334 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 335} // isCodeGenOnly 336 337 338def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 339 (SETB_C16r)>; 340def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 341 (SETB_C32r)>; 342def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 343 (SETB_C64r)>; 344 345def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 346 (SETB_C16r)>; 347def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 348 (SETB_C32r)>; 349def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 350 (SETB_C64r)>; 351 352// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and 353// will be eliminated and that the sbb can be extended up to a wider type. When 354// this happens, it is great. However, if we are left with an 8-bit sbb and an 355// and, we might as well just match it as a setb. 356def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), 357 (SETCCr (i8 2))>; 358 359// Patterns to give priority when both inputs are zero so that we don't use 360// an immediate for the RHS. 361// TODO: Should we use a 32-bit sbb for 8/16 to push the extract_subreg out? 362def : Pat<(X86sbb_flag (i8 0), (i8 0), EFLAGS), 363 (SBB8rr (EXTRACT_SUBREG (MOV32r0), sub_8bit), 364 (EXTRACT_SUBREG (MOV32r0), sub_8bit))>; 365def : Pat<(X86sbb_flag (i16 0), (i16 0), EFLAGS), 366 (SBB16rr (EXTRACT_SUBREG (MOV32r0), sub_16bit), 367 (EXTRACT_SUBREG (MOV32r0), sub_16bit))>; 368def : Pat<(X86sbb_flag (i32 0), (i32 0), EFLAGS), 369 (SBB32rr (MOV32r0), (MOV32r0))>; 370def : Pat<(X86sbb_flag (i64 0), (i64 0), EFLAGS), 371 (SBB64rr (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit), 372 (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit))>; 373 374//===----------------------------------------------------------------------===// 375// String Pseudo Instructions 376// 377let SchedRW = [WriteMicrocoded] in { 378let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 379def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), 380 "{rep;movsb (%esi), %es:(%edi)|rep movsb es:[edi], [esi]}", 381 [(X86rep_movs i8)]>, REP, AdSize32, 382 Requires<[NotLP64]>; 383def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), 384 "{rep;movsw (%esi), %es:(%edi)|rep movsw es:[edi], [esi]}", 385 [(X86rep_movs i16)]>, REP, AdSize32, OpSize16, 386 Requires<[NotLP64]>; 387def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), 388 "{rep;movsl (%esi), %es:(%edi)|rep movsd es:[edi], [esi]}", 389 [(X86rep_movs i32)]>, REP, AdSize32, OpSize32, 390 Requires<[NotLP64]>; 391def REP_MOVSQ_32 : RI<0xA5, RawFrm, (outs), (ins), 392 "{rep;movsq (%esi), %es:(%edi)|rep movsq es:[edi], [esi]}", 393 [(X86rep_movs i64)]>, REP, AdSize32, 394 Requires<[NotLP64, In64BitMode]>; 395} 396 397let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 398def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), 399 "{rep;movsb (%rsi), %es:(%rdi)|rep movsb es:[rdi], [rsi]}", 400 [(X86rep_movs i8)]>, REP, AdSize64, 401 Requires<[IsLP64]>; 402def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), 403 "{rep;movsw (%rsi), %es:(%rdi)|rep movsw es:[rdi], [rsi]}", 404 [(X86rep_movs i16)]>, REP, AdSize64, OpSize16, 405 Requires<[IsLP64]>; 406def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), 407 "{rep;movsl (%rsi), %es:(%rdi)|rep movsdi es:[rdi], [rsi]}", 408 [(X86rep_movs i32)]>, REP, AdSize64, OpSize32, 409 Requires<[IsLP64]>; 410def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), 411 "{rep;movsq (%rsi), %es:(%rdi)|rep movsq es:[rdi], [rsi]}", 412 [(X86rep_movs i64)]>, REP, AdSize64, 413 Requires<[IsLP64]>; 414} 415 416// FIXME: Should use "(X86rep_stos AL)" as the pattern. 417let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 418 let Uses = [AL,ECX,EDI] in 419 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), 420 "{rep;stosb %al, %es:(%edi)|rep stosb es:[edi], al}", 421 [(X86rep_stos i8)]>, REP, AdSize32, 422 Requires<[NotLP64]>; 423 let Uses = [AX,ECX,EDI] in 424 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), 425 "{rep;stosw %ax, %es:(%edi)|rep stosw es:[edi], ax}", 426 [(X86rep_stos i16)]>, REP, AdSize32, OpSize16, 427 Requires<[NotLP64]>; 428 let Uses = [EAX,ECX,EDI] in 429 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), 430 "{rep;stosl %eax, %es:(%edi)|rep stosd es:[edi], eax}", 431 [(X86rep_stos i32)]>, REP, AdSize32, OpSize32, 432 Requires<[NotLP64]>; 433 let Uses = [RAX,RCX,RDI] in 434 def REP_STOSQ_32 : RI<0xAB, RawFrm, (outs), (ins), 435 "{rep;stosq %rax, %es:(%edi)|rep stosq es:[edi], rax}", 436 [(X86rep_stos i64)]>, REP, AdSize32, 437 Requires<[NotLP64, In64BitMode]>; 438} 439 440let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 441 let Uses = [AL,RCX,RDI] in 442 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), 443 "{rep;stosb %al, %es:(%rdi)|rep stosb es:[rdi], al}", 444 [(X86rep_stos i8)]>, REP, AdSize64, 445 Requires<[IsLP64]>; 446 let Uses = [AX,RCX,RDI] in 447 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), 448 "{rep;stosw %ax, %es:(%rdi)|rep stosw es:[rdi], ax}", 449 [(X86rep_stos i16)]>, REP, AdSize64, OpSize16, 450 Requires<[IsLP64]>; 451 let Uses = [RAX,RCX,RDI] in 452 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), 453 "{rep;stosl %eax, %es:(%rdi)|rep stosd es:[rdi], eax}", 454 [(X86rep_stos i32)]>, REP, AdSize64, OpSize32, 455 Requires<[IsLP64]>; 456 457 let Uses = [RAX,RCX,RDI] in 458 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), 459 "{rep;stosq %rax, %es:(%rdi)|rep stosq es:[rdi], rax}", 460 [(X86rep_stos i64)]>, REP, AdSize64, 461 Requires<[IsLP64]>; 462} 463} // SchedRW 464 465//===----------------------------------------------------------------------===// 466// Thread Local Storage Instructions 467// 468let SchedRW = [WriteSystem] in { 469 470// ELF TLS Support 471// All calls clobber the non-callee saved registers. ESP is marked as 472// a use to prevent stack-pointer assignments that appear immediately 473// before calls from potentially appearing dead. 474let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 475 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 476 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 477 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 478 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 479 usesCustomInserter = 1, Uses = [ESP, SSP] in { 480def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 481 "# TLS_addr32", 482 [(X86tlsaddr tls32addr:$sym)]>, 483 Requires<[Not64BitMode]>; 484def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 485 "# TLS_base_addr32", 486 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 487 Requires<[Not64BitMode]>; 488} 489 490// All calls clobber the non-callee saved registers. RSP is marked as 491// a use to prevent stack-pointer assignments that appear immediately 492// before calls from potentially appearing dead. 493let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 494 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 495 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 496 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 497 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 498 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 499 usesCustomInserter = 1, Uses = [RSP, SSP] in { 500def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 501 "# TLS_addr64", 502 [(X86tlsaddr tls64addr:$sym)]>, 503 Requires<[In64BitMode]>; 504def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 505 "# TLS_base_addr64", 506 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 507 Requires<[In64BitMode]>; 508} 509 510// Darwin TLS Support 511// For i386, the address of the thunk is passed on the stack, on return the 512// address of the variable is in %eax. %ecx is trashed during the function 513// call. All other registers are preserved. 514let Defs = [EAX, ECX, EFLAGS, DF], 515 Uses = [ESP, SSP], 516 usesCustomInserter = 1 in 517def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 518 "# TLSCall_32", 519 [(X86TLSCall addr:$sym)]>, 520 Requires<[Not64BitMode]>; 521 522// For x86_64, the address of the thunk is passed in %rdi, but the 523// pseudo directly use the symbol, so do not add an implicit use of 524// %rdi. The lowering will do the right thing with RDI. 525// On return the address of the variable is in %rax. All other 526// registers are preserved. 527let Defs = [RAX, EFLAGS, DF], 528 Uses = [RSP, SSP], 529 usesCustomInserter = 1 in 530def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 531 "# TLSCall_64", 532 [(X86TLSCall addr:$sym)]>, 533 Requires<[In64BitMode]>; 534} // SchedRW 535 536//===----------------------------------------------------------------------===// 537// Conditional Move Pseudo Instructions 538 539// CMOV* - Used to implement the SELECT DAG operation. Expanded after 540// instruction selection into a branch sequence. 541multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> { 542 def CMOV#NAME : I<0, Pseudo, 543 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), 544 "#CMOV_"#NAME#" PSEUDO!", 545 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond, 546 EFLAGS)))]>; 547} 548 549let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in { 550 // X86 doesn't have 8-bit conditional moves. Use a customInserter to 551 // emit control flow. An alternative to this is to mark i8 SELECT as Promote, 552 // however that requires promoting the operands, and can induce additional 553 // i8 register pressure. 554 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>; 555 556 let Predicates = [NoCMov] in { 557 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>; 558 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>; 559 } // Predicates = [NoCMov] 560 561 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 562 // SSE1/SSE2. 563 let Predicates = [FPStackf32] in 564 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>; 565 566 let Predicates = [FPStackf64] in 567 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>; 568 569 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>; 570 571 let Predicates = [NoAVX512] in { 572 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 573 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>; 574 } 575 let Predicates = [HasAVX512] in { 576 defm _FR32X : CMOVrr_PSEUDO<FR32X, f32>; 577 defm _FR64X : CMOVrr_PSEUDO<FR64X, f64>; 578 } 579 let Predicates = [NoVLX] in { 580 defm _VR128 : CMOVrr_PSEUDO<VR128, v2i64>; 581 defm _VR256 : CMOVrr_PSEUDO<VR256, v4i64>; 582 } 583 let Predicates = [HasVLX] in { 584 defm _VR128X : CMOVrr_PSEUDO<VR128X, v2i64>; 585 defm _VR256X : CMOVrr_PSEUDO<VR256X, v4i64>; 586 } 587 defm _VR512 : CMOVrr_PSEUDO<VR512, v8i64>; 588 defm _VK2 : CMOVrr_PSEUDO<VK2, v2i1>; 589 defm _VK4 : CMOVrr_PSEUDO<VK4, v4i1>; 590 defm _VK8 : CMOVrr_PSEUDO<VK8, v8i1>; 591 defm _VK16 : CMOVrr_PSEUDO<VK16, v16i1>; 592 defm _VK32 : CMOVrr_PSEUDO<VK32, v32i1>; 593 defm _VK64 : CMOVrr_PSEUDO<VK64, v64i1>; 594} // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] 595 596def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)), 597 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>; 598 599let Predicates = [NoVLX] in { 600 def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)), 601 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>; 602 def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)), 603 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>; 604 def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)), 605 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>; 606 def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)), 607 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>; 608 def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)), 609 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>; 610 611 def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)), 612 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>; 613 def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)), 614 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>; 615 def : Pat<(v8i32 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)), 616 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>; 617 def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)), 618 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>; 619 def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)), 620 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>; 621} 622let Predicates = [HasVLX] in { 623 def : Pat<(v16i8 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)), 624 (CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>; 625 def : Pat<(v8i16 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)), 626 (CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>; 627 def : Pat<(v4i32 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)), 628 (CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>; 629 def : Pat<(v4f32 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)), 630 (CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>; 631 def : Pat<(v2f64 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)), 632 (CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>; 633 634 def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)), 635 (CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>; 636 def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)), 637 (CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>; 638 def : Pat<(v8i32 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)), 639 (CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>; 640 def : Pat<(v8f32 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)), 641 (CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>; 642 def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)), 643 (CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>; 644} 645 646def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)), 647 (CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>; 648def : Pat<(v32i16 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)), 649 (CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>; 650def : Pat<(v16i32 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)), 651 (CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>; 652def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)), 653 (CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>; 654def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)), 655 (CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>; 656 657//===----------------------------------------------------------------------===// 658// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 659//===----------------------------------------------------------------------===// 660 661// FIXME: Use normal instructions and add lock prefix dynamically. 662 663// Memory barriers 664 665let isCodeGenOnly = 1, Defs = [EFLAGS] in 666def OR32mi8Locked : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$zero), 667 "or{l}\t{$zero, $dst|$dst, $zero}", []>, 668 Requires<[Not64BitMode]>, OpSize32, LOCK, 669 Sched<[WriteALURMW]>; 670 671let hasSideEffects = 1 in 672def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 673 "#MEMBARRIER", 674 [(X86MemBarrier)]>, Sched<[WriteLoad]>; 675 676// RegOpc corresponds to the mr version of the instruction 677// ImmOpc corresponds to the mi version of the instruction 678// ImmOpc8 corresponds to the mi8 version of the instruction 679// ImmMod corresponds to the instruction format of the mi and mi8 versions 680multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 681 Format ImmMod, SDNode Op, string mnemonic> { 682let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 683 SchedRW = [WriteALURMW] in { 684 685def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 686 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 687 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 688 !strconcat(mnemonic, "{b}\t", 689 "{$src2, $dst|$dst, $src2}"), 690 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK; 691 692def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 693 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 694 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 695 !strconcat(mnemonic, "{w}\t", 696 "{$src2, $dst|$dst, $src2}"), 697 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>, 698 OpSize16, LOCK; 699 700def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 701 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 702 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 703 !strconcat(mnemonic, "{l}\t", 704 "{$src2, $dst|$dst, $src2}"), 705 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>, 706 OpSize32, LOCK; 707 708def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 709 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 710 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 711 !strconcat(mnemonic, "{q}\t", 712 "{$src2, $dst|$dst, $src2}"), 713 [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK; 714 715// NOTE: These are order specific, we want the mi8 forms to be listed 716// first so that they are slightly preferred to the mi forms. 717def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 718 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 719 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 720 !strconcat(mnemonic, "{w}\t", 721 "{$src2, $dst|$dst, $src2}"), 722 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>, 723 OpSize16, LOCK; 724 725def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 726 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 727 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 728 !strconcat(mnemonic, "{l}\t", 729 "{$src2, $dst|$dst, $src2}"), 730 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>, 731 OpSize32, LOCK; 732 733def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 734 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 735 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 736 !strconcat(mnemonic, "{q}\t", 737 "{$src2, $dst|$dst, $src2}"), 738 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>, 739 LOCK; 740 741def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 742 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 743 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 744 !strconcat(mnemonic, "{b}\t", 745 "{$src2, $dst|$dst, $src2}"), 746 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK; 747 748def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 749 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 750 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 751 !strconcat(mnemonic, "{w}\t", 752 "{$src2, $dst|$dst, $src2}"), 753 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>, 754 OpSize16, LOCK; 755 756def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 757 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 758 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 759 !strconcat(mnemonic, "{l}\t", 760 "{$src2, $dst|$dst, $src2}"), 761 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>, 762 OpSize32, LOCK; 763 764def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 765 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 766 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 767 !strconcat(mnemonic, "{q}\t", 768 "{$src2, $dst|$dst, $src2}"), 769 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>, 770 LOCK; 771} 772 773} 774 775defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">; 776defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">; 777defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">; 778defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; 779defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; 780 781def X86lock_add_nocf : PatFrag<(ops node:$lhs, node:$rhs), 782 (X86lock_add node:$lhs, node:$rhs), [{ 783 return hasNoCarryFlagUses(SDValue(N, 0)); 784}]>; 785 786def X86lock_sub_nocf : PatFrag<(ops node:$lhs, node:$rhs), 787 (X86lock_sub node:$lhs, node:$rhs), [{ 788 return hasNoCarryFlagUses(SDValue(N, 0)); 789}]>; 790 791let Predicates = [UseIncDec] in { 792 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 793 SchedRW = [WriteALURMW] in { 794 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), 795 "inc{b}\t$dst", 796 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i8 1)))]>, 797 LOCK; 798 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), 799 "inc{w}\t$dst", 800 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i16 1)))]>, 801 OpSize16, LOCK; 802 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), 803 "inc{l}\t$dst", 804 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i32 1)))]>, 805 OpSize32, LOCK; 806 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), 807 "inc{q}\t$dst", 808 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i64 1)))]>, 809 LOCK; 810 811 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), 812 "dec{b}\t$dst", 813 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i8 1)))]>, 814 LOCK; 815 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), 816 "dec{w}\t$dst", 817 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i16 1)))]>, 818 OpSize16, LOCK; 819 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), 820 "dec{l}\t$dst", 821 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i32 1)))]>, 822 OpSize32, LOCK; 823 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), 824 "dec{q}\t$dst", 825 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i64 1)))]>, 826 LOCK; 827 } 828 829 // Additional patterns for -1 constant. 830 def : Pat<(X86lock_add addr:$dst, (i8 -1)), (LOCK_DEC8m addr:$dst)>; 831 def : Pat<(X86lock_add addr:$dst, (i16 -1)), (LOCK_DEC16m addr:$dst)>; 832 def : Pat<(X86lock_add addr:$dst, (i32 -1)), (LOCK_DEC32m addr:$dst)>; 833 def : Pat<(X86lock_add addr:$dst, (i64 -1)), (LOCK_DEC64m addr:$dst)>; 834 def : Pat<(X86lock_sub addr:$dst, (i8 -1)), (LOCK_INC8m addr:$dst)>; 835 def : Pat<(X86lock_sub addr:$dst, (i16 -1)), (LOCK_INC16m addr:$dst)>; 836 def : Pat<(X86lock_sub addr:$dst, (i32 -1)), (LOCK_INC32m addr:$dst)>; 837 def : Pat<(X86lock_sub addr:$dst, (i64 -1)), (LOCK_INC64m addr:$dst)>; 838} 839 840// Atomic compare and swap. 841multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic, 842 SDPatternOperator frag, X86MemOperand x86memop> { 843let isCodeGenOnly = 1, usesCustomInserter = 1 in { 844 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr), 845 !strconcat(mnemonic, "\t$ptr"), 846 [(frag addr:$ptr)]>, TB, LOCK; 847} 848} 849 850multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 851 string mnemonic, SDPatternOperator frag> { 852let isCodeGenOnly = 1, SchedRW = [WriteCMPXCHGRMW] in { 853 let Defs = [AL, EFLAGS], Uses = [AL] in 854 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 855 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 856 [(frag addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; 857 let Defs = [AX, EFLAGS], Uses = [AX] in 858 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 859 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 860 [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK; 861 let Defs = [EAX, EFLAGS], Uses = [EAX] in 862 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 863 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 864 [(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK; 865 let Defs = [RAX, EFLAGS], Uses = [RAX] in 866 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 867 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 868 [(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK; 869} 870} 871 872let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 873 Predicates = [HasCmpxchg8b], SchedRW = [WriteCMPXCHGRMW] in { 874defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", X86cas8, i64mem>; 875} 876 877// This pseudo must be used when the frame uses RBX as 878// the base pointer. Indeed, in such situation RBX is a reserved 879// register and the register allocator will ignore any use/def of 880// it. In other words, the register will not fix the clobbering of 881// RBX that will happen when setting the arguments for the instrucion. 882// 883// Unlike the actual related instuction, we mark that this one 884// defines EBX (instead of using EBX). 885// The rationale is that we will define RBX during the expansion of 886// the pseudo. The argument feeding EBX is ebx_input. 887// 888// The additional argument, $ebx_save, is a temporary register used to 889// save the value of RBX across the actual instruction. 890// 891// To make sure the register assigned to $ebx_save does not interfere with 892// the definition of the actual instruction, we use a definition $dst which 893// is tied to $rbx_save. That way, the live-range of $rbx_save spans across 894// the instruction and we are sure we will have a valid register to restore 895// the value of RBX. 896let Defs = [EAX, EDX, EBX, EFLAGS], Uses = [EAX, ECX, EDX], 897 Predicates = [HasCmpxchg8b], SchedRW = [WriteCMPXCHGRMW], 898 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$ebx_save = $dst", 899 usesCustomInserter = 1 in { 900def LCMPXCHG8B_SAVE_EBX : 901 I<0, Pseudo, (outs GR32:$dst), 902 (ins i64mem:$ptr, GR32:$ebx_input, GR32:$ebx_save), 903 !strconcat("cmpxchg8b", "\t$ptr"), 904 [(set GR32:$dst, (X86cas8save_ebx addr:$ptr, GR32:$ebx_input, 905 GR32:$ebx_save))]>; 906} 907 908 909let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 910 Predicates = [HasCmpxchg16b,In64BitMode], SchedRW = [WriteCMPXCHGRMW] in { 911defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", 912 X86cas16, i128mem>, REX_W; 913} 914 915// Same as LCMPXCHG8B_SAVE_RBX but for the 16 Bytes variant. 916let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX], 917 Predicates = [HasCmpxchg16b,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 918 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst", 919 usesCustomInserter = 1 in { 920def LCMPXCHG16B_SAVE_RBX : 921 I<0, Pseudo, (outs GR64:$dst), 922 (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), 923 !strconcat("cmpxchg16b", "\t$ptr"), 924 [(set GR64:$dst, (X86cas16save_rbx addr:$ptr, GR64:$rbx_input, 925 GR64:$rbx_save))]>; 926} 927 928defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>; 929 930// Atomic exchange and add 931multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 932 string frag> { 933 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1, 934 SchedRW = [WriteALURMW] in { 935 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 936 (ins GR8:$val, i8mem:$ptr), 937 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 938 [(set GR8:$dst, 939 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>; 940 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 941 (ins GR16:$val, i16mem:$ptr), 942 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 943 [(set 944 GR16:$dst, 945 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, 946 OpSize16; 947 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 948 (ins GR32:$val, i32mem:$ptr), 949 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 950 [(set 951 GR32:$dst, 952 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, 953 OpSize32; 954 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 955 (ins GR64:$val, i64mem:$ptr), 956 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 957 [(set 958 GR64:$dst, 959 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; 960 } 961} 962 963defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK; 964 965/* The following multiclass tries to make sure that in code like 966 * x.store (immediate op x.load(acquire), release) 967 * and 968 * x.store (register op x.load(acquire), release) 969 * an operation directly on memory is generated instead of wasting a register. 970 * It is not automatic as atomic_store/load are only lowered to MOV instructions 971 * extremely late to prevent them from being accidentally reordered in the backend 972 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) 973 */ 974multiclass RELEASE_BINOP_MI<string Name, SDNode op> { 975 def : Pat<(atomic_store_8 addr:$dst, 976 (op (atomic_load_8 addr:$dst), (i8 imm:$src))), 977 (!cast<Instruction>(Name#"8mi") addr:$dst, imm:$src)>; 978 def : Pat<(atomic_store_16 addr:$dst, 979 (op (atomic_load_16 addr:$dst), (i16 imm:$src))), 980 (!cast<Instruction>(Name#"16mi") addr:$dst, imm:$src)>; 981 def : Pat<(atomic_store_32 addr:$dst, 982 (op (atomic_load_32 addr:$dst), (i32 imm:$src))), 983 (!cast<Instruction>(Name#"32mi") addr:$dst, imm:$src)>; 984 def : Pat<(atomic_store_64 addr:$dst, 985 (op (atomic_load_64 addr:$dst), (i64immSExt32:$src))), 986 (!cast<Instruction>(Name#"64mi32") addr:$dst, (i64immSExt32:$src))>; 987 988 def : Pat<(atomic_store_8 addr:$dst, 989 (op (atomic_load_8 addr:$dst), (i8 GR8:$src))), 990 (!cast<Instruction>(Name#"8mr") addr:$dst, GR8:$src)>; 991 def : Pat<(atomic_store_16 addr:$dst, 992 (op (atomic_load_16 addr:$dst), (i16 GR16:$src))), 993 (!cast<Instruction>(Name#"16mr") addr:$dst, GR16:$src)>; 994 def : Pat<(atomic_store_32 addr:$dst, 995 (op (atomic_load_32 addr:$dst), (i32 GR32:$src))), 996 (!cast<Instruction>(Name#"32mr") addr:$dst, GR32:$src)>; 997 def : Pat<(atomic_store_64 addr:$dst, 998 (op (atomic_load_64 addr:$dst), (i64 GR64:$src))), 999 (!cast<Instruction>(Name#"64mr") addr:$dst, GR64:$src)>; 1000} 1001defm : RELEASE_BINOP_MI<"ADD", add>; 1002defm : RELEASE_BINOP_MI<"AND", and>; 1003defm : RELEASE_BINOP_MI<"OR", or>; 1004defm : RELEASE_BINOP_MI<"XOR", xor>; 1005defm : RELEASE_BINOP_MI<"SUB", sub>; 1006 1007// Atomic load + floating point patterns. 1008// FIXME: This could also handle SIMD operations with *ps and *pd instructions. 1009multiclass ATOMIC_LOAD_FP_BINOP_MI<string Name, SDNode op> { 1010 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1011 (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>, 1012 Requires<[UseSSE1]>; 1013 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1014 (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>, 1015 Requires<[UseAVX]>; 1016 def : Pat<(op FR32X:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1017 (!cast<Instruction>("V"#Name#"SSZrm") FR32X:$src1, addr:$src2)>, 1018 Requires<[HasAVX512]>; 1019 1020 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1021 (!cast<Instruction>(Name#"SDrm") FR64:$src1, addr:$src2)>, 1022 Requires<[UseSSE1]>; 1023 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1024 (!cast<Instruction>("V"#Name#"SDrm") FR64:$src1, addr:$src2)>, 1025 Requires<[UseAVX]>; 1026 def : Pat<(op FR64X:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1027 (!cast<Instruction>("V"#Name#"SDZrm") FR64X:$src1, addr:$src2)>, 1028 Requires<[HasAVX512]>; 1029} 1030defm : ATOMIC_LOAD_FP_BINOP_MI<"ADD", fadd>; 1031// FIXME: Add fsub, fmul, fdiv, ... 1032 1033multiclass RELEASE_UNOP<string Name, dag dag8, dag dag16, dag dag32, 1034 dag dag64> { 1035 def : Pat<(atomic_store_8 addr:$dst, dag8), 1036 (!cast<Instruction>(Name#8m) addr:$dst)>; 1037 def : Pat<(atomic_store_16 addr:$dst, dag16), 1038 (!cast<Instruction>(Name#16m) addr:$dst)>; 1039 def : Pat<(atomic_store_32 addr:$dst, dag32), 1040 (!cast<Instruction>(Name#32m) addr:$dst)>; 1041 def : Pat<(atomic_store_64 addr:$dst, dag64), 1042 (!cast<Instruction>(Name#64m) addr:$dst)>; 1043} 1044 1045let Predicates = [UseIncDec] in { 1046 defm : RELEASE_UNOP<"INC", 1047 (add (atomic_load_8 addr:$dst), (i8 1)), 1048 (add (atomic_load_16 addr:$dst), (i16 1)), 1049 (add (atomic_load_32 addr:$dst), (i32 1)), 1050 (add (atomic_load_64 addr:$dst), (i64 1))>; 1051 defm : RELEASE_UNOP<"DEC", 1052 (add (atomic_load_8 addr:$dst), (i8 -1)), 1053 (add (atomic_load_16 addr:$dst), (i16 -1)), 1054 (add (atomic_load_32 addr:$dst), (i32 -1)), 1055 (add (atomic_load_64 addr:$dst), (i64 -1))>; 1056} 1057 1058defm : RELEASE_UNOP<"NEG", 1059 (ineg (i8 (atomic_load_8 addr:$dst))), 1060 (ineg (i16 (atomic_load_16 addr:$dst))), 1061 (ineg (i32 (atomic_load_32 addr:$dst))), 1062 (ineg (i64 (atomic_load_64 addr:$dst)))>; 1063defm : RELEASE_UNOP<"NOT", 1064 (not (i8 (atomic_load_8 addr:$dst))), 1065 (not (i16 (atomic_load_16 addr:$dst))), 1066 (not (i32 (atomic_load_32 addr:$dst))), 1067 (not (i64 (atomic_load_64 addr:$dst)))>; 1068 1069def : Pat<(atomic_store_8 addr:$dst, (i8 imm:$src)), 1070 (MOV8mi addr:$dst, imm:$src)>; 1071def : Pat<(atomic_store_16 addr:$dst, (i16 imm:$src)), 1072 (MOV16mi addr:$dst, imm:$src)>; 1073def : Pat<(atomic_store_32 addr:$dst, (i32 imm:$src)), 1074 (MOV32mi addr:$dst, imm:$src)>; 1075def : Pat<(atomic_store_64 addr:$dst, (i64immSExt32:$src)), 1076 (MOV64mi32 addr:$dst, i64immSExt32:$src)>; 1077 1078def : Pat<(atomic_store_8 addr:$dst, GR8:$src), 1079 (MOV8mr addr:$dst, GR8:$src)>; 1080def : Pat<(atomic_store_16 addr:$dst, GR16:$src), 1081 (MOV16mr addr:$dst, GR16:$src)>; 1082def : Pat<(atomic_store_32 addr:$dst, GR32:$src), 1083 (MOV32mr addr:$dst, GR32:$src)>; 1084def : Pat<(atomic_store_64 addr:$dst, GR64:$src), 1085 (MOV64mr addr:$dst, GR64:$src)>; 1086 1087def : Pat<(i8 (atomic_load_8 addr:$src)), (MOV8rm addr:$src)>; 1088def : Pat<(i16 (atomic_load_16 addr:$src)), (MOV16rm addr:$src)>; 1089def : Pat<(i32 (atomic_load_32 addr:$src)), (MOV32rm addr:$src)>; 1090def : Pat<(i64 (atomic_load_64 addr:$src)), (MOV64rm addr:$src)>; 1091 1092// Floating point loads/stores. 1093def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1094 (MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>; 1095def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1096 (VMOVSSmr addr:$dst, FR32:$src)>, Requires<[UseAVX]>; 1097def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1098 (VMOVSSZmr addr:$dst, FR32:$src)>, Requires<[HasAVX512]>; 1099 1100def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))), 1101 (MOVSDmr addr:$dst, FR64:$src)>, Requires<[UseSSE2]>; 1102def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))), 1103 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[UseAVX]>; 1104def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))), 1105 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[HasAVX512]>; 1106 1107def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1108 (MOVSSrm_alt addr:$src)>, Requires<[UseSSE1]>; 1109def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1110 (VMOVSSrm_alt addr:$src)>, Requires<[UseAVX]>; 1111def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1112 (VMOVSSZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1113 1114def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1115 (MOVSDrm_alt addr:$src)>, Requires<[UseSSE2]>; 1116def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1117 (VMOVSDrm_alt addr:$src)>, Requires<[UseAVX]>; 1118def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1119 (VMOVSDZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1120 1121//===----------------------------------------------------------------------===// 1122// DAG Pattern Matching Rules 1123//===----------------------------------------------------------------------===// 1124 1125// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves 1126// binary size compared to a regular MOV, but it introduces an unnecessary 1127// load, so is not suitable for regular or optsize functions. 1128let Predicates = [OptForMinSize] in { 1129def : Pat<(nonvolatile_store (i16 0), addr:$dst), (AND16mi8 addr:$dst, 0)>; 1130def : Pat<(nonvolatile_store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>; 1131def : Pat<(nonvolatile_store (i64 0), addr:$dst), (AND64mi8 addr:$dst, 0)>; 1132def : Pat<(nonvolatile_store (i16 -1), addr:$dst), (OR16mi8 addr:$dst, -1)>; 1133def : Pat<(nonvolatile_store (i32 -1), addr:$dst), (OR32mi8 addr:$dst, -1)>; 1134def : Pat<(nonvolatile_store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>; 1135} 1136 1137// In kernel code model, we can get the address of a label 1138// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 1139// the MOV64ri32 should accept these. 1140def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 1141 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 1142def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 1143 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 1144def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 1145 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 1146def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 1147 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 1148def : Pat<(i64 (X86Wrapper mcsym:$dst)), 1149 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; 1150def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 1151 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 1152 1153// If we have small model and -static mode, it is safe to store global addresses 1154// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 1155// for MOV64mi32 should handle this sort of thing. 1156def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 1157 (MOV64mi32 addr:$dst, tconstpool:$src)>, 1158 Requires<[NearData, IsNotPIC]>; 1159def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 1160 (MOV64mi32 addr:$dst, tjumptable:$src)>, 1161 Requires<[NearData, IsNotPIC]>; 1162def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1163 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 1164 Requires<[NearData, IsNotPIC]>; 1165def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 1166 (MOV64mi32 addr:$dst, texternalsym:$src)>, 1167 Requires<[NearData, IsNotPIC]>; 1168def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), 1169 (MOV64mi32 addr:$dst, mcsym:$src)>, 1170 Requires<[NearData, IsNotPIC]>; 1171def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 1172 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 1173 Requires<[NearData, IsNotPIC]>; 1174 1175def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; 1176def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; 1177 1178// Calls 1179 1180// tls has some funny stuff here... 1181// This corresponds to movabs $foo@tpoff, %rax 1182def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 1183 (MOV64ri32 tglobaltlsaddr :$dst)>; 1184// This corresponds to add $foo@tpoff, %rax 1185def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 1186 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 1187 1188 1189// Direct PC relative function call for small code model. 32-bit displacement 1190// sign extended to 64-bit. 1191def : Pat<(X86call (i64 tglobaladdr:$dst)), 1192 (CALL64pcrel32 tglobaladdr:$dst)>; 1193def : Pat<(X86call (i64 texternalsym:$dst)), 1194 (CALL64pcrel32 texternalsym:$dst)>; 1195 1196// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1197// can never use callee-saved registers. That is the purpose of the GR64_TC 1198// register classes. 1199// 1200// The only volatile register that is never used by the calling convention is 1201// %r11. This happens when calling a vararg function with 6 arguments. 1202// 1203// Match an X86tcret that uses less than 7 volatile registers. 1204def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 1205 (X86tcret node:$ptr, node:$off), [{ 1206 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1207 unsigned NumRegs = 0; 1208 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1209 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 1210 return false; 1211 return true; 1212}]>; 1213 1214def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1215 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, 1216 Requires<[Not64BitMode, NotUseRetpolineIndirectCalls]>; 1217 1218// FIXME: This is disabled for 32-bit PIC mode because the global base 1219// register which is part of the address mode may be assigned a 1220// callee-saved register. 1221def : Pat<(X86tcret (load addr:$dst), imm:$off), 1222 (TCRETURNmi addr:$dst, imm:$off)>, 1223 Requires<[Not64BitMode, IsNotPIC, NotUseRetpolineIndirectCalls]>; 1224 1225def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), 1226 (TCRETURNdi tglobaladdr:$dst, imm:$off)>, 1227 Requires<[NotLP64]>; 1228 1229def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), 1230 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1231 Requires<[NotLP64]>; 1232 1233def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1234 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, 1235 Requires<[In64BitMode, NotUseRetpolineIndirectCalls]>; 1236 1237// Don't fold loads into X86tcret requiring more than 6 regs. 1238// There wouldn't be enough scratch registers for base+index. 1239def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), 1240 (TCRETURNmi64 addr:$dst, imm:$off)>, 1241 Requires<[In64BitMode, NotUseRetpolineIndirectCalls]>; 1242 1243def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1244 (RETPOLINE_TCRETURN64 ptr_rc_tailcall:$dst, imm:$off)>, 1245 Requires<[In64BitMode, UseRetpolineIndirectCalls]>; 1246 1247def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1248 (RETPOLINE_TCRETURN32 ptr_rc_tailcall:$dst, imm:$off)>, 1249 Requires<[Not64BitMode, UseRetpolineIndirectCalls]>; 1250 1251def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), 1252 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, 1253 Requires<[IsLP64]>; 1254 1255def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), 1256 (TCRETURNdi64 texternalsym:$dst, imm:$off)>, 1257 Requires<[IsLP64]>; 1258 1259// Normal calls, with various flavors of addresses. 1260def : Pat<(X86call (i32 tglobaladdr:$dst)), 1261 (CALLpcrel32 tglobaladdr:$dst)>; 1262def : Pat<(X86call (i32 texternalsym:$dst)), 1263 (CALLpcrel32 texternalsym:$dst)>; 1264def : Pat<(X86call (i32 imm:$dst)), 1265 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1266 1267// Comparisons. 1268 1269// TEST R,R is smaller than CMP R,0 1270def : Pat<(X86cmp GR8:$src1, 0), 1271 (TEST8rr GR8:$src1, GR8:$src1)>; 1272def : Pat<(X86cmp GR16:$src1, 0), 1273 (TEST16rr GR16:$src1, GR16:$src1)>; 1274def : Pat<(X86cmp GR32:$src1, 0), 1275 (TEST32rr GR32:$src1, GR32:$src1)>; 1276def : Pat<(X86cmp GR64:$src1, 0), 1277 (TEST64rr GR64:$src1, GR64:$src1)>; 1278 1279def inv_cond_XFORM : SDNodeXForm<imm, [{ 1280 X86::CondCode CC = static_cast<X86::CondCode>(N->getZExtValue()); 1281 return CurDAG->getTargetConstant(X86::GetOppositeBranchCondition(CC), 1282 SDLoc(N), MVT::i8); 1283}]>; 1284 1285// Conditional moves with folded loads with operands swapped and conditions 1286// inverted. 1287let Predicates = [HasCMov] in { 1288 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, imm:$cond, EFLAGS), 1289 (CMOV16rm GR16:$src2, addr:$src1, (inv_cond_XFORM imm:$cond))>; 1290 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, imm:$cond, EFLAGS), 1291 (CMOV32rm GR32:$src2, addr:$src1, (inv_cond_XFORM imm:$cond))>; 1292 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, imm:$cond, EFLAGS), 1293 (CMOV64rm GR64:$src2, addr:$src1, (inv_cond_XFORM imm:$cond))>; 1294} 1295 1296// zextload bool -> zextload byte 1297// i1 stored in one byte in zero-extended form. 1298// Upper bits cleanup should be executed before Store. 1299def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1300def : Pat<(zextloadi16i1 addr:$src), 1301 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1302def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1303def : Pat<(zextloadi64i1 addr:$src), 1304 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1305 1306// extload bool -> extload byte 1307// When extloading from 16-bit and smaller memory locations into 64-bit 1308// registers, use zero-extending loads so that the entire 64-bit register is 1309// defined, avoiding partial-register updates. 1310 1311def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1312def : Pat<(extloadi16i1 addr:$src), 1313 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1314def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1315def : Pat<(extloadi16i8 addr:$src), 1316 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1317def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1318def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1319 1320// For other extloads, use subregs, since the high contents of the register are 1321// defined after an extload. 1322// NOTE: The extloadi64i32 pattern needs to be first as it will try to form 1323// 32-bit loads for 4 byte aligned i8/i16 loads. 1324def : Pat<(extloadi64i32 addr:$src), 1325 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1326def : Pat<(extloadi64i1 addr:$src), 1327 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1328def : Pat<(extloadi64i8 addr:$src), 1329 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1330def : Pat<(extloadi64i16 addr:$src), 1331 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1332 1333// anyext. Define these to do an explicit zero-extend to 1334// avoid partial-register updates. 1335def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1336 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1337def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1338 1339// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1340def : Pat<(i32 (anyext GR16:$src)), 1341 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1342 1343def : Pat<(i64 (anyext GR8 :$src)), 1344 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1345def : Pat<(i64 (anyext GR16:$src)), 1346 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1347def : Pat<(i64 (anyext GR32:$src)), 1348 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>; 1349 1350// If this is an anyext of the remainder of an 8-bit sdivrem, use a MOVSX 1351// instead of a MOVZX. The sdivrem lowering will emit emit a MOVSX to move 1352// %ah to the lower byte of a register. By using a MOVSX here we allow a 1353// post-isel peephole to merge the two MOVSX instructions into one. 1354def anyext_sdiv : PatFrag<(ops node:$lhs), (anyext node:$lhs),[{ 1355 return (N->getOperand(0).getOpcode() == ISD::SDIVREM && 1356 N->getOperand(0).getResNo() == 1); 1357}]>; 1358def : Pat<(i32 (anyext_sdiv GR8:$src)), (MOVSX32rr8 GR8:$src)>; 1359 1360// Any instruction that defines a 32-bit result leaves the high half of the 1361// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1362// be copying from a truncate. Any other 32-bit operation will zero-extend 1363// up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper 1364// 32 bits, they're probably just qualifying a CopyFromReg. 1365def def32 : PatLeaf<(i32 GR32:$src), [{ 1366 return N->getOpcode() != ISD::TRUNCATE && 1367 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1368 N->getOpcode() != ISD::CopyFromReg && 1369 N->getOpcode() != ISD::AssertSext && 1370 N->getOpcode() != ISD::AssertZext; 1371}]>; 1372 1373// In the case of a 32-bit def that is known to implicitly zero-extend, 1374// we can use a SUBREG_TO_REG. 1375def : Pat<(i64 (zext def32:$src)), 1376 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1377def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)), 1378 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1379 1380//===----------------------------------------------------------------------===// 1381// Pattern match OR as ADD 1382//===----------------------------------------------------------------------===// 1383 1384// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1385// 3-addressified into an LEA instruction to avoid copies. However, we also 1386// want to finally emit these instructions as an or at the end of the code 1387// generator to make the generated code easier to read. To do this, we select 1388// into "disjoint bits" pseudo ops. 1389 1390// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1391def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1392 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1393 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1394 1395 KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0); 1396 KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0); 1397 return (~Known0.Zero & ~Known1.Zero) == 0; 1398}]>; 1399 1400 1401// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1402// Try this before the selecting to OR. 1403let SchedRW = [WriteALU] in { 1404 1405let isConvertibleToThreeAddress = 1, isPseudo = 1, 1406 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1407let isCommutable = 1 in { 1408def ADD8rr_DB : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), 1409 "", // orb/addb REG, REG 1410 [(set GR8:$dst, (or_is_add GR8:$src1, GR8:$src2))]>; 1411def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1412 "", // orw/addw REG, REG 1413 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1414def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1415 "", // orl/addl REG, REG 1416 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1417def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1418 "", // orq/addq REG, REG 1419 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1420} // isCommutable 1421 1422// NOTE: These are order specific, we want the ri8 forms to be listed 1423// first so that they are slightly preferred to the ri forms. 1424 1425def ADD8ri_DB : I<0, Pseudo, 1426 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), 1427 "", // orb/addb REG, imm8 1428 [(set GR8:$dst, (or_is_add GR8:$src1, imm:$src2))]>; 1429def ADD16ri8_DB : I<0, Pseudo, 1430 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1431 "", // orw/addw REG, imm8 1432 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1433def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1434 "", // orw/addw REG, imm 1435 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1436 1437def ADD32ri8_DB : I<0, Pseudo, 1438 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1439 "", // orl/addl REG, imm8 1440 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1441def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1442 "", // orl/addl REG, imm 1443 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1444 1445 1446def ADD64ri8_DB : I<0, Pseudo, 1447 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1448 "", // orq/addq REG, imm8 1449 [(set GR64:$dst, (or_is_add GR64:$src1, 1450 i64immSExt8:$src2))]>; 1451def ADD64ri32_DB : I<0, Pseudo, 1452 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1453 "", // orq/addq REG, imm 1454 [(set GR64:$dst, (or_is_add GR64:$src1, 1455 i64immSExt32:$src2))]>; 1456} 1457} // AddedComplexity, SchedRW 1458 1459//===----------------------------------------------------------------------===// 1460// Pattern match SUB as XOR 1461//===----------------------------------------------------------------------===// 1462 1463// An immediate in the LHS of a subtract can't be encoded in the instruction. 1464// If there is no possibility of a borrow we can use an XOR instead of a SUB 1465// to enable the immediate to be folded. 1466// TODO: Move this to a DAG combine? 1467 1468def sub_is_xor : PatFrag<(ops node:$lhs, node:$rhs), (sub node:$lhs, node:$rhs),[{ 1469 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 1470 KnownBits Known = CurDAG->computeKnownBits(N->getOperand(1)); 1471 1472 // If all possible ones in the RHS are set in the LHS then there can't be 1473 // a borrow and we can use xor. 1474 return (~Known.Zero).isSubsetOf(CN->getAPIntValue()); 1475 } 1476 1477 return false; 1478}]>; 1479 1480let AddedComplexity = 5 in { 1481def : Pat<(sub_is_xor imm:$src2, GR8:$src1), 1482 (XOR8ri GR8:$src1, imm:$src2)>; 1483def : Pat<(sub_is_xor i16immSExt8:$src2, GR16:$src1), 1484 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1485def : Pat<(sub_is_xor imm:$src2, GR16:$src1), 1486 (XOR16ri GR16:$src1, imm:$src2)>; 1487def : Pat<(sub_is_xor i32immSExt8:$src2, GR32:$src1), 1488 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1489def : Pat<(sub_is_xor imm:$src2, GR32:$src1), 1490 (XOR32ri GR32:$src1, imm:$src2)>; 1491def : Pat<(sub_is_xor i64immSExt8:$src2, GR64:$src1), 1492 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1493def : Pat<(sub_is_xor i64immSExt32:$src2, GR64:$src1), 1494 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1495} 1496 1497//===----------------------------------------------------------------------===// 1498// Some peepholes 1499//===----------------------------------------------------------------------===// 1500 1501// Odd encoding trick: -128 fits into an 8-bit immediate field while 1502// +128 doesn't, so in this special case use a sub instead of an add. 1503def : Pat<(add GR16:$src1, 128), 1504 (SUB16ri8 GR16:$src1, -128)>; 1505def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1506 (SUB16mi8 addr:$dst, -128)>; 1507 1508def : Pat<(add GR32:$src1, 128), 1509 (SUB32ri8 GR32:$src1, -128)>; 1510def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1511 (SUB32mi8 addr:$dst, -128)>; 1512 1513def : Pat<(add GR64:$src1, 128), 1514 (SUB64ri8 GR64:$src1, -128)>; 1515def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1516 (SUB64mi8 addr:$dst, -128)>; 1517 1518def : Pat<(X86add_flag_nocf GR16:$src1, 128), 1519 (SUB16ri8 GR16:$src1, -128)>; 1520def : Pat<(X86add_flag_nocf GR32:$src1, 128), 1521 (SUB32ri8 GR32:$src1, -128)>; 1522def : Pat<(X86add_flag_nocf GR64:$src1, 128), 1523 (SUB64ri8 GR64:$src1, -128)>; 1524 1525// The same trick applies for 32-bit immediate fields in 64-bit 1526// instructions. 1527def : Pat<(add GR64:$src1, 0x0000000080000000), 1528 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1529def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst), 1530 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1531 1532def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000), 1533 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1534 1535// To avoid needing to materialize an immediate in a register, use a 32-bit and 1536// with implicit zero-extension instead of a 64-bit and if the immediate has at 1537// least 32 bits of leading zeros. If in addition the last 32 bits can be 1538// represented with a sign extension of a 8 bit constant, use that. 1539// This can also reduce instruction size by eliminating the need for the REX 1540// prefix. 1541 1542// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. 1543let AddedComplexity = 1 in { 1544def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1545 (SUBREG_TO_REG 1546 (i64 0), 1547 (AND32ri8 1548 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1549 (i32 (GetLo32XForm imm:$imm))), 1550 sub_32bit)>; 1551 1552def : Pat<(and GR64:$src, i64immZExt32:$imm), 1553 (SUBREG_TO_REG 1554 (i64 0), 1555 (AND32ri 1556 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1557 (i32 (GetLo32XForm imm:$imm))), 1558 sub_32bit)>; 1559} // AddedComplexity = 1 1560 1561 1562// AddedComplexity is needed due to the increased complexity on the 1563// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all 1564// the MOVZX patterns keeps thems together in DAGIsel tables. 1565let AddedComplexity = 1 in { 1566// r & (2^16-1) ==> movz 1567def : Pat<(and GR32:$src1, 0xffff), 1568 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1569// r & (2^8-1) ==> movz 1570def : Pat<(and GR32:$src1, 0xff), 1571 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>; 1572// r & (2^8-1) ==> movz 1573def : Pat<(and GR16:$src1, 0xff), 1574 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)), 1575 sub_16bit)>; 1576 1577// r & (2^32-1) ==> movz 1578def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1579 (SUBREG_TO_REG (i64 0), 1580 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1581 sub_32bit)>; 1582// r & (2^16-1) ==> movz 1583def : Pat<(and GR64:$src, 0xffff), 1584 (SUBREG_TO_REG (i64 0), 1585 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1586 sub_32bit)>; 1587// r & (2^8-1) ==> movz 1588def : Pat<(and GR64:$src, 0xff), 1589 (SUBREG_TO_REG (i64 0), 1590 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1591 sub_32bit)>; 1592} // AddedComplexity = 1 1593 1594 1595// Try to use BTS/BTR/BTC for single bit operations on the upper 32-bits. 1596 1597def BTRXForm : SDNodeXForm<imm, [{ 1598 // Transformation function: Find the lowest 0. 1599 return getI64Imm((uint8_t)N->getAPIntValue().countTrailingOnes(), SDLoc(N)); 1600}]>; 1601 1602def BTCBTSXForm : SDNodeXForm<imm, [{ 1603 // Transformation function: Find the lowest 1. 1604 return getI64Imm((uint8_t)N->getAPIntValue().countTrailingZeros(), SDLoc(N)); 1605}]>; 1606 1607def BTRMask64 : ImmLeaf<i64, [{ 1608 return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm); 1609}]>; 1610 1611def BTCBTSMask64 : ImmLeaf<i64, [{ 1612 return !isInt<32>(Imm) && isPowerOf2_64(Imm); 1613}]>; 1614 1615// For now only do this for optsize. 1616let AddedComplexity = 1, Predicates=[OptForSize] in { 1617 def : Pat<(and GR64:$src1, BTRMask64:$mask), 1618 (BTR64ri8 GR64:$src1, (BTRXForm imm:$mask))>; 1619 def : Pat<(or GR64:$src1, BTCBTSMask64:$mask), 1620 (BTS64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1621 def : Pat<(xor GR64:$src1, BTCBTSMask64:$mask), 1622 (BTC64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1623} 1624 1625 1626// sext_inreg patterns 1627def : Pat<(sext_inreg GR32:$src, i16), 1628 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1629def : Pat<(sext_inreg GR32:$src, i8), 1630 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>; 1631 1632def : Pat<(sext_inreg GR16:$src, i8), 1633 (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)), 1634 sub_16bit)>; 1635 1636def : Pat<(sext_inreg GR64:$src, i32), 1637 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1638def : Pat<(sext_inreg GR64:$src, i16), 1639 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1640def : Pat<(sext_inreg GR64:$src, i8), 1641 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1642 1643// sext, sext_load, zext, zext_load 1644def: Pat<(i16 (sext GR8:$src)), 1645 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1646def: Pat<(sextloadi16i8 addr:$src), 1647 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1648def: Pat<(i16 (zext GR8:$src)), 1649 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1650def: Pat<(zextloadi16i8 addr:$src), 1651 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1652 1653// trunc patterns 1654def : Pat<(i16 (trunc GR32:$src)), 1655 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1656def : Pat<(i8 (trunc GR32:$src)), 1657 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1658 sub_8bit)>, 1659 Requires<[Not64BitMode]>; 1660def : Pat<(i8 (trunc GR16:$src)), 1661 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1662 sub_8bit)>, 1663 Requires<[Not64BitMode]>; 1664def : Pat<(i32 (trunc GR64:$src)), 1665 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1666def : Pat<(i16 (trunc GR64:$src)), 1667 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1668def : Pat<(i8 (trunc GR64:$src)), 1669 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1670def : Pat<(i8 (trunc GR32:$src)), 1671 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1672 Requires<[In64BitMode]>; 1673def : Pat<(i8 (trunc GR16:$src)), 1674 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1675 Requires<[In64BitMode]>; 1676 1677def immff00_ffff : ImmLeaf<i32, [{ 1678 return Imm >= 0xff00 && Imm <= 0xffff; 1679}]>; 1680 1681// h-register tricks 1682def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1683 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1684 Requires<[Not64BitMode]>; 1685def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))), 1686 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1687 Requires<[Not64BitMode]>; 1688def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1689 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>, 1690 Requires<[Not64BitMode]>; 1691def : Pat<(srl GR16:$src, (i8 8)), 1692 (EXTRACT_SUBREG 1693 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1694 sub_16bit)>; 1695def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1696 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1697def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1698 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1699def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1700 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1701def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)), 1702 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1703 1704// h-register tricks. 1705// For now, be conservative on x86-64 and use an h-register extract only if the 1706// value is immediately zero-extended or stored, which are somewhat common 1707// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1708// from being allocated in the same instruction as the h register, as there's 1709// currently no way to describe this requirement to the register allocator. 1710 1711// h-register extract and zero-extend. 1712def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1713 (SUBREG_TO_REG 1714 (i64 0), 1715 (MOVZX32rr8_NOREX 1716 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), 1717 sub_32bit)>; 1718def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1719 (SUBREG_TO_REG 1720 (i64 0), 1721 (MOVZX32rr8_NOREX 1722 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1723 sub_32bit)>; 1724def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1725 (SUBREG_TO_REG 1726 (i64 0), 1727 (MOVZX32rr8_NOREX 1728 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1729 sub_32bit)>; 1730 1731// h-register extract and store. 1732def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1733 (MOV8mr_NOREX 1734 addr:$dst, 1735 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>; 1736def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1737 (MOV8mr_NOREX 1738 addr:$dst, 1739 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, 1740 Requires<[In64BitMode]>; 1741def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1742 (MOV8mr_NOREX 1743 addr:$dst, 1744 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, 1745 Requires<[In64BitMode]>; 1746 1747 1748// (shl x, 1) ==> (add x, x) 1749// Note that if x is undef (immediate or otherwise), we could theoretically 1750// end up with the two uses of x getting different values, producing a result 1751// where the least significant bit is not 0. However, the probability of this 1752// happening is considered low enough that this is officially not a 1753// "real problem". 1754def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1755def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1756def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1757def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1758 1759def shiftMask8 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1760 return isUnneededShiftMask(N, 3); 1761}]>; 1762 1763def shiftMask16 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1764 return isUnneededShiftMask(N, 4); 1765}]>; 1766 1767def shiftMask32 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1768 return isUnneededShiftMask(N, 5); 1769}]>; 1770 1771def shiftMask64 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1772 return isUnneededShiftMask(N, 6); 1773}]>; 1774 1775 1776// Shift amount is implicitly masked. 1777multiclass MaskedShiftAmountPats<SDNode frag, string name> { 1778 // (shift x (and y, 31)) ==> (shift x, y) 1779 def : Pat<(frag GR8:$src1, (shiftMask32 CL)), 1780 (!cast<Instruction>(name # "8rCL") GR8:$src1)>; 1781 def : Pat<(frag GR16:$src1, (shiftMask32 CL)), 1782 (!cast<Instruction>(name # "16rCL") GR16:$src1)>; 1783 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1784 (!cast<Instruction>(name # "32rCL") GR32:$src1)>; 1785 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask32 CL)), addr:$dst), 1786 (!cast<Instruction>(name # "8mCL") addr:$dst)>; 1787 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask32 CL)), addr:$dst), 1788 (!cast<Instruction>(name # "16mCL") addr:$dst)>; 1789 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1790 (!cast<Instruction>(name # "32mCL") addr:$dst)>; 1791 1792 // (shift x (and y, 63)) ==> (shift x, y) 1793 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1794 (!cast<Instruction>(name # "64rCL") GR64:$src1)>; 1795 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1796 (!cast<Instruction>(name # "64mCL") addr:$dst)>; 1797} 1798 1799defm : MaskedShiftAmountPats<shl, "SHL">; 1800defm : MaskedShiftAmountPats<srl, "SHR">; 1801defm : MaskedShiftAmountPats<sra, "SAR">; 1802 1803// ROL/ROR instructions allow a stronger mask optimization than shift for 8- and 1804// 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount 1805// because over-rotating produces the same result. This is noted in the Intel 1806// docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation 1807// amount could affect EFLAGS results, but that does not matter because we are 1808// not tracking flags for these nodes. 1809multiclass MaskedRotateAmountPats<SDNode frag, string name> { 1810 // (rot x (and y, BitWidth - 1)) ==> (rot x, y) 1811 def : Pat<(frag GR8:$src1, (shiftMask8 CL)), 1812 (!cast<Instruction>(name # "8rCL") GR8:$src1)>; 1813 def : Pat<(frag GR16:$src1, (shiftMask16 CL)), 1814 (!cast<Instruction>(name # "16rCL") GR16:$src1)>; 1815 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1816 (!cast<Instruction>(name # "32rCL") GR32:$src1)>; 1817 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask8 CL)), addr:$dst), 1818 (!cast<Instruction>(name # "8mCL") addr:$dst)>; 1819 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask16 CL)), addr:$dst), 1820 (!cast<Instruction>(name # "16mCL") addr:$dst)>; 1821 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1822 (!cast<Instruction>(name # "32mCL") addr:$dst)>; 1823 1824 // (rot x (and y, 63)) ==> (rot x, y) 1825 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1826 (!cast<Instruction>(name # "64rCL") GR64:$src1)>; 1827 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1828 (!cast<Instruction>(name # "64mCL") addr:$dst)>; 1829} 1830 1831 1832defm : MaskedRotateAmountPats<rotl, "ROL">; 1833defm : MaskedRotateAmountPats<rotr, "ROR">; 1834 1835// Double shift amount is implicitly masked. 1836multiclass MaskedDoubleShiftAmountPats<SDNode frag, string name> { 1837 // (shift x (and y, 31)) ==> (shift x, y) 1838 def : Pat<(frag GR16:$src1, GR16:$src2, (shiftMask32 CL)), 1839 (!cast<Instruction>(name # "16rrCL") GR16:$src1, GR16:$src2)>; 1840 def : Pat<(frag GR32:$src1, GR32:$src2, (shiftMask32 CL)), 1841 (!cast<Instruction>(name # "32rrCL") GR32:$src1, GR32:$src2)>; 1842 1843 // (shift x (and y, 63)) ==> (shift x, y) 1844 def : Pat<(frag GR64:$src1, GR64:$src2, (shiftMask32 CL)), 1845 (!cast<Instruction>(name # "64rrCL") GR64:$src1, GR64:$src2)>; 1846} 1847 1848defm : MaskedDoubleShiftAmountPats<X86shld, "SHLD">; 1849defm : MaskedDoubleShiftAmountPats<X86shrd, "SHRD">; 1850 1851let Predicates = [HasBMI2] in { 1852 let AddedComplexity = 1 in { 1853 def : Pat<(sra GR32:$src1, (shiftMask32 GR8:$src2)), 1854 (SARX32rr GR32:$src1, 1855 (INSERT_SUBREG 1856 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1857 def : Pat<(sra GR64:$src1, (shiftMask64 GR8:$src2)), 1858 (SARX64rr GR64:$src1, 1859 (INSERT_SUBREG 1860 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1861 1862 def : Pat<(srl GR32:$src1, (shiftMask32 GR8:$src2)), 1863 (SHRX32rr GR32:$src1, 1864 (INSERT_SUBREG 1865 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1866 def : Pat<(srl GR64:$src1, (shiftMask64 GR8:$src2)), 1867 (SHRX64rr GR64:$src1, 1868 (INSERT_SUBREG 1869 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1870 1871 def : Pat<(shl GR32:$src1, (shiftMask32 GR8:$src2)), 1872 (SHLX32rr GR32:$src1, 1873 (INSERT_SUBREG 1874 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1875 def : Pat<(shl GR64:$src1, (shiftMask64 GR8:$src2)), 1876 (SHLX64rr GR64:$src1, 1877 (INSERT_SUBREG 1878 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1879 } 1880 1881 def : Pat<(sra (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), 1882 (SARX32rm addr:$src1, 1883 (INSERT_SUBREG 1884 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1885 def : Pat<(sra (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), 1886 (SARX64rm addr:$src1, 1887 (INSERT_SUBREG 1888 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1889 1890 def : Pat<(srl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), 1891 (SHRX32rm addr:$src1, 1892 (INSERT_SUBREG 1893 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1894 def : Pat<(srl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), 1895 (SHRX64rm addr:$src1, 1896 (INSERT_SUBREG 1897 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1898 1899 def : Pat<(shl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), 1900 (SHLX32rm addr:$src1, 1901 (INSERT_SUBREG 1902 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1903 def : Pat<(shl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), 1904 (SHLX64rm addr:$src1, 1905 (INSERT_SUBREG 1906 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1907} 1908 1909// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location. 1910multiclass one_bit_patterns<RegisterClass RC, ValueType VT, Instruction BTR, 1911 Instruction BTS, Instruction BTC, 1912 PatFrag ShiftMask> { 1913 def : Pat<(and RC:$src1, (rotl -2, GR8:$src2)), 1914 (BTR RC:$src1, 1915 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1916 def : Pat<(or RC:$src1, (shl 1, GR8:$src2)), 1917 (BTS RC:$src1, 1918 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1919 def : Pat<(xor RC:$src1, (shl 1, GR8:$src2)), 1920 (BTC RC:$src1, 1921 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1922 1923 // Similar to above, but removing unneeded masking of the shift amount. 1924 def : Pat<(and RC:$src1, (rotl -2, (ShiftMask GR8:$src2))), 1925 (BTR RC:$src1, 1926 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1927 def : Pat<(or RC:$src1, (shl 1, (ShiftMask GR8:$src2))), 1928 (BTS RC:$src1, 1929 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1930 def : Pat<(xor RC:$src1, (shl 1, (ShiftMask GR8:$src2))), 1931 (BTC RC:$src1, 1932 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1933} 1934 1935defm : one_bit_patterns<GR16, i16, BTR16rr, BTS16rr, BTC16rr, shiftMask16>; 1936defm : one_bit_patterns<GR32, i32, BTR32rr, BTS32rr, BTC32rr, shiftMask32>; 1937defm : one_bit_patterns<GR64, i64, BTR64rr, BTS64rr, BTC64rr, shiftMask64>; 1938 1939 1940// (anyext (setcc_carry)) -> (setcc_carry) 1941def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1942 (SETB_C16r)>; 1943def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1944 (SETB_C32r)>; 1945def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), 1946 (SETB_C32r)>; 1947 1948//===----------------------------------------------------------------------===// 1949// EFLAGS-defining Patterns 1950//===----------------------------------------------------------------------===// 1951 1952// add reg, reg 1953def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1954def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1955def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1956def : Pat<(add GR64:$src1, GR64:$src2), (ADD64rr GR64:$src1, GR64:$src2)>; 1957 1958// add reg, mem 1959def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1960 (ADD8rm GR8:$src1, addr:$src2)>; 1961def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1962 (ADD16rm GR16:$src1, addr:$src2)>; 1963def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1964 (ADD32rm GR32:$src1, addr:$src2)>; 1965def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1966 (ADD64rm GR64:$src1, addr:$src2)>; 1967 1968// add reg, imm 1969def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1970def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1971def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1972def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1973 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1974def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1975 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1976def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1977 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1978def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1979 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1980 1981// sub reg, reg 1982def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1983def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1984def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1985def : Pat<(sub GR64:$src1, GR64:$src2), (SUB64rr GR64:$src1, GR64:$src2)>; 1986 1987// sub reg, mem 1988def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1989 (SUB8rm GR8:$src1, addr:$src2)>; 1990def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1991 (SUB16rm GR16:$src1, addr:$src2)>; 1992def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1993 (SUB32rm GR32:$src1, addr:$src2)>; 1994def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1995 (SUB64rm GR64:$src1, addr:$src2)>; 1996 1997// sub reg, imm 1998def : Pat<(sub GR8:$src1, imm:$src2), 1999 (SUB8ri GR8:$src1, imm:$src2)>; 2000def : Pat<(sub GR16:$src1, imm:$src2), 2001 (SUB16ri GR16:$src1, imm:$src2)>; 2002def : Pat<(sub GR32:$src1, imm:$src2), 2003 (SUB32ri GR32:$src1, imm:$src2)>; 2004def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 2005 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 2006def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 2007 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 2008def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 2009 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 2010def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 2011 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 2012 2013// sub 0, reg 2014def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; 2015def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; 2016def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; 2017def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; 2018 2019// sub reg, relocImm 2020def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt8_su:$src2), 2021 (SUB64ri8 GR64:$src1, i64relocImmSExt8_su:$src2)>; 2022 2023// mul reg, reg 2024def : Pat<(mul GR16:$src1, GR16:$src2), 2025 (IMUL16rr GR16:$src1, GR16:$src2)>; 2026def : Pat<(mul GR32:$src1, GR32:$src2), 2027 (IMUL32rr GR32:$src1, GR32:$src2)>; 2028def : Pat<(mul GR64:$src1, GR64:$src2), 2029 (IMUL64rr GR64:$src1, GR64:$src2)>; 2030 2031// mul reg, mem 2032def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 2033 (IMUL16rm GR16:$src1, addr:$src2)>; 2034def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 2035 (IMUL32rm GR32:$src1, addr:$src2)>; 2036def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 2037 (IMUL64rm GR64:$src1, addr:$src2)>; 2038 2039// mul reg, imm 2040def : Pat<(mul GR16:$src1, imm:$src2), 2041 (IMUL16rri GR16:$src1, imm:$src2)>; 2042def : Pat<(mul GR32:$src1, imm:$src2), 2043 (IMUL32rri GR32:$src1, imm:$src2)>; 2044def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 2045 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 2046def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 2047 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 2048def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 2049 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 2050def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 2051 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 2052 2053// reg = mul mem, imm 2054def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 2055 (IMUL16rmi addr:$src1, imm:$src2)>; 2056def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 2057 (IMUL32rmi addr:$src1, imm:$src2)>; 2058def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 2059 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 2060def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 2061 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 2062def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 2063 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 2064def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 2065 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 2066 2067// Increment/Decrement reg. 2068// Do not make INC/DEC if it is slow 2069let Predicates = [UseIncDec] in { 2070 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>; 2071 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>; 2072 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>; 2073 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 2074 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>; 2075 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>; 2076 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>; 2077 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 2078 2079 def : Pat<(X86add_flag_nocf GR8:$src, -1), (DEC8r GR8:$src)>; 2080 def : Pat<(X86add_flag_nocf GR16:$src, -1), (DEC16r GR16:$src)>; 2081 def : Pat<(X86add_flag_nocf GR32:$src, -1), (DEC32r GR32:$src)>; 2082 def : Pat<(X86add_flag_nocf GR64:$src, -1), (DEC64r GR64:$src)>; 2083 def : Pat<(X86sub_flag_nocf GR8:$src, -1), (INC8r GR8:$src)>; 2084 def : Pat<(X86sub_flag_nocf GR16:$src, -1), (INC16r GR16:$src)>; 2085 def : Pat<(X86sub_flag_nocf GR32:$src, -1), (INC32r GR32:$src)>; 2086 def : Pat<(X86sub_flag_nocf GR64:$src, -1), (INC64r GR64:$src)>; 2087} 2088 2089// or reg/reg. 2090def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 2091def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 2092def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 2093def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 2094 2095// or reg/mem 2096def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 2097 (OR8rm GR8:$src1, addr:$src2)>; 2098def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 2099 (OR16rm GR16:$src1, addr:$src2)>; 2100def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 2101 (OR32rm GR32:$src1, addr:$src2)>; 2102def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 2103 (OR64rm GR64:$src1, addr:$src2)>; 2104 2105// or reg/imm 2106def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 2107def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 2108def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 2109def : Pat<(or GR16:$src1, i16immSExt8:$src2), 2110 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 2111def : Pat<(or GR32:$src1, i32immSExt8:$src2), 2112 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 2113def : Pat<(or GR64:$src1, i64immSExt8:$src2), 2114 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 2115def : Pat<(or GR64:$src1, i64immSExt32:$src2), 2116 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 2117 2118// xor reg/reg 2119def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 2120def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 2121def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 2122def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 2123 2124// xor reg/mem 2125def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 2126 (XOR8rm GR8:$src1, addr:$src2)>; 2127def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 2128 (XOR16rm GR16:$src1, addr:$src2)>; 2129def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 2130 (XOR32rm GR32:$src1, addr:$src2)>; 2131def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 2132 (XOR64rm GR64:$src1, addr:$src2)>; 2133 2134// xor reg/imm 2135def : Pat<(xor GR8:$src1, imm:$src2), 2136 (XOR8ri GR8:$src1, imm:$src2)>; 2137def : Pat<(xor GR16:$src1, imm:$src2), 2138 (XOR16ri GR16:$src1, imm:$src2)>; 2139def : Pat<(xor GR32:$src1, imm:$src2), 2140 (XOR32ri GR32:$src1, imm:$src2)>; 2141def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 2142 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 2143def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 2144 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 2145def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 2146 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 2147def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 2148 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 2149 2150// and reg/reg 2151def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 2152def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 2153def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 2154def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 2155 2156// and reg/mem 2157def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 2158 (AND8rm GR8:$src1, addr:$src2)>; 2159def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 2160 (AND16rm GR16:$src1, addr:$src2)>; 2161def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 2162 (AND32rm GR32:$src1, addr:$src2)>; 2163def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 2164 (AND64rm GR64:$src1, addr:$src2)>; 2165 2166// and reg/imm 2167def : Pat<(and GR8:$src1, imm:$src2), 2168 (AND8ri GR8:$src1, imm:$src2)>; 2169def : Pat<(and GR16:$src1, imm:$src2), 2170 (AND16ri GR16:$src1, imm:$src2)>; 2171def : Pat<(and GR32:$src1, imm:$src2), 2172 (AND32ri GR32:$src1, imm:$src2)>; 2173def : Pat<(and GR16:$src1, i16immSExt8:$src2), 2174 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 2175def : Pat<(and GR32:$src1, i32immSExt8:$src2), 2176 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 2177def : Pat<(and GR64:$src1, i64immSExt8:$src2), 2178 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 2179def : Pat<(and GR64:$src1, i64immSExt32:$src2), 2180 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 2181 2182// Bit scan instruction patterns to match explicit zero-undef behavior. 2183def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 2184def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 2185def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 2186def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 2187def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 2188def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 2189 2190// When HasMOVBE is enabled it is possible to get a non-legalized 2191// register-register 16 bit bswap. This maps it to a ROL instruction. 2192let Predicates = [HasMOVBE] in { 2193 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; 2194} 2195