1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the various pseudo instructions used by the compiler, 10// as well as Pat patterns used during instruction selection. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Pattern Matching Support 16 17def GetLo32XForm : SDNodeXForm<imm, [{ 18 // Transformation function: get the low 32 bits. 19 return getI32Imm((uint32_t)N->getZExtValue(), SDLoc(N)); 20}]>; 21 22 23//===----------------------------------------------------------------------===// 24// Random Pseudo Instructions. 25 26// PIC base construction. This expands to code that looks like this: 27// call $next_inst 28// popl %destreg" 29let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP], 30 SchedRW = [WriteJump] in 31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 32 "", []>; 33 34// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 35// a stack adjustment and the codegen must know that they may modify the stack 36// pointer before prolog-epilog rewriting occurs. 37// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 38// sub / add which can clobber EFLAGS. 39let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in { 40def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), 41 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 42 "#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>; 43def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 44 "#ADJCALLSTACKUP", 45 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 46 Requires<[NotLP64]>; 47} 48def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 49 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>; 50 51 52// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 53// a stack adjustment and the codegen must know that they may modify the stack 54// pointer before prolog-epilog rewriting occurs. 55// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 56// sub / add which can clobber EFLAGS. 57let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in { 58def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), 59 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 60 "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>; 61def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 62 "#ADJCALLSTACKUP", 63 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 64 Requires<[IsLP64]>; 65} 66def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 67 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>; 68 69let SchedRW = [WriteSystem] in { 70 71// x86-64 va_start lowering magic. 72let hasSideEffects = 1, mayStore = 1, Defs = [EFLAGS] in { 73def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 74 (outs), 75 (ins GR8:$al, i8mem:$regsavefi, variable_ops), 76 "#VASTART_SAVE_XMM_REGS $al, $regsavefi", 77 [(X86vastart_save_xmm_regs GR8:$al, addr:$regsavefi), 78 (implicit EFLAGS)]>; 79} 80 81let usesCustomInserter = 1, Defs = [EFLAGS] in { 82// The VAARG_64 and VAARG_X32 pseudo-instructions take the address of the 83// va_list, and place the address of the next argument into a register. 84let Defs = [EFLAGS] in { 85def VAARG_64 : I<0, Pseudo, 86 (outs GR64:$dst), 87 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 88 "#VAARG_64 $dst, $ap, $size, $mode, $align", 89 [(set GR64:$dst, 90 (X86vaarg64 addr:$ap, timm:$size, timm:$mode, timm:$align)), 91 (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>; 92def VAARG_X32 : I<0, Pseudo, 93 (outs GR32:$dst), 94 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 95 "#VAARG_X32 $dst, $ap, $size, $mode, $align", 96 [(set GR32:$dst, 97 (X86vaargx32 addr:$ap, timm:$size, timm:$mode, timm:$align)), 98 (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>; 99} 100 101// When using segmented stacks these are lowered into instructions which first 102// check if the current stacklet has enough free memory. If it does, memory is 103// allocated by bumping the stack pointer. Otherwise memory is allocated from 104// the heap. 105 106let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 107def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 108 "# variable sized alloca for segmented stacks", 109 [(set GR32:$dst, 110 (X86SegAlloca GR32:$size))]>, 111 Requires<[NotLP64]>; 112 113let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 114def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 115 "# variable sized alloca for segmented stacks", 116 [(set GR64:$dst, 117 (X86SegAlloca GR64:$size))]>, 118 Requires<[In64BitMode]>; 119 120// To protect against stack clash, dynamic allocation should perform a memory 121// probe at each page. 122 123let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 124def PROBED_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 125 "# variable sized alloca with probing", 126 [(set GR32:$dst, 127 (X86ProbedAlloca GR32:$size))]>, 128 Requires<[NotLP64]>; 129 130let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 131def PROBED_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 132 "# variable sized alloca with probing", 133 [(set GR64:$dst, 134 (X86ProbedAlloca GR64:$size))]>, 135 Requires<[In64BitMode]>; 136} 137 138let hasNoSchedulingInfo = 1 in 139def STACKALLOC_W_PROBING : I<0, Pseudo, (outs), (ins i64imm:$stacksize), 140 "# fixed size alloca with probing", 141 []>; 142 143// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 144// targets. These calls are needed to probe the stack when allocating more than 145// 4k bytes in one go. Touching the stack at 4K increments is necessary to 146// ensure that the guard pages used by the OS virtual memory manager are 147// allocated in correct sequence. 148// The main point of having separate instruction are extra unmodelled effects 149// (compared to ordinary calls) like stack pointer change. 150 151let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 152def DYN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size), 153 "# dynamic stack allocation", 154 [(X86DynAlloca GR32:$size)]>, 155 Requires<[NotLP64]>; 156 157let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 158def DYN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size), 159 "# dynamic stack allocation", 160 [(X86DynAlloca GR64:$size)]>, 161 Requires<[In64BitMode]>; 162} // SchedRW 163 164// These instructions XOR the frame pointer into a GPR. They are used in some 165// stack protection schemes. These are post-RA pseudos because we only know the 166// frame register after register allocation. 167let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in { 168 def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src), 169 "xorl\t$$FP, $src", []>, 170 Requires<[NotLP64]>, Sched<[WriteALU]>; 171 def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src), 172 "xorq\t$$FP $src", []>, 173 Requires<[In64BitMode]>, Sched<[WriteALU]>; 174} 175 176//===----------------------------------------------------------------------===// 177// EH Pseudo Instructions 178// 179let SchedRW = [WriteSystem] in { 180let isTerminator = 1, isReturn = 1, isBarrier = 1, 181 hasCtrlDep = 1, isCodeGenOnly = 1 in { 182def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 183 "ret\t#eh_return, addr: $addr", 184 [(X86ehret GR32:$addr)]>, Sched<[WriteJumpLd]>; 185 186} 187 188let isTerminator = 1, isReturn = 1, isBarrier = 1, 189 hasCtrlDep = 1, isCodeGenOnly = 1 in { 190def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 191 "ret\t#eh_return, addr: $addr", 192 [(X86ehret GR64:$addr)]>, Sched<[WriteJumpLd]>; 193 194} 195 196let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 197 isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1 in { 198 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>; 199 200 // CATCHRET needs a custom inserter for SEH. 201 let usesCustomInserter = 1 in 202 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), 203 "# CATCHRET", 204 [(catchret bb:$dst, bb:$from)]>; 205} 206 207let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 208 usesCustomInserter = 1 in { 209 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 210 "#EH_SJLJ_SETJMP32", 211 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 212 Requires<[Not64BitMode]>; 213 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 214 "#EH_SJLJ_SETJMP64", 215 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 216 Requires<[In64BitMode]>; 217 let isTerminator = 1 in { 218 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 219 "#EH_SJLJ_LONGJMP32", 220 [(X86eh_sjlj_longjmp addr:$buf)]>, 221 Requires<[Not64BitMode]>; 222 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 223 "#EH_SJLJ_LONGJMP64", 224 [(X86eh_sjlj_longjmp addr:$buf)]>, 225 Requires<[In64BitMode]>; 226 } 227} 228 229let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 230 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 231 "#EH_SjLj_Setup\t$dst", []>; 232} 233} // SchedRW 234 235//===----------------------------------------------------------------------===// 236// Pseudo instructions used by unwind info. 237// 238let isPseudo = 1, SchedRW = [WriteSystem] in { 239 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), 240 "#SEH_PushReg $reg", []>; 241 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 242 "#SEH_SaveReg $reg, $dst", []>; 243 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 244 "#SEH_SaveXMM $reg, $dst", []>; 245 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), 246 "#SEH_StackAlloc $size", []>; 247 def SEH_StackAlign : I<0, Pseudo, (outs), (ins i32imm:$align), 248 "#SEH_StackAlign $align", []>; 249 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), 250 "#SEH_SetFrame $reg, $offset", []>; 251 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), 252 "#SEH_PushFrame $mode", []>; 253 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), 254 "#SEH_EndPrologue", []>; 255 def SEH_Epilogue : I<0, Pseudo, (outs), (ins), 256 "#SEH_Epilogue", []>; 257} 258 259//===----------------------------------------------------------------------===// 260// Pseudo instructions used by KCFI. 261//===----------------------------------------------------------------------===// 262let 263 Defs = [R10, R11, EFLAGS] in { 264def KCFI_CHECK : PseudoI< 265 (outs), (ins GR64:$ptr, i32imm:$type), []>, Sched<[]>; 266} 267 268//===----------------------------------------------------------------------===// 269// Pseudo instructions used by address sanitizer. 270//===----------------------------------------------------------------------===// 271let 272 Defs = [R10, R11, EFLAGS] in { 273def ASAN_CHECK_MEMACCESS : PseudoI< 274 (outs), (ins GR64PLTSafe:$addr, i32imm:$accessinfo), 275 [(int_asan_check_memaccess GR64PLTSafe:$addr, (i32 timm:$accessinfo))]>, 276 Sched<[]>; 277} 278 279//===----------------------------------------------------------------------===// 280// Pseudo instructions used by segmented stacks. 281// 282 283// This is lowered into a RET instruction by MCInstLower. We need 284// this so that we don't have to have a MachineBasicBlock which ends 285// with a RET and also has successors. 286let isPseudo = 1, SchedRW = [WriteJumpLd] in { 287def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>; 288 289// This instruction is lowered to a RET followed by a MOV. The two 290// instructions are not generated on a higher level since then the 291// verifier sees a MachineBasicBlock ending with a non-terminator. 292def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>; 293} 294 295//===----------------------------------------------------------------------===// 296// Alias Instructions 297//===----------------------------------------------------------------------===// 298 299// Alias instruction mapping movr0 to xor. 300// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 301let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 302 isPseudo = 1, isMoveImm = 1, AddedComplexity = 10 in 303def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 304 [(set GR32:$dst, 0)]>, Sched<[WriteZero]>; 305 306// Other widths can also make use of the 32-bit xor, which may have a smaller 307// encoding and avoid partial register updates. 308let AddedComplexity = 10 in { 309def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 310def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 311def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>; 312} 313 314let Predicates = [OptForSize, Not64BitMode], 315 AddedComplexity = 10 in { 316 let SchedRW = [WriteALU] in { 317 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, 318 // which only require 3 bytes compared to MOV32ri which requires 5. 319 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { 320 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 321 [(set GR32:$dst, 1)]>; 322 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 323 [(set GR32:$dst, -1)]>; 324 } 325 } // SchedRW 326 327 // MOV16ri is 4 bytes, so the instructions above are smaller. 328 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; 329 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; 330} 331 332let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5, 333 SchedRW = [WriteALU] in { 334// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1. 335def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "", 336 [(set GR32:$dst, i32immSExt8:$src)]>, 337 Requires<[OptForMinSize, NotWin64WithoutFP]>; 338def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", 339 [(set GR64:$dst, i64immSExt8:$src)]>, 340 Requires<[OptForMinSize, NotWin64WithoutFP]>; 341} 342 343// Materialize i64 constant where top 32-bits are zero. This could theoretically 344// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 345// that would make it more difficult to rematerialize. 346let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 347 isPseudo = 1, SchedRW = [WriteMove] in 348def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "", 349 [(set GR64:$dst, i64immZExt32:$src)]>; 350 351// This 64-bit pseudo-move can also be used for labels in the x86-64 small code 352// model. 353def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [X86Wrapper]>; 354def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>; 355 356// Use sbb to materialize carry bit. 357let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteADC], 358 hasSideEffects = 0 in { 359// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 360// However, Pat<> can't replicate the destination reg into the inputs of the 361// result. 362def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", []>; 363def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", []>; 364} // isCodeGenOnly 365 366//===----------------------------------------------------------------------===// 367// String Pseudo Instructions 368// 369let SchedRW = [WriteMicrocoded] in { 370let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 371def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), 372 "{rep;movsb (%esi), %es:(%edi)|rep movsb es:[edi], [esi]}", 373 [(X86rep_movs i8)]>, REP, AdSize32, 374 Requires<[NotLP64]>; 375def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), 376 "{rep;movsw (%esi), %es:(%edi)|rep movsw es:[edi], [esi]}", 377 [(X86rep_movs i16)]>, REP, AdSize32, OpSize16, 378 Requires<[NotLP64]>; 379def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), 380 "{rep;movsl (%esi), %es:(%edi)|rep movsd es:[edi], [esi]}", 381 [(X86rep_movs i32)]>, REP, AdSize32, OpSize32, 382 Requires<[NotLP64]>; 383def REP_MOVSQ_32 : RI<0xA5, RawFrm, (outs), (ins), 384 "{rep;movsq (%esi), %es:(%edi)|rep movsq es:[edi], [esi]}", 385 [(X86rep_movs i64)]>, REP, AdSize32, 386 Requires<[NotLP64, In64BitMode]>; 387} 388 389let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 390def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), 391 "{rep;movsb (%rsi), %es:(%rdi)|rep movsb es:[rdi], [rsi]}", 392 [(X86rep_movs i8)]>, REP, AdSize64, 393 Requires<[IsLP64]>; 394def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), 395 "{rep;movsw (%rsi), %es:(%rdi)|rep movsw es:[rdi], [rsi]}", 396 [(X86rep_movs i16)]>, REP, AdSize64, OpSize16, 397 Requires<[IsLP64]>; 398def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), 399 "{rep;movsl (%rsi), %es:(%rdi)|rep movsdi es:[rdi], [rsi]}", 400 [(X86rep_movs i32)]>, REP, AdSize64, OpSize32, 401 Requires<[IsLP64]>; 402def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), 403 "{rep;movsq (%rsi), %es:(%rdi)|rep movsq es:[rdi], [rsi]}", 404 [(X86rep_movs i64)]>, REP, AdSize64, 405 Requires<[IsLP64]>; 406} 407 408// FIXME: Should use "(X86rep_stos AL)" as the pattern. 409let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 410 let Uses = [AL,ECX,EDI] in 411 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), 412 "{rep;stosb %al, %es:(%edi)|rep stosb es:[edi], al}", 413 [(X86rep_stos i8)]>, REP, AdSize32, 414 Requires<[NotLP64]>; 415 let Uses = [AX,ECX,EDI] in 416 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), 417 "{rep;stosw %ax, %es:(%edi)|rep stosw es:[edi], ax}", 418 [(X86rep_stos i16)]>, REP, AdSize32, OpSize16, 419 Requires<[NotLP64]>; 420 let Uses = [EAX,ECX,EDI] in 421 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), 422 "{rep;stosl %eax, %es:(%edi)|rep stosd es:[edi], eax}", 423 [(X86rep_stos i32)]>, REP, AdSize32, OpSize32, 424 Requires<[NotLP64]>; 425 let Uses = [RAX,RCX,RDI] in 426 def REP_STOSQ_32 : RI<0xAB, RawFrm, (outs), (ins), 427 "{rep;stosq %rax, %es:(%edi)|rep stosq es:[edi], rax}", 428 [(X86rep_stos i64)]>, REP, AdSize32, 429 Requires<[NotLP64, In64BitMode]>; 430} 431 432let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 433 let Uses = [AL,RCX,RDI] in 434 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), 435 "{rep;stosb %al, %es:(%rdi)|rep stosb es:[rdi], al}", 436 [(X86rep_stos i8)]>, REP, AdSize64, 437 Requires<[IsLP64]>; 438 let Uses = [AX,RCX,RDI] in 439 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), 440 "{rep;stosw %ax, %es:(%rdi)|rep stosw es:[rdi], ax}", 441 [(X86rep_stos i16)]>, REP, AdSize64, OpSize16, 442 Requires<[IsLP64]>; 443 let Uses = [RAX,RCX,RDI] in 444 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), 445 "{rep;stosl %eax, %es:(%rdi)|rep stosd es:[rdi], eax}", 446 [(X86rep_stos i32)]>, REP, AdSize64, OpSize32, 447 Requires<[IsLP64]>; 448 449 let Uses = [RAX,RCX,RDI] in 450 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), 451 "{rep;stosq %rax, %es:(%rdi)|rep stosq es:[rdi], rax}", 452 [(X86rep_stos i64)]>, REP, AdSize64, 453 Requires<[IsLP64]>; 454} 455} // SchedRW 456 457//===----------------------------------------------------------------------===// 458// Thread Local Storage Instructions 459// 460let SchedRW = [WriteSystem] in { 461 462// ELF TLS Support 463// All calls clobber the non-callee saved registers. ESP is marked as 464// a use to prevent stack-pointer assignments that appear immediately 465// before calls from potentially appearing dead. 466let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 467 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 468 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 469 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 470 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 471 usesCustomInserter = 1, Uses = [ESP, SSP] in { 472def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 473 "# TLS_addr32", 474 [(X86tlsaddr tls32addr:$sym)]>, 475 Requires<[Not64BitMode]>; 476def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 477 "# TLS_base_addr32", 478 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 479 Requires<[Not64BitMode]>; 480} 481 482// All calls clobber the non-callee saved registers. RSP is marked as 483// a use to prevent stack-pointer assignments that appear immediately 484// before calls from potentially appearing dead. 485let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 486 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 487 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 488 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 489 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 490 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 491 usesCustomInserter = 1, Uses = [RSP, SSP] in { 492def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 493 "# TLS_addr64", 494 [(X86tlsaddr tls64addr:$sym)]>, 495 Requires<[In64BitMode, IsLP64]>; 496def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 497 "# TLS_base_addr64", 498 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 499 Requires<[In64BitMode, IsLP64]>; 500def TLS_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 501 "# TLS_addrX32", 502 [(X86tlsaddr tls32addr:$sym)]>, 503 Requires<[In64BitMode, NotLP64]>; 504def TLS_base_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 505 "# TLS_base_addrX32", 506 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 507 Requires<[In64BitMode, NotLP64]>; 508} 509 510// TLSDESC only clobbers EAX and EFLAGS. ESP is marked as a use to prevent 511// stack-pointer assignments that appear immediately before calls from 512// potentially appearing dead. 513let Defs = [EAX, EFLAGS], usesCustomInserter = 1, Uses = [RSP, SSP] in { 514 def TLS_desc32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 515 "# TLS_desc32", [(X86tlsdesc tls32addr:$sym)]>; 516 def TLS_desc64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 517 "# TLS_desc64", [(X86tlsdesc tls64addr:$sym)]>; 518} 519 520// Darwin TLS Support 521// For i386, the address of the thunk is passed on the stack, on return the 522// address of the variable is in %eax. %ecx is trashed during the function 523// call. All other registers are preserved. 524let Defs = [EAX, ECX, EFLAGS, DF], 525 Uses = [ESP, SSP], 526 usesCustomInserter = 1 in 527def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 528 "# TLSCall_32", 529 [(X86TLSCall addr:$sym)]>, 530 Requires<[Not64BitMode]>; 531 532// For x86_64, the address of the thunk is passed in %rdi, but the 533// pseudo directly use the symbol, so do not add an implicit use of 534// %rdi. The lowering will do the right thing with RDI. 535// On return the address of the variable is in %rax. All other 536// registers are preserved. 537let Defs = [RAX, EFLAGS, DF], 538 Uses = [RSP, SSP], 539 usesCustomInserter = 1 in 540def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 541 "# TLSCall_64", 542 [(X86TLSCall addr:$sym)]>, 543 Requires<[In64BitMode]>; 544} // SchedRW 545 546//===----------------------------------------------------------------------===// 547// Conditional Move Pseudo Instructions 548 549// CMOV* - Used to implement the SELECT DAG operation. Expanded after 550// instruction selection into a branch sequence. 551multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> { 552 def CMOV#NAME : I<0, Pseudo, 553 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), 554 "#CMOV_"#NAME#" PSEUDO!", 555 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, timm:$cond, 556 EFLAGS)))]>; 557} 558 559let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in { 560 // X86 doesn't have 8-bit conditional moves. Use a customInserter to 561 // emit control flow. An alternative to this is to mark i8 SELECT as Promote, 562 // however that requires promoting the operands, and can induce additional 563 // i8 register pressure. 564 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>; 565 566 let Predicates = [NoCMOV] in { 567 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>; 568 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>; 569 } // Predicates = [NoCMOV] 570 571 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 572 // SSE1/SSE2. 573 let Predicates = [FPStackf32] in 574 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>; 575 576 let Predicates = [FPStackf64] in 577 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>; 578 579 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>; 580 581 let Predicates = [HasMMX] in 582 defm _VR64 : CMOVrr_PSEUDO<VR64, x86mmx>; 583 584 let Predicates = [HasSSE1,NoAVX512] in 585 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 586 let Predicates = [HasSSE2,NoAVX512] in { 587 defm _FR16 : CMOVrr_PSEUDO<FR16, f16>; 588 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>; 589 } 590 let Predicates = [HasAVX512] in { 591 defm _FR16X : CMOVrr_PSEUDO<FR16X, f16>; 592 defm _FR32X : CMOVrr_PSEUDO<FR32X, f32>; 593 defm _FR64X : CMOVrr_PSEUDO<FR64X, f64>; 594 } 595 let Predicates = [NoVLX] in { 596 defm _VR128 : CMOVrr_PSEUDO<VR128, v2i64>; 597 defm _VR256 : CMOVrr_PSEUDO<VR256, v4i64>; 598 } 599 let Predicates = [HasVLX] in { 600 defm _VR128X : CMOVrr_PSEUDO<VR128X, v2i64>; 601 defm _VR256X : CMOVrr_PSEUDO<VR256X, v4i64>; 602 } 603 defm _VR512 : CMOVrr_PSEUDO<VR512, v8i64>; 604 defm _VK1 : CMOVrr_PSEUDO<VK1, v1i1>; 605 defm _VK2 : CMOVrr_PSEUDO<VK2, v2i1>; 606 defm _VK4 : CMOVrr_PSEUDO<VK4, v4i1>; 607 defm _VK8 : CMOVrr_PSEUDO<VK8, v8i1>; 608 defm _VK16 : CMOVrr_PSEUDO<VK16, v16i1>; 609 defm _VK32 : CMOVrr_PSEUDO<VK32, v32i1>; 610 defm _VK64 : CMOVrr_PSEUDO<VK64, v64i1>; 611} // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] 612 613def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 614 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 615 616let Predicates = [NoVLX] in { 617 def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 618 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 619 def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 620 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 621 def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 622 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 623 def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 624 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 625 def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 626 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 627 628 def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 629 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 630 def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 631 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 632 def : Pat<(v8i32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 633 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 634 def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 635 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 636 def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 637 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 638} 639let Predicates = [HasVLX] in { 640 def : Pat<(v16i8 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 641 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 642 def : Pat<(v8i16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 643 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 644 def : Pat<(v8f16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 645 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 646 def : Pat<(v4i32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 647 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 648 def : Pat<(v4f32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 649 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 650 def : Pat<(v2f64 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 651 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 652 653 def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 654 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 655 def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 656 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 657 def : Pat<(v16f16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 658 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 659 def : Pat<(v8i32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 660 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 661 def : Pat<(v8f32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 662 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 663 def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 664 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 665} 666 667def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 668 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 669def : Pat<(v32i16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 670 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 671def : Pat<(v32f16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 672 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 673def : Pat<(v16i32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 674 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 675def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 676 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 677def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 678 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 679 680//===----------------------------------------------------------------------===// 681// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 682//===----------------------------------------------------------------------===// 683 684// FIXME: Use normal instructions and add lock prefix dynamically. 685 686// Memory barriers 687 688let isCodeGenOnly = 1, Defs = [EFLAGS] in 689def OR32mi8Locked : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$zero), 690 "or{l}\t{$zero, $dst|$dst, $zero}", []>, 691 Requires<[Not64BitMode]>, OpSize32, LOCK, 692 Sched<[WriteALURMW]>; 693 694// RegOpc corresponds to the mr version of the instruction 695// ImmOpc corresponds to the mi version of the instruction 696// ImmOpc8 corresponds to the mi8 version of the instruction 697// ImmMod corresponds to the instruction format of the mi and mi8 versions 698multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 699 Format ImmMod, SDNode Op, string mnemonic> { 700let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 701 SchedRW = [WriteALURMW] in { 702 703def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 704 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 705 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 706 !strconcat(mnemonic, "{b}\t", 707 "{$src2, $dst|$dst, $src2}"), 708 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK; 709 710def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 711 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 712 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 713 !strconcat(mnemonic, "{w}\t", 714 "{$src2, $dst|$dst, $src2}"), 715 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>, 716 OpSize16, LOCK; 717 718def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 719 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 720 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 721 !strconcat(mnemonic, "{l}\t", 722 "{$src2, $dst|$dst, $src2}"), 723 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>, 724 OpSize32, LOCK; 725 726def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 727 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 728 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 729 !strconcat(mnemonic, "{q}\t", 730 "{$src2, $dst|$dst, $src2}"), 731 [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK; 732 733// NOTE: These are order specific, we want the mi8 forms to be listed 734// first so that they are slightly preferred to the mi forms. 735def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 736 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 737 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 738 !strconcat(mnemonic, "{w}\t", 739 "{$src2, $dst|$dst, $src2}"), 740 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>, 741 OpSize16, LOCK; 742 743def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 744 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 745 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 746 !strconcat(mnemonic, "{l}\t", 747 "{$src2, $dst|$dst, $src2}"), 748 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>, 749 OpSize32, LOCK; 750 751def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 752 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 753 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 754 !strconcat(mnemonic, "{q}\t", 755 "{$src2, $dst|$dst, $src2}"), 756 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>, 757 LOCK; 758 759def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 760 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 761 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 762 !strconcat(mnemonic, "{b}\t", 763 "{$src2, $dst|$dst, $src2}"), 764 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK; 765 766def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 767 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 768 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 769 !strconcat(mnemonic, "{w}\t", 770 "{$src2, $dst|$dst, $src2}"), 771 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>, 772 OpSize16, LOCK; 773 774def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 775 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 776 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 777 !strconcat(mnemonic, "{l}\t", 778 "{$src2, $dst|$dst, $src2}"), 779 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>, 780 OpSize32, LOCK; 781 782def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 783 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 784 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 785 !strconcat(mnemonic, "{q}\t", 786 "{$src2, $dst|$dst, $src2}"), 787 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>, 788 LOCK; 789} 790 791} 792 793defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">; 794defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">; 795defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">; 796defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; 797defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; 798 799let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 800 SchedRW = [WriteALURMW] in { 801 let Predicates = [UseIncDec] in { 802 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), 803 "inc{b}\t$dst", 804 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i8 1)))]>, 805 LOCK; 806 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), 807 "inc{w}\t$dst", 808 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i16 1)))]>, 809 OpSize16, LOCK; 810 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), 811 "inc{l}\t$dst", 812 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i32 1)))]>, 813 OpSize32, LOCK; 814 815 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), 816 "dec{b}\t$dst", 817 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i8 1)))]>, 818 LOCK; 819 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), 820 "dec{w}\t$dst", 821 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i16 1)))]>, 822 OpSize16, LOCK; 823 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), 824 "dec{l}\t$dst", 825 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i32 1)))]>, 826 OpSize32, LOCK; 827 } 828 829 let Predicates = [UseIncDec, In64BitMode] in { 830 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), 831 "inc{q}\t$dst", 832 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i64 1)))]>, 833 LOCK; 834 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), 835 "dec{q}\t$dst", 836 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i64 1)))]>, 837 LOCK; 838 } 839} 840 841let Predicates = [UseIncDec] in { 842 // Additional patterns for -1 constant. 843 def : Pat<(X86lock_add addr:$dst, (i8 -1)), (LOCK_DEC8m addr:$dst)>; 844 def : Pat<(X86lock_add addr:$dst, (i16 -1)), (LOCK_DEC16m addr:$dst)>; 845 def : Pat<(X86lock_add addr:$dst, (i32 -1)), (LOCK_DEC32m addr:$dst)>; 846 def : Pat<(X86lock_sub addr:$dst, (i8 -1)), (LOCK_INC8m addr:$dst)>; 847 def : Pat<(X86lock_sub addr:$dst, (i16 -1)), (LOCK_INC16m addr:$dst)>; 848 def : Pat<(X86lock_sub addr:$dst, (i32 -1)), (LOCK_INC32m addr:$dst)>; 849} 850 851let Predicates = [UseIncDec, In64BitMode] in { 852 // Additional patterns for -1 constant. 853 def : Pat<(X86lock_add addr:$dst, (i64 -1)), (LOCK_DEC64m addr:$dst)>; 854 def : Pat<(X86lock_sub addr:$dst, (i64 -1)), (LOCK_INC64m addr:$dst)>; 855} 856 857// Atomic bit test. 858def X86LBTest : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisPtrTy<1>, 859 SDTCisVT<2, i8>, SDTCisVT<3, i32>]>; 860def x86bts : SDNode<"X86ISD::LBTS", X86LBTest, 861 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 862def x86btc : SDNode<"X86ISD::LBTC", X86LBTest, 863 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 864def x86btr : SDNode<"X86ISD::LBTR", X86LBTest, 865 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 866 867def X86LBTestRM : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>, 868 SDTCisInt<2>]>; 869 870def x86_rm_bts : SDNode<"X86ISD::LBTS_RM", X86LBTestRM, 871 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 872def x86_rm_btc : SDNode<"X86ISD::LBTC_RM", X86LBTestRM, 873 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 874def x86_rm_btr : SDNode<"X86ISD::LBTR_RM", X86LBTestRM, 875 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; 876 877 878multiclass ATOMIC_LOGIC_OP<Format Form, string s> { 879 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 880 SchedRW = [WriteBitTestSetRegRMW] in { 881 def 16m : Ii8<0xBA, Form, (outs), (ins i16mem:$src1, i8imm:$src2), 882 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"), 883 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 16)))]>, 884 OpSize16, TB, LOCK; 885 def 32m : Ii8<0xBA, Form, (outs), (ins i32mem:$src1, i8imm:$src2), 886 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"), 887 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 32)))]>, 888 OpSize32, TB, LOCK; 889 def 64m : RIi8<0xBA, Form, (outs), (ins i64mem:$src1, i8imm:$src2), 890 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"), 891 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 64)))]>, 892 TB, LOCK; 893 } 894} 895 896multiclass ATOMIC_LOGIC_OP_RM<bits<8> Opc8, string s> { 897 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 898 SchedRW = [WriteBitTestSetRegRMW] in { 899 def 16rm : I<Opc8, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 900 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"), 901 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR16:$src2))]>, 902 OpSize16, TB, LOCK; 903 def 32rm : I<Opc8, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 904 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"), 905 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR32:$src2))]>, 906 OpSize32, TB, LOCK; 907 def 64rm : RI<Opc8, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 908 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"), 909 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR64:$src2))]>, 910 TB, LOCK; 911 } 912} 913 914 915defm LOCK_BTS : ATOMIC_LOGIC_OP<MRM5m, "bts">; 916defm LOCK_BTC : ATOMIC_LOGIC_OP<MRM7m, "btc">; 917defm LOCK_BTR : ATOMIC_LOGIC_OP<MRM6m, "btr">; 918 919defm LOCK_BTS_RM : ATOMIC_LOGIC_OP_RM<0xAB, "bts">; 920defm LOCK_BTC_RM : ATOMIC_LOGIC_OP_RM<0xBB, "btc">; 921defm LOCK_BTR_RM : ATOMIC_LOGIC_OP_RM<0xB3, "btr">; 922 923// Atomic compare and swap. 924multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 925 string mnemonic, SDPatternOperator frag> { 926let isCodeGenOnly = 1, SchedRW = [WriteCMPXCHGRMW] in { 927 let Defs = [AL, EFLAGS], Uses = [AL] in 928 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 929 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 930 [(frag addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; 931 let Defs = [AX, EFLAGS], Uses = [AX] in 932 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 933 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 934 [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK; 935 let Defs = [EAX, EFLAGS], Uses = [EAX] in 936 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 937 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 938 [(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK; 939 let Defs = [RAX, EFLAGS], Uses = [RAX] in 940 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 941 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 942 [(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK; 943} 944} 945 946let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 947 Predicates = [HasCX8], SchedRW = [WriteCMPXCHGRMW], 948 isCodeGenOnly = 1, usesCustomInserter = 1 in { 949def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr), 950 "cmpxchg8b\t$ptr", 951 [(X86cas8 addr:$ptr)]>, TB, LOCK; 952} 953 954let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 955 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 956 isCodeGenOnly = 1, mayLoad = 1, mayStore = 1, hasSideEffects = 0 in { 957def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr), 958 "cmpxchg16b\t$ptr", 959 []>, TB, LOCK; 960} 961 962// This pseudo must be used when the frame uses RBX as 963// the base pointer. Indeed, in such situation RBX is a reserved 964// register and the register allocator will ignore any use/def of 965// it. In other words, the register will not fix the clobbering of 966// RBX that will happen when setting the arguments for the instrucion. 967// 968// Unlike the actual related instruction, we mark that this one 969// defines RBX (instead of using RBX). 970// The rationale is that we will define RBX during the expansion of 971// the pseudo. The argument feeding RBX is rbx_input. 972// 973// The additional argument, $rbx_save, is a temporary register used to 974// save the value of RBX across the actual instruction. 975// 976// To make sure the register assigned to $rbx_save does not interfere with 977// the definition of the actual instruction, we use a definition $dst which 978// is tied to $rbx_save. That way, the live-range of $rbx_save spans across 979// the instruction and we are sure we will have a valid register to restore 980// the value of RBX. 981let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX], 982 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 983 isCodeGenOnly = 1, isPseudo = 1, 984 mayLoad = 1, mayStore = 1, hasSideEffects = 0, 985 Constraints = "$rbx_save = $dst" in { 986def LCMPXCHG16B_SAVE_RBX : 987 I<0, Pseudo, (outs GR64:$dst), 988 (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), "", []>; 989} 990 991// Pseudo instruction that doesn't read/write RBX. Will be turned into either 992// LCMPXCHG16B_SAVE_RBX or LCMPXCHG16B via a custom inserter. 993let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RCX, RDX], 994 Predicates = [HasCX16,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 995 isCodeGenOnly = 1, isPseudo = 1, 996 mayLoad = 1, mayStore = 1, hasSideEffects = 0, 997 usesCustomInserter = 1 in { 998def LCMPXCHG16B_NO_RBX : 999 I<0, Pseudo, (outs), (ins i128mem:$ptr, GR64:$rbx_input), "", 1000 [(X86cas16 addr:$ptr, GR64:$rbx_input)]>; 1001} 1002 1003// This pseudo must be used when the frame uses RBX/EBX as 1004// the base pointer. 1005// cf comment for LCMPXCHG16B_SAVE_RBX. 1006let Defs = [EBX], Uses = [ECX, EAX], 1007 Predicates = [HasMWAITX], SchedRW = [WriteSystem], 1008 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst" in { 1009def MWAITX_SAVE_RBX : 1010 I<0, Pseudo, (outs GR64:$dst), 1011 (ins GR32:$ebx_input, GR64:$rbx_save), 1012 "mwaitx", 1013 []>; 1014} 1015 1016// Pseudo mwaitx instruction to use for custom insertion. 1017let Predicates = [HasMWAITX], SchedRW = [WriteSystem], 1018 isCodeGenOnly = 1, isPseudo = 1, 1019 usesCustomInserter = 1 in { 1020def MWAITX : 1021 I<0, Pseudo, (outs), (ins GR32:$ecx, GR32:$eax, GR32:$ebx), 1022 "mwaitx", 1023 [(int_x86_mwaitx GR32:$ecx, GR32:$eax, GR32:$ebx)]>; 1024} 1025 1026 1027defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>; 1028 1029// Atomic exchange and add 1030multiclass ATOMIC_RMW_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 1031 string frag> { 1032 let Constraints = "$val = $dst", Defs = [EFLAGS], mayLoad = 1, mayStore = 1, 1033 isCodeGenOnly = 1, SchedRW = [WriteALURMW] in { 1034 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 1035 (ins GR8:$val, i8mem:$ptr), 1036 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 1037 [(set GR8:$dst, 1038 (!cast<PatFrag>(frag # "_i8") addr:$ptr, GR8:$val))]>; 1039 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 1040 (ins GR16:$val, i16mem:$ptr), 1041 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 1042 [(set 1043 GR16:$dst, 1044 (!cast<PatFrag>(frag # "_i16") addr:$ptr, GR16:$val))]>, 1045 OpSize16; 1046 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 1047 (ins GR32:$val, i32mem:$ptr), 1048 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 1049 [(set 1050 GR32:$dst, 1051 (!cast<PatFrag>(frag # "_i32") addr:$ptr, GR32:$val))]>, 1052 OpSize32; 1053 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 1054 (ins GR64:$val, i64mem:$ptr), 1055 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 1056 [(set 1057 GR64:$dst, 1058 (!cast<PatFrag>(frag # "_i64") addr:$ptr, GR64:$val))]>; 1059 } 1060} 1061 1062defm LXADD : ATOMIC_RMW_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK; 1063 1064/* The following multiclass tries to make sure that in code like 1065 * x.store (immediate op x.load(acquire), release) 1066 * and 1067 * x.store (register op x.load(acquire), release) 1068 * an operation directly on memory is generated instead of wasting a register. 1069 * It is not automatic as atomic_store/load are only lowered to MOV instructions 1070 * extremely late to prevent them from being accidentally reordered in the backend 1071 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) 1072 */ 1073multiclass RELEASE_BINOP_MI<string Name, SDNode op> { 1074 def : Pat<(atomic_store_8 (op (atomic_load_8 addr:$dst), (i8 imm:$src)), 1075 addr:$dst), 1076 (!cast<Instruction>(Name#"8mi") addr:$dst, imm:$src)>; 1077 def : Pat<(atomic_store_16 (op (atomic_load_16 addr:$dst), (i16 imm:$src)), 1078 addr:$dst), 1079 (!cast<Instruction>(Name#"16mi") addr:$dst, imm:$src)>; 1080 def : Pat<(atomic_store_32 (op (atomic_load_32 addr:$dst), (i32 imm:$src)), 1081 addr:$dst), 1082 (!cast<Instruction>(Name#"32mi") addr:$dst, imm:$src)>; 1083 def : Pat<(atomic_store_64 (op (atomic_load_64 addr:$dst), (i64immSExt32:$src)), 1084 addr:$dst), 1085 (!cast<Instruction>(Name#"64mi32") addr:$dst, (i64immSExt32:$src))>; 1086 def : Pat<(atomic_store_8 (op (atomic_load_8 addr:$dst), (i8 GR8:$src)), addr:$dst), 1087 (!cast<Instruction>(Name#"8mr") addr:$dst, GR8:$src)>; 1088 def : Pat<(atomic_store_16 (op (atomic_load_16 addr:$dst), (i16 GR16:$src)), 1089 addr:$dst), 1090 (!cast<Instruction>(Name#"16mr") addr:$dst, GR16:$src)>; 1091 def : Pat<(atomic_store_32 (op (atomic_load_32 addr:$dst), (i32 GR32:$src)), 1092 addr:$dst), 1093 (!cast<Instruction>(Name#"32mr") addr:$dst, GR32:$src)>; 1094 def : Pat<(atomic_store_64 (op (atomic_load_64 addr:$dst), (i64 GR64:$src)), 1095 addr:$dst), 1096 (!cast<Instruction>(Name#"64mr") addr:$dst, GR64:$src)>; 1097} 1098defm : RELEASE_BINOP_MI<"ADD", add>; 1099defm : RELEASE_BINOP_MI<"AND", and>; 1100defm : RELEASE_BINOP_MI<"OR", or>; 1101defm : RELEASE_BINOP_MI<"XOR", xor>; 1102defm : RELEASE_BINOP_MI<"SUB", sub>; 1103 1104// Atomic load + floating point patterns. 1105// FIXME: This could also handle SIMD operations with *ps and *pd instructions. 1106multiclass ATOMIC_LOAD_FP_BINOP_MI<string Name, SDNode op> { 1107 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1108 (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>, 1109 Requires<[UseSSE1]>; 1110 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1111 (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>, 1112 Requires<[UseAVX]>; 1113 def : Pat<(op FR32X:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1114 (!cast<Instruction>("V"#Name#"SSZrm") FR32X:$src1, addr:$src2)>, 1115 Requires<[HasAVX512]>; 1116 1117 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1118 (!cast<Instruction>(Name#"SDrm") FR64:$src1, addr:$src2)>, 1119 Requires<[UseSSE1]>; 1120 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1121 (!cast<Instruction>("V"#Name#"SDrm") FR64:$src1, addr:$src2)>, 1122 Requires<[UseAVX]>; 1123 def : Pat<(op FR64X:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1124 (!cast<Instruction>("V"#Name#"SDZrm") FR64X:$src1, addr:$src2)>, 1125 Requires<[HasAVX512]>; 1126} 1127defm : ATOMIC_LOAD_FP_BINOP_MI<"ADD", fadd>; 1128defm : ATOMIC_LOAD_FP_BINOP_MI<"SUB", fsub>; 1129defm : ATOMIC_LOAD_FP_BINOP_MI<"MUL", fmul>; 1130defm : ATOMIC_LOAD_FP_BINOP_MI<"DIV", fdiv>; 1131 1132multiclass RELEASE_UNOP<string Name, dag dag8, dag dag16, dag dag32, 1133 dag dag64> { 1134 def : Pat<(atomic_store_8 dag8, addr:$dst), 1135 (!cast<Instruction>(Name#8m) addr:$dst)>; 1136 def : Pat<(atomic_store_16 dag16, addr:$dst), 1137 (!cast<Instruction>(Name#16m) addr:$dst)>; 1138 def : Pat<(atomic_store_32 dag32, addr:$dst), 1139 (!cast<Instruction>(Name#32m) addr:$dst)>; 1140 def : Pat<(atomic_store_64 dag64, addr:$dst), 1141 (!cast<Instruction>(Name#64m) addr:$dst)>; 1142} 1143 1144let Predicates = [UseIncDec] in { 1145 defm : RELEASE_UNOP<"INC", 1146 (add (atomic_load_8 addr:$dst), (i8 1)), 1147 (add (atomic_load_16 addr:$dst), (i16 1)), 1148 (add (atomic_load_32 addr:$dst), (i32 1)), 1149 (add (atomic_load_64 addr:$dst), (i64 1))>; 1150 defm : RELEASE_UNOP<"DEC", 1151 (add (atomic_load_8 addr:$dst), (i8 -1)), 1152 (add (atomic_load_16 addr:$dst), (i16 -1)), 1153 (add (atomic_load_32 addr:$dst), (i32 -1)), 1154 (add (atomic_load_64 addr:$dst), (i64 -1))>; 1155} 1156 1157defm : RELEASE_UNOP<"NEG", 1158 (ineg (i8 (atomic_load_8 addr:$dst))), 1159 (ineg (i16 (atomic_load_16 addr:$dst))), 1160 (ineg (i32 (atomic_load_32 addr:$dst))), 1161 (ineg (i64 (atomic_load_64 addr:$dst)))>; 1162defm : RELEASE_UNOP<"NOT", 1163 (not (i8 (atomic_load_8 addr:$dst))), 1164 (not (i16 (atomic_load_16 addr:$dst))), 1165 (not (i32 (atomic_load_32 addr:$dst))), 1166 (not (i64 (atomic_load_64 addr:$dst)))>; 1167 1168def : Pat<(atomic_store_8 (i8 imm:$src), addr:$dst), 1169 (MOV8mi addr:$dst, imm:$src)>; 1170def : Pat<(atomic_store_16 (i16 imm:$src), addr:$dst), 1171 (MOV16mi addr:$dst, imm:$src)>; 1172def : Pat<(atomic_store_32 (i32 imm:$src), addr:$dst), 1173 (MOV32mi addr:$dst, imm:$src)>; 1174def : Pat<(atomic_store_64 (i64immSExt32:$src), addr:$dst), 1175 (MOV64mi32 addr:$dst, i64immSExt32:$src)>; 1176 1177def : Pat<(atomic_store_8 GR8:$src, addr:$dst), 1178 (MOV8mr addr:$dst, GR8:$src)>; 1179def : Pat<(atomic_store_16 GR16:$src, addr:$dst), 1180 (MOV16mr addr:$dst, GR16:$src)>; 1181def : Pat<(atomic_store_32 GR32:$src, addr:$dst), 1182 (MOV32mr addr:$dst, GR32:$src)>; 1183def : Pat<(atomic_store_64 GR64:$src, addr:$dst), 1184 (MOV64mr addr:$dst, GR64:$src)>; 1185 1186def : Pat<(i8 (atomic_load_8 addr:$src)), (MOV8rm addr:$src)>; 1187def : Pat<(i16 (atomic_load_16 addr:$src)), (MOV16rm addr:$src)>; 1188def : Pat<(i32 (atomic_load_32 addr:$src)), (MOV32rm addr:$src)>; 1189def : Pat<(i64 (atomic_load_64 addr:$src)), (MOV64rm addr:$src)>; 1190 1191// Floating point loads/stores. 1192def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst), 1193 (MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>; 1194def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst), 1195 (VMOVSSmr addr:$dst, FR32:$src)>, Requires<[UseAVX]>; 1196def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst), 1197 (VMOVSSZmr addr:$dst, FR32:$src)>, Requires<[HasAVX512]>; 1198 1199def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst), 1200 (MOVSDmr addr:$dst, FR64:$src)>, Requires<[UseSSE2]>; 1201def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst), 1202 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[UseAVX]>; 1203def : Pat<(atomic_store_64 (i64 (bitconvert (f64 FR64:$src))), addr:$dst), 1204 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[HasAVX512]>; 1205 1206def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1207 (MOVSSrm_alt addr:$src)>, Requires<[UseSSE1]>; 1208def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1209 (VMOVSSrm_alt addr:$src)>, Requires<[UseAVX]>; 1210def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1211 (VMOVSSZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1212 1213def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1214 (MOVSDrm_alt addr:$src)>, Requires<[UseSSE2]>; 1215def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1216 (VMOVSDrm_alt addr:$src)>, Requires<[UseAVX]>; 1217def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1218 (VMOVSDZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1219 1220//===----------------------------------------------------------------------===// 1221// DAG Pattern Matching Rules 1222//===----------------------------------------------------------------------===// 1223 1224// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves 1225// binary size compared to a regular MOV, but it introduces an unnecessary 1226// load, so is not suitable for regular or optsize functions. 1227let Predicates = [OptForMinSize] in { 1228def : Pat<(simple_store (i16 0), addr:$dst), (AND16mi addr:$dst, 0)>; 1229def : Pat<(simple_store (i32 0), addr:$dst), (AND32mi addr:$dst, 0)>; 1230def : Pat<(simple_store (i64 0), addr:$dst), (AND64mi32 addr:$dst, 0)>; 1231def : Pat<(simple_store (i16 -1), addr:$dst), (OR16mi addr:$dst, -1)>; 1232def : Pat<(simple_store (i32 -1), addr:$dst), (OR32mi addr:$dst, -1)>; 1233def : Pat<(simple_store (i64 -1), addr:$dst), (OR64mi32 addr:$dst, -1)>; 1234} 1235 1236// In kernel code model, we can get the address of a label 1237// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 1238// the MOV64ri32 should accept these. 1239def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 1240 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 1241def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 1242 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 1243def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 1244 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 1245def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 1246 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 1247def : Pat<(i64 (X86Wrapper mcsym:$dst)), 1248 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; 1249def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 1250 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 1251 1252// If we have small model and -static mode, it is safe to store global addresses 1253// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 1254// for MOV64mi32 should handle this sort of thing. 1255def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 1256 (MOV64mi32 addr:$dst, tconstpool:$src)>, 1257 Requires<[NearData, IsNotPIC]>; 1258def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 1259 (MOV64mi32 addr:$dst, tjumptable:$src)>, 1260 Requires<[NearData, IsNotPIC]>; 1261def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1262 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 1263 Requires<[NearData, IsNotPIC]>; 1264def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 1265 (MOV64mi32 addr:$dst, texternalsym:$src)>, 1266 Requires<[NearData, IsNotPIC]>; 1267def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), 1268 (MOV64mi32 addr:$dst, mcsym:$src)>, 1269 Requires<[NearData, IsNotPIC]>; 1270def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 1271 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 1272 Requires<[NearData, IsNotPIC]>; 1273 1274def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; 1275def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; 1276 1277// Calls 1278 1279// tls has some funny stuff here... 1280// This corresponds to movabs $foo@tpoff, %rax 1281def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 1282 (MOV64ri32 tglobaltlsaddr :$dst)>; 1283// This corresponds to add $foo@tpoff, %rax 1284def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 1285 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 1286 1287 1288// Direct PC relative function call for small code model. 32-bit displacement 1289// sign extended to 64-bit. 1290def : Pat<(X86call (i64 tglobaladdr:$dst)), 1291 (CALL64pcrel32 tglobaladdr:$dst)>; 1292def : Pat<(X86call (i64 texternalsym:$dst)), 1293 (CALL64pcrel32 texternalsym:$dst)>; 1294 1295def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 texternalsym:$dst)), 1296 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, texternalsym:$dst)>; 1297def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 tglobaladdr:$dst)), 1298 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, tglobaladdr:$dst)>; 1299 1300 1301// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1302// can never use callee-saved registers. That is the purpose of the GR64_TC 1303// register classes. 1304// 1305// The only volatile register that is never used by the calling convention is 1306// %r11. This happens when calling a vararg function with 6 arguments. 1307// 1308// Match an X86tcret that uses less than 7 volatile registers. 1309def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1310 (TCRETURNri ptr_rc_tailcall:$dst, timm:$off)>, 1311 Requires<[Not64BitMode, NotUseIndirectThunkCalls]>; 1312 1313// FIXME: This is disabled for 32-bit PIC mode because the global base 1314// register which is part of the address mode may be assigned a 1315// callee-saved register. 1316// Similar to X86tcret_6regs, here we only have 1 register left 1317def : Pat<(X86tcret_1reg (load addr:$dst), timm:$off), 1318 (TCRETURNmi addr:$dst, timm:$off)>, 1319 Requires<[Not64BitMode, IsNotPIC, NotUseIndirectThunkCalls]>; 1320 1321def : Pat<(X86tcret (i32 tglobaladdr:$dst), timm:$off), 1322 (TCRETURNdi tglobaladdr:$dst, timm:$off)>, 1323 Requires<[NotLP64]>; 1324 1325def : Pat<(X86tcret (i32 texternalsym:$dst), timm:$off), 1326 (TCRETURNdi texternalsym:$dst, timm:$off)>, 1327 Requires<[NotLP64]>; 1328 1329def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1330 (TCRETURNri64 ptr_rc_tailcall:$dst, timm:$off)>, 1331 Requires<[In64BitMode, NotUseIndirectThunkCalls]>; 1332 1333// Don't fold loads into X86tcret requiring more than 6 regs. 1334// There wouldn't be enough scratch registers for base+index. 1335def : Pat<(X86tcret_6regs (load addr:$dst), timm:$off), 1336 (TCRETURNmi64 addr:$dst, timm:$off)>, 1337 Requires<[In64BitMode, NotUseIndirectThunkCalls]>; 1338 1339def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1340 (INDIRECT_THUNK_TCRETURN64 ptr_rc_tailcall:$dst, timm:$off)>, 1341 Requires<[In64BitMode, UseIndirectThunkCalls]>; 1342 1343def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1344 (INDIRECT_THUNK_TCRETURN32 ptr_rc_tailcall:$dst, timm:$off)>, 1345 Requires<[Not64BitMode, UseIndirectThunkCalls]>; 1346 1347def : Pat<(X86tcret (i64 tglobaladdr:$dst), timm:$off), 1348 (TCRETURNdi64 tglobaladdr:$dst, timm:$off)>, 1349 Requires<[IsLP64]>; 1350 1351def : Pat<(X86tcret (i64 texternalsym:$dst), timm:$off), 1352 (TCRETURNdi64 texternalsym:$dst, timm:$off)>, 1353 Requires<[IsLP64]>; 1354 1355// Normal calls, with various flavors of addresses. 1356def : Pat<(X86call (i32 tglobaladdr:$dst)), 1357 (CALLpcrel32 tglobaladdr:$dst)>; 1358def : Pat<(X86call (i32 texternalsym:$dst)), 1359 (CALLpcrel32 texternalsym:$dst)>; 1360def : Pat<(X86call (i32 imm:$dst)), 1361 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1362 1363// Comparisons. 1364 1365// TEST R,R is smaller than CMP R,0 1366def : Pat<(X86cmp GR8:$src1, 0), 1367 (TEST8rr GR8:$src1, GR8:$src1)>; 1368def : Pat<(X86cmp GR16:$src1, 0), 1369 (TEST16rr GR16:$src1, GR16:$src1)>; 1370def : Pat<(X86cmp GR32:$src1, 0), 1371 (TEST32rr GR32:$src1, GR32:$src1)>; 1372def : Pat<(X86cmp GR64:$src1, 0), 1373 (TEST64rr GR64:$src1, GR64:$src1)>; 1374 1375// zextload bool -> zextload byte 1376// i1 stored in one byte in zero-extended form. 1377// Upper bits cleanup should be executed before Store. 1378def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1379def : Pat<(zextloadi16i1 addr:$src), 1380 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1381def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1382def : Pat<(zextloadi64i1 addr:$src), 1383 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1384 1385// extload bool -> extload byte 1386// When extloading from 16-bit and smaller memory locations into 64-bit 1387// registers, use zero-extending loads so that the entire 64-bit register is 1388// defined, avoiding partial-register updates. 1389 1390def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1391def : Pat<(extloadi16i1 addr:$src), 1392 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1393def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1394def : Pat<(extloadi16i8 addr:$src), 1395 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1396def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1397def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1398 1399// For other extloads, use subregs, since the high contents of the register are 1400// defined after an extload. 1401// NOTE: The extloadi64i32 pattern needs to be first as it will try to form 1402// 32-bit loads for 4 byte aligned i8/i16 loads. 1403def : Pat<(extloadi64i32 addr:$src), 1404 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1405def : Pat<(extloadi64i1 addr:$src), 1406 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1407def : Pat<(extloadi64i8 addr:$src), 1408 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1409def : Pat<(extloadi64i16 addr:$src), 1410 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1411 1412// anyext. Define these to do an explicit zero-extend to 1413// avoid partial-register updates. 1414def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1415 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1416def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1417 1418// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1419def : Pat<(i32 (anyext GR16:$src)), 1420 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1421 1422def : Pat<(i64 (anyext GR8 :$src)), 1423 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1424def : Pat<(i64 (anyext GR16:$src)), 1425 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1426def : Pat<(i64 (anyext GR32:$src)), 1427 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>; 1428 1429def : Pat<(i32 (anyext_sdiv GR8:$src)), (MOVSX32rr8 GR8:$src)>; 1430 1431// In the case of a 32-bit def that is known to implicitly zero-extend, 1432// we can use a SUBREG_TO_REG. 1433def : Pat<(i64 (zext def32:$src)), 1434 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1435def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)), 1436 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1437 1438//===----------------------------------------------------------------------===// 1439// Pattern match OR as ADD 1440//===----------------------------------------------------------------------===// 1441 1442// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1443// 3-addressified into an LEA instruction to avoid copies. However, we also 1444// want to finally emit these instructions as an or at the end of the code 1445// generator to make the generated code easier to read. To do this, we select 1446// into "disjoint bits" pseudo ops. 1447 1448// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1449// Try this before the selecting to OR. 1450let SchedRW = [WriteALU] in { 1451 1452let isConvertibleToThreeAddress = 1, isPseudo = 1, 1453 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1454let isCommutable = 1 in { 1455def ADD8rr_DB : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), 1456 "", // orb/addb REG, REG 1457 [(set GR8:$dst, (or_is_add GR8:$src1, GR8:$src2))]>; 1458def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1459 "", // orw/addw REG, REG 1460 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1461def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1462 "", // orl/addl REG, REG 1463 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1464def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1465 "", // orq/addq REG, REG 1466 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1467} // isCommutable 1468 1469def ADD8ri_DB : I<0, Pseudo, 1470 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), 1471 "", // orb/addb REG, imm8 1472 [(set GR8:$dst, (or_is_add GR8:$src1, imm:$src2))]>; 1473def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1474 "", // orw/addw REG, imm 1475 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1476def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1477 "", // orl/addl REG, imm 1478 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1479def ADD64ri32_DB : I<0, Pseudo, 1480 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1481 "", // orq/addq REG, imm 1482 [(set GR64:$dst, (or_is_add GR64:$src1, 1483 i64immSExt32:$src2))]>; 1484} 1485} // AddedComplexity, SchedRW 1486 1487//===----------------------------------------------------------------------===// 1488// Pattern match XOR as ADD 1489//===----------------------------------------------------------------------===// 1490 1491// Prefer to pattern match XOR with min_signed_value as ADD at isel time. 1492// ADD can be 3-addressified into an LEA instruction to avoid copies. 1493let AddedComplexity = 5 in { 1494def : Pat<(xor GR8:$src1, -128), 1495 (ADD8ri GR8:$src1, -128)>; 1496def : Pat<(xor GR16:$src1, -32768), 1497 (ADD16ri GR16:$src1, -32768)>; 1498def : Pat<(xor GR32:$src1, -2147483648), 1499 (ADD32ri GR32:$src1, -2147483648)>; 1500} 1501 1502//===----------------------------------------------------------------------===// 1503// Some peepholes 1504//===----------------------------------------------------------------------===// 1505 1506// Odd encoding trick: -128 fits into an 8-bit immediate field while 1507// +128 doesn't, so in this special case use a sub instead of an add. 1508let Predicates = [NoNDD] in { 1509 def : Pat<(add GR16:$src1, 128), 1510 (SUB16ri GR16:$src1, -128)>; 1511 def : Pat<(add GR32:$src1, 128), 1512 (SUB32ri GR32:$src1, -128)>; 1513 def : Pat<(add GR64:$src1, 128), 1514 (SUB64ri32 GR64:$src1, -128)>; 1515 1516 def : Pat<(X86add_flag_nocf GR16:$src1, 128), 1517 (SUB16ri GR16:$src1, -128)>; 1518 def : Pat<(X86add_flag_nocf GR32:$src1, 128), 1519 (SUB32ri GR32:$src1, -128)>; 1520 def : Pat<(X86add_flag_nocf GR64:$src1, 128), 1521 (SUB64ri32 GR64:$src1, -128)>; 1522} 1523let Predicates = [HasNDD] in { 1524 def : Pat<(add GR16:$src1, 128), 1525 (SUB16ri_ND GR16:$src1, -128)>; 1526 def : Pat<(add GR32:$src1, 128), 1527 (SUB32ri_ND GR32:$src1, -128)>; 1528 def : Pat<(add GR64:$src1, 128), 1529 (SUB64ri32_ND GR64:$src1, -128)>; 1530 1531 def : Pat<(X86add_flag_nocf GR16:$src1, 128), 1532 (SUB16ri_ND GR16:$src1, -128)>; 1533 def : Pat<(X86add_flag_nocf GR32:$src1, 128), 1534 (SUB32ri_ND GR32:$src1, -128)>; 1535 def : Pat<(X86add_flag_nocf GR64:$src1, 128), 1536 (SUB64ri32_ND GR64:$src1, -128)>; 1537} 1538def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1539 (SUB16mi addr:$dst, -128)>; 1540def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1541 (SUB32mi addr:$dst, -128)>; 1542def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1543 (SUB64mi32 addr:$dst, -128)>; 1544let Predicates = [HasNDD] in { 1545 def : Pat<(add (loadi16 addr:$src), 128), 1546 (SUB16mi_ND addr:$src, -128)>; 1547 def : Pat<(add (loadi32 addr:$src), 128), 1548 (SUB32mi_ND addr:$src, -128)>; 1549 def : Pat<(add (loadi64 addr:$src), 128), 1550 (SUB64mi32_ND addr:$src, -128)>; 1551} 1552 1553// The same trick applies for 32-bit immediate fields in 64-bit 1554// instructions. 1555let Predicates = [NoNDD] in { 1556 def : Pat<(add GR64:$src1, 0x0000000080000000), 1557 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1558 def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000), 1559 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1560} 1561let Predicates = [HasNDD] in { 1562 def : Pat<(add GR64:$src1, 0x0000000080000000), 1563 (SUB64ri32_ND GR64:$src1, 0xffffffff80000000)>; 1564 def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000), 1565 (SUB64ri32_ND GR64:$src1, 0xffffffff80000000)>; 1566} 1567def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst), 1568 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1569let Predicates = [HasNDD] in { 1570 def : Pat<(add(loadi64 addr:$src), 0x0000000080000000), 1571 (SUB64mi32_ND addr:$src, 0xffffffff80000000)>; 1572} 1573 1574// Depositing value to 8/16 bit subreg: 1575def : Pat<(or (and GR64:$dst, -256), 1576 (i64 (zextloadi8 addr:$src))), 1577 (INSERT_SUBREG (i64 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>; 1578 1579def : Pat<(or (and GR32:$dst, -256), 1580 (i32 (zextloadi8 addr:$src))), 1581 (INSERT_SUBREG (i32 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>; 1582 1583def : Pat<(or (and GR64:$dst, -65536), 1584 (i64 (zextloadi16 addr:$src))), 1585 (INSERT_SUBREG (i64 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit)>; 1586 1587def : Pat<(or (and GR32:$dst, -65536), 1588 (i32 (zextloadi16 addr:$src))), 1589 (INSERT_SUBREG (i32 (COPY $dst)), (MOV16rm i16mem:$src), sub_16bit)>; 1590 1591// To avoid needing to materialize an immediate in a register, use a 32-bit and 1592// with implicit zero-extension instead of a 64-bit and if the immediate has at 1593// least 32 bits of leading zeros. If in addition the last 32 bits can be 1594// represented with a sign extension of a 8 bit constant, use that. 1595// This can also reduce instruction size by eliminating the need for the REX 1596// prefix. 1597 1598// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. 1599let AddedComplexity = 1 in { 1600 let Predicates = [NoNDD] in { 1601 def : Pat<(and GR64:$src, i64immZExt32:$imm), 1602 (SUBREG_TO_REG 1603 (i64 0), 1604 (AND32ri 1605 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1606 (i32 (GetLo32XForm imm:$imm))), 1607 sub_32bit)>; 1608 } 1609 let Predicates = [HasNDD] in { 1610 def : Pat<(and GR64:$src, i64immZExt32:$imm), 1611 (SUBREG_TO_REG 1612 (i64 0), 1613 (AND32ri_ND 1614 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1615 (i32 (GetLo32XForm imm:$imm))), 1616 sub_32bit)>; 1617 } 1618} // AddedComplexity = 1 1619 1620 1621// AddedComplexity is needed due to the increased complexity on the 1622// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all 1623// the MOVZX patterns keeps thems together in DAGIsel tables. 1624let AddedComplexity = 1 in { 1625// r & (2^16-1) ==> movz 1626def : Pat<(and GR32:$src1, 0xffff), 1627 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1628// r & (2^8-1) ==> movz 1629def : Pat<(and GR32:$src1, 0xff), 1630 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>; 1631// r & (2^8-1) ==> movz 1632def : Pat<(and GR16:$src1, 0xff), 1633 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)), 1634 sub_16bit)>; 1635 1636// r & (2^32-1) ==> movz 1637def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1638 (SUBREG_TO_REG (i64 0), 1639 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1640 sub_32bit)>; 1641// r & (2^16-1) ==> movz 1642def : Pat<(and GR64:$src, 0xffff), 1643 (SUBREG_TO_REG (i64 0), 1644 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1645 sub_32bit)>; 1646// r & (2^8-1) ==> movz 1647def : Pat<(and GR64:$src, 0xff), 1648 (SUBREG_TO_REG (i64 0), 1649 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1650 sub_32bit)>; 1651} // AddedComplexity = 1 1652 1653 1654// Try to use BTS/BTR/BTC for single bit operations on the upper 32-bits. 1655 1656def BTRXForm : SDNodeXForm<imm, [{ 1657 // Transformation function: Find the lowest 0. 1658 return getI64Imm((uint8_t)N->getAPIntValue().countr_one(), SDLoc(N)); 1659}]>; 1660 1661def BTCBTSXForm : SDNodeXForm<imm, [{ 1662 // Transformation function: Find the lowest 1. 1663 return getI64Imm((uint8_t)N->getAPIntValue().countr_zero(), SDLoc(N)); 1664}]>; 1665 1666def BTRMask64 : ImmLeaf<i64, [{ 1667 return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm); 1668}]>; 1669 1670def BTCBTSMask64 : ImmLeaf<i64, [{ 1671 return !isInt<32>(Imm) && isPowerOf2_64(Imm); 1672}]>; 1673 1674// For now only do this for optsize. 1675let AddedComplexity = 1, Predicates=[OptForSize] in { 1676 def : Pat<(and GR64:$src1, BTRMask64:$mask), 1677 (BTR64ri8 GR64:$src1, (BTRXForm imm:$mask))>; 1678 def : Pat<(or GR64:$src1, BTCBTSMask64:$mask), 1679 (BTS64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1680 def : Pat<(xor GR64:$src1, BTCBTSMask64:$mask), 1681 (BTC64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1682} 1683 1684 1685// sext_inreg patterns 1686def : Pat<(sext_inreg GR32:$src, i16), 1687 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1688def : Pat<(sext_inreg GR32:$src, i8), 1689 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>; 1690 1691def : Pat<(sext_inreg GR16:$src, i8), 1692 (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)), 1693 sub_16bit)>; 1694 1695def : Pat<(sext_inreg GR64:$src, i32), 1696 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1697def : Pat<(sext_inreg GR64:$src, i16), 1698 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1699def : Pat<(sext_inreg GR64:$src, i8), 1700 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1701 1702// sext, sext_load, zext, zext_load 1703def: Pat<(i16 (sext GR8:$src)), 1704 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1705def: Pat<(sextloadi16i8 addr:$src), 1706 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1707def: Pat<(i16 (zext GR8:$src)), 1708 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1709def: Pat<(zextloadi16i8 addr:$src), 1710 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1711 1712// trunc patterns 1713def : Pat<(i16 (trunc GR32:$src)), 1714 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1715def : Pat<(i8 (trunc GR32:$src)), 1716 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1717 sub_8bit)>, 1718 Requires<[Not64BitMode]>; 1719def : Pat<(i8 (trunc GR16:$src)), 1720 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1721 sub_8bit)>, 1722 Requires<[Not64BitMode]>; 1723def : Pat<(i32 (trunc GR64:$src)), 1724 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1725def : Pat<(i16 (trunc GR64:$src)), 1726 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1727def : Pat<(i8 (trunc GR64:$src)), 1728 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1729def : Pat<(i8 (trunc GR32:$src)), 1730 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1731 Requires<[In64BitMode]>; 1732def : Pat<(i8 (trunc GR16:$src)), 1733 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1734 Requires<[In64BitMode]>; 1735 1736def immff00_ffff : ImmLeaf<i32, [{ 1737 return Imm >= 0xff00 && Imm <= 0xffff; 1738}]>; 1739 1740// h-register tricks 1741def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1742 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1743 Requires<[Not64BitMode]>; 1744def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))), 1745 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1746 Requires<[Not64BitMode]>; 1747def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1748 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>, 1749 Requires<[Not64BitMode]>; 1750def : Pat<(srl GR16:$src, (i8 8)), 1751 (EXTRACT_SUBREG 1752 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1753 sub_16bit)>; 1754def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1755 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1756def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1757 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1758def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1759 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1760def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)), 1761 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1762 1763// h-register tricks. 1764// For now, be conservative on x86-64 and use an h-register extract only if the 1765// value is immediately zero-extended or stored, which are somewhat common 1766// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1767// from being allocated in the same instruction as the h register, as there's 1768// currently no way to describe this requirement to the register allocator. 1769 1770// h-register extract and zero-extend. 1771def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1772 (SUBREG_TO_REG 1773 (i64 0), 1774 (MOVZX32rr8_NOREX 1775 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), 1776 sub_32bit)>; 1777def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1778 (SUBREG_TO_REG 1779 (i64 0), 1780 (MOVZX32rr8_NOREX 1781 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1782 sub_32bit)>; 1783def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1784 (SUBREG_TO_REG 1785 (i64 0), 1786 (MOVZX32rr8_NOREX 1787 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1788 sub_32bit)>; 1789 1790// h-register extract and store. 1791def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1792 (MOV8mr_NOREX 1793 addr:$dst, 1794 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>; 1795def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1796 (MOV8mr_NOREX 1797 addr:$dst, 1798 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, 1799 Requires<[In64BitMode]>; 1800def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1801 (MOV8mr_NOREX 1802 addr:$dst, 1803 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, 1804 Requires<[In64BitMode]>; 1805 1806// Special pattern to catch the last step of __builtin_parity handling. Our 1807// goal is to use an xor of an h-register with the corresponding l-register. 1808// The above patterns would handle this on non 64-bit targets, but for 64-bit 1809// we need to be more careful. We're using a NOREX instruction here in case 1810// register allocation fails to keep the two registers together. So we need to 1811// make sure we can't accidentally mix R8-R15 with an h-register. 1812def : Pat<(X86xor_flag (i8 (trunc GR32:$src)), 1813 (i8 (trunc (srl_su GR32:$src, (i8 8))))), 1814 (XOR8rr_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit), 1815 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1816 1817// (shl x, 1) ==> (add x, x) 1818// Note that if x is undef (immediate or otherwise), we could theoretically 1819// end up with the two uses of x getting different values, producing a result 1820// where the least significant bit is not 0. However, the probability of this 1821// happening is considered low enough that this is officially not a 1822// "real problem". 1823let Predicates = [NoNDD] in { 1824 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1825 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1826 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1827 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1828} 1829let Predicates = [HasNDD] in { 1830 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr_ND GR8 :$src1, GR8 :$src1)>; 1831 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr_ND GR16:$src1, GR16:$src1)>; 1832 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr_ND GR32:$src1, GR32:$src1)>; 1833 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr_ND GR64:$src1, GR64:$src1)>; 1834} 1835 1836// Shift amount is implicitly masked. 1837multiclass MaskedShiftAmountPats<SDNode frag> { 1838 // (shift x (and y, 31)) ==> (shift x, y) 1839 // (shift x (and y, 63)) ==> (shift x, y) 1840 let Predicates = [NoNDD] in { 1841 def : Pat<(frag GR8:$src1, (shiftMask32 CL)), 1842 (!cast<Instruction>(NAME # "8rCL") GR8:$src1)>; 1843 def : Pat<(frag GR16:$src1, (shiftMask32 CL)), 1844 (!cast<Instruction>(NAME # "16rCL") GR16:$src1)>; 1845 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1846 (!cast<Instruction>(NAME # "32rCL") GR32:$src1)>; 1847 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1848 (!cast<Instruction>(NAME # "64rCL") GR64:$src1)>; 1849 } 1850 let Predicates = [HasNDD] in { 1851 def : Pat<(frag GR8:$src1, (shiftMask32 CL)), 1852 (!cast<Instruction>(NAME # "8rCL_ND") GR8:$src1)>; 1853 def : Pat<(frag GR16:$src1, (shiftMask32 CL)), 1854 (!cast<Instruction>(NAME # "16rCL_ND") GR16:$src1)>; 1855 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1856 (!cast<Instruction>(NAME # "32rCL_ND") GR32:$src1)>; 1857 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1858 (!cast<Instruction>(NAME # "64rCL_ND") GR64:$src1)>; 1859 } 1860 1861 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask32 CL)), addr:$dst), 1862 (!cast<Instruction>(NAME # "8mCL") addr:$dst)>; 1863 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask32 CL)), addr:$dst), 1864 (!cast<Instruction>(NAME # "16mCL") addr:$dst)>; 1865 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1866 (!cast<Instruction>(NAME # "32mCL") addr:$dst)>; 1867 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1868 (!cast<Instruction>(NAME # "64mCL") addr:$dst)>; 1869 1870 let Predicates = [HasNDD] in { 1871 def : Pat<(frag (loadi8 addr:$src), (shiftMask32 CL)), 1872 (!cast<Instruction>(NAME # "8mCL_ND") addr:$src)>; 1873 def : Pat<(frag (loadi16 addr:$src), (shiftMask32 CL)), 1874 (!cast<Instruction>(NAME # "16mCL_ND") addr:$src)>; 1875 def : Pat<(frag (loadi32 addr:$src), (shiftMask32 CL)), 1876 (!cast<Instruction>(NAME # "32mCL_ND") addr:$src)>; 1877 def : Pat<(frag (loadi64 addr:$src), (shiftMask64 CL)), 1878 (!cast<Instruction>(NAME # "64mCL_ND") addr:$src)>; 1879 } 1880} 1881 1882defm SHL : MaskedShiftAmountPats<shl>; 1883defm SHR : MaskedShiftAmountPats<srl>; 1884defm SAR : MaskedShiftAmountPats<sra>; 1885 1886// ROL/ROR instructions allow a stronger mask optimization than shift for 8- and 1887// 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount 1888// because over-rotating produces the same result. This is noted in the Intel 1889// docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation 1890// amount could affect EFLAGS results, but that does not matter because we are 1891// not tracking flags for these nodes. 1892multiclass MaskedRotateAmountPats<SDNode frag> { 1893 // (rot x (and y, BitWidth - 1)) ==> (rot x, y) 1894 let Predicates = [NoNDD] in { 1895 def : Pat<(frag GR8:$src1, (shiftMask8 CL)), 1896 (!cast<Instruction>(NAME # "8rCL") GR8:$src1)>; 1897 def : Pat<(frag GR16:$src1, (shiftMask16 CL)), 1898 (!cast<Instruction>(NAME # "16rCL") GR16:$src1)>; 1899 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1900 (!cast<Instruction>(NAME # "32rCL") GR32:$src1)>; 1901 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1902 (!cast<Instruction>(NAME # "64rCL") GR64:$src1)>; 1903 } 1904 let Predicates = [HasNDD] in { 1905 def : Pat<(frag GR8:$src1, (shiftMask8 CL)), 1906 (!cast<Instruction>(NAME # "8rCL_ND") GR8:$src1)>; 1907 def : Pat<(frag GR16:$src1, (shiftMask16 CL)), 1908 (!cast<Instruction>(NAME # "16rCL_ND") GR16:$src1)>; 1909 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1910 (!cast<Instruction>(NAME # "32rCL_ND") GR32:$src1)>; 1911 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1912 (!cast<Instruction>(NAME # "64rCL_ND") GR64:$src1)>; 1913 } 1914 1915 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask8 CL)), addr:$dst), 1916 (!cast<Instruction>(NAME # "8mCL") addr:$dst)>; 1917 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask16 CL)), addr:$dst), 1918 (!cast<Instruction>(NAME # "16mCL") addr:$dst)>; 1919 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1920 (!cast<Instruction>(NAME # "32mCL") addr:$dst)>; 1921 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1922 (!cast<Instruction>(NAME # "64mCL") addr:$dst)>; 1923 1924 let Predicates = [HasNDD] in { 1925 def : Pat<(frag (loadi8 addr:$src), (shiftMask8 CL)), 1926 (!cast<Instruction>(NAME # "8mCL_ND") addr:$src)>; 1927 def : Pat<(frag (loadi16 addr:$src), (shiftMask16 CL)), 1928 (!cast<Instruction>(NAME # "16mCL_ND") addr:$src)>; 1929 def : Pat<(frag (loadi32 addr:$src), (shiftMask32 CL)), 1930 (!cast<Instruction>(NAME # "32mCL_ND") addr:$src)>; 1931 def : Pat<(frag (loadi64 addr:$src), (shiftMask64 CL)), 1932 (!cast<Instruction>(NAME # "64mCL_ND") addr:$src)>; 1933 } 1934} 1935 1936defm ROL : MaskedRotateAmountPats<rotl>; 1937defm ROR : MaskedRotateAmountPats<rotr>; 1938 1939multiclass MaskedShlrdAmountPats<string suffix, Predicate p> { 1940 let Predicates = [p] in { 1941 // Double "funnel" shift amount is implicitly masked. 1942 // (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) (NOTE: modulo32) 1943 def : Pat<(X86fshl GR16:$src1, GR16:$src2, (shiftMask32 CL)), 1944 (!cast<Instruction>(SHLD16rrCL#suffix) GR16:$src1, GR16:$src2)>; 1945 def : Pat<(X86fshr GR16:$src2, GR16:$src1, (shiftMask32 CL)), 1946 (!cast<Instruction>(SHRD16rrCL#suffix) GR16:$src1, GR16:$src2)>; 1947 1948 // (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) 1949 def : Pat<(fshl GR32:$src1, GR32:$src2, (shiftMask32 CL)), 1950 (!cast<Instruction>(SHLD32rrCL#suffix) GR32:$src1, GR32:$src2)>; 1951 def : Pat<(fshr GR32:$src2, GR32:$src1, (shiftMask32 CL)), 1952 (!cast<Instruction>(SHRD32rrCL#suffix) GR32:$src1, GR32:$src2)>; 1953 1954 // (fshl/fshr x (and y, 63)) ==> (fshl/fshr x, y) 1955 def : Pat<(fshl GR64:$src1, GR64:$src2, (shiftMask64 CL)), 1956 (!cast<Instruction>(SHLD64rrCL#suffix) GR64:$src1, GR64:$src2)>; 1957 def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)), 1958 (!cast<Instruction>(SHRD64rrCL#suffix) GR64:$src1, GR64:$src2)>; 1959 } 1960} 1961 1962defm : MaskedShlrdAmountPats<"", NoNDD>; 1963defm : MaskedShlrdAmountPats<"_ND", HasNDD>; 1964 1965// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location. 1966multiclass OneBitPats<RegisterClass rc, ValueType vt, Instruction btr, 1967 Instruction bts, Instruction btc, PatFrag mask> { 1968 def : Pat<(and rc:$src1, (rotl -2, GR8:$src2)), 1969 (btr rc:$src1, 1970 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1971 def : Pat<(or rc:$src1, (shl 1, GR8:$src2)), 1972 (bts rc:$src1, 1973 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1974 def : Pat<(xor rc:$src1, (shl 1, GR8:$src2)), 1975 (btc rc:$src1, 1976 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1977 1978 // Similar to above, but removing unneeded masking of the shift amount. 1979 def : Pat<(and rc:$src1, (rotl -2, (mask GR8:$src2))), 1980 (btr rc:$src1, 1981 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1982 def : Pat<(or rc:$src1, (shl 1, (mask GR8:$src2))), 1983 (bts rc:$src1, 1984 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1985 def : Pat<(xor rc:$src1, (shl 1, (mask GR8:$src2))), 1986 (btc rc:$src1, 1987 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1988} 1989 1990defm : OneBitPats<GR16, i16, BTR16rr, BTS16rr, BTC16rr, shiftMask16>; 1991defm : OneBitPats<GR32, i32, BTR32rr, BTS32rr, BTC32rr, shiftMask32>; 1992defm : OneBitPats<GR64, i64, BTR64rr, BTS64rr, BTC64rr, shiftMask64>; 1993 1994//===----------------------------------------------------------------------===// 1995// EFLAGS-defining Patterns 1996//===----------------------------------------------------------------------===// 1997 1998multiclass EFLAGSDefiningPats<string suffix, Predicate p> { 1999 let Predicates = [p] in { 2000 // add reg, reg 2001 def : Pat<(add GR8 :$src1, GR8 :$src2), (!cast<Instruction>(ADD8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2002 def : Pat<(add GR16:$src1, GR16:$src2), (!cast<Instruction>(ADD16rr#suffix) GR16:$src1, GR16:$src2)>; 2003 def : Pat<(add GR32:$src1, GR32:$src2), (!cast<Instruction>(ADD32rr#suffix) GR32:$src1, GR32:$src2)>; 2004 def : Pat<(add GR64:$src1, GR64:$src2), (!cast<Instruction>(ADD64rr#suffix) GR64:$src1, GR64:$src2)>; 2005 2006 // add reg, mem 2007 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 2008 (!cast<Instruction>(ADD8rm#suffix) GR8:$src1, addr:$src2)>; 2009 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 2010 (!cast<Instruction>(ADD16rm#suffix) GR16:$src1, addr:$src2)>; 2011 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 2012 (!cast<Instruction>(ADD32rm#suffix) GR32:$src1, addr:$src2)>; 2013 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 2014 (!cast<Instruction>(ADD64rm#suffix) GR64:$src1, addr:$src2)>; 2015 2016 // add reg, imm 2017 def : Pat<(add GR8 :$src1, imm:$src2), (!cast<Instruction>(ADD8ri#suffix) GR8:$src1 , imm:$src2)>; 2018 def : Pat<(add GR16:$src1, imm:$src2), (!cast<Instruction>(ADD16ri#suffix) GR16:$src1, imm:$src2)>; 2019 def : Pat<(add GR32:$src1, imm:$src2), (!cast<Instruction>(ADD32ri#suffix) GR32:$src1, imm:$src2)>; 2020 def : Pat<(add GR64:$src1, i64immSExt32:$src2), (!cast<Instruction>(ADD64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2021 2022 // sub reg, reg 2023 def : Pat<(sub GR8 :$src1, GR8 :$src2), (!cast<Instruction>(SUB8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2024 def : Pat<(sub GR16:$src1, GR16:$src2), (!cast<Instruction>(SUB16rr#suffix) GR16:$src1, GR16:$src2)>; 2025 def : Pat<(sub GR32:$src1, GR32:$src2), (!cast<Instruction>(SUB32rr#suffix) GR32:$src1, GR32:$src2)>; 2026 def : Pat<(sub GR64:$src1, GR64:$src2), (!cast<Instruction>(SUB64rr#suffix) GR64:$src1, GR64:$src2)>; 2027 2028 // sub reg, mem 2029 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 2030 (!cast<Instruction>(SUB8rm#suffix) GR8:$src1, addr:$src2)>; 2031 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 2032 (!cast<Instruction>(SUB16rm#suffix) GR16:$src1, addr:$src2)>; 2033 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 2034 (!cast<Instruction>(SUB32rm#suffix) GR32:$src1, addr:$src2)>; 2035 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 2036 (!cast<Instruction>(SUB64rm#suffix) GR64:$src1, addr:$src2)>; 2037 2038 // sub reg, imm 2039 def : Pat<(sub GR8:$src1, imm:$src2), 2040 (!cast<Instruction>(SUB8ri#suffix) GR8:$src1, imm:$src2)>; 2041 def : Pat<(sub GR16:$src1, imm:$src2), 2042 (!cast<Instruction>(SUB16ri#suffix) GR16:$src1, imm:$src2)>; 2043 def : Pat<(sub GR32:$src1, imm:$src2), 2044 (!cast<Instruction>(SUB32ri#suffix) GR32:$src1, imm:$src2)>; 2045 def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 2046 (!cast<Instruction>(SUB64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2047 2048 // sub 0, reg 2049 def : Pat<(X86sub_flag 0, GR8 :$src), (!cast<Instruction>(NEG8r#suffix) GR8 :$src)>; 2050 def : Pat<(X86sub_flag 0, GR16:$src), (!cast<Instruction>(NEG16r#suffix) GR16:$src)>; 2051 def : Pat<(X86sub_flag 0, GR32:$src), (!cast<Instruction>(NEG32r#suffix) GR32:$src)>; 2052 def : Pat<(X86sub_flag 0, GR64:$src), (!cast<Instruction>(NEG64r#suffix) GR64:$src)>; 2053 2054 // mul reg, reg 2055 def : Pat<(mul GR16:$src1, GR16:$src2), 2056 (!cast<Instruction>(IMUL16rr#suffix) GR16:$src1, GR16:$src2)>; 2057 def : Pat<(mul GR32:$src1, GR32:$src2), 2058 (!cast<Instruction>(IMUL32rr#suffix) GR32:$src1, GR32:$src2)>; 2059 def : Pat<(mul GR64:$src1, GR64:$src2), 2060 (!cast<Instruction>(IMUL64rr#suffix) GR64:$src1, GR64:$src2)>; 2061 2062 // mul reg, mem 2063 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 2064 (!cast<Instruction>(IMUL16rm#suffix) GR16:$src1, addr:$src2)>; 2065 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 2066 (!cast<Instruction>(IMUL32rm#suffix) GR32:$src1, addr:$src2)>; 2067 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 2068 (!cast<Instruction>(IMUL64rm#suffix) GR64:$src1, addr:$src2)>; 2069 2070 // or reg/reg. 2071 def : Pat<(or GR8 :$src1, GR8 :$src2), (!cast<Instruction>(OR8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2072 def : Pat<(or GR16:$src1, GR16:$src2), (!cast<Instruction>(OR16rr#suffix) GR16:$src1, GR16:$src2)>; 2073 def : Pat<(or GR32:$src1, GR32:$src2), (!cast<Instruction>(OR32rr#suffix) GR32:$src1, GR32:$src2)>; 2074 def : Pat<(or GR64:$src1, GR64:$src2), (!cast<Instruction>(OR64rr#suffix) GR64:$src1, GR64:$src2)>; 2075 2076 // or reg/mem 2077 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 2078 (!cast<Instruction>(OR8rm#suffix) GR8:$src1, addr:$src2)>; 2079 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 2080 (!cast<Instruction>(OR16rm#suffix) GR16:$src1, addr:$src2)>; 2081 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 2082 (!cast<Instruction>(OR32rm#suffix) GR32:$src1, addr:$src2)>; 2083 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 2084 (!cast<Instruction>(OR64rm#suffix) GR64:$src1, addr:$src2)>; 2085 2086 // or reg/imm 2087 def : Pat<(or GR8:$src1 , imm:$src2), (!cast<Instruction>(OR8ri#suffix) GR8 :$src1, imm:$src2)>; 2088 def : Pat<(or GR16:$src1, imm:$src2), (!cast<Instruction>(OR16ri#suffix) GR16:$src1, imm:$src2)>; 2089 def : Pat<(or GR32:$src1, imm:$src2), (!cast<Instruction>(OR32ri#suffix) GR32:$src1, imm:$src2)>; 2090 def : Pat<(or GR64:$src1, i64immSExt32:$src2), 2091 (!cast<Instruction>(OR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2092 2093 // xor reg/reg 2094 def : Pat<(xor GR8 :$src1, GR8 :$src2), (!cast<Instruction>(XOR8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2095 def : Pat<(xor GR16:$src1, GR16:$src2), (!cast<Instruction>(XOR16rr#suffix) GR16:$src1, GR16:$src2)>; 2096 def : Pat<(xor GR32:$src1, GR32:$src2), (!cast<Instruction>(XOR32rr#suffix) GR32:$src1, GR32:$src2)>; 2097 def : Pat<(xor GR64:$src1, GR64:$src2), (!cast<Instruction>(XOR64rr#suffix) GR64:$src1, GR64:$src2)>; 2098 2099 // xor reg/mem 2100 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 2101 (!cast<Instruction>(XOR8rm#suffix) GR8:$src1, addr:$src2)>; 2102 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 2103 (!cast<Instruction>(XOR16rm#suffix) GR16:$src1, addr:$src2)>; 2104 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 2105 (!cast<Instruction>(XOR32rm#suffix) GR32:$src1, addr:$src2)>; 2106 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 2107 (!cast<Instruction>(XOR64rm#suffix) GR64:$src1, addr:$src2)>; 2108 2109 // xor reg/imm 2110 def : Pat<(xor GR8:$src1, imm:$src2), 2111 (!cast<Instruction>(XOR8ri#suffix) GR8:$src1, imm:$src2)>; 2112 def : Pat<(xor GR16:$src1, imm:$src2), 2113 (!cast<Instruction>(XOR16ri#suffix) GR16:$src1, imm:$src2)>; 2114 def : Pat<(xor GR32:$src1, imm:$src2), 2115 (!cast<Instruction>(XOR32ri#suffix) GR32:$src1, imm:$src2)>; 2116 def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 2117 (!cast<Instruction>(XOR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2118 2119 // and reg/reg 2120 def : Pat<(and GR8 :$src1, GR8 :$src2), (!cast<Instruction>(AND8rr#suffix) GR8 :$src1, GR8 :$src2)>; 2121 def : Pat<(and GR16:$src1, GR16:$src2), (!cast<Instruction>(AND16rr#suffix) GR16:$src1, GR16:$src2)>; 2122 def : Pat<(and GR32:$src1, GR32:$src2), (!cast<Instruction>(AND32rr#suffix) GR32:$src1, GR32:$src2)>; 2123 def : Pat<(and GR64:$src1, GR64:$src2), (!cast<Instruction>(AND64rr#suffix) GR64:$src1, GR64:$src2)>; 2124 2125 // and reg/mem 2126 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 2127 (!cast<Instruction>(AND8rm#suffix) GR8:$src1, addr:$src2)>; 2128 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 2129 (!cast<Instruction>(AND16rm#suffix) GR16:$src1, addr:$src2)>; 2130 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 2131 (!cast<Instruction>(AND32rm#suffix) GR32:$src1, addr:$src2)>; 2132 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 2133 (!cast<Instruction>(AND64rm#suffix) GR64:$src1, addr:$src2)>; 2134 2135 // and reg/imm 2136 def : Pat<(and GR8:$src1, imm:$src2), 2137 (!cast<Instruction>(AND8ri#suffix) GR8:$src1, imm:$src2)>; 2138 def : Pat<(and GR16:$src1, imm:$src2), 2139 (!cast<Instruction>(AND16ri#suffix) GR16:$src1, imm:$src2)>; 2140 def : Pat<(and GR32:$src1, imm:$src2), 2141 (!cast<Instruction>(AND32ri#suffix) GR32:$src1, imm:$src2)>; 2142 def : Pat<(and GR64:$src1, i64immSExt32:$src2), 2143 (!cast<Instruction>(AND64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>; 2144 } 2145 2146 // Increment/Decrement reg. 2147 // Do not make INC/DEC if it is slow 2148 let Predicates = [UseIncDec, p] in { 2149 def : Pat<(add GR8:$src, 1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>; 2150 def : Pat<(add GR16:$src, 1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>; 2151 def : Pat<(add GR32:$src, 1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>; 2152 def : Pat<(add GR64:$src, 1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>; 2153 def : Pat<(add GR8:$src, -1), (!cast<Instruction>(DEC8r#suffix) GR8:$src)>; 2154 def : Pat<(add GR16:$src, -1), (!cast<Instruction>(DEC16r#suffix) GR16:$src)>; 2155 def : Pat<(add GR32:$src, -1), (!cast<Instruction>(DEC32r#suffix) GR32:$src)>; 2156 def : Pat<(add GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>; 2157 2158 def : Pat<(X86add_flag_nocf GR8:$src, -1), (!cast<Instruction>(DEC8r#suffix) GR8:$src)>; 2159 def : Pat<(X86add_flag_nocf GR16:$src, -1), (!cast<Instruction>(DEC16r#suffix) GR16:$src)>; 2160 def : Pat<(X86add_flag_nocf GR32:$src, -1), (!cast<Instruction>(DEC32r#suffix) GR32:$src)>; 2161 def : Pat<(X86add_flag_nocf GR64:$src, -1), (!cast<Instruction>(DEC64r#suffix) GR64:$src)>; 2162 def : Pat<(X86sub_flag_nocf GR8:$src, -1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>; 2163 def : Pat<(X86sub_flag_nocf GR16:$src, -1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>; 2164 def : Pat<(X86sub_flag_nocf GR32:$src, -1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>; 2165 def : Pat<(X86sub_flag_nocf GR64:$src, -1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>; 2166 2167 def : Pat<(or_is_add GR8:$src, 1), (!cast<Instruction>(INC8r#suffix) GR8:$src)>; 2168 def : Pat<(or_is_add GR16:$src, 1), (!cast<Instruction>(INC16r#suffix) GR16:$src)>; 2169 def : Pat<(or_is_add GR32:$src, 1), (!cast<Instruction>(INC32r#suffix) GR32:$src)>; 2170 def : Pat<(or_is_add GR64:$src, 1), (!cast<Instruction>(INC64r#suffix) GR64:$src)>; 2171 } 2172} 2173 2174defm : EFLAGSDefiningPats<"", NoNDD>; 2175defm : EFLAGSDefiningPats<"_ND", HasNDD>; 2176 2177// mul reg, imm 2178def : Pat<(mul GR16:$src1, imm:$src2), 2179 (IMUL16rri GR16:$src1, imm:$src2)>; 2180def : Pat<(mul GR32:$src1, imm:$src2), 2181 (IMUL32rri GR32:$src1, imm:$src2)>; 2182def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 2183 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 2184 2185// reg = mul mem, imm 2186def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 2187 (IMUL16rmi addr:$src1, imm:$src2)>; 2188def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 2189 (IMUL32rmi addr:$src1, imm:$src2)>; 2190def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 2191 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 2192 2193// Bit scan instruction patterns to match explicit zero-undef behavior. 2194def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 2195def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 2196def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 2197def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 2198def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 2199def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 2200 2201// When HasMOVBE is enabled it is possible to get a non-legalized 2202// register-register 16 bit bswap. This maps it to a ROL instruction. 2203let Predicates = [HasMOVBE] in { 2204 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; 2205} 2206