1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the various pseudo instructions used by the compiler, 10// as well as Pat patterns used during instruction selection. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Pattern Matching Support 16 17def GetLo32XForm : SDNodeXForm<imm, [{ 18 // Transformation function: get the low 32 bits. 19 return getI32Imm((uint32_t)N->getZExtValue(), SDLoc(N)); 20}]>; 21 22 23//===----------------------------------------------------------------------===// 24// Random Pseudo Instructions. 25 26// PIC base construction. This expands to code that looks like this: 27// call $next_inst 28// popl %destreg" 29let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP], 30 SchedRW = [WriteJump] in 31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 32 "", []>; 33 34// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 35// a stack adjustment and the codegen must know that they may modify the stack 36// pointer before prolog-epilog rewriting occurs. 37// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 38// sub / add which can clobber EFLAGS. 39let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in { 40def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), 41 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 42 "#ADJCALLSTACKDOWN", []>, Requires<[NotLP64]>; 43def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 44 "#ADJCALLSTACKUP", 45 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 46 Requires<[NotLP64]>; 47} 48def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 49 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>; 50 51 52// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 53// a stack adjustment and the codegen must know that they may modify the stack 54// pointer before prolog-epilog rewriting occurs. 55// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 56// sub / add which can clobber EFLAGS. 57let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in { 58def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), 59 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3), 60 "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>; 61def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 62 "#ADJCALLSTACKUP", 63 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 64 Requires<[IsLP64]>; 65} 66def : Pat<(X86callseq_start timm:$amt1, timm:$amt2), 67 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>; 68 69let SchedRW = [WriteSystem] in { 70 71// x86-64 va_start lowering magic. 72let hasSideEffects = 1, mayStore = 1, Defs = [EFLAGS] in { 73def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 74 (outs), 75 (ins GR8:$al, i8mem:$regsavefi, variable_ops), 76 "#VASTART_SAVE_XMM_REGS $al, $regsavefi", 77 [(X86vastart_save_xmm_regs GR8:$al, addr:$regsavefi), 78 (implicit EFLAGS)]>; 79} 80 81let usesCustomInserter = 1, Defs = [EFLAGS] in { 82// The VAARG_64 and VAARG_X32 pseudo-instructions take the address of the 83// va_list, and place the address of the next argument into a register. 84let Defs = [EFLAGS] in { 85def VAARG_64 : I<0, Pseudo, 86 (outs GR64:$dst), 87 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 88 "#VAARG_64 $dst, $ap, $size, $mode, $align", 89 [(set GR64:$dst, 90 (X86vaarg64 addr:$ap, timm:$size, timm:$mode, timm:$align)), 91 (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>; 92def VAARG_X32 : I<0, Pseudo, 93 (outs GR32:$dst), 94 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 95 "#VAARG_X32 $dst, $ap, $size, $mode, $align", 96 [(set GR32:$dst, 97 (X86vaargx32 addr:$ap, timm:$size, timm:$mode, timm:$align)), 98 (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>; 99} 100 101// When using segmented stacks these are lowered into instructions which first 102// check if the current stacklet has enough free memory. If it does, memory is 103// allocated by bumping the stack pointer. Otherwise memory is allocated from 104// the heap. 105 106let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 107def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 108 "# variable sized alloca for segmented stacks", 109 [(set GR32:$dst, 110 (X86SegAlloca GR32:$size))]>, 111 Requires<[NotLP64]>; 112 113let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 114def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 115 "# variable sized alloca for segmented stacks", 116 [(set GR64:$dst, 117 (X86SegAlloca GR64:$size))]>, 118 Requires<[In64BitMode]>; 119 120// To protect against stack clash, dynamic allocation should perform a memory 121// probe at each page. 122 123let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 124def PROBED_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 125 "# variable sized alloca with probing", 126 [(set GR32:$dst, 127 (X86ProbedAlloca GR32:$size))]>, 128 Requires<[NotLP64]>; 129 130let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 131def PROBED_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 132 "# variable sized alloca with probing", 133 [(set GR64:$dst, 134 (X86ProbedAlloca GR64:$size))]>, 135 Requires<[In64BitMode]>; 136} 137 138let hasNoSchedulingInfo = 1 in 139def STACKALLOC_W_PROBING : I<0, Pseudo, (outs), (ins i64imm:$stacksize), 140 "# fixed size alloca with probing", 141 []>; 142 143// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 144// targets. These calls are needed to probe the stack when allocating more than 145// 4k bytes in one go. Touching the stack at 4K increments is necessary to 146// ensure that the guard pages used by the OS virtual memory manager are 147// allocated in correct sequence. 148// The main point of having separate instruction are extra unmodelled effects 149// (compared to ordinary calls) like stack pointer change. 150 151let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 152def DYN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size), 153 "# dynamic stack allocation", 154 [(X86DynAlloca GR32:$size)]>, 155 Requires<[NotLP64]>; 156 157let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 158def DYN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size), 159 "# dynamic stack allocation", 160 [(X86DynAlloca GR64:$size)]>, 161 Requires<[In64BitMode]>; 162} // SchedRW 163 164// These instructions XOR the frame pointer into a GPR. They are used in some 165// stack protection schemes. These are post-RA pseudos because we only know the 166// frame register after register allocation. 167let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in { 168 def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src), 169 "xorl\t$$FP, $src", []>, 170 Requires<[NotLP64]>, Sched<[WriteALU]>; 171 def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src), 172 "xorq\t$$FP $src", []>, 173 Requires<[In64BitMode]>, Sched<[WriteALU]>; 174} 175 176//===----------------------------------------------------------------------===// 177// EH Pseudo Instructions 178// 179let SchedRW = [WriteSystem] in { 180let isTerminator = 1, isReturn = 1, isBarrier = 1, 181 hasCtrlDep = 1, isCodeGenOnly = 1 in { 182def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 183 "ret\t#eh_return, addr: $addr", 184 [(X86ehret GR32:$addr)]>, Sched<[WriteJumpLd]>; 185 186} 187 188let isTerminator = 1, isReturn = 1, isBarrier = 1, 189 hasCtrlDep = 1, isCodeGenOnly = 1 in { 190def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 191 "ret\t#eh_return, addr: $addr", 192 [(X86ehret GR64:$addr)]>, Sched<[WriteJumpLd]>; 193 194} 195 196let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 197 isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1 in { 198 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>; 199 200 // CATCHRET needs a custom inserter for SEH. 201 let usesCustomInserter = 1 in 202 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), 203 "# CATCHRET", 204 [(catchret bb:$dst, bb:$from)]>; 205} 206 207let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 208 usesCustomInserter = 1 in { 209 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 210 "#EH_SJLJ_SETJMP32", 211 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 212 Requires<[Not64BitMode]>; 213 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 214 "#EH_SJLJ_SETJMP64", 215 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 216 Requires<[In64BitMode]>; 217 let isTerminator = 1 in { 218 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 219 "#EH_SJLJ_LONGJMP32", 220 [(X86eh_sjlj_longjmp addr:$buf)]>, 221 Requires<[Not64BitMode]>; 222 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 223 "#EH_SJLJ_LONGJMP64", 224 [(X86eh_sjlj_longjmp addr:$buf)]>, 225 Requires<[In64BitMode]>; 226 } 227} 228 229let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 230 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 231 "#EH_SjLj_Setup\t$dst", []>; 232} 233} // SchedRW 234 235//===----------------------------------------------------------------------===// 236// Pseudo instructions used by unwind info. 237// 238let isPseudo = 1, SchedRW = [WriteSystem] in { 239 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), 240 "#SEH_PushReg $reg", []>; 241 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 242 "#SEH_SaveReg $reg, $dst", []>; 243 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 244 "#SEH_SaveXMM $reg, $dst", []>; 245 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), 246 "#SEH_StackAlloc $size", []>; 247 def SEH_StackAlign : I<0, Pseudo, (outs), (ins i32imm:$align), 248 "#SEH_StackAlign $align", []>; 249 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), 250 "#SEH_SetFrame $reg, $offset", []>; 251 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), 252 "#SEH_PushFrame $mode", []>; 253 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), 254 "#SEH_EndPrologue", []>; 255 def SEH_Epilogue : I<0, Pseudo, (outs), (ins), 256 "#SEH_Epilogue", []>; 257} 258 259//===----------------------------------------------------------------------===// 260// Pseudo instructions used by address sanitizer. 261//===----------------------------------------------------------------------===// 262let 263 Defs = [R10, R11, EFLAGS] in { 264def ASAN_CHECK_MEMACCESS : PseudoI< 265 (outs), (ins GR64PLTSafe:$addr, i32imm:$accessinfo), 266 [(int_asan_check_memaccess GR64PLTSafe:$addr, (i32 timm:$accessinfo))]>, 267 Sched<[]>; 268} 269 270//===----------------------------------------------------------------------===// 271// Pseudo instructions used by segmented stacks. 272// 273 274// This is lowered into a RET instruction by MCInstLower. We need 275// this so that we don't have to have a MachineBasicBlock which ends 276// with a RET and also has successors. 277let isPseudo = 1, SchedRW = [WriteJumpLd] in { 278def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>; 279 280// This instruction is lowered to a RET followed by a MOV. The two 281// instructions are not generated on a higher level since then the 282// verifier sees a MachineBasicBlock ending with a non-terminator. 283def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>; 284} 285 286//===----------------------------------------------------------------------===// 287// Alias Instructions 288//===----------------------------------------------------------------------===// 289 290// Alias instruction mapping movr0 to xor. 291// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 292let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 293 isPseudo = 1, isMoveImm = 1, AddedComplexity = 10 in 294def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 295 [(set GR32:$dst, 0)]>, Sched<[WriteZero]>; 296 297// Other widths can also make use of the 32-bit xor, which may have a smaller 298// encoding and avoid partial register updates. 299let AddedComplexity = 10 in { 300def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 301def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 302def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>; 303} 304 305let Predicates = [OptForSize, Not64BitMode], 306 AddedComplexity = 10 in { 307 let SchedRW = [WriteALU] in { 308 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, 309 // which only require 3 bytes compared to MOV32ri which requires 5. 310 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { 311 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 312 [(set GR32:$dst, 1)]>; 313 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 314 [(set GR32:$dst, -1)]>; 315 } 316 } // SchedRW 317 318 // MOV16ri is 4 bytes, so the instructions above are smaller. 319 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; 320 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; 321} 322 323let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5, 324 SchedRW = [WriteALU] in { 325// AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1. 326def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "", 327 [(set GR32:$dst, i32immSExt8:$src)]>, 328 Requires<[OptForMinSize, NotWin64WithoutFP]>; 329def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", 330 [(set GR64:$dst, i64immSExt8:$src)]>, 331 Requires<[OptForMinSize, NotWin64WithoutFP]>; 332} 333 334// Materialize i64 constant where top 32-bits are zero. This could theoretically 335// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 336// that would make it more difficult to rematerialize. 337let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 338 isPseudo = 1, SchedRW = [WriteMove] in 339def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "", 340 [(set GR64:$dst, i64immZExt32:$src)]>; 341 342// This 64-bit pseudo-move can also be used for labels in the x86-64 small code 343// model. 344def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [X86Wrapper]>; 345def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>; 346 347// Use sbb to materialize carry bit. 348let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteADC], 349 hasSideEffects = 0 in { 350// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 351// However, Pat<> can't replicate the destination reg into the inputs of the 352// result. 353def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", []>; 354def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", []>; 355} // isCodeGenOnly 356 357//===----------------------------------------------------------------------===// 358// String Pseudo Instructions 359// 360let SchedRW = [WriteMicrocoded] in { 361let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 362def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), 363 "{rep;movsb (%esi), %es:(%edi)|rep movsb es:[edi], [esi]}", 364 [(X86rep_movs i8)]>, REP, AdSize32, 365 Requires<[NotLP64]>; 366def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), 367 "{rep;movsw (%esi), %es:(%edi)|rep movsw es:[edi], [esi]}", 368 [(X86rep_movs i16)]>, REP, AdSize32, OpSize16, 369 Requires<[NotLP64]>; 370def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), 371 "{rep;movsl (%esi), %es:(%edi)|rep movsd es:[edi], [esi]}", 372 [(X86rep_movs i32)]>, REP, AdSize32, OpSize32, 373 Requires<[NotLP64]>; 374def REP_MOVSQ_32 : RI<0xA5, RawFrm, (outs), (ins), 375 "{rep;movsq (%esi), %es:(%edi)|rep movsq es:[edi], [esi]}", 376 [(X86rep_movs i64)]>, REP, AdSize32, 377 Requires<[NotLP64, In64BitMode]>; 378} 379 380let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 381def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), 382 "{rep;movsb (%rsi), %es:(%rdi)|rep movsb es:[rdi], [rsi]}", 383 [(X86rep_movs i8)]>, REP, AdSize64, 384 Requires<[IsLP64]>; 385def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), 386 "{rep;movsw (%rsi), %es:(%rdi)|rep movsw es:[rdi], [rsi]}", 387 [(X86rep_movs i16)]>, REP, AdSize64, OpSize16, 388 Requires<[IsLP64]>; 389def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), 390 "{rep;movsl (%rsi), %es:(%rdi)|rep movsdi es:[rdi], [rsi]}", 391 [(X86rep_movs i32)]>, REP, AdSize64, OpSize32, 392 Requires<[IsLP64]>; 393def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), 394 "{rep;movsq (%rsi), %es:(%rdi)|rep movsq es:[rdi], [rsi]}", 395 [(X86rep_movs i64)]>, REP, AdSize64, 396 Requires<[IsLP64]>; 397} 398 399// FIXME: Should use "(X86rep_stos AL)" as the pattern. 400let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 401 let Uses = [AL,ECX,EDI] in 402 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), 403 "{rep;stosb %al, %es:(%edi)|rep stosb es:[edi], al}", 404 [(X86rep_stos i8)]>, REP, AdSize32, 405 Requires<[NotLP64]>; 406 let Uses = [AX,ECX,EDI] in 407 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), 408 "{rep;stosw %ax, %es:(%edi)|rep stosw es:[edi], ax}", 409 [(X86rep_stos i16)]>, REP, AdSize32, OpSize16, 410 Requires<[NotLP64]>; 411 let Uses = [EAX,ECX,EDI] in 412 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), 413 "{rep;stosl %eax, %es:(%edi)|rep stosd es:[edi], eax}", 414 [(X86rep_stos i32)]>, REP, AdSize32, OpSize32, 415 Requires<[NotLP64]>; 416 let Uses = [RAX,RCX,RDI] in 417 def REP_STOSQ_32 : RI<0xAB, RawFrm, (outs), (ins), 418 "{rep;stosq %rax, %es:(%edi)|rep stosq es:[edi], rax}", 419 [(X86rep_stos i64)]>, REP, AdSize32, 420 Requires<[NotLP64, In64BitMode]>; 421} 422 423let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 424 let Uses = [AL,RCX,RDI] in 425 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), 426 "{rep;stosb %al, %es:(%rdi)|rep stosb es:[rdi], al}", 427 [(X86rep_stos i8)]>, REP, AdSize64, 428 Requires<[IsLP64]>; 429 let Uses = [AX,RCX,RDI] in 430 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), 431 "{rep;stosw %ax, %es:(%rdi)|rep stosw es:[rdi], ax}", 432 [(X86rep_stos i16)]>, REP, AdSize64, OpSize16, 433 Requires<[IsLP64]>; 434 let Uses = [RAX,RCX,RDI] in 435 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), 436 "{rep;stosl %eax, %es:(%rdi)|rep stosd es:[rdi], eax}", 437 [(X86rep_stos i32)]>, REP, AdSize64, OpSize32, 438 Requires<[IsLP64]>; 439 440 let Uses = [RAX,RCX,RDI] in 441 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), 442 "{rep;stosq %rax, %es:(%rdi)|rep stosq es:[rdi], rax}", 443 [(X86rep_stos i64)]>, REP, AdSize64, 444 Requires<[IsLP64]>; 445} 446} // SchedRW 447 448//===----------------------------------------------------------------------===// 449// Thread Local Storage Instructions 450// 451let SchedRW = [WriteSystem] in { 452 453// ELF TLS Support 454// All calls clobber the non-callee saved registers. ESP is marked as 455// a use to prevent stack-pointer assignments that appear immediately 456// before calls from potentially appearing dead. 457let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 458 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 459 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 460 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 461 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 462 usesCustomInserter = 1, Uses = [ESP, SSP] in { 463def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 464 "# TLS_addr32", 465 [(X86tlsaddr tls32addr:$sym)]>, 466 Requires<[Not64BitMode]>; 467def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 468 "# TLS_base_addr32", 469 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 470 Requires<[Not64BitMode]>; 471} 472 473// All calls clobber the non-callee saved registers. RSP is marked as 474// a use to prevent stack-pointer assignments that appear immediately 475// before calls from potentially appearing dead. 476let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 477 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 478 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 479 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 480 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 481 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF], 482 usesCustomInserter = 1, Uses = [RSP, SSP] in { 483def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 484 "# TLS_addr64", 485 [(X86tlsaddr tls64addr:$sym)]>, 486 Requires<[In64BitMode, IsLP64]>; 487def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 488 "# TLS_base_addr64", 489 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 490 Requires<[In64BitMode, IsLP64]>; 491def TLS_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 492 "# TLS_addrX32", 493 [(X86tlsaddr tls32addr:$sym)]>, 494 Requires<[In64BitMode, NotLP64]>; 495def TLS_base_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 496 "# TLS_base_addrX32", 497 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 498 Requires<[In64BitMode, NotLP64]>; 499} 500 501// Darwin TLS Support 502// For i386, the address of the thunk is passed on the stack, on return the 503// address of the variable is in %eax. %ecx is trashed during the function 504// call. All other registers are preserved. 505let Defs = [EAX, ECX, EFLAGS, DF], 506 Uses = [ESP, SSP], 507 usesCustomInserter = 1 in 508def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 509 "# TLSCall_32", 510 [(X86TLSCall addr:$sym)]>, 511 Requires<[Not64BitMode]>; 512 513// For x86_64, the address of the thunk is passed in %rdi, but the 514// pseudo directly use the symbol, so do not add an implicit use of 515// %rdi. The lowering will do the right thing with RDI. 516// On return the address of the variable is in %rax. All other 517// registers are preserved. 518let Defs = [RAX, EFLAGS, DF], 519 Uses = [RSP, SSP], 520 usesCustomInserter = 1 in 521def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 522 "# TLSCall_64", 523 [(X86TLSCall addr:$sym)]>, 524 Requires<[In64BitMode]>; 525} // SchedRW 526 527//===----------------------------------------------------------------------===// 528// Conditional Move Pseudo Instructions 529 530// CMOV* - Used to implement the SELECT DAG operation. Expanded after 531// instruction selection into a branch sequence. 532multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> { 533 def CMOV#NAME : I<0, Pseudo, 534 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), 535 "#CMOV_"#NAME#" PSEUDO!", 536 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, timm:$cond, 537 EFLAGS)))]>; 538} 539 540let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in { 541 // X86 doesn't have 8-bit conditional moves. Use a customInserter to 542 // emit control flow. An alternative to this is to mark i8 SELECT as Promote, 543 // however that requires promoting the operands, and can induce additional 544 // i8 register pressure. 545 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>; 546 547 let Predicates = [NoCMov] in { 548 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>; 549 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>; 550 } // Predicates = [NoCMov] 551 552 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 553 // SSE1/SSE2. 554 let Predicates = [FPStackf32] in 555 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>; 556 557 let Predicates = [FPStackf64] in 558 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>; 559 560 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>; 561 562 let Predicates = [HasMMX] in 563 defm _VR64 : CMOVrr_PSEUDO<VR64, x86mmx>; 564 565 defm _FR16X : CMOVrr_PSEUDO<FR16X, f16>; 566 let Predicates = [HasSSE1,NoAVX512] in 567 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 568 let Predicates = [HasSSE2,NoAVX512] in 569 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>; 570 let Predicates = [HasAVX512] in { 571 defm _FR32X : CMOVrr_PSEUDO<FR32X, f32>; 572 defm _FR64X : CMOVrr_PSEUDO<FR64X, f64>; 573 } 574 let Predicates = [NoVLX] in { 575 defm _VR128 : CMOVrr_PSEUDO<VR128, v2i64>; 576 defm _VR256 : CMOVrr_PSEUDO<VR256, v4i64>; 577 } 578 let Predicates = [HasVLX] in { 579 defm _VR128X : CMOVrr_PSEUDO<VR128X, v2i64>; 580 defm _VR256X : CMOVrr_PSEUDO<VR256X, v4i64>; 581 } 582 defm _VR512 : CMOVrr_PSEUDO<VR512, v8i64>; 583 defm _VK1 : CMOVrr_PSEUDO<VK1, v1i1>; 584 defm _VK2 : CMOVrr_PSEUDO<VK2, v2i1>; 585 defm _VK4 : CMOVrr_PSEUDO<VK4, v4i1>; 586 defm _VK8 : CMOVrr_PSEUDO<VK8, v8i1>; 587 defm _VK16 : CMOVrr_PSEUDO<VK16, v16i1>; 588 defm _VK32 : CMOVrr_PSEUDO<VK32, v32i1>; 589 defm _VK64 : CMOVrr_PSEUDO<VK64, v64i1>; 590} // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] 591 592def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 593 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 594 595let Predicates = [NoVLX] in { 596 def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 597 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 598 def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 599 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 600 def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 601 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 602 def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 603 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 604 def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)), 605 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>; 606 607 def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 608 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 609 def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 610 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 611 def : Pat<(v8i32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 612 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 613 def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 614 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 615 def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)), 616 (CMOV_VR256 VR256:$t, VR256:$f, timm:$cond)>; 617} 618let Predicates = [HasVLX] in { 619 def : Pat<(v16i8 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 620 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 621 def : Pat<(v8i16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 622 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 623 def : Pat<(v8f16 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 624 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 625 def : Pat<(v4i32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 626 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 627 def : Pat<(v4f32 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 628 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 629 def : Pat<(v2f64 (X86cmov VR128X:$t, VR128X:$f, timm:$cond, EFLAGS)), 630 (CMOV_VR128X VR128X:$t, VR128X:$f, timm:$cond)>; 631 632 def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 633 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 634 def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 635 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 636 def : Pat<(v16f16 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 637 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 638 def : Pat<(v8i32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 639 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 640 def : Pat<(v8f32 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 641 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 642 def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)), 643 (CMOV_VR256X VR256X:$t, VR256X:$f, timm:$cond)>; 644} 645 646def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 647 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 648def : Pat<(v32i16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 649 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 650def : Pat<(v32f16 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 651 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 652def : Pat<(v16i32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 653 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 654def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 655 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 656def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)), 657 (CMOV_VR512 VR512:$t, VR512:$f, timm:$cond)>; 658 659//===----------------------------------------------------------------------===// 660// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 661//===----------------------------------------------------------------------===// 662 663// FIXME: Use normal instructions and add lock prefix dynamically. 664 665// Memory barriers 666 667let isCodeGenOnly = 1, Defs = [EFLAGS] in 668def OR32mi8Locked : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$zero), 669 "or{l}\t{$zero, $dst|$dst, $zero}", []>, 670 Requires<[Not64BitMode]>, OpSize32, LOCK, 671 Sched<[WriteALURMW]>; 672 673let hasSideEffects = 1 in 674def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 675 "#MEMBARRIER", 676 [(X86MemBarrier)]>, Sched<[WriteLoad]>; 677 678// RegOpc corresponds to the mr version of the instruction 679// ImmOpc corresponds to the mi version of the instruction 680// ImmOpc8 corresponds to the mi8 version of the instruction 681// ImmMod corresponds to the instruction format of the mi and mi8 versions 682multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 683 Format ImmMod, SDNode Op, string mnemonic> { 684let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 685 SchedRW = [WriteALURMW] in { 686 687def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 688 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 689 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 690 !strconcat(mnemonic, "{b}\t", 691 "{$src2, $dst|$dst, $src2}"), 692 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK; 693 694def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 695 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 696 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 697 !strconcat(mnemonic, "{w}\t", 698 "{$src2, $dst|$dst, $src2}"), 699 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>, 700 OpSize16, LOCK; 701 702def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 703 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 704 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 705 !strconcat(mnemonic, "{l}\t", 706 "{$src2, $dst|$dst, $src2}"), 707 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>, 708 OpSize32, LOCK; 709 710def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 711 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 712 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 713 !strconcat(mnemonic, "{q}\t", 714 "{$src2, $dst|$dst, $src2}"), 715 [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK; 716 717// NOTE: These are order specific, we want the mi8 forms to be listed 718// first so that they are slightly preferred to the mi forms. 719def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 720 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 721 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 722 !strconcat(mnemonic, "{w}\t", 723 "{$src2, $dst|$dst, $src2}"), 724 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>, 725 OpSize16, LOCK; 726 727def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 728 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 729 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 730 !strconcat(mnemonic, "{l}\t", 731 "{$src2, $dst|$dst, $src2}"), 732 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>, 733 OpSize32, LOCK; 734 735def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 736 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 737 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 738 !strconcat(mnemonic, "{q}\t", 739 "{$src2, $dst|$dst, $src2}"), 740 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>, 741 LOCK; 742 743def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 744 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 745 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 746 !strconcat(mnemonic, "{b}\t", 747 "{$src2, $dst|$dst, $src2}"), 748 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK; 749 750def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 751 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 752 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 753 !strconcat(mnemonic, "{w}\t", 754 "{$src2, $dst|$dst, $src2}"), 755 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>, 756 OpSize16, LOCK; 757 758def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 759 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 760 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 761 !strconcat(mnemonic, "{l}\t", 762 "{$src2, $dst|$dst, $src2}"), 763 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>, 764 OpSize32, LOCK; 765 766def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 767 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 768 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 769 !strconcat(mnemonic, "{q}\t", 770 "{$src2, $dst|$dst, $src2}"), 771 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>, 772 LOCK; 773} 774 775} 776 777defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">; 778defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">; 779defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">; 780defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">; 781defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">; 782 783def X86lock_add_nocf : PatFrag<(ops node:$lhs, node:$rhs), 784 (X86lock_add node:$lhs, node:$rhs), [{ 785 return hasNoCarryFlagUses(SDValue(N, 0)); 786}]>; 787 788def X86lock_sub_nocf : PatFrag<(ops node:$lhs, node:$rhs), 789 (X86lock_sub node:$lhs, node:$rhs), [{ 790 return hasNoCarryFlagUses(SDValue(N, 0)); 791}]>; 792 793let Predicates = [UseIncDec] in { 794 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 795 SchedRW = [WriteALURMW] in { 796 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), 797 "inc{b}\t$dst", 798 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i8 1)))]>, 799 LOCK; 800 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), 801 "inc{w}\t$dst", 802 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i16 1)))]>, 803 OpSize16, LOCK; 804 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), 805 "inc{l}\t$dst", 806 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i32 1)))]>, 807 OpSize32, LOCK; 808 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), 809 "inc{q}\t$dst", 810 [(set EFLAGS, (X86lock_add_nocf addr:$dst, (i64 1)))]>, 811 LOCK; 812 813 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), 814 "dec{b}\t$dst", 815 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i8 1)))]>, 816 LOCK; 817 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), 818 "dec{w}\t$dst", 819 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i16 1)))]>, 820 OpSize16, LOCK; 821 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), 822 "dec{l}\t$dst", 823 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i32 1)))]>, 824 OpSize32, LOCK; 825 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), 826 "dec{q}\t$dst", 827 [(set EFLAGS, (X86lock_sub_nocf addr:$dst, (i64 1)))]>, 828 LOCK; 829 } 830 831 // Additional patterns for -1 constant. 832 def : Pat<(X86lock_add addr:$dst, (i8 -1)), (LOCK_DEC8m addr:$dst)>; 833 def : Pat<(X86lock_add addr:$dst, (i16 -1)), (LOCK_DEC16m addr:$dst)>; 834 def : Pat<(X86lock_add addr:$dst, (i32 -1)), (LOCK_DEC32m addr:$dst)>; 835 def : Pat<(X86lock_add addr:$dst, (i64 -1)), (LOCK_DEC64m addr:$dst)>; 836 def : Pat<(X86lock_sub addr:$dst, (i8 -1)), (LOCK_INC8m addr:$dst)>; 837 def : Pat<(X86lock_sub addr:$dst, (i16 -1)), (LOCK_INC16m addr:$dst)>; 838 def : Pat<(X86lock_sub addr:$dst, (i32 -1)), (LOCK_INC32m addr:$dst)>; 839 def : Pat<(X86lock_sub addr:$dst, (i64 -1)), (LOCK_INC64m addr:$dst)>; 840} 841 842// Atomic compare and swap. 843multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 844 string mnemonic, SDPatternOperator frag> { 845let isCodeGenOnly = 1, SchedRW = [WriteCMPXCHGRMW] in { 846 let Defs = [AL, EFLAGS], Uses = [AL] in 847 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 848 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 849 [(frag addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; 850 let Defs = [AX, EFLAGS], Uses = [AX] in 851 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 852 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 853 [(frag addr:$ptr, GR16:$swap, 2)]>, TB, OpSize16, LOCK; 854 let Defs = [EAX, EFLAGS], Uses = [EAX] in 855 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 856 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 857 [(frag addr:$ptr, GR32:$swap, 4)]>, TB, OpSize32, LOCK; 858 let Defs = [RAX, EFLAGS], Uses = [RAX] in 859 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 860 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 861 [(frag addr:$ptr, GR64:$swap, 8)]>, TB, LOCK; 862} 863} 864 865let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 866 Predicates = [HasCmpxchg8b], SchedRW = [WriteCMPXCHGRMW], 867 isCodeGenOnly = 1, usesCustomInserter = 1 in { 868def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr), 869 "cmpxchg8b\t$ptr", 870 [(X86cas8 addr:$ptr)]>, TB, LOCK; 871} 872 873let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 874 Predicates = [HasCmpxchg16b,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 875 isCodeGenOnly = 1, mayLoad = 1, mayStore = 1, hasSideEffects = 0 in { 876def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr), 877 "cmpxchg16b\t$ptr", 878 []>, TB, LOCK; 879} 880 881// This pseudo must be used when the frame uses RBX as 882// the base pointer. Indeed, in such situation RBX is a reserved 883// register and the register allocator will ignore any use/def of 884// it. In other words, the register will not fix the clobbering of 885// RBX that will happen when setting the arguments for the instrucion. 886// 887// Unlike the actual related instruction, we mark that this one 888// defines RBX (instead of using RBX). 889// The rationale is that we will define RBX during the expansion of 890// the pseudo. The argument feeding RBX is rbx_input. 891// 892// The additional argument, $rbx_save, is a temporary register used to 893// save the value of RBX across the actual instruction. 894// 895// To make sure the register assigned to $rbx_save does not interfere with 896// the definition of the actual instruction, we use a definition $dst which 897// is tied to $rbx_save. That way, the live-range of $rbx_save spans across 898// the instruction and we are sure we will have a valid register to restore 899// the value of RBX. 900let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX], 901 Predicates = [HasCmpxchg16b,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 902 isCodeGenOnly = 1, isPseudo = 1, 903 mayLoad = 1, mayStore = 1, hasSideEffects = 0, 904 Constraints = "$rbx_save = $dst" in { 905def LCMPXCHG16B_SAVE_RBX : 906 I<0, Pseudo, (outs GR64:$dst), 907 (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save), "", []>; 908} 909 910// Pseudo instruction that doesn't read/write RBX. Will be turned into either 911// LCMPXCHG16B_SAVE_RBX or LCMPXCHG16B via a custom inserter. 912let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RCX, RDX], 913 Predicates = [HasCmpxchg16b,In64BitMode], SchedRW = [WriteCMPXCHGRMW], 914 isCodeGenOnly = 1, isPseudo = 1, 915 mayLoad = 1, mayStore = 1, hasSideEffects = 0, 916 usesCustomInserter = 1 in { 917def LCMPXCHG16B_NO_RBX : 918 I<0, Pseudo, (outs), (ins i128mem:$ptr, GR64:$rbx_input), "", 919 [(X86cas16 addr:$ptr, GR64:$rbx_input)]>; 920} 921 922// This pseudo must be used when the frame uses RBX/EBX as 923// the base pointer. 924// cf comment for LCMPXCHG16B_SAVE_RBX. 925let Defs = [EBX], Uses = [ECX, EAX], 926 Predicates = [HasMWAITX], SchedRW = [WriteSystem], 927 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst" in { 928def MWAITX_SAVE_RBX : 929 I<0, Pseudo, (outs GR64:$dst), 930 (ins GR32:$ebx_input, GR64:$rbx_save), 931 "mwaitx", 932 []>; 933} 934 935// Pseudo mwaitx instruction to use for custom insertion. 936let Predicates = [HasMWAITX], SchedRW = [WriteSystem], 937 isCodeGenOnly = 1, isPseudo = 1, 938 usesCustomInserter = 1 in { 939def MWAITX : 940 I<0, Pseudo, (outs), (ins GR32:$ecx, GR32:$eax, GR32:$ebx), 941 "mwaitx", 942 [(int_x86_mwaitx GR32:$ecx, GR32:$eax, GR32:$ebx)]>; 943} 944 945 946defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>; 947 948// Atomic exchange and add 949multiclass ATOMIC_RMW_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 950 string frag> { 951 let Constraints = "$val = $dst", Defs = [EFLAGS], mayLoad = 1, mayStore = 1, 952 isCodeGenOnly = 1, SchedRW = [WriteALURMW] in { 953 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 954 (ins GR8:$val, i8mem:$ptr), 955 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 956 [(set GR8:$dst, 957 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>; 958 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 959 (ins GR16:$val, i16mem:$ptr), 960 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 961 [(set 962 GR16:$dst, 963 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, 964 OpSize16; 965 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 966 (ins GR32:$val, i32mem:$ptr), 967 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 968 [(set 969 GR32:$dst, 970 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, 971 OpSize32; 972 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 973 (ins GR64:$val, i64mem:$ptr), 974 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 975 [(set 976 GR64:$dst, 977 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; 978 } 979} 980 981defm LXADD : ATOMIC_RMW_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK; 982 983/* The following multiclass tries to make sure that in code like 984 * x.store (immediate op x.load(acquire), release) 985 * and 986 * x.store (register op x.load(acquire), release) 987 * an operation directly on memory is generated instead of wasting a register. 988 * It is not automatic as atomic_store/load are only lowered to MOV instructions 989 * extremely late to prevent them from being accidentally reordered in the backend 990 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) 991 */ 992multiclass RELEASE_BINOP_MI<string Name, SDNode op> { 993 def : Pat<(atomic_store_8 addr:$dst, 994 (op (atomic_load_8 addr:$dst), (i8 imm:$src))), 995 (!cast<Instruction>(Name#"8mi") addr:$dst, imm:$src)>; 996 def : Pat<(atomic_store_16 addr:$dst, 997 (op (atomic_load_16 addr:$dst), (i16 imm:$src))), 998 (!cast<Instruction>(Name#"16mi") addr:$dst, imm:$src)>; 999 def : Pat<(atomic_store_32 addr:$dst, 1000 (op (atomic_load_32 addr:$dst), (i32 imm:$src))), 1001 (!cast<Instruction>(Name#"32mi") addr:$dst, imm:$src)>; 1002 def : Pat<(atomic_store_64 addr:$dst, 1003 (op (atomic_load_64 addr:$dst), (i64immSExt32:$src))), 1004 (!cast<Instruction>(Name#"64mi32") addr:$dst, (i64immSExt32:$src))>; 1005 1006 def : Pat<(atomic_store_8 addr:$dst, 1007 (op (atomic_load_8 addr:$dst), (i8 GR8:$src))), 1008 (!cast<Instruction>(Name#"8mr") addr:$dst, GR8:$src)>; 1009 def : Pat<(atomic_store_16 addr:$dst, 1010 (op (atomic_load_16 addr:$dst), (i16 GR16:$src))), 1011 (!cast<Instruction>(Name#"16mr") addr:$dst, GR16:$src)>; 1012 def : Pat<(atomic_store_32 addr:$dst, 1013 (op (atomic_load_32 addr:$dst), (i32 GR32:$src))), 1014 (!cast<Instruction>(Name#"32mr") addr:$dst, GR32:$src)>; 1015 def : Pat<(atomic_store_64 addr:$dst, 1016 (op (atomic_load_64 addr:$dst), (i64 GR64:$src))), 1017 (!cast<Instruction>(Name#"64mr") addr:$dst, GR64:$src)>; 1018} 1019defm : RELEASE_BINOP_MI<"ADD", add>; 1020defm : RELEASE_BINOP_MI<"AND", and>; 1021defm : RELEASE_BINOP_MI<"OR", or>; 1022defm : RELEASE_BINOP_MI<"XOR", xor>; 1023defm : RELEASE_BINOP_MI<"SUB", sub>; 1024 1025// Atomic load + floating point patterns. 1026// FIXME: This could also handle SIMD operations with *ps and *pd instructions. 1027multiclass ATOMIC_LOAD_FP_BINOP_MI<string Name, SDNode op> { 1028 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1029 (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>, 1030 Requires<[UseSSE1]>; 1031 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1032 (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>, 1033 Requires<[UseAVX]>; 1034 def : Pat<(op FR32X:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))), 1035 (!cast<Instruction>("V"#Name#"SSZrm") FR32X:$src1, addr:$src2)>, 1036 Requires<[HasAVX512]>; 1037 1038 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1039 (!cast<Instruction>(Name#"SDrm") FR64:$src1, addr:$src2)>, 1040 Requires<[UseSSE1]>; 1041 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1042 (!cast<Instruction>("V"#Name#"SDrm") FR64:$src1, addr:$src2)>, 1043 Requires<[UseAVX]>; 1044 def : Pat<(op FR64X:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))), 1045 (!cast<Instruction>("V"#Name#"SDZrm") FR64X:$src1, addr:$src2)>, 1046 Requires<[HasAVX512]>; 1047} 1048defm : ATOMIC_LOAD_FP_BINOP_MI<"ADD", fadd>; 1049// FIXME: Add fsub, fmul, fdiv, ... 1050 1051multiclass RELEASE_UNOP<string Name, dag dag8, dag dag16, dag dag32, 1052 dag dag64> { 1053 def : Pat<(atomic_store_8 addr:$dst, dag8), 1054 (!cast<Instruction>(Name#8m) addr:$dst)>; 1055 def : Pat<(atomic_store_16 addr:$dst, dag16), 1056 (!cast<Instruction>(Name#16m) addr:$dst)>; 1057 def : Pat<(atomic_store_32 addr:$dst, dag32), 1058 (!cast<Instruction>(Name#32m) addr:$dst)>; 1059 def : Pat<(atomic_store_64 addr:$dst, dag64), 1060 (!cast<Instruction>(Name#64m) addr:$dst)>; 1061} 1062 1063let Predicates = [UseIncDec] in { 1064 defm : RELEASE_UNOP<"INC", 1065 (add (atomic_load_8 addr:$dst), (i8 1)), 1066 (add (atomic_load_16 addr:$dst), (i16 1)), 1067 (add (atomic_load_32 addr:$dst), (i32 1)), 1068 (add (atomic_load_64 addr:$dst), (i64 1))>; 1069 defm : RELEASE_UNOP<"DEC", 1070 (add (atomic_load_8 addr:$dst), (i8 -1)), 1071 (add (atomic_load_16 addr:$dst), (i16 -1)), 1072 (add (atomic_load_32 addr:$dst), (i32 -1)), 1073 (add (atomic_load_64 addr:$dst), (i64 -1))>; 1074} 1075 1076defm : RELEASE_UNOP<"NEG", 1077 (ineg (i8 (atomic_load_8 addr:$dst))), 1078 (ineg (i16 (atomic_load_16 addr:$dst))), 1079 (ineg (i32 (atomic_load_32 addr:$dst))), 1080 (ineg (i64 (atomic_load_64 addr:$dst)))>; 1081defm : RELEASE_UNOP<"NOT", 1082 (not (i8 (atomic_load_8 addr:$dst))), 1083 (not (i16 (atomic_load_16 addr:$dst))), 1084 (not (i32 (atomic_load_32 addr:$dst))), 1085 (not (i64 (atomic_load_64 addr:$dst)))>; 1086 1087def : Pat<(atomic_store_8 addr:$dst, (i8 imm:$src)), 1088 (MOV8mi addr:$dst, imm:$src)>; 1089def : Pat<(atomic_store_16 addr:$dst, (i16 imm:$src)), 1090 (MOV16mi addr:$dst, imm:$src)>; 1091def : Pat<(atomic_store_32 addr:$dst, (i32 imm:$src)), 1092 (MOV32mi addr:$dst, imm:$src)>; 1093def : Pat<(atomic_store_64 addr:$dst, (i64immSExt32:$src)), 1094 (MOV64mi32 addr:$dst, i64immSExt32:$src)>; 1095 1096def : Pat<(atomic_store_8 addr:$dst, GR8:$src), 1097 (MOV8mr addr:$dst, GR8:$src)>; 1098def : Pat<(atomic_store_16 addr:$dst, GR16:$src), 1099 (MOV16mr addr:$dst, GR16:$src)>; 1100def : Pat<(atomic_store_32 addr:$dst, GR32:$src), 1101 (MOV32mr addr:$dst, GR32:$src)>; 1102def : Pat<(atomic_store_64 addr:$dst, GR64:$src), 1103 (MOV64mr addr:$dst, GR64:$src)>; 1104 1105def : Pat<(i8 (atomic_load_8 addr:$src)), (MOV8rm addr:$src)>; 1106def : Pat<(i16 (atomic_load_16 addr:$src)), (MOV16rm addr:$src)>; 1107def : Pat<(i32 (atomic_load_32 addr:$src)), (MOV32rm addr:$src)>; 1108def : Pat<(i64 (atomic_load_64 addr:$src)), (MOV64rm addr:$src)>; 1109 1110// Floating point loads/stores. 1111def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1112 (MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>; 1113def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1114 (VMOVSSmr addr:$dst, FR32:$src)>, Requires<[UseAVX]>; 1115def : Pat<(atomic_store_32 addr:$dst, (i32 (bitconvert (f32 FR32:$src)))), 1116 (VMOVSSZmr addr:$dst, FR32:$src)>, Requires<[HasAVX512]>; 1117 1118def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))), 1119 (MOVSDmr addr:$dst, FR64:$src)>, Requires<[UseSSE2]>; 1120def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))), 1121 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[UseAVX]>; 1122def : Pat<(atomic_store_64 addr:$dst, (i64 (bitconvert (f64 FR64:$src)))), 1123 (VMOVSDmr addr:$dst, FR64:$src)>, Requires<[HasAVX512]>; 1124 1125def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1126 (MOVSSrm_alt addr:$src)>, Requires<[UseSSE1]>; 1127def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1128 (VMOVSSrm_alt addr:$src)>, Requires<[UseAVX]>; 1129def : Pat<(f32 (bitconvert (i32 (atomic_load_32 addr:$src)))), 1130 (VMOVSSZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1131 1132def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1133 (MOVSDrm_alt addr:$src)>, Requires<[UseSSE2]>; 1134def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1135 (VMOVSDrm_alt addr:$src)>, Requires<[UseAVX]>; 1136def : Pat<(f64 (bitconvert (i64 (atomic_load_64 addr:$src)))), 1137 (VMOVSDZrm_alt addr:$src)>, Requires<[HasAVX512]>; 1138 1139//===----------------------------------------------------------------------===// 1140// DAG Pattern Matching Rules 1141//===----------------------------------------------------------------------===// 1142 1143// Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves 1144// binary size compared to a regular MOV, but it introduces an unnecessary 1145// load, so is not suitable for regular or optsize functions. 1146let Predicates = [OptForMinSize] in { 1147def : Pat<(simple_store (i16 0), addr:$dst), (AND16mi8 addr:$dst, 0)>; 1148def : Pat<(simple_store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>; 1149def : Pat<(simple_store (i64 0), addr:$dst), (AND64mi8 addr:$dst, 0)>; 1150def : Pat<(simple_store (i16 -1), addr:$dst), (OR16mi8 addr:$dst, -1)>; 1151def : Pat<(simple_store (i32 -1), addr:$dst), (OR32mi8 addr:$dst, -1)>; 1152def : Pat<(simple_store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>; 1153} 1154 1155// In kernel code model, we can get the address of a label 1156// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 1157// the MOV64ri32 should accept these. 1158def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 1159 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 1160def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 1161 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 1162def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 1163 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 1164def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 1165 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 1166def : Pat<(i64 (X86Wrapper mcsym:$dst)), 1167 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; 1168def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 1169 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 1170 1171// If we have small model and -static mode, it is safe to store global addresses 1172// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 1173// for MOV64mi32 should handle this sort of thing. 1174def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 1175 (MOV64mi32 addr:$dst, tconstpool:$src)>, 1176 Requires<[NearData, IsNotPIC]>; 1177def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 1178 (MOV64mi32 addr:$dst, tjumptable:$src)>, 1179 Requires<[NearData, IsNotPIC]>; 1180def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1181 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 1182 Requires<[NearData, IsNotPIC]>; 1183def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 1184 (MOV64mi32 addr:$dst, texternalsym:$src)>, 1185 Requires<[NearData, IsNotPIC]>; 1186def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), 1187 (MOV64mi32 addr:$dst, mcsym:$src)>, 1188 Requires<[NearData, IsNotPIC]>; 1189def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 1190 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 1191 Requires<[NearData, IsNotPIC]>; 1192 1193def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; 1194def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; 1195 1196// Calls 1197 1198// tls has some funny stuff here... 1199// This corresponds to movabs $foo@tpoff, %rax 1200def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 1201 (MOV64ri32 tglobaltlsaddr :$dst)>; 1202// This corresponds to add $foo@tpoff, %rax 1203def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 1204 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 1205 1206 1207// Direct PC relative function call for small code model. 32-bit displacement 1208// sign extended to 64-bit. 1209def : Pat<(X86call (i64 tglobaladdr:$dst)), 1210 (CALL64pcrel32 tglobaladdr:$dst)>; 1211def : Pat<(X86call (i64 texternalsym:$dst)), 1212 (CALL64pcrel32 texternalsym:$dst)>; 1213 1214def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 texternalsym:$dst)), 1215 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, texternalsym:$dst)>; 1216def : Pat<(X86call_rvmarker (i64 tglobaladdr:$rvfunc), (i64 tglobaladdr:$dst)), 1217 (CALL64pcrel32_RVMARKER tglobaladdr:$rvfunc, tglobaladdr:$dst)>; 1218 1219 1220// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1221// can never use callee-saved registers. That is the purpose of the GR64_TC 1222// register classes. 1223// 1224// The only volatile register that is never used by the calling convention is 1225// %r11. This happens when calling a vararg function with 6 arguments. 1226// 1227// Match an X86tcret that uses less than 7 volatile registers. 1228def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 1229 (X86tcret node:$ptr, node:$off), [{ 1230 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1231 unsigned NumRegs = 0; 1232 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1233 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 1234 return false; 1235 return true; 1236}]>; 1237 1238def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1239 (TCRETURNri ptr_rc_tailcall:$dst, timm:$off)>, 1240 Requires<[Not64BitMode, NotUseIndirectThunkCalls]>; 1241 1242// FIXME: This is disabled for 32-bit PIC mode because the global base 1243// register which is part of the address mode may be assigned a 1244// callee-saved register. 1245def : Pat<(X86tcret (load addr:$dst), timm:$off), 1246 (TCRETURNmi addr:$dst, timm:$off)>, 1247 Requires<[Not64BitMode, IsNotPIC, NotUseIndirectThunkCalls]>; 1248 1249def : Pat<(X86tcret (i32 tglobaladdr:$dst), timm:$off), 1250 (TCRETURNdi tglobaladdr:$dst, timm:$off)>, 1251 Requires<[NotLP64]>; 1252 1253def : Pat<(X86tcret (i32 texternalsym:$dst), timm:$off), 1254 (TCRETURNdi texternalsym:$dst, timm:$off)>, 1255 Requires<[NotLP64]>; 1256 1257def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1258 (TCRETURNri64 ptr_rc_tailcall:$dst, timm:$off)>, 1259 Requires<[In64BitMode, NotUseIndirectThunkCalls]>; 1260 1261// Don't fold loads into X86tcret requiring more than 6 regs. 1262// There wouldn't be enough scratch registers for base+index. 1263def : Pat<(X86tcret_6regs (load addr:$dst), timm:$off), 1264 (TCRETURNmi64 addr:$dst, timm:$off)>, 1265 Requires<[In64BitMode, NotUseIndirectThunkCalls]>; 1266 1267def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1268 (INDIRECT_THUNK_TCRETURN64 ptr_rc_tailcall:$dst, timm:$off)>, 1269 Requires<[In64BitMode, UseIndirectThunkCalls]>; 1270 1271def : Pat<(X86tcret ptr_rc_tailcall:$dst, timm:$off), 1272 (INDIRECT_THUNK_TCRETURN32 ptr_rc_tailcall:$dst, timm:$off)>, 1273 Requires<[Not64BitMode, UseIndirectThunkCalls]>; 1274 1275def : Pat<(X86tcret (i64 tglobaladdr:$dst), timm:$off), 1276 (TCRETURNdi64 tglobaladdr:$dst, timm:$off)>, 1277 Requires<[IsLP64]>; 1278 1279def : Pat<(X86tcret (i64 texternalsym:$dst), timm:$off), 1280 (TCRETURNdi64 texternalsym:$dst, timm:$off)>, 1281 Requires<[IsLP64]>; 1282 1283// Normal calls, with various flavors of addresses. 1284def : Pat<(X86call (i32 tglobaladdr:$dst)), 1285 (CALLpcrel32 tglobaladdr:$dst)>; 1286def : Pat<(X86call (i32 texternalsym:$dst)), 1287 (CALLpcrel32 texternalsym:$dst)>; 1288def : Pat<(X86call (i32 imm:$dst)), 1289 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1290 1291// Comparisons. 1292 1293// TEST R,R is smaller than CMP R,0 1294def : Pat<(X86cmp GR8:$src1, 0), 1295 (TEST8rr GR8:$src1, GR8:$src1)>; 1296def : Pat<(X86cmp GR16:$src1, 0), 1297 (TEST16rr GR16:$src1, GR16:$src1)>; 1298def : Pat<(X86cmp GR32:$src1, 0), 1299 (TEST32rr GR32:$src1, GR32:$src1)>; 1300def : Pat<(X86cmp GR64:$src1, 0), 1301 (TEST64rr GR64:$src1, GR64:$src1)>; 1302 1303// zextload bool -> zextload byte 1304// i1 stored in one byte in zero-extended form. 1305// Upper bits cleanup should be executed before Store. 1306def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1307def : Pat<(zextloadi16i1 addr:$src), 1308 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1309def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1310def : Pat<(zextloadi64i1 addr:$src), 1311 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1312 1313// extload bool -> extload byte 1314// When extloading from 16-bit and smaller memory locations into 64-bit 1315// registers, use zero-extending loads so that the entire 64-bit register is 1316// defined, avoiding partial-register updates. 1317 1318def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1319def : Pat<(extloadi16i1 addr:$src), 1320 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1321def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1322def : Pat<(extloadi16i8 addr:$src), 1323 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1324def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1325def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1326 1327// For other extloads, use subregs, since the high contents of the register are 1328// defined after an extload. 1329// NOTE: The extloadi64i32 pattern needs to be first as it will try to form 1330// 32-bit loads for 4 byte aligned i8/i16 loads. 1331def : Pat<(extloadi64i32 addr:$src), 1332 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1333def : Pat<(extloadi64i1 addr:$src), 1334 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1335def : Pat<(extloadi64i8 addr:$src), 1336 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1337def : Pat<(extloadi64i16 addr:$src), 1338 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1339 1340// anyext. Define these to do an explicit zero-extend to 1341// avoid partial-register updates. 1342def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1343 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1344def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1345 1346// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1347def : Pat<(i32 (anyext GR16:$src)), 1348 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1349 1350def : Pat<(i64 (anyext GR8 :$src)), 1351 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1352def : Pat<(i64 (anyext GR16:$src)), 1353 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1354def : Pat<(i64 (anyext GR32:$src)), 1355 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>; 1356 1357// If this is an anyext of the remainder of an 8-bit sdivrem, use a MOVSX 1358// instead of a MOVZX. The sdivrem lowering will emit emit a MOVSX to move 1359// %ah to the lower byte of a register. By using a MOVSX here we allow a 1360// post-isel peephole to merge the two MOVSX instructions into one. 1361def anyext_sdiv : PatFrag<(ops node:$lhs), (anyext node:$lhs),[{ 1362 return (N->getOperand(0).getOpcode() == ISD::SDIVREM && 1363 N->getOperand(0).getResNo() == 1); 1364}]>; 1365def : Pat<(i32 (anyext_sdiv GR8:$src)), (MOVSX32rr8 GR8:$src)>; 1366 1367// Any instruction that defines a 32-bit result leaves the high half of the 1368// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1369// be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying 1370// anything about the upper 32 bits, they're probably just qualifying a 1371// CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit 1372// operation will zero-extend up to 64 bits. 1373def def32 : PatLeaf<(i32 GR32:$src), [{ 1374 return N->getOpcode() != ISD::TRUNCATE && 1375 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1376 N->getOpcode() != ISD::CopyFromReg && 1377 N->getOpcode() != ISD::AssertSext && 1378 N->getOpcode() != ISD::AssertZext && 1379 N->getOpcode() != ISD::AssertAlign && 1380 N->getOpcode() != ISD::FREEZE; 1381}]>; 1382 1383// In the case of a 32-bit def that is known to implicitly zero-extend, 1384// we can use a SUBREG_TO_REG. 1385def : Pat<(i64 (zext def32:$src)), 1386 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1387def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)), 1388 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1389 1390//===----------------------------------------------------------------------===// 1391// Pattern match OR as ADD 1392//===----------------------------------------------------------------------===// 1393 1394// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1395// 3-addressified into an LEA instruction to avoid copies. However, we also 1396// want to finally emit these instructions as an or at the end of the code 1397// generator to make the generated code easier to read. To do this, we select 1398// into "disjoint bits" pseudo ops. 1399 1400// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1401def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1402 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1403 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1404 1405 KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0); 1406 KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0); 1407 return (~Known0.Zero & ~Known1.Zero) == 0; 1408}]>; 1409 1410 1411// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1412// Try this before the selecting to OR. 1413let SchedRW = [WriteALU] in { 1414 1415let isConvertibleToThreeAddress = 1, isPseudo = 1, 1416 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1417let isCommutable = 1 in { 1418def ADD8rr_DB : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), 1419 "", // orb/addb REG, REG 1420 [(set GR8:$dst, (or_is_add GR8:$src1, GR8:$src2))]>; 1421def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1422 "", // orw/addw REG, REG 1423 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1424def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1425 "", // orl/addl REG, REG 1426 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1427def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1428 "", // orq/addq REG, REG 1429 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1430} // isCommutable 1431 1432// NOTE: These are order specific, we want the ri8 forms to be listed 1433// first so that they are slightly preferred to the ri forms. 1434 1435def ADD8ri_DB : I<0, Pseudo, 1436 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), 1437 "", // orb/addb REG, imm8 1438 [(set GR8:$dst, (or_is_add GR8:$src1, imm:$src2))]>; 1439def ADD16ri8_DB : I<0, Pseudo, 1440 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1441 "", // orw/addw REG, imm8 1442 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1443def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1444 "", // orw/addw REG, imm 1445 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1446 1447def ADD32ri8_DB : I<0, Pseudo, 1448 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1449 "", // orl/addl REG, imm8 1450 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1451def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1452 "", // orl/addl REG, imm 1453 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1454 1455 1456def ADD64ri8_DB : I<0, Pseudo, 1457 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1458 "", // orq/addq REG, imm8 1459 [(set GR64:$dst, (or_is_add GR64:$src1, 1460 i64immSExt8:$src2))]>; 1461def ADD64ri32_DB : I<0, Pseudo, 1462 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1463 "", // orq/addq REG, imm 1464 [(set GR64:$dst, (or_is_add GR64:$src1, 1465 i64immSExt32:$src2))]>; 1466} 1467} // AddedComplexity, SchedRW 1468 1469//===----------------------------------------------------------------------===// 1470// Pattern match SUB as XOR 1471//===----------------------------------------------------------------------===// 1472 1473// An immediate in the LHS of a subtract can't be encoded in the instruction. 1474// If there is no possibility of a borrow we can use an XOR instead of a SUB 1475// to enable the immediate to be folded. 1476// TODO: Move this to a DAG combine? 1477 1478def sub_is_xor : PatFrag<(ops node:$lhs, node:$rhs), (sub node:$lhs, node:$rhs),[{ 1479 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 1480 KnownBits Known = CurDAG->computeKnownBits(N->getOperand(1)); 1481 1482 // If all possible ones in the RHS are set in the LHS then there can't be 1483 // a borrow and we can use xor. 1484 return (~Known.Zero).isSubsetOf(CN->getAPIntValue()); 1485 } 1486 1487 return false; 1488}]>; 1489 1490let AddedComplexity = 5 in { 1491def : Pat<(sub_is_xor imm:$src2, GR8:$src1), 1492 (XOR8ri GR8:$src1, imm:$src2)>; 1493def : Pat<(sub_is_xor i16immSExt8:$src2, GR16:$src1), 1494 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1495def : Pat<(sub_is_xor imm:$src2, GR16:$src1), 1496 (XOR16ri GR16:$src1, imm:$src2)>; 1497def : Pat<(sub_is_xor i32immSExt8:$src2, GR32:$src1), 1498 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1499def : Pat<(sub_is_xor imm:$src2, GR32:$src1), 1500 (XOR32ri GR32:$src1, imm:$src2)>; 1501def : Pat<(sub_is_xor i64immSExt8:$src2, GR64:$src1), 1502 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1503def : Pat<(sub_is_xor i64immSExt32:$src2, GR64:$src1), 1504 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1505} 1506 1507//===----------------------------------------------------------------------===// 1508// Some peepholes 1509//===----------------------------------------------------------------------===// 1510 1511// Odd encoding trick: -128 fits into an 8-bit immediate field while 1512// +128 doesn't, so in this special case use a sub instead of an add. 1513def : Pat<(add GR16:$src1, 128), 1514 (SUB16ri8 GR16:$src1, -128)>; 1515def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1516 (SUB16mi8 addr:$dst, -128)>; 1517 1518def : Pat<(add GR32:$src1, 128), 1519 (SUB32ri8 GR32:$src1, -128)>; 1520def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1521 (SUB32mi8 addr:$dst, -128)>; 1522 1523def : Pat<(add GR64:$src1, 128), 1524 (SUB64ri8 GR64:$src1, -128)>; 1525def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1526 (SUB64mi8 addr:$dst, -128)>; 1527 1528def : Pat<(X86add_flag_nocf GR16:$src1, 128), 1529 (SUB16ri8 GR16:$src1, -128)>; 1530def : Pat<(X86add_flag_nocf GR32:$src1, 128), 1531 (SUB32ri8 GR32:$src1, -128)>; 1532def : Pat<(X86add_flag_nocf GR64:$src1, 128), 1533 (SUB64ri8 GR64:$src1, -128)>; 1534 1535// The same trick applies for 32-bit immediate fields in 64-bit 1536// instructions. 1537def : Pat<(add GR64:$src1, 0x0000000080000000), 1538 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1539def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst), 1540 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1541 1542def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000), 1543 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1544 1545// To avoid needing to materialize an immediate in a register, use a 32-bit and 1546// with implicit zero-extension instead of a 64-bit and if the immediate has at 1547// least 32 bits of leading zeros. If in addition the last 32 bits can be 1548// represented with a sign extension of a 8 bit constant, use that. 1549// This can also reduce instruction size by eliminating the need for the REX 1550// prefix. 1551 1552// AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. 1553let AddedComplexity = 1 in { 1554def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1555 (SUBREG_TO_REG 1556 (i64 0), 1557 (AND32ri8 1558 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1559 (i32 (GetLo32XForm imm:$imm))), 1560 sub_32bit)>; 1561 1562def : Pat<(and GR64:$src, i64immZExt32:$imm), 1563 (SUBREG_TO_REG 1564 (i64 0), 1565 (AND32ri 1566 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1567 (i32 (GetLo32XForm imm:$imm))), 1568 sub_32bit)>; 1569} // AddedComplexity = 1 1570 1571 1572// AddedComplexity is needed due to the increased complexity on the 1573// i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all 1574// the MOVZX patterns keeps thems together in DAGIsel tables. 1575let AddedComplexity = 1 in { 1576// r & (2^16-1) ==> movz 1577def : Pat<(and GR32:$src1, 0xffff), 1578 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1579// r & (2^8-1) ==> movz 1580def : Pat<(and GR32:$src1, 0xff), 1581 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>; 1582// r & (2^8-1) ==> movz 1583def : Pat<(and GR16:$src1, 0xff), 1584 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)), 1585 sub_16bit)>; 1586 1587// r & (2^32-1) ==> movz 1588def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1589 (SUBREG_TO_REG (i64 0), 1590 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1591 sub_32bit)>; 1592// r & (2^16-1) ==> movz 1593def : Pat<(and GR64:$src, 0xffff), 1594 (SUBREG_TO_REG (i64 0), 1595 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1596 sub_32bit)>; 1597// r & (2^8-1) ==> movz 1598def : Pat<(and GR64:$src, 0xff), 1599 (SUBREG_TO_REG (i64 0), 1600 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1601 sub_32bit)>; 1602} // AddedComplexity = 1 1603 1604 1605// Try to use BTS/BTR/BTC for single bit operations on the upper 32-bits. 1606 1607def BTRXForm : SDNodeXForm<imm, [{ 1608 // Transformation function: Find the lowest 0. 1609 return getI64Imm((uint8_t)N->getAPIntValue().countTrailingOnes(), SDLoc(N)); 1610}]>; 1611 1612def BTCBTSXForm : SDNodeXForm<imm, [{ 1613 // Transformation function: Find the lowest 1. 1614 return getI64Imm((uint8_t)N->getAPIntValue().countTrailingZeros(), SDLoc(N)); 1615}]>; 1616 1617def BTRMask64 : ImmLeaf<i64, [{ 1618 return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm); 1619}]>; 1620 1621def BTCBTSMask64 : ImmLeaf<i64, [{ 1622 return !isInt<32>(Imm) && isPowerOf2_64(Imm); 1623}]>; 1624 1625// For now only do this for optsize. 1626let AddedComplexity = 1, Predicates=[OptForSize] in { 1627 def : Pat<(and GR64:$src1, BTRMask64:$mask), 1628 (BTR64ri8 GR64:$src1, (BTRXForm imm:$mask))>; 1629 def : Pat<(or GR64:$src1, BTCBTSMask64:$mask), 1630 (BTS64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1631 def : Pat<(xor GR64:$src1, BTCBTSMask64:$mask), 1632 (BTC64ri8 GR64:$src1, (BTCBTSXForm imm:$mask))>; 1633} 1634 1635 1636// sext_inreg patterns 1637def : Pat<(sext_inreg GR32:$src, i16), 1638 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1639def : Pat<(sext_inreg GR32:$src, i8), 1640 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>; 1641 1642def : Pat<(sext_inreg GR16:$src, i8), 1643 (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)), 1644 sub_16bit)>; 1645 1646def : Pat<(sext_inreg GR64:$src, i32), 1647 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1648def : Pat<(sext_inreg GR64:$src, i16), 1649 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1650def : Pat<(sext_inreg GR64:$src, i8), 1651 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1652 1653// sext, sext_load, zext, zext_load 1654def: Pat<(i16 (sext GR8:$src)), 1655 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1656def: Pat<(sextloadi16i8 addr:$src), 1657 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1658def: Pat<(i16 (zext GR8:$src)), 1659 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1660def: Pat<(zextloadi16i8 addr:$src), 1661 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1662 1663// trunc patterns 1664def : Pat<(i16 (trunc GR32:$src)), 1665 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1666def : Pat<(i8 (trunc GR32:$src)), 1667 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1668 sub_8bit)>, 1669 Requires<[Not64BitMode]>; 1670def : Pat<(i8 (trunc GR16:$src)), 1671 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1672 sub_8bit)>, 1673 Requires<[Not64BitMode]>; 1674def : Pat<(i32 (trunc GR64:$src)), 1675 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1676def : Pat<(i16 (trunc GR64:$src)), 1677 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1678def : Pat<(i8 (trunc GR64:$src)), 1679 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1680def : Pat<(i8 (trunc GR32:$src)), 1681 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1682 Requires<[In64BitMode]>; 1683def : Pat<(i8 (trunc GR16:$src)), 1684 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1685 Requires<[In64BitMode]>; 1686 1687def immff00_ffff : ImmLeaf<i32, [{ 1688 return Imm >= 0xff00 && Imm <= 0xffff; 1689}]>; 1690 1691// h-register tricks 1692def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1693 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1694 Requires<[Not64BitMode]>; 1695def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))), 1696 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>, 1697 Requires<[Not64BitMode]>; 1698def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1699 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>, 1700 Requires<[Not64BitMode]>; 1701def : Pat<(srl GR16:$src, (i8 8)), 1702 (EXTRACT_SUBREG 1703 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1704 sub_16bit)>; 1705def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1706 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1707def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1708 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>; 1709def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1710 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1711def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)), 1712 (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1713 1714// h-register tricks. 1715// For now, be conservative on x86-64 and use an h-register extract only if the 1716// value is immediately zero-extended or stored, which are somewhat common 1717// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1718// from being allocated in the same instruction as the h register, as there's 1719// currently no way to describe this requirement to the register allocator. 1720 1721// h-register extract and zero-extend. 1722def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1723 (SUBREG_TO_REG 1724 (i64 0), 1725 (MOVZX32rr8_NOREX 1726 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), 1727 sub_32bit)>; 1728def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1729 (SUBREG_TO_REG 1730 (i64 0), 1731 (MOVZX32rr8_NOREX 1732 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1733 sub_32bit)>; 1734def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1735 (SUBREG_TO_REG 1736 (i64 0), 1737 (MOVZX32rr8_NOREX 1738 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), 1739 sub_32bit)>; 1740 1741// h-register extract and store. 1742def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1743 (MOV8mr_NOREX 1744 addr:$dst, 1745 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>; 1746def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1747 (MOV8mr_NOREX 1748 addr:$dst, 1749 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>, 1750 Requires<[In64BitMode]>; 1751def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1752 (MOV8mr_NOREX 1753 addr:$dst, 1754 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>, 1755 Requires<[In64BitMode]>; 1756 1757// Special pattern to catch the last step of __builtin_parity handling. Our 1758// goal is to use an xor of an h-register with the corresponding l-register. 1759// The above patterns would handle this on non 64-bit targets, but for 64-bit 1760// we need to be more careful. We're using a NOREX instruction here in case 1761// register allocation fails to keep the two registers together. So we need to 1762// make sure we can't accidentally mix R8-R15 with an h-register. 1763def : Pat<(X86xor_flag (i8 (trunc GR32:$src)), 1764 (i8 (trunc (srl_su GR32:$src, (i8 8))))), 1765 (XOR8rr_NOREX (EXTRACT_SUBREG GR32:$src, sub_8bit), 1766 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>; 1767 1768// (shl x, 1) ==> (add x, x) 1769// Note that if x is undef (immediate or otherwise), we could theoretically 1770// end up with the two uses of x getting different values, producing a result 1771// where the least significant bit is not 0. However, the probability of this 1772// happening is considered low enough that this is officially not a 1773// "real problem". 1774def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1775def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1776def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1777def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1778 1779def shiftMask8 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1780 return isUnneededShiftMask(N, 3); 1781}]>; 1782 1783def shiftMask16 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1784 return isUnneededShiftMask(N, 4); 1785}]>; 1786 1787def shiftMask32 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1788 return isUnneededShiftMask(N, 5); 1789}]>; 1790 1791def shiftMask64 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 1792 return isUnneededShiftMask(N, 6); 1793}]>; 1794 1795 1796// Shift amount is implicitly masked. 1797multiclass MaskedShiftAmountPats<SDNode frag, string name> { 1798 // (shift x (and y, 31)) ==> (shift x, y) 1799 def : Pat<(frag GR8:$src1, (shiftMask32 CL)), 1800 (!cast<Instruction>(name # "8rCL") GR8:$src1)>; 1801 def : Pat<(frag GR16:$src1, (shiftMask32 CL)), 1802 (!cast<Instruction>(name # "16rCL") GR16:$src1)>; 1803 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1804 (!cast<Instruction>(name # "32rCL") GR32:$src1)>; 1805 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask32 CL)), addr:$dst), 1806 (!cast<Instruction>(name # "8mCL") addr:$dst)>; 1807 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask32 CL)), addr:$dst), 1808 (!cast<Instruction>(name # "16mCL") addr:$dst)>; 1809 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1810 (!cast<Instruction>(name # "32mCL") addr:$dst)>; 1811 1812 // (shift x (and y, 63)) ==> (shift x, y) 1813 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1814 (!cast<Instruction>(name # "64rCL") GR64:$src1)>; 1815 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1816 (!cast<Instruction>(name # "64mCL") addr:$dst)>; 1817} 1818 1819defm : MaskedShiftAmountPats<shl, "SHL">; 1820defm : MaskedShiftAmountPats<srl, "SHR">; 1821defm : MaskedShiftAmountPats<sra, "SAR">; 1822 1823// ROL/ROR instructions allow a stronger mask optimization than shift for 8- and 1824// 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount 1825// because over-rotating produces the same result. This is noted in the Intel 1826// docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation 1827// amount could affect EFLAGS results, but that does not matter because we are 1828// not tracking flags for these nodes. 1829multiclass MaskedRotateAmountPats<SDNode frag, string name> { 1830 // (rot x (and y, BitWidth - 1)) ==> (rot x, y) 1831 def : Pat<(frag GR8:$src1, (shiftMask8 CL)), 1832 (!cast<Instruction>(name # "8rCL") GR8:$src1)>; 1833 def : Pat<(frag GR16:$src1, (shiftMask16 CL)), 1834 (!cast<Instruction>(name # "16rCL") GR16:$src1)>; 1835 def : Pat<(frag GR32:$src1, (shiftMask32 CL)), 1836 (!cast<Instruction>(name # "32rCL") GR32:$src1)>; 1837 def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask8 CL)), addr:$dst), 1838 (!cast<Instruction>(name # "8mCL") addr:$dst)>; 1839 def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask16 CL)), addr:$dst), 1840 (!cast<Instruction>(name # "16mCL") addr:$dst)>; 1841 def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), 1842 (!cast<Instruction>(name # "32mCL") addr:$dst)>; 1843 1844 // (rot x (and y, 63)) ==> (rot x, y) 1845 def : Pat<(frag GR64:$src1, (shiftMask64 CL)), 1846 (!cast<Instruction>(name # "64rCL") GR64:$src1)>; 1847 def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), 1848 (!cast<Instruction>(name # "64mCL") addr:$dst)>; 1849} 1850 1851 1852defm : MaskedRotateAmountPats<rotl, "ROL">; 1853defm : MaskedRotateAmountPats<rotr, "ROR">; 1854 1855// Double "funnel" shift amount is implicitly masked. 1856// (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) (NOTE: modulo32) 1857def : Pat<(X86fshl GR16:$src1, GR16:$src2, (shiftMask32 CL)), 1858 (SHLD16rrCL GR16:$src1, GR16:$src2)>; 1859def : Pat<(X86fshr GR16:$src2, GR16:$src1, (shiftMask32 CL)), 1860 (SHRD16rrCL GR16:$src1, GR16:$src2)>; 1861 1862// (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) 1863def : Pat<(fshl GR32:$src1, GR32:$src2, (shiftMask32 CL)), 1864 (SHLD32rrCL GR32:$src1, GR32:$src2)>; 1865def : Pat<(fshr GR32:$src2, GR32:$src1, (shiftMask32 CL)), 1866 (SHRD32rrCL GR32:$src1, GR32:$src2)>; 1867 1868// (fshl/fshr x (and y, 63)) ==> (fshl/fshr x, y) 1869def : Pat<(fshl GR64:$src1, GR64:$src2, (shiftMask64 CL)), 1870 (SHLD64rrCL GR64:$src1, GR64:$src2)>; 1871def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)), 1872 (SHRD64rrCL GR64:$src1, GR64:$src2)>; 1873 1874let Predicates = [HasBMI2] in { 1875 let AddedComplexity = 1 in { 1876 def : Pat<(sra GR32:$src1, (shiftMask32 GR8:$src2)), 1877 (SARX32rr GR32:$src1, 1878 (INSERT_SUBREG 1879 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1880 def : Pat<(sra GR64:$src1, (shiftMask64 GR8:$src2)), 1881 (SARX64rr GR64:$src1, 1882 (INSERT_SUBREG 1883 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1884 1885 def : Pat<(srl GR32:$src1, (shiftMask32 GR8:$src2)), 1886 (SHRX32rr GR32:$src1, 1887 (INSERT_SUBREG 1888 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1889 def : Pat<(srl GR64:$src1, (shiftMask64 GR8:$src2)), 1890 (SHRX64rr GR64:$src1, 1891 (INSERT_SUBREG 1892 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1893 1894 def : Pat<(shl GR32:$src1, (shiftMask32 GR8:$src2)), 1895 (SHLX32rr GR32:$src1, 1896 (INSERT_SUBREG 1897 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1898 def : Pat<(shl GR64:$src1, (shiftMask64 GR8:$src2)), 1899 (SHLX64rr GR64:$src1, 1900 (INSERT_SUBREG 1901 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1902 } 1903 1904 def : Pat<(sra (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), 1905 (SARX32rm addr:$src1, 1906 (INSERT_SUBREG 1907 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1908 def : Pat<(sra (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), 1909 (SARX64rm addr:$src1, 1910 (INSERT_SUBREG 1911 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1912 1913 def : Pat<(srl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), 1914 (SHRX32rm addr:$src1, 1915 (INSERT_SUBREG 1916 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1917 def : Pat<(srl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), 1918 (SHRX64rm addr:$src1, 1919 (INSERT_SUBREG 1920 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1921 1922 def : Pat<(shl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), 1923 (SHLX32rm addr:$src1, 1924 (INSERT_SUBREG 1925 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1926 def : Pat<(shl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), 1927 (SHLX64rm addr:$src1, 1928 (INSERT_SUBREG 1929 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1930} 1931 1932// Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location. 1933multiclass one_bit_patterns<RegisterClass RC, ValueType VT, Instruction BTR, 1934 Instruction BTS, Instruction BTC, 1935 PatFrag ShiftMask> { 1936 def : Pat<(and RC:$src1, (rotl -2, GR8:$src2)), 1937 (BTR RC:$src1, 1938 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1939 def : Pat<(or RC:$src1, (shl 1, GR8:$src2)), 1940 (BTS RC:$src1, 1941 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1942 def : Pat<(xor RC:$src1, (shl 1, GR8:$src2)), 1943 (BTC RC:$src1, 1944 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1945 1946 // Similar to above, but removing unneeded masking of the shift amount. 1947 def : Pat<(and RC:$src1, (rotl -2, (ShiftMask GR8:$src2))), 1948 (BTR RC:$src1, 1949 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1950 def : Pat<(or RC:$src1, (shl 1, (ShiftMask GR8:$src2))), 1951 (BTS RC:$src1, 1952 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1953 def : Pat<(xor RC:$src1, (shl 1, (ShiftMask GR8:$src2))), 1954 (BTC RC:$src1, 1955 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; 1956} 1957 1958defm : one_bit_patterns<GR16, i16, BTR16rr, BTS16rr, BTC16rr, shiftMask16>; 1959defm : one_bit_patterns<GR32, i32, BTR32rr, BTS32rr, BTC32rr, shiftMask32>; 1960defm : one_bit_patterns<GR64, i64, BTR64rr, BTS64rr, BTC64rr, shiftMask64>; 1961 1962//===----------------------------------------------------------------------===// 1963// EFLAGS-defining Patterns 1964//===----------------------------------------------------------------------===// 1965 1966// add reg, reg 1967def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1968def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1969def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1970def : Pat<(add GR64:$src1, GR64:$src2), (ADD64rr GR64:$src1, GR64:$src2)>; 1971 1972// add reg, mem 1973def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1974 (ADD8rm GR8:$src1, addr:$src2)>; 1975def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1976 (ADD16rm GR16:$src1, addr:$src2)>; 1977def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1978 (ADD32rm GR32:$src1, addr:$src2)>; 1979def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1980 (ADD64rm GR64:$src1, addr:$src2)>; 1981 1982// add reg, imm 1983def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1984def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1985def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1986def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1987 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1988def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1989 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1990def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1991 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1992def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1993 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1994 1995// sub reg, reg 1996def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1997def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1998def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1999def : Pat<(sub GR64:$src1, GR64:$src2), (SUB64rr GR64:$src1, GR64:$src2)>; 2000 2001// sub reg, mem 2002def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 2003 (SUB8rm GR8:$src1, addr:$src2)>; 2004def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 2005 (SUB16rm GR16:$src1, addr:$src2)>; 2006def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 2007 (SUB32rm GR32:$src1, addr:$src2)>; 2008def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 2009 (SUB64rm GR64:$src1, addr:$src2)>; 2010 2011// sub reg, imm 2012def : Pat<(sub GR8:$src1, imm:$src2), 2013 (SUB8ri GR8:$src1, imm:$src2)>; 2014def : Pat<(sub GR16:$src1, imm:$src2), 2015 (SUB16ri GR16:$src1, imm:$src2)>; 2016def : Pat<(sub GR32:$src1, imm:$src2), 2017 (SUB32ri GR32:$src1, imm:$src2)>; 2018def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 2019 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 2020def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 2021 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 2022def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 2023 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 2024def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 2025 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 2026 2027// sub 0, reg 2028def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; 2029def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; 2030def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; 2031def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; 2032 2033// mul reg, reg 2034def : Pat<(mul GR16:$src1, GR16:$src2), 2035 (IMUL16rr GR16:$src1, GR16:$src2)>; 2036def : Pat<(mul GR32:$src1, GR32:$src2), 2037 (IMUL32rr GR32:$src1, GR32:$src2)>; 2038def : Pat<(mul GR64:$src1, GR64:$src2), 2039 (IMUL64rr GR64:$src1, GR64:$src2)>; 2040 2041// mul reg, mem 2042def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 2043 (IMUL16rm GR16:$src1, addr:$src2)>; 2044def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 2045 (IMUL32rm GR32:$src1, addr:$src2)>; 2046def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 2047 (IMUL64rm GR64:$src1, addr:$src2)>; 2048 2049// mul reg, imm 2050def : Pat<(mul GR16:$src1, imm:$src2), 2051 (IMUL16rri GR16:$src1, imm:$src2)>; 2052def : Pat<(mul GR32:$src1, imm:$src2), 2053 (IMUL32rri GR32:$src1, imm:$src2)>; 2054def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 2055 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 2056def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 2057 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 2058def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 2059 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 2060def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 2061 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 2062 2063// reg = mul mem, imm 2064def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 2065 (IMUL16rmi addr:$src1, imm:$src2)>; 2066def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 2067 (IMUL32rmi addr:$src1, imm:$src2)>; 2068def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 2069 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 2070def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 2071 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 2072def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 2073 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 2074def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 2075 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 2076 2077// Increment/Decrement reg. 2078// Do not make INC/DEC if it is slow 2079let Predicates = [UseIncDec] in { 2080 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>; 2081 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>; 2082 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>; 2083 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 2084 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>; 2085 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>; 2086 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>; 2087 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 2088 2089 def : Pat<(X86add_flag_nocf GR8:$src, -1), (DEC8r GR8:$src)>; 2090 def : Pat<(X86add_flag_nocf GR16:$src, -1), (DEC16r GR16:$src)>; 2091 def : Pat<(X86add_flag_nocf GR32:$src, -1), (DEC32r GR32:$src)>; 2092 def : Pat<(X86add_flag_nocf GR64:$src, -1), (DEC64r GR64:$src)>; 2093 def : Pat<(X86sub_flag_nocf GR8:$src, -1), (INC8r GR8:$src)>; 2094 def : Pat<(X86sub_flag_nocf GR16:$src, -1), (INC16r GR16:$src)>; 2095 def : Pat<(X86sub_flag_nocf GR32:$src, -1), (INC32r GR32:$src)>; 2096 def : Pat<(X86sub_flag_nocf GR64:$src, -1), (INC64r GR64:$src)>; 2097} 2098 2099// or reg/reg. 2100def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 2101def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 2102def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 2103def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 2104 2105// or reg/mem 2106def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 2107 (OR8rm GR8:$src1, addr:$src2)>; 2108def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 2109 (OR16rm GR16:$src1, addr:$src2)>; 2110def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 2111 (OR32rm GR32:$src1, addr:$src2)>; 2112def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 2113 (OR64rm GR64:$src1, addr:$src2)>; 2114 2115// or reg/imm 2116def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 2117def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 2118def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 2119def : Pat<(or GR16:$src1, i16immSExt8:$src2), 2120 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 2121def : Pat<(or GR32:$src1, i32immSExt8:$src2), 2122 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 2123def : Pat<(or GR64:$src1, i64immSExt8:$src2), 2124 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 2125def : Pat<(or GR64:$src1, i64immSExt32:$src2), 2126 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 2127 2128// xor reg/reg 2129def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 2130def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 2131def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 2132def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 2133 2134// xor reg/mem 2135def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 2136 (XOR8rm GR8:$src1, addr:$src2)>; 2137def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 2138 (XOR16rm GR16:$src1, addr:$src2)>; 2139def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 2140 (XOR32rm GR32:$src1, addr:$src2)>; 2141def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 2142 (XOR64rm GR64:$src1, addr:$src2)>; 2143 2144// xor reg/imm 2145def : Pat<(xor GR8:$src1, imm:$src2), 2146 (XOR8ri GR8:$src1, imm:$src2)>; 2147def : Pat<(xor GR16:$src1, imm:$src2), 2148 (XOR16ri GR16:$src1, imm:$src2)>; 2149def : Pat<(xor GR32:$src1, imm:$src2), 2150 (XOR32ri GR32:$src1, imm:$src2)>; 2151def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 2152 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 2153def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 2154 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 2155def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 2156 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 2157def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 2158 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 2159 2160// and reg/reg 2161def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 2162def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 2163def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 2164def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 2165 2166// and reg/mem 2167def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 2168 (AND8rm GR8:$src1, addr:$src2)>; 2169def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 2170 (AND16rm GR16:$src1, addr:$src2)>; 2171def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 2172 (AND32rm GR32:$src1, addr:$src2)>; 2173def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 2174 (AND64rm GR64:$src1, addr:$src2)>; 2175 2176// and reg/imm 2177def : Pat<(and GR8:$src1, imm:$src2), 2178 (AND8ri GR8:$src1, imm:$src2)>; 2179def : Pat<(and GR16:$src1, imm:$src2), 2180 (AND16ri GR16:$src1, imm:$src2)>; 2181def : Pat<(and GR32:$src1, imm:$src2), 2182 (AND32ri GR32:$src1, imm:$src2)>; 2183def : Pat<(and GR16:$src1, i16immSExt8:$src2), 2184 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 2185def : Pat<(and GR32:$src1, i32immSExt8:$src2), 2186 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 2187def : Pat<(and GR64:$src1, i64immSExt8:$src2), 2188 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 2189def : Pat<(and GR64:$src1, i64immSExt32:$src2), 2190 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 2191 2192// Bit scan instruction patterns to match explicit zero-undef behavior. 2193def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 2194def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 2195def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 2196def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 2197def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 2198def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 2199 2200// When HasMOVBE is enabled it is possible to get a non-legalized 2201// register-register 16 bit bswap. This maps it to a ROL instruction. 2202let Predicates = [HasMOVBE] in { 2203 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; 2204} 2205