1//===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 conditional move and set on condition 10// instructions. 11// 12//===----------------------------------------------------------------------===// 13 14 15// CMOV instructions. 16let isCodeGenOnly = 1, ForceDisassemble = 1 in { 17let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", 18 isCommutable = 1, SchedRW = [WriteCMOV] in { 19 def CMOV16rr 20 : I<0x40, MRMSrcRegCC, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, ccode:$cond), 21 "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}", 22 [(set GR16:$dst, 23 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>, 24 TB, OpSize16; 25 def CMOV32rr 26 : I<0x40, MRMSrcRegCC, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, ccode:$cond), 27 "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}", 28 [(set GR32:$dst, 29 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>, 30 TB, OpSize32; 31 def CMOV64rr 32 :RI<0x40, MRMSrcRegCC, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, ccode:$cond), 33 "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}", 34 [(set GR64:$dst, 35 (X86cmov GR64:$src1, GR64:$src2, imm:$cond, EFLAGS))]>, TB; 36} 37 38let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", 39 SchedRW = [WriteCMOV.Folded, WriteCMOV.ReadAfterFold] in { 40 def CMOV16rm 41 : I<0x40, MRMSrcMemCC, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2, ccode:$cond), 42 "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}", 43 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), 44 imm:$cond, EFLAGS))]>, TB, OpSize16; 45 def CMOV32rm 46 : I<0x40, MRMSrcMemCC, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2, ccode:$cond), 47 "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}", 48 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), 49 imm:$cond, EFLAGS))]>, TB, OpSize32; 50 def CMOV64rm 51 :RI<0x40, MRMSrcMemCC, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2, ccode:$cond), 52 "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}", 53 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), 54 imm:$cond, EFLAGS))]>, TB; 55} // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" 56} // isCodeGenOnly = 1, ForceDisassemble = 1 57 58// SetCC instructions. 59let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in { 60 def SETCCr : I<0x90, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond), 61 "set${cond}\t$dst", 62 [(set GR8:$dst, (X86setcc imm:$cond, EFLAGS))]>, 63 TB, Sched<[WriteSETCC]>; 64 def SETCCm : I<0x90, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond), 65 "set${cond}\t$dst", 66 [(store (X86setcc imm:$cond, EFLAGS), addr:$dst)]>, 67 TB, Sched<[WriteSETCCStore]>; 68} // Uses = [EFLAGS] 69 70multiclass CMOV_SETCC_Aliases<string Cond, int CC> { 71 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}", 72 (CMOV16rr GR16:$dst, GR16:$src, CC), 0>; 73 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}", 74 (CMOV16rm GR16:$dst, i16mem:$src, CC), 0>; 75 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}", 76 (CMOV32rr GR32:$dst, GR32:$src, CC), 0>; 77 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}", 78 (CMOV32rm GR32:$dst, i32mem:$src, CC), 0>; 79 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}", 80 (CMOV64rr GR64:$dst, GR64:$src, CC), 0>; 81 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}", 82 (CMOV64rm GR64:$dst, i64mem:$src, CC), 0>; 83 84 def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>; 85 def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>; 86} 87 88defm : CMOV_SETCC_Aliases<"o" , 0>; 89defm : CMOV_SETCC_Aliases<"no", 1>; 90defm : CMOV_SETCC_Aliases<"b" , 2>; 91defm : CMOV_SETCC_Aliases<"ae", 3>; 92defm : CMOV_SETCC_Aliases<"e" , 4>; 93defm : CMOV_SETCC_Aliases<"ne", 5>; 94defm : CMOV_SETCC_Aliases<"be", 6>; 95defm : CMOV_SETCC_Aliases<"a" , 7>; 96defm : CMOV_SETCC_Aliases<"s" , 8>; 97defm : CMOV_SETCC_Aliases<"ns", 9>; 98defm : CMOV_SETCC_Aliases<"p" , 10>; 99defm : CMOV_SETCC_Aliases<"np", 11>; 100defm : CMOV_SETCC_Aliases<"l" , 12>; 101defm : CMOV_SETCC_Aliases<"ge", 13>; 102defm : CMOV_SETCC_Aliases<"le", 14>; 103defm : CMOV_SETCC_Aliases<"g" , 15>; 104 105// SALC is an undocumented instruction. Information for this instruction can be found 106// here http://www.rcollins.org/secrets/opcodes/SALC.html 107// Set AL if carry. 108let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in { 109 def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>; 110} 111