1//==- X86InstrAsmAlias.td - Assembler Instruction Aliases --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the assembler mnemonic/instruction aliases in the X86 10// architecture. 11// 12//===----------------------------------------------------------------------===// 13 14// Reversed version with ".s" suffix for GAS compatibility. 15def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}", 16 (MOV8rr_REV GR8:$dst, GR8:$src), 0>; 17def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}", 18 (MOV16rr_REV GR16:$dst, GR16:$src), 0>; 19def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}", 20 (MOV32rr_REV GR32:$dst, GR32:$src), 0>; 21def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}", 22 (MOV64rr_REV GR64:$dst, GR64:$src), 0>; 23def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 24 (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">; 25def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 26 (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">; 27def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 28 (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">; 29def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 30 (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">; 31 32// MONITORX/MWAITX Instructions Alias 33def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>, 34 Requires<[ Not64BitMode ]>; 35def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>, 36 Requires<[ In64BitMode ]>; 37 38// MONITORX/MWAITX Instructions Alias 39def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORX32rrr)>, 40 Requires<[ Not64BitMode ]>; 41def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORX64rrr)>, 42 Requires<[ In64BitMode ]>; 43 44// CLZERO Instruction Alias 45def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>; 46def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>; 47 48// INVLPGB Instruction Alias 49def : InstAlias<"invlpgb\t{%eax, %edx|eax, edx}", (INVLPGB32)>, Requires<[Not64BitMode]>; 50def : InstAlias<"invlpgb\t{%rax, %edx|rax, edx}", (INVLPGB64)>, Requires<[In64BitMode]>; 51 52// CMPCCXADD Instructions Alias 53multiclass CMPCCXADD_Aliases<string Cond, int CC> { 54 let Predicates = [In64BitMode] in { 55 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 56 (CMPCCXADDmr32 GR32:$dst, i32mem:$dstsrc2, GR32:$src3, CC), 0>; 57 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 58 (CMPCCXADDmr64 GR64:$dst, i64mem:$dstsrc2, GR64:$src3, CC), 0>; 59 60 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 61 (CMPCCXADDmr32_EVEX GR32:$dst, i32mem:$dstsrc2, GR32:$src3, CC), 0>; 62 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 63 (CMPCCXADDmr64_EVEX GR64:$dst, i64mem:$dstsrc2, GR64:$src3, CC), 0>; 64 } 65} 66 67// CCMP Instructions Alias 68multiclass CCMP_Aliases<string Cond, int CC> { 69let Predicates = [In64BitMode] in { 70def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}", 71 (CCMP8rr GR8:$src1, GR8:$src2, cflags:$dcf, CC), 0>; 72def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}", 73 (CCMP16rr GR16:$src1, GR16:$src2, cflags:$dcf, CC), 0>; 74def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}", 75 (CCMP32rr GR32:$src1, GR32:$src2, cflags:$dcf, CC), 0>; 76def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}", 77 (CCMP64rr GR64:$src1, GR64:$src2, cflags:$dcf, CC), 0>; 78def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}", 79 (CCMP8rm GR8:$src1, i8mem:$src2, cflags:$dcf, CC), 0>; 80def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}", 81 (CCMP16rm GR16:$src1, i16mem:$src2, cflags:$dcf, CC), 0>; 82def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}", 83 (CCMP32rm GR32:$src1, i32mem:$src2, cflags:$dcf, CC), 0>; 84def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}", 85 (CCMP64rm GR64:$src1, i64mem:$src2, cflags:$dcf, CC), 0>; 86def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}", 87 (CCMP8mr i8mem:$src1, GR8:$src2, cflags:$dcf, CC), 0>; 88def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}", 89 (CCMP16mr i16mem:$src1, GR16:$src2, cflags:$dcf, CC), 0>; 90def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}", 91 (CCMP32mr i32mem:$src1, GR32:$src2, cflags:$dcf, CC), 0>; 92def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}", 93 (CCMP64mr i64mem:$src1, GR64:$src2, cflags:$dcf, CC), 0>; 94def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}", 95 (CCMP8ri GR8:$src1, i8imm:$src2, cflags:$dcf, CC), 0>; 96def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}", 97 (CCMP16ri GR16:$src1, i16imm:$src2, cflags:$dcf, CC), 0>; 98def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}", 99 (CCMP32ri GR32:$src1, i32imm:$src2, cflags:$dcf, CC), 0>; 100def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}", 101 (CCMP64ri32 GR64:$src1, i64i32imm:$src2, cflags:$dcf, CC), 0>; 102def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}", 103 (CCMP16ri8 GR16:$src1, i16i8imm:$src2, cflags:$dcf, CC), 0>; 104def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}", 105 (CCMP32ri8 GR32:$src1, i32i8imm:$src2, cflags:$dcf, CC), 0>; 106def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}", 107 (CCMP64ri8 GR64:$src1, i64i8imm:$src2, cflags:$dcf, CC), 0>; 108def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}", 109 (CCMP8mi i8mem:$src1, i8imm:$src2, cflags:$dcf, CC), 0>; 110def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}", 111 (CCMP16mi i16mem:$src1, i16imm:$src2, cflags:$dcf, CC), 0>; 112def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}", 113 (CCMP32mi i32mem:$src1, i32imm:$src2, cflags:$dcf, CC), 0>; 114def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}", 115 (CCMP64mi32 i64mem:$src1, i64i32imm:$src2, cflags:$dcf, CC), 0>; 116def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}", 117 (CCMP16mi8 i16mem:$src1, i16i8imm:$src2, cflags:$dcf, CC), 0>; 118def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}", 119 (CCMP32mi8 i32mem:$src1, i32i8imm:$src2, cflags:$dcf, CC), 0>; 120def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}", 121 (CCMP64mi8 i64mem:$src1, i64i8imm:$src2, cflags:$dcf, CC), 0>; 122} 123} 124defm : CCMP_Aliases<"o" , 0>; 125defm : CCMP_Aliases<"no", 1>; 126defm : CCMP_Aliases<"b" , 2>; 127defm : CCMP_Aliases<"ae", 3>; 128defm : CCMP_Aliases<"e" , 4>; 129defm : CCMP_Aliases<"ne", 5>; 130defm : CCMP_Aliases<"be", 6>; 131defm : CCMP_Aliases<"a" , 7>; 132defm : CCMP_Aliases<"s" , 8>; 133defm : CCMP_Aliases<"ns", 9>; 134defm : CCMP_Aliases<"t" , 10>; 135defm : CCMP_Aliases<"f", 11>; 136defm : CCMP_Aliases<"l" , 12>; 137defm : CCMP_Aliases<"ge", 13>; 138defm : CCMP_Aliases<"le", 14>; 139defm : CCMP_Aliases<"g" , 15>; 140 141// CTEST Instructions Alias 142multiclass CTEST_Aliases<string Cond, int CC> { 143let Predicates = [In64BitMode] in { 144def : InstAlias<"ctest"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}", 145 (CTEST8rr GR8:$src1, GR8:$src2, cflags:$dcf, CC), 0>; 146def : InstAlias<"ctest"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}", 147 (CTEST16rr GR16:$src1, GR16:$src2, cflags:$dcf, CC), 0>; 148def : InstAlias<"ctest"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}", 149 (CTEST32rr GR32:$src1, GR32:$src2, cflags:$dcf, CC), 0>; 150def : InstAlias<"ctest"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}", 151 (CTEST64rr GR64:$src1, GR64:$src2, cflags:$dcf, CC), 0>; 152def : InstAlias<"ctest"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}", 153 (CTEST8mr i8mem:$src1, GR8:$src2, cflags:$dcf, CC), 0>; 154def : InstAlias<"ctest"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}", 155 (CTEST16mr i16mem:$src1, GR16:$src2, cflags:$dcf, CC), 0>; 156def : InstAlias<"ctest"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}", 157 (CTEST32mr i32mem:$src1, GR32:$src2, cflags:$dcf, CC), 0>; 158def : InstAlias<"ctest"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}", 159 (CTEST64mr i64mem:$src1, GR64:$src2, cflags:$dcf, CC), 0>; 160def : InstAlias<"ctest"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}", 161 (CTEST8ri GR8:$src1, i8imm:$src2, cflags:$dcf, CC), 0>; 162def : InstAlias<"ctest"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}", 163 (CTEST16ri GR16:$src1, i16imm:$src2, cflags:$dcf, CC), 0>; 164def : InstAlias<"ctest"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}", 165 (CTEST32ri GR32:$src1, i32imm:$src2, cflags:$dcf, CC), 0>; 166def : InstAlias<"ctest"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}", 167 (CTEST64ri32 GR64:$src1, i64i32imm:$src2, cflags:$dcf, CC), 0>; 168def : InstAlias<"ctest"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}", 169 (CTEST8mi i8mem:$src1, i8imm:$src2, cflags:$dcf, CC), 0>; 170def : InstAlias<"ctest"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}", 171 (CTEST16mi i16mem:$src1, i16imm:$src2, cflags:$dcf, CC), 0>; 172def : InstAlias<"ctest"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}", 173 (CTEST32mi i32mem:$src1, i32imm:$src2, cflags:$dcf, CC), 0>; 174def : InstAlias<"ctest"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}", 175 (CTEST64mi32 i64mem:$src1, i64i32imm:$src2, cflags:$dcf, CC), 0>; 176} 177} 178defm : CTEST_Aliases<"o" , 0>; 179defm : CTEST_Aliases<"no", 1>; 180defm : CTEST_Aliases<"b" , 2>; 181defm : CTEST_Aliases<"ae", 3>; 182defm : CTEST_Aliases<"e" , 4>; 183defm : CTEST_Aliases<"ne", 5>; 184defm : CTEST_Aliases<"be", 6>; 185defm : CTEST_Aliases<"a" , 7>; 186defm : CTEST_Aliases<"s" , 8>; 187defm : CTEST_Aliases<"ns", 9>; 188defm : CTEST_Aliases<"t" , 10>; 189defm : CTEST_Aliases<"f", 11>; 190defm : CTEST_Aliases<"l" , 12>; 191defm : CTEST_Aliases<"ge", 13>; 192defm : CTEST_Aliases<"le", 14>; 193defm : CTEST_Aliases<"g" , 15>; 194 195//===----------------------------------------------------------------------===// 196// Assembler Mnemonic Aliases 197//===----------------------------------------------------------------------===// 198 199defm : CMPCCXADD_Aliases<"o" , 0>; 200defm : CMPCCXADD_Aliases<"no", 1>; 201defm : CMPCCXADD_Aliases<"b" , 2>; 202defm : CMPCCXADD_Aliases<"ae", 3>; 203defm : CMPCCXADD_Aliases<"nb", 3>; 204defm : CMPCCXADD_Aliases<"e" , 4>; 205defm : CMPCCXADD_Aliases<"z" , 4>; 206defm : CMPCCXADD_Aliases<"ne", 5>; 207defm : CMPCCXADD_Aliases<"nz", 5>; 208defm : CMPCCXADD_Aliases<"be", 6>; 209defm : CMPCCXADD_Aliases<"nbe", 7>; 210defm : CMPCCXADD_Aliases<"a", 7>; 211defm : CMPCCXADD_Aliases<"s" , 8>; 212defm : CMPCCXADD_Aliases<"ns", 9>; 213defm : CMPCCXADD_Aliases<"p" , 10>; 214defm : CMPCCXADD_Aliases<"np", 11>; 215defm : CMPCCXADD_Aliases<"l" , 12>; 216defm : CMPCCXADD_Aliases<"ge", 13>; 217defm : CMPCCXADD_Aliases<"nl", 13>; 218defm : CMPCCXADD_Aliases<"le", 14>; 219defm : CMPCCXADD_Aliases<"g", 15>; 220defm : CMPCCXADD_Aliases<"nle",15>; 221 222 223def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 224def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 225def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 226 227def : MnemonicAlias<"cbw", "cbtw", "att">; 228def : MnemonicAlias<"cwde", "cwtl", "att">; 229def : MnemonicAlias<"cwd", "cwtd", "att">; 230def : MnemonicAlias<"cdq", "cltd", "att">; 231def : MnemonicAlias<"cdqe", "cltq", "att">; 232def : MnemonicAlias<"cqo", "cqto", "att">; 233 234// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 235def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 236def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 237 238def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 239def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 240 241def : MnemonicAlias<"loopz", "loope">; 242def : MnemonicAlias<"loopnz", "loopne">; 243 244def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 245def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 246def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 247def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 248def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 249def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 250def : MnemonicAlias<"popf", "popfq", "intel">, Requires<[In64BitMode]>; 251def : MnemonicAlias<"popfd", "popfl", "att">; 252def : MnemonicAlias<"popfw", "popf", "intel">, Requires<[In32BitMode]>; 253def : MnemonicAlias<"popfw", "popf", "intel">, Requires<[In64BitMode]>; 254 255// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 256// all modes. However: "push (addr)" and "push $42" should default to 257// pushl/pushq depending on the current mode. Similar for "pop %bx" 258def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 259def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 260def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 261def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 262def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 263def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 264def : MnemonicAlias<"pushf", "pushfq", "intel">, Requires<[In64BitMode]>; 265def : MnemonicAlias<"pushfd", "pushfl", "att">; 266def : MnemonicAlias<"pushfw", "pushf", "intel">, Requires<[In32BitMode]>; 267def : MnemonicAlias<"pushfw", "pushf", "intel">, Requires<[In64BitMode]>; 268 269def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 270def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 271def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 272def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 273def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 274def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 275 276def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 277def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 278def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 279def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 280 281def : MnemonicAlias<"repe", "rep">; 282def : MnemonicAlias<"repz", "rep">; 283def : MnemonicAlias<"repnz", "repne">; 284 285def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 286def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 287def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 288 289// Apply 'ret' behavior to 'retn' 290def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; 291def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; 292def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; 293def : MnemonicAlias<"retn", "ret", "intel">; 294 295def : MnemonicAlias<"sal", "shl", "intel">; 296def : MnemonicAlias<"salb", "shlb", "att">; 297def : MnemonicAlias<"salw", "shlw", "att">; 298def : MnemonicAlias<"sall", "shll", "att">; 299def : MnemonicAlias<"salq", "shlq", "att">; 300 301def : MnemonicAlias<"smovb", "movsb", "att">; 302def : MnemonicAlias<"smovw", "movsw", "att">; 303def : MnemonicAlias<"smovl", "movsl", "att">; 304def : MnemonicAlias<"smovq", "movsq", "att">; 305 306def : MnemonicAlias<"ud2a", "ud2", "att">; 307def : MnemonicAlias<"ud2bw", "ud1w", "att">; 308def : MnemonicAlias<"ud2bl", "ud1l", "att">; 309def : MnemonicAlias<"ud2bq", "ud1q", "att">; 310def : MnemonicAlias<"verrw", "verr", "att">; 311 312// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release' 313def : MnemonicAlias<"acquire", "xacquire", "intel">; 314def : MnemonicAlias<"release", "xrelease", "intel">; 315 316// System instruction aliases. 317def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 318def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 319def : MnemonicAlias<"sysret", "sysretl", "att">; 320def : MnemonicAlias<"sysexit", "sysexitl", "att">; 321 322def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 323def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 324def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 325def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 326def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 327def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 328def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 329def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 330def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 331def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 332def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 333def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 334def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>; 335def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>; 336def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>; 337def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>; 338def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>; 339def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>; 340def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>; 341def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>; 342 343 344// Floating point stack aliases. 345def : MnemonicAlias<"fcmovz", "fcmove", "att">; 346def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 347def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 348def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 349def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 350def : MnemonicAlias<"fcomip", "fcompi">; 351def : MnemonicAlias<"fildq", "fildll", "att">; 352def : MnemonicAlias<"fistpq", "fistpll", "att">; 353def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 354def : MnemonicAlias<"fldcww", "fldcw", "att">; 355def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 356def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 357def : MnemonicAlias<"fucomip", "fucompi">; 358def : MnemonicAlias<"fwait", "wait">; 359 360def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; 361def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; 362def : MnemonicAlias<"xsaveq", "xsave64", "att">; 363def : MnemonicAlias<"xrstorq", "xrstor64", "att">; 364def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; 365def : MnemonicAlias<"xrstorsq", "xrstors64", "att">; 366def : MnemonicAlias<"xsavecq", "xsavec64", "att">; 367def : MnemonicAlias<"xsavesq", "xsaves64", "att">; 368 369class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 370 string VariantName> 371 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 372 !strconcat(Prefix, NewCond, Suffix), VariantName>; 373 374/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 375/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 376/// example "setz" -> "sete". 377multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 378 string V = ""> { 379 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 380 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 381 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 382 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 383 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 384 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 385 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 386 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 387 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 388 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 389 390 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 391 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 392 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 393 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 394} 395 396// Aliases for set<CC> 397defm : IntegerCondCodeMnemonicAlias<"set", "">; 398// Aliases for j<CC> 399defm : IntegerCondCodeMnemonicAlias<"j", "">; 400// Aliases for cmov<CC>{w,l,q} 401defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 402defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 403defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 404// No size suffix for intel-style asm. 405defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 406 407// Aliases for cfcmov<CC>{w,l,q} 408defm : IntegerCondCodeMnemonicAlias<"cfcmov", "w", "att">; 409defm : IntegerCondCodeMnemonicAlias<"cfcmov", "l", "att">; 410defm : IntegerCondCodeMnemonicAlias<"cfcmov", "q", "att">; 411// No size suffix for intel-style asm. 412defm : IntegerCondCodeMnemonicAlias<"cfcmov", "", "intel">; 413//===----------------------------------------------------------------------===// 414// Assembler Instruction Aliases 415//===----------------------------------------------------------------------===// 416 417// aad/aam default to base 10 if no operand is specified. 418def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>; 419def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>; 420 421// Disambiguate the mem/imm form of bt-without-a-suffix as btl. 422// Likewise for btc/btr/bts. 423def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}", 424 (BT32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 425def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}", 426 (BTC32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 427def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}", 428 (BTR32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 429def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}", 430 (BTS32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 431 432// clr aliases. 433def : InstAlias<"clr{b}\t$reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 434def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 435def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 436def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 437 438// lods aliases. Accept the destination being omitted because it's implicit 439// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 440// in the destination. 441def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src), 0>; 442def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>; 443def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>; 444def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 445def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 446def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 447def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 448def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 449def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0, "intel">; 450def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">; 451def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">; 452def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 453 454 455// stos aliases. Accept the source being omitted because it's implicit in 456// the mnemonic, or the mnemonic suffix being omitted because it's implicit 457// in the source. 458def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst), 0>; 459def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>; 460def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>; 461def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 462def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 463def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 464def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 465def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 466def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0, "intel">; 467def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">; 468def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">; 469def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 470 471 472// scas aliases. Accept the destination being omitted because it's implicit 473// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 474// in the destination. 475def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst), 0>; 476def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>; 477def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>; 478def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 479def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 480def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 481def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 482def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 483def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0, "intel">; 484def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">; 485def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">; 486def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 487 488// cmps aliases. Mnemonic suffix being omitted because it's implicit 489// in the destination. 490def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 491def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 492def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 493def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 494 495// movs aliases. Mnemonic suffix being omitted because it's implicit 496// in the destination. 497def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 498def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 499def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 500def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 501 502// div and idiv aliases for explicit A register. 503def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 504def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 505def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 506def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 507def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 508def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 509def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 510def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 511def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 512def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 513def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 514def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 515def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 516def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 517def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 518def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 519 520 521 522// Various unary fpstack operations default to operating on ST1. 523// For example, "fxch" -> "fxch %st(1)" 524def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 525def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; 526def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 527def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 528def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; 529def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 530def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 531def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 532def : InstAlias<"fxch", (XCH_F ST1), 0>; 533def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 534def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 535def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 536def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 537def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 538def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 539def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 540def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 541 542// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 543// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 544// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 545// gas. 546multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 547 def : InstAlias<!strconcat(Mnemonic, "\t$op"), 548 (Inst RSTi:$op), EmitAlias>; 549 def : InstAlias<!strconcat(Mnemonic, "\t{%st, %st|st, st}"), 550 (Inst ST0), EmitAlias>; 551} 552 553defm : FpUnaryAlias<"fadd", ADD_FST0r, 0>; 554defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 555defm : FpUnaryAlias<"fsub", SUB_FST0r, 0>; 556defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0, 0>; 557defm : FpUnaryAlias<"fsubr", SUBR_FST0r, 0>; 558defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0, 0>; 559defm : FpUnaryAlias<"fmul", MUL_FST0r, 0>; 560defm : FpUnaryAlias<"fmulp", MUL_FPrST0, 0>; 561defm : FpUnaryAlias<"fdiv", DIV_FST0r, 0>; 562defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0, 0>; 563defm : FpUnaryAlias<"fdivr", DIVR_FST0r, 0>; 564defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0, 0>; 565defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 566defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 567defm : FpUnaryAlias<"fcompi", COM_FIPr, 0>; 568defm : FpUnaryAlias<"fucompi", UCOM_FIPr, 0>; 569 570 571// Handle "f{mulp,addp} $op, %st(0)" the same as "f{mulp,addp} $op", since they 572// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 573// solely because gas supports it. 574def : InstAlias<"faddp\t{$op, %st|st, $op}", (ADD_FPrST0 RSTi:$op), 0>; 575def : InstAlias<"fmulp\t{$op, %st|st, $op}", (MUL_FPrST0 RSTi:$op), 0>; 576def : InstAlias<"fsub{|r}p\t{$op, %st|st, $op}", (SUBR_FPrST0 RSTi:$op), 0>; 577def : InstAlias<"fsub{r|}p\t{$op, %st|st, $op}", (SUB_FPrST0 RSTi:$op), 0>; 578def : InstAlias<"fdiv{|r}p\t{$op, %st|st, $op}", (DIVR_FPrST0 RSTi:$op), 0>; 579def : InstAlias<"fdiv{r|}p\t{$op, %st|st, $op}", (DIV_FPrST0 RSTi:$op), 0>; 580 581def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; 582 583// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 584// this is compatible with what GAS does. 585def : InstAlias<"lcall\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 586def : InstAlias<"ljmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 587def : InstAlias<"lcall\t{*}$dst", (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 588def : InstAlias<"ljmp\t{*}$dst", (FARJMP32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 589def : InstAlias<"lcall\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 590def : InstAlias<"ljmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 591def : InstAlias<"lcall\t{*}$dst", (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 592def : InstAlias<"ljmp\t{*}$dst", (FARJMP16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 593 594def : InstAlias<"jmp\t{*}$dst", (JMP64m i64mem:$dst), 0, "att">, Requires<[In64BitMode]>; 595def : InstAlias<"jmp\t{*}$dst", (JMP32m i32mem:$dst), 0, "att">, Requires<[In32BitMode]>; 596def : InstAlias<"jmp\t{*}$dst", (JMP16m i16mem:$dst), 0, "att">, Requires<[In16BitMode]>; 597 598 599// "imul <imm>, B" is an alias for "imul <imm>, B, B". 600def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; 601def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; 602def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; 603def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; 604def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; 605def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; 606 607// ins aliases. Accept the mnemonic suffix being omitted because it's implicit 608// in the destination. 609def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0, "intel">; 610def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">; 611def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">; 612 613// outs aliases. Accept the mnemonic suffix being omitted because it's implicit 614// in the source. 615def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0, "intel">; 616def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">; 617def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">; 618 619// inb %dx -> inb %al, %dx 620def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 621def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 622def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 623def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>; 624def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>; 625def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>; 626 627 628// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 629def : InstAlias<"call\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 630def : InstAlias<"jmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 631def : InstAlias<"call\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 632def : InstAlias<"jmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 633def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 634def : InstAlias<"jmpw\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 635def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 636def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 637 638// Match 'movq <largeimm>, <reg>' as an alias for movabsq. 639def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 640 641// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, 642// which supports this due to an old AMD documentation bug when 64-bit mode was 643// created. 644def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 645 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 646def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 647 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 648 649// movsx aliases 650def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">; 651def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 652def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">; 653def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">; 654def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">; 655def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">; 656def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">; 657 658// movzx aliases 659def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">; 660def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 661def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">; 662def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">; 663def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">; 664def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">; 665// Note: No GR32->GR64 movzx form. 666 667// outb %dx -> outb %al, %dx 668def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 669def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 670def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 671def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>; 672def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>; 673def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>; 674 675// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 676// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 677// errors, since its encoding is the most compact. 678def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 679 680// shld/shrd op,op -> shld op, op, CL 681def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 682def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 683def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 684def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 685def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 686def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 687 688def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 689def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 690def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 691def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 692def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 693def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 694 695// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 696def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", 697 (TEST8mr i8mem :$mem, GR8 :$val), 0>; 698def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", 699 (TEST16mr i16mem:$mem, GR16:$val), 0>; 700def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", 701 (TEST32mr i32mem:$mem, GR32:$val), 0>; 702def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", 703 (TEST64mr i64mem:$mem, GR64:$val), 0>; 704 705// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 706def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 707 (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 708def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 709 (XCHG16rm GR16:$val, i16mem:$mem), 0>; 710def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 711 (XCHG32rm GR32:$val, i32mem:$mem), 0>; 712def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 713 (XCHG64rm GR64:$val, i64mem:$mem), 0>; 714 715// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 716def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 717def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>; 718def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 719 720// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we 721// would get by default because it's defined as NOP. But xchg %eax, %eax implies 722// implicit zeroing of the upper 32 bits. So alias to the longer encoding. 723def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}", 724 (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>; 725 726// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this 727// we emit an unneeded REX.w prefix. 728def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>; 729 730// These aliases exist to get the parser to prioritize matching 8-bit 731// immediate encodings over matching the implicit ax/eax/rax encodings. By 732// explicitly mentioning the A register here, these entries will be ordered 733// first due to the more explicit immediate type. 734def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; 735def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; 736def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; 737def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; 738def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; 739def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; 740def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; 741def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>; 742 743def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>; 744def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>; 745def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>; 746def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>; 747def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>; 748def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>; 749def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>; 750def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>; 751 752def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>; 753def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>; 754def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>; 755def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>; 756def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>; 757def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>; 758def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>; 759def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>; 760 761// MMX instr alia 762def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}", 763 (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>; 764 765// CMOV SETCC SETZUCC Aliases 766multiclass CMOV_SETCC_Aliases<string Cond, int CC> { 767 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}", 768 (CMOV16rr GR16:$dst, GR16:$src, CC), 0>; 769 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}", 770 (CMOV16rm GR16:$dst, i16mem:$src, CC), 0>; 771 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}", 772 (CMOV32rr GR32:$dst, GR32:$src, CC), 0>; 773 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}", 774 (CMOV32rm GR32:$dst, i32mem:$src, CC), 0>; 775 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}", 776 (CMOV64rr GR64:$dst, GR64:$src, CC), 0>; 777 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}", 778 (CMOV64rm GR64:$dst, i64mem:$src, CC), 0>; 779let Predicates = [In64BitMode] in { 780 def : InstAlias<"cmov"#Cond#"{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 781 (CMOV16rr_ND GR16:$dst, GR16:$src1, GR16:$src2, CC), 0>; 782 def : InstAlias<"cmov"#Cond#"{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 783 (CMOV16rm_ND GR16:$dst, GR16:$src1, i16mem:$src2, CC), 0>; 784 def : InstAlias<"cmov"#Cond#"{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 785 (CMOV32rr_ND GR32:$dst, GR32:$src1, GR32:$src2, CC), 0>; 786 def : InstAlias<"cmov"#Cond#"{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 787 (CMOV32rm_ND GR32:$dst, GR32:$src1, i32mem:$src2, CC), 0>; 788 def : InstAlias<"cmov"#Cond#"{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 789 (CMOV64rr_ND GR64:$dst, GR64:$src1, GR64:$src2, CC), 0>; 790 def : InstAlias<"cmov"#Cond#"{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 791 (CMOV64rm_ND GR64:$dst, GR64:$src1, i64mem:$src2, CC), 0>; 792 793 def : InstAlias<"setzu"#Cond#"\t$dst", (SETZUCCr GR8:$dst, CC), 0>; 794 def : InstAlias<"setzu"#Cond#"\t$dst", (SETZUCCm i8mem:$dst, CC), 0>; 795 def : InstAlias<"set"#Cond#"\t$dst", (SETCCr_EVEX GR8:$dst, CC), 0>; 796 def : InstAlias<"set"#Cond#"\t$dst", (SETCCm_EVEX i8mem:$dst, CC), 0>; 797} 798 def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>; 799 def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>; 800} 801 802defm : CMOV_SETCC_Aliases<"o" , 0>; 803defm : CMOV_SETCC_Aliases<"no", 1>; 804defm : CMOV_SETCC_Aliases<"b" , 2>; 805defm : CMOV_SETCC_Aliases<"ae", 3>; 806defm : CMOV_SETCC_Aliases<"e" , 4>; 807defm : CMOV_SETCC_Aliases<"ne", 5>; 808defm : CMOV_SETCC_Aliases<"be", 6>; 809defm : CMOV_SETCC_Aliases<"a" , 7>; 810defm : CMOV_SETCC_Aliases<"s" , 8>; 811defm : CMOV_SETCC_Aliases<"ns", 9>; 812defm : CMOV_SETCC_Aliases<"p" , 10>; 813defm : CMOV_SETCC_Aliases<"np", 11>; 814defm : CMOV_SETCC_Aliases<"l" , 12>; 815defm : CMOV_SETCC_Aliases<"ge", 13>; 816defm : CMOV_SETCC_Aliases<"le", 14>; 817defm : CMOV_SETCC_Aliases<"g" , 15>; 818 819multiclass CFCMOV_Aliases<string Cond, int CC> { 820let Predicates = [In64BitMode] in { 821 def : InstAlias<"cfcmov"#Cond#"{w}\t{$src, $dst|$dst, $src}", 822 (CFCMOV16rr GR16:$dst, GR16:$src, CC), 0>; 823 def : InstAlias<"cfcmov"#Cond#"{l}\t{$src, $dst|$dst, $src}", 824 (CFCMOV32rr GR32:$dst, GR32:$src, CC), 0>; 825 def : InstAlias<"cfcmov"#Cond#"{q}\t{$src, $dst|$dst, $src}", 826 (CFCMOV64rr GR64:$dst, GR64:$src, CC), 0>; 827 def : InstAlias<"cfcmov"#Cond#"{w}\t{$src, $dst|$dst, $src}", 828 (CFCMOV16rm GR16:$dst, i16mem:$src, CC), 0>; 829 def : InstAlias<"cfcmov"#Cond#"{l}\t{$src, $dst|$dst, $src}", 830 (CFCMOV32rm GR32:$dst, i32mem:$src, CC), 0>; 831 def : InstAlias<"cfcmov"#Cond#"{q}\t{$src, $dst|$dst, $src}", 832 (CFCMOV64rm GR64:$dst, i64mem:$src, CC), 0>; 833 def : InstAlias<"cfcmov"#Cond#"{w}\t{$src, $dst|$dst, $src}", 834 (CFCMOV16mr i16mem:$dst, GR16:$src, CC), 0>; 835 def : InstAlias<"cfcmov"#Cond#"{l}\t{$src, $dst|$dst, $src}", 836 (CFCMOV32mr i32mem:$dst, GR32:$src, CC), 0>; 837 def : InstAlias<"cfcmov"#Cond#"{q}\t{$src, $dst|$dst, $src}", 838 (CFCMOV64mr i64mem:$dst, GR64:$src, CC), 0>; 839 def : InstAlias<"cfcmov"#Cond#"{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 840 (CFCMOV16rr_ND GR16:$dst, GR16:$src1, GR16:$src2, CC), 0>; 841 def : InstAlias<"cfcmov"#Cond#"{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 842 (CFCMOV32rr_ND GR32:$dst, GR32:$src1, GR32:$src2, CC), 0>; 843 def : InstAlias<"cfcmov"#Cond#"{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 844 (CFCMOV64rr_ND GR64:$dst, GR64:$src1, GR64:$src2, CC), 0>; 845 def : InstAlias<"cfcmov"#Cond#"{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 846 (CFCMOV16rm_ND GR16:$dst, GR16:$src1, i16mem:$src2, CC), 0>; 847 def : InstAlias<"cfcmov"#Cond#"{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 848 (CFCMOV32rm_ND GR32:$dst, GR32:$src1, i32mem:$src2, CC), 0>; 849 def : InstAlias<"cfcmov"#Cond#"{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", 850 (CFCMOV64rm_ND GR64:$dst, GR64:$src1, i64mem:$src2, CC), 0>; 851} 852} 853defm : CFCMOV_Aliases<"o" , 0>; 854defm : CFCMOV_Aliases<"no", 1>; 855defm : CFCMOV_Aliases<"b" , 2>; 856defm : CFCMOV_Aliases<"ae", 3>; 857defm : CFCMOV_Aliases<"e" , 4>; 858defm : CFCMOV_Aliases<"ne", 5>; 859defm : CFCMOV_Aliases<"be", 6>; 860defm : CFCMOV_Aliases<"a" , 7>; 861defm : CFCMOV_Aliases<"s" , 8>; 862defm : CFCMOV_Aliases<"ns", 9>; 863defm : CFCMOV_Aliases<"p" , 10>; 864defm : CFCMOV_Aliases<"np", 11>; 865defm : CFCMOV_Aliases<"l" , 12>; 866defm : CFCMOV_Aliases<"ge", 13>; 867defm : CFCMOV_Aliases<"le", 14>; 868defm : CFCMOV_Aliases<"g" , 15>; 869 870// Condition dump instructions Alias 871def : InstAlias<"jo\t$dst", (JCC_1 brtarget8:$dst, 0), 0>; 872def : InstAlias<"jno\t$dst", (JCC_1 brtarget8:$dst, 1), 0>; 873def : InstAlias<"jb\t$dst", (JCC_1 brtarget8:$dst, 2), 0>; 874def : InstAlias<"jae\t$dst", (JCC_1 brtarget8:$dst, 3), 0>; 875def : InstAlias<"je\t$dst", (JCC_1 brtarget8:$dst, 4), 0>; 876def : InstAlias<"jne\t$dst", (JCC_1 brtarget8:$dst, 5), 0>; 877def : InstAlias<"jbe\t$dst", (JCC_1 brtarget8:$dst, 6), 0>; 878def : InstAlias<"ja\t$dst", (JCC_1 brtarget8:$dst, 7), 0>; 879def : InstAlias<"js\t$dst", (JCC_1 brtarget8:$dst, 8), 0>; 880def : InstAlias<"jns\t$dst", (JCC_1 brtarget8:$dst, 9), 0>; 881def : InstAlias<"jp\t$dst", (JCC_1 brtarget8:$dst, 10), 0>; 882def : InstAlias<"jnp\t$dst", (JCC_1 brtarget8:$dst, 11), 0>; 883def : InstAlias<"jl\t$dst", (JCC_1 brtarget8:$dst, 12), 0>; 884def : InstAlias<"jge\t$dst", (JCC_1 brtarget8:$dst, 13), 0>; 885def : InstAlias<"jle\t$dst", (JCC_1 brtarget8:$dst, 14), 0>; 886def : InstAlias<"jg\t$dst", (JCC_1 brtarget8:$dst, 15), 0>; 887 888// SVM instructions Alias 889def : InstAlias<"skinit\t{%eax|eax}", (SKINIT), 0>; 890def : InstAlias<"vmrun\t{%eax|eax}", (VMRUN32), 0>, Requires<[Not64BitMode]>; 891def : InstAlias<"vmrun\t{%rax|rax}", (VMRUN64), 0>, Requires<[In64BitMode]>; 892def : InstAlias<"vmload\t{%eax|eax}", (VMLOAD32), 0>, Requires<[Not64BitMode]>; 893def : InstAlias<"vmload\t{%rax|rax}", (VMLOAD64), 0>, Requires<[In64BitMode]>; 894def : InstAlias<"vmsave\t{%eax|eax}", (VMSAVE32), 0>, Requires<[Not64BitMode]>; 895def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>; 896def : InstAlias<"invlpga\t{%eax, %ecx|eax, ecx}", (INVLPGA32), 0>, Requires<[Not64BitMode]>; 897def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>; 898 899// Aliases with explicit %xmm0 900def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", 901 (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>; 902def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", 903 (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>; 904