1//===---- X86InstrAMX.td - AMX Instruction Set Extension --*- tablegen -*--===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the instructions that make up the Intel AMX instruction 10// set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// AMX instructions 16 17let Predicates = [HasAMXTILE, In64BitMode] in { 18 let SchedRW = [WriteSystem] in { 19 let hasSideEffects = 1, 20 Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in 21 def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src), 22 "ldtilecfg\t$src", 23 [(int_x86_ldtilecfg addr:$src)]>, VEX, T8PS; 24 let hasSideEffects = 1 in 25 def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src), 26 "sttilecfg\t$src", 27 [(int_x86_sttilecfg addr:$src)]>, VEX, T8PD; 28 let mayLoad = 1 in 29 def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst), 30 (ins sibmem:$src), 31 "tileloadd\t{$src, $dst|$dst, $src}", []>, 32 VEX, T8XD; 33 let mayLoad = 1 in 34 def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst), 35 (ins sibmem:$src), 36 "tileloaddt1\t{$src, $dst|$dst, $src}", []>, 37 VEX, T8PD; 38 let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in 39 def TILERELEASE : I<0x49, MRM_C0, (outs), (ins), 40 "tilerelease", [(int_x86_tilerelease)]>, VEX, T8PS; 41 let mayStore = 1 in 42 def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs), 43 (ins sibmem:$dst, TILE:$src), 44 "tilestored\t{$src, $dst|$dst, $src}", []>, 45 VEX, T8XS; 46 def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins), 47 "tilezero\t$dst", []>, 48 VEX, T8XD; 49 50 // Pseduo instruction for RA. 51 let hasSideEffects = 1, mayLoad = 1, 52 Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in 53 def PLDTILECFG : PseudoI <(outs TILECFG:$cfg), (ins opaquemem:$src), []>; 54 55 let hasSideEffects = 1, mayStore = 1 in 56 def PSTTILECFG : PseudoI<(outs), (ins opaquemem:$dst, TILECFG:$cfg), []>; 57 58 def PTILELOADDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1, 59 GR16:$src2, 60 opaquemem:$src3, 61 TILECFG:$cfg), []>; 62 def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1, 63 GR16:$src2, opaquemem:$src3, 64 TILE:$src4, TILECFG:$cfg), []>; 65 def PTILEZEROV : PseudoI<(outs TILE: $dst), (ins GR16:$src1, 66 GR16:$src2, 67 TILECFG:$cfg), []>; 68 69 let usesCustomInserter = 1 in { 70 // Pseudo instructions, using immediates instead of tile registers. 71 // To be translated to the actual instructions in X86ISelLowering.cpp 72 def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>; 73 def PTILELOADDT1 : PseudoI<(outs), (ins u8imm:$src1, 74 sibmem:$src2), []>; 75 def PTILESTORED : PseudoI<(outs), (ins i8mem:$dst, u8imm:$src), []>; 76 def PTILEZERO : PseudoI<(outs), (ins u8imm:$src), 77 [(int_x86_tilezero timm:$src)]>; 78 } 79 } // SchedRW 80} // HasAMXTILE 81 82let Predicates = [HasAMXINT8, In64BitMode] in { 83 let SchedRW = [WriteSystem] in { 84 let Constraints = "$src1 = $dst" in { 85 def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst), 86 (ins TILE:$src1, TILE:$src2, TILE:$src3), 87 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, 88 VEX_4V, T8XD; 89 def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst), 90 (ins TILE:$src1, TILE:$src2, TILE:$src3), 91 "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, 92 VEX_4V, T8XS; 93 def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst), 94 (ins TILE:$src1, TILE:$src2, TILE:$src3), 95 "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, 96 VEX_4V, T8PD; 97 def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst), 98 (ins TILE:$src1, TILE:$src2, TILE:$src3), 99 "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, 100 VEX_4V, T8PS; 101 } 102 103 // Pseduo instruction for RA. 104 let Constraints = "$src4 = $dst" in 105 def PTDPBSSDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1, 106 GR16:$src2, GR16:$src3, TILE:$src4, 107 TILE:$src5, TILE:$src6, TILECFG:$cfg), []>; 108 109 let usesCustomInserter = 1 in { 110 // Pseudo instructions, using immediates instead of tile registers. 111 // To be translated to the actual instructions in X86ISelLowering.cpp 112 def PTDPBSSD : PseudoI<(outs), (ins u8imm:$src1, 113 u8imm:$src2, u8imm:$src3), 114 [(int_x86_tdpbssd timm:$src1, 115 timm:$src2, timm:$src3)]>; 116 def PTDPBSUD : PseudoI<(outs), (ins u8imm:$src1, 117 u8imm:$src2, u8imm:$src3), 118 [(int_x86_tdpbsud timm:$src1, 119 timm:$src2, timm:$src3)]>; 120 def PTDPBUSD : PseudoI<(outs), (ins u8imm:$src1, 121 u8imm:$src2, u8imm:$src3), 122 [(int_x86_tdpbusd timm:$src1, 123 timm:$src2, timm:$src3)]>; 124 def PTDPBUUD : PseudoI<(outs), (ins u8imm:$src1, 125 u8imm:$src2, u8imm:$src3), 126 [(int_x86_tdpbuud timm:$src1, 127 timm:$src2, timm:$src3)]>; 128 } 129 } 130} // HasAMXTILE 131 132let Predicates = [HasAMXBF16, In64BitMode] in { 133 let SchedRW = [WriteSystem] in { 134 let Constraints = "$src1 = $dst" in 135 def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst), 136 (ins TILE:$src1, TILE:$src2, TILE:$src3), 137 "tdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}", 138 []>, VEX_4V, T8XS; 139 140 let usesCustomInserter = 1 in { 141 // Pseudo instructions, using immediates instead of tile registers. 142 // To be translated to the actual instructions in X86ISelLowering.cpp 143 def PTDPBF16PS : PseudoI<(outs), (ins u8imm:$src1, 144 u8imm:$src2, u8imm:$src3), 145 [(int_x86_tdpbf16ps timm:$src1, 146 timm:$src2, timm:$src3)]>; 147 } 148 } 149} // HasAMXTILE, HasAMXBF16 150