1//===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the 3DNow! instruction set, which extends MMX to support 10// floating point and also adds a few more random instructions for good measure. 11// 12//===----------------------------------------------------------------------===// 13 14class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat> 15 : I<o, F, outs, ins, asm, pat>, Requires<[Has3DNow]> { 16} 17 18class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat> 19 : I3DNow<o, F, (outs VR64:$dst), ins, 20 !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat>, ThreeDNow { 21 let Constraints = "$src1 = $dst"; 22} 23 24class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat> 25 : I3DNow<o, F, (outs VR64:$dst), ins, 26 !strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat>, ThreeDNow; 27 28multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, 29 X86FoldableSchedWrite sched, bit Commutable = 0, 30 string Ver = ""> { 31 let isCommutable = Commutable in 32 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, 33 [(set VR64:$dst, (!cast<Intrinsic>( 34 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>, 35 Sched<[sched]>; 36 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, 37 [(set VR64:$dst, (!cast<Intrinsic>( 38 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, 39 (bitconvert (load_mmx addr:$src2))))]>, 40 Sched<[sched.Folded, sched.ReadAfterFold]>; 41} 42 43multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, 44 X86FoldableSchedWrite sched, string Ver = ""> { 45 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn, 46 [(set VR64:$dst, (!cast<Intrinsic>( 47 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))]>, 48 Sched<[sched]>; 49 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn, 50 [(set VR64:$dst, (!cast<Intrinsic>( 51 !strconcat("int_x86_3dnow", Ver, "_", Mn)) 52 (bitconvert (load_mmx addr:$src))))]>, 53 Sched<[sched.Folded, sched.ReadAfterFold]>; 54} 55 56defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", SchedWriteVecALU.MMX, 1>; 57defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id", WriteCvtPS2I>; 58defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc", WriteFAdd>; 59defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", WriteFAdd, 1>; 60defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", WriteFAdd, 1>; 61defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge", WriteFAdd>; 62defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt", WriteFAdd>; 63defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax", WriteFAdd>; 64defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin", WriteFAdd>; 65defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", WriteFAdd, 1>; 66defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp", WriteFAdd>; 67defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1", WriteFAdd>; 68defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", WriteFAdd>; 69defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", WriteFAdd>; 70defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt", WriteFAdd>; 71defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", WriteFAdd, 1>; 72defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", WriteFAdd, 1>; 73defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", WriteCvtI2PS>; 74defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>; 75 76let SchedRW = [WriteEMMS], 77 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 78 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in 79def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", 80 [(int_x86_mmx_femms)]>, TB; 81 82// PREFETCHWT1 is supported we want to use it for everything but T0. 83def PrefetchWLevel : PatFrag<(ops), (i32 imm), [{ 84 return N->getSExtValue() == 3 || !Subtarget->hasPREFETCHWT1(); 85}]>; 86 87// Use PREFETCHWT1 for NTA, T2, T1. 88def PrefetchWT1Level : ImmLeaf<i32, [{ 89 return Imm < 3; 90}]>; 91 92let SchedRW = [WriteLoad] in { 93let Predicates = [Has3DNow, NoSSEPrefetch] in 94def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr), 95 "prefetch\t$addr", 96 [(prefetch addr:$addr, imm, imm, (i32 1))]>, TB; 97 98def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr", 99 [(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))]>, 100 TB, Requires<[HasPrefetchW]>; 101 102def PREFETCHWT1 : I<0x0D, MRM2m, (outs), (ins i8mem:$addr), "prefetchwt1\t$addr", 103 [(prefetch addr:$addr, (i32 1), (i32 PrefetchWT1Level), (i32 1))]>, 104 TB, Requires<[HasPREFETCHWT1]>; 105} 106 107// "3DNowA" instructions 108defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", WriteCvtPS2I, "a">; 109defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", WriteCvtI2PS, "a">; 110defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", WriteFAdd, 0, "a">; 111defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", WriteFAdd, 0, "a">; 112defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", SchedWriteShuffle.MMX, "a">; 113