1//===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the 3DNow! instruction set, which extends MMX to support 10// floating point and also adds a few more random instructions for good measure. 11// 12//===----------------------------------------------------------------------===// 13 14class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat> 15 : I<o, F, outs, ins, asm, pat> { 16} 17 18class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat> 19 : I3DNow<o, F, (outs VR64:$dst), ins, 20 !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat>, ThreeDNow { 21 let Constraints = "$src1 = $dst"; 22} 23 24class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat> 25 : I3DNow<o, F, (outs VR64:$dst), ins, 26 !strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat>, ThreeDNow; 27 28multiclass I3DNow_binop_rm<bits<8> opc, string Mn, 29 X86FoldableSchedWrite sched, bit Commutable = 0> { 30 let mayStore=0, hasSideEffects=0 in { 31 let isCommutable = Commutable, mayLoad=0 in 32 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, 33 []>, Sched<[sched]>; 34 let mayLoad=1 in 35 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, 36 []>, Sched<[sched.Folded, sched.ReadAfterFold]>; 37 } 38} 39 40multiclass I3DNow_conv_rm<bits<8> opc, string Mn, 41 X86FoldableSchedWrite sched> { 42 let mayStore=0, hasSideEffects=0 in { 43 let mayLoad=0 in 44 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn, 45 []>, Sched<[sched]>; 46 let mayLoad=1 in 47 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn, 48 []>, Sched<[sched.Folded, sched.ReadAfterFold]>; 49 } 50} 51 52defm PAVGUSB : I3DNow_binop_rm<0xBF, "pavgusb", SchedWriteVecALU.MMX, 1>; 53defm PF2ID : I3DNow_conv_rm<0x1D, "pf2id", WriteCvtPS2I>; 54defm PFACC : I3DNow_binop_rm<0xAE, "pfacc", WriteFAdd>; 55defm PFADD : I3DNow_binop_rm<0x9E, "pfadd", WriteFAdd, 1>; 56defm PFCMPEQ : I3DNow_binop_rm<0xB0, "pfcmpeq", WriteFAdd, 1>; 57defm PFCMPGE : I3DNow_binop_rm<0x90, "pfcmpge", WriteFAdd>; 58defm PFCMPGT : I3DNow_binop_rm<0xA0, "pfcmpgt", WriteFAdd>; 59defm PFMAX : I3DNow_binop_rm<0xA4, "pfmax", WriteFAdd>; 60defm PFMIN : I3DNow_binop_rm<0x94, "pfmin", WriteFAdd>; 61defm PFMUL : I3DNow_binop_rm<0xB4, "pfmul", WriteFAdd, 1>; 62defm PFRCP : I3DNow_conv_rm<0x96, "pfrcp", WriteFAdd>; 63defm PFRCPIT1 : I3DNow_binop_rm<0xA6, "pfrcpit1", WriteFAdd>; 64defm PFRCPIT2 : I3DNow_binop_rm<0xB6, "pfrcpit2", WriteFAdd>; 65defm PFRSQIT1 : I3DNow_binop_rm<0xA7, "pfrsqit1", WriteFAdd>; 66defm PFRSQRT : I3DNow_conv_rm<0x97, "pfrsqrt", WriteFAdd>; 67defm PFSUB : I3DNow_binop_rm<0x9A, "pfsub", WriteFAdd, 1>; 68defm PFSUBR : I3DNow_binop_rm<0xAA, "pfsubr", WriteFAdd, 1>; 69defm PI2FD : I3DNow_conv_rm<0x0D, "pi2fd", WriteCvtI2PS>; 70defm PMULHRW : I3DNow_binop_rm<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>; 71 72let SchedRW = [WriteEMMS], mayLoad=1, mayStore=1, hasSideEffects=1 in 73def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", 74 []>, TB; 75 76let SchedRW = [WriteLoad], mayLoad=1, mayStore=1, hasSideEffects=0 in { 77def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr), 78 "prefetch\t$addr", 79 []>, TB; 80 81// Note: PREFETCHW is the only instruction in this file which is NOT specific to 3DNow! 82def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr", 83 [(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))]>, 84 TB, Requires<[HasPrefetchW]>; 85 86def PREFETCHWT1 : I<0x0D, MRM2m, (outs), (ins i8mem:$addr), "prefetchwt1\t$addr", 87 []>, TB; 88} 89 90// "3DNowA" instructions 91defm PF2IW : I3DNow_conv_rm<0x1C, "pf2iw", WriteCvtPS2I>; 92defm PI2FW : I3DNow_conv_rm<0x0C, "pi2fw", WriteCvtI2PS>; 93defm PFNACC : I3DNow_binop_rm<0x8A, "pfnacc", WriteFAdd, 0>; 94defm PFPNACC : I3DNow_binop_rm<0x8E, "pfpnacc", WriteFAdd, 0>; 95defm PSWAPD : I3DNow_conv_rm<0xBB, "pswapd", SchedWriteShuffle.MMX>; 96