1//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for the X86-32 and X86-64 10// architectures. 11// 12//===----------------------------------------------------------------------===// 13 14/// CCIfSubtarget - Match if the current subtarget has a feature F. 15class CCIfSubtarget<string F, CCAction A> 16 : CCIf<!strconcat("static_cast<const X86Subtarget&>" 17 "(State.getMachineFunction().getSubtarget()).", F), 18 A>; 19 20/// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F. 21class CCIfNotSubtarget<string F, CCAction A> 22 : CCIf<!strconcat("!static_cast<const X86Subtarget&>" 23 "(State.getMachineFunction().getSubtarget()).", F), 24 A>; 25 26// Register classes for RegCall 27class RC_X86_RegCall { 28 list<Register> GPR_8 = []; 29 list<Register> GPR_16 = []; 30 list<Register> GPR_32 = []; 31 list<Register> GPR_64 = []; 32 list<Register> FP_CALL = [FP0]; 33 list<Register> FP_RET = [FP0, FP1]; 34 list<Register> XMM = []; 35 list<Register> YMM = []; 36 list<Register> ZMM = []; 37} 38 39// RegCall register classes for 32 bits 40def RC_X86_32_RegCall : RC_X86_RegCall { 41 let GPR_8 = [AL, CL, DL, DIL, SIL]; 42 let GPR_16 = [AX, CX, DX, DI, SI]; 43 let GPR_32 = [EAX, ECX, EDX, EDI, ESI]; 44 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle [] 45 ///< \todo Fix AssignToReg to enable empty lists 46 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]; 47 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]; 48 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]; 49} 50 51class RC_X86_64_RegCall : RC_X86_RegCall { 52 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 53 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]; 54 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, 55 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15]; 56 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, 57 ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15]; 58} 59 60def RC_X86_64_RegCall_Win : RC_X86_64_RegCall { 61 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B]; 62 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W]; 63 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D]; 64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15]; 65} 66 67def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall { 68 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B]; 69 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W]; 70 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D]; 71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15]; 72} 73 74// X86-64 Intel regcall calling convention. 75multiclass X86_RegCall_base<RC_X86_RegCall RC> { 76def CC_#NAME : CallingConv<[ 77 // Handles byval parameters. 78 CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>, 79 CCIfByVal<CCPassByVal<4, 4>>, 80 81 // Promote i1/i8/i16/v1i1 arguments to i32. 82 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 83 84 // Promote v8i1/v16i1/v32i1 arguments to i32. 85 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>, 86 87 // bool, char, int, enum, long, pointer --> GPR 88 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 89 90 // long long, __int64 --> GPR 91 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 92 93 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 94 CCIfType<[v64i1], CCPromoteToType<i64>>, 95 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 96 CCAssignToReg<RC.GPR_64>>>, 97 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 98 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 99 100 // float, double, float128 --> XMM 101 // In the case of SSE disabled --> save to stack 102 CCIfType<[f32, f64, f128], 103 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 104 105 // long double --> FP 106 CCIfType<[f80], CCAssignToReg<RC.FP_CALL>>, 107 108 // __m128, __m128i, __m128d --> XMM 109 // In the case of SSE disabled --> save to stack 110 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 111 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 112 113 // __m256, __m256i, __m256d --> YMM 114 // In the case of SSE disabled --> save to stack 115 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 116 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 117 118 // __m512, __m512i, __m512d --> ZMM 119 // In the case of SSE disabled --> save to stack 120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 121 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>, 122 123 // If no register was found -> assign to stack 124 125 // In 64 bit, assign 64/32 bit values to 8 byte stack 126 CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64], 127 CCAssignToStack<8, 8>>>, 128 129 // In 32 bit, assign 64/32 bit values to 8/4 byte stack 130 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 131 CCIfType<[i64, f64], CCAssignToStack<8, 4>>, 132 133 // MMX type gets 8 byte slot in stack , while alignment depends on target 134 CCIfSubtarget<"is64Bit()", CCIfType<[x86mmx], CCAssignToStack<8, 8>>>, 135 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 136 137 // float 128 get stack slots whose size and alignment depends 138 // on the subtarget. 139 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 140 141 // Vectors get 16-byte stack slots that are 16-byte aligned. 142 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 143 CCAssignToStack<16, 16>>, 144 145 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 146 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 147 CCAssignToStack<32, 32>>, 148 149 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 151 CCAssignToStack<64, 64>> 152]>; 153 154def RetCC_#NAME : CallingConv<[ 155 // Promote i1, v1i1, v8i1 arguments to i8. 156 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>, 157 158 // Promote v16i1 arguments to i16. 159 CCIfType<[v16i1], CCPromoteToType<i16>>, 160 161 // Promote v32i1 arguments to i32. 162 CCIfType<[v32i1], CCPromoteToType<i32>>, 163 164 // bool, char, int, enum, long, pointer --> GPR 165 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>, 166 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>, 167 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 168 169 // long long, __int64 --> GPR 170 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 171 172 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 173 CCIfType<[v64i1], CCPromoteToType<i64>>, 174 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 175 CCAssignToReg<RC.GPR_64>>>, 176 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 177 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 178 179 // long double --> FP 180 CCIfType<[f80], CCAssignToReg<RC.FP_RET>>, 181 182 // float, double, float128 --> XMM 183 CCIfType<[f32, f64, f128], 184 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 185 186 // __m128, __m128i, __m128d --> XMM 187 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 188 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 189 190 // __m256, __m256i, __m256d --> YMM 191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 192 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 193 194 // __m512, __m512i, __m512d --> ZMM 195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 196 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>> 197]>; 198} 199 200//===----------------------------------------------------------------------===// 201// Return Value Calling Conventions 202//===----------------------------------------------------------------------===// 203 204// Return-value conventions common to all X86 CC's. 205def RetCC_X86Common : CallingConv<[ 206 // Scalar values are returned in AX first, then DX. For i8, the ABI 207 // requires the values to be in AL and AH, however this code uses AL and DL 208 // instead. This is because using AH for the second register conflicts with 209 // the way LLVM does multiple return values -- a return of {i16,i8} would end 210 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI 211 // for functions that return two i8 values are currently expected to pack the 212 // values into an i16 (which uses AX, and thus AL:AH). 213 // 214 // For code that doesn't care about the ABI, we allow returning more than two 215 // integer values in registers. 216 CCIfType<[v1i1], CCPromoteToType<i8>>, 217 CCIfType<[i1], CCPromoteToType<i8>>, 218 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>, 219 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 220 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 221 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, 222 223 // Boolean vectors of AVX-512 are returned in SIMD registers. 224 // The call from AVX to AVX-512 function should work, 225 // since the boolean types in AVX/AVX2 are promoted by default. 226 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 227 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 228 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 229 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 230 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 231 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 232 233 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 234 // can only be used by ABI non-compliant code. If the target doesn't have XMM 235 // registers, it won't have vector types. 236 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 237 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 238 239 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3 240 // can only be used by ABI non-compliant code. This vector type is only 241 // supported while using the AVX target feature. 242 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 243 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 244 245 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3 246 // can only be used by ABI non-compliant code. This vector type is only 247 // supported while using the AVX-512 target feature. 248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 249 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 250 251 // MMX vector types are always returned in MM0. If the target doesn't have 252 // MM0, it doesn't support these vector types. 253 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>, 254 255 // Long double types are always returned in FP0 (even with SSE), 256 // except on Win64. 257 CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>> 258]>; 259 260// X86-32 C return-value convention. 261def RetCC_X86_32_C : CallingConv<[ 262 // The X86-32 calling convention returns FP values in FP0, unless marked 263 // with "inreg" (used here to distinguish one kind of reg from another, 264 // weirdly; this is really the sse-regparm calling convention) in which 265 // case they use XMM0, otherwise it is the same as the common X86 calling 266 // conv. 267 CCIfInReg<CCIfSubtarget<"hasSSE2()", 268 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 269 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>, 270 CCDelegateTo<RetCC_X86Common> 271]>; 272 273// X86-32 FastCC return-value convention. 274def RetCC_X86_32_Fast : CallingConv<[ 275 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has 276 // SSE2. 277 // This can happen when a float, 2 x float, or 3 x float vector is split by 278 // target lowering, and is returned in 1-3 sse regs. 279 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 280 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 281 282 // For integers, ECX can be used as an extra return register 283 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>, 284 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 285 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 286 287 // Otherwise, it is the same as the common X86 calling convention. 288 CCDelegateTo<RetCC_X86Common> 289]>; 290 291// Intel_OCL_BI return-value convention. 292def RetCC_Intel_OCL_BI : CallingConv<[ 293 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. 294 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 295 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 296 297 // 256-bit FP vectors 298 // No more than 4 registers 299 CCIfType<[v8f32, v4f64, v8i32, v4i64], 300 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 301 302 // 512-bit FP vectors 303 CCIfType<[v16f32, v8f64, v16i32, v8i64], 304 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 305 306 // i32, i64 in the standard way 307 CCDelegateTo<RetCC_X86Common> 308]>; 309 310// X86-32 HiPE return-value convention. 311def RetCC_X86_32_HiPE : CallingConv<[ 312 // Promote all types to i32 313 CCIfType<[i8, i16], CCPromoteToType<i32>>, 314 315 // Return: HP, P, VAL1, VAL2 316 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> 317]>; 318 319// X86-32 Vectorcall return-value convention. 320def RetCC_X86_32_VectorCall : CallingConv<[ 321 // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3. 322 CCIfType<[f32, f64, f128], 323 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 324 325 // Return integers in the standard way. 326 CCDelegateTo<RetCC_X86Common> 327]>; 328 329// X86-64 C return-value convention. 330def RetCC_X86_64_C : CallingConv<[ 331 // The X86-64 calling convention always returns FP values in XMM0. 332 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>, 333 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>, 334 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>, 335 336 // MMX vector types are always returned in XMM0. 337 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>, 338 339 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 340 341 CCDelegateTo<RetCC_X86Common> 342]>; 343 344// X86-Win64 C return-value convention. 345def RetCC_X86_Win64_C : CallingConv<[ 346 // The X86-Win64 calling convention always returns __m64 values in RAX. 347 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 348 349 // Otherwise, everything is the same as 'normal' X86-64 C CC. 350 CCDelegateTo<RetCC_X86_64_C> 351]>; 352 353// X86-64 vectorcall return-value convention. 354def RetCC_X86_64_Vectorcall : CallingConv<[ 355 // Vectorcall calling convention always returns FP values in XMMs. 356 CCIfType<[f32, f64, f128], 357 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 358 359 // Otherwise, everything is the same as Windows X86-64 C CC. 360 CCDelegateTo<RetCC_X86_Win64_C> 361]>; 362 363// X86-64 HiPE return-value convention. 364def RetCC_X86_64_HiPE : CallingConv<[ 365 // Promote all types to i64 366 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 367 368 // Return: HP, P, VAL1, VAL2 369 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> 370]>; 371 372// X86-64 WebKit_JS return-value convention. 373def RetCC_X86_64_WebKit_JS : CallingConv<[ 374 // Promote all types to i64 375 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 376 377 // Return: RAX 378 CCIfType<[i64], CCAssignToReg<[RAX]>> 379]>; 380 381def RetCC_X86_64_Swift : CallingConv<[ 382 383 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 384 385 // For integers, ECX, R8D can be used as extra return registers. 386 CCIfType<[v1i1], CCPromoteToType<i8>>, 387 CCIfType<[i1], CCPromoteToType<i8>>, 388 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>, 389 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>, 390 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>, 391 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>, 392 393 // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values. 394 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 395 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 396 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 397 398 // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3. 399 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 400 CCDelegateTo<RetCC_X86Common> 401]>; 402 403// X86-64 AnyReg return-value convention. No explicit register is specified for 404// the return-value. The register allocator is allowed and expected to choose 405// any free register. 406// 407// This calling convention is currently only supported by the stackmap and 408// patchpoint intrinsics. All other uses will result in an assert on Debug 409// builds. On Release builds we fallback to the X86 C calling convention. 410def RetCC_X86_64_AnyReg : CallingConv<[ 411 CCCustom<"CC_X86_AnyReg_Error"> 412]>; 413 414// X86-64 HHVM return-value convention. 415def RetCC_X86_64_HHVM: CallingConv<[ 416 // Promote all types to i64 417 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 418 419 // Return: could return in any GP register save RSP and R12. 420 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9, 421 RAX, R10, R11, R13, R14, R15]>> 422]>; 423 424 425defm X86_32_RegCall : 426 X86_RegCall_base<RC_X86_32_RegCall>; 427defm X86_Win64_RegCall : 428 X86_RegCall_base<RC_X86_64_RegCall_Win>; 429defm X86_SysV64_RegCall : 430 X86_RegCall_base<RC_X86_64_RegCall_SysV>; 431 432// This is the root return-value convention for the X86-32 backend. 433def RetCC_X86_32 : CallingConv<[ 434 // If FastCC, use RetCC_X86_32_Fast. 435 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>, 436 CCIfCC<"CallingConv::Tail", CCDelegateTo<RetCC_X86_32_Fast>>, 437 // If HiPE, use RetCC_X86_32_HiPE. 438 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>, 439 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>, 440 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_32_RegCall>>, 441 442 // Otherwise, use RetCC_X86_32_C. 443 CCDelegateTo<RetCC_X86_32_C> 444]>; 445 446// This is the root return-value convention for the X86-64 backend. 447def RetCC_X86_64 : CallingConv<[ 448 // HiPE uses RetCC_X86_64_HiPE 449 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>, 450 451 // Handle JavaScript calls. 452 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>, 453 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>, 454 455 // Handle Swift calls. 456 CCIfCC<"CallingConv::Swift", CCDelegateTo<RetCC_X86_64_Swift>>, 457 458 // Handle explicit CC selection 459 CCIfCC<"CallingConv::Win64", CCDelegateTo<RetCC_X86_Win64_C>>, 460 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>, 461 462 // Handle Vectorcall CC 463 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_64_Vectorcall>>, 464 465 // Handle HHVM calls. 466 CCIfCC<"CallingConv::HHVM", CCDelegateTo<RetCC_X86_64_HHVM>>, 467 468 CCIfCC<"CallingConv::X86_RegCall", 469 CCIfSubtarget<"isTargetWin64()", 470 CCDelegateTo<RetCC_X86_Win64_RegCall>>>, 471 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_SysV64_RegCall>>, 472 473 // Mingw64 and native Win64 use Win64 CC 474 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>, 475 476 // Otherwise, drop to normal X86-64 CC 477 CCDelegateTo<RetCC_X86_64_C> 478]>; 479 480// This is the return-value convention used for the entire X86 backend. 481let Entry = 1 in 482def RetCC_X86 : CallingConv<[ 483 484 // Check if this is the Intel OpenCL built-ins calling convention 485 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>, 486 487 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>, 488 CCDelegateTo<RetCC_X86_32> 489]>; 490 491//===----------------------------------------------------------------------===// 492// X86-64 Argument Calling Conventions 493//===----------------------------------------------------------------------===// 494 495def CC_X86_64_C : CallingConv<[ 496 // Handles byval parameters. 497 CCIfByVal<CCPassByVal<8, 8>>, 498 499 // Promote i1/i8/i16/v1i1 arguments to i32. 500 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 501 502 // The 'nest' parameter, if any, is passed in R10. 503 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>, 504 CCIfNest<CCAssignToReg<[R10]>>, 505 506 // Pass SwiftSelf in a callee saved register. 507 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 508 509 // A SwiftError is passed in R12. 510 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 511 512 // For Swift Calling Convention, pass sret in %rax. 513 CCIfCC<"CallingConv::Swift", 514 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 515 516 // The first 6 integer arguments are passed in integer registers. 517 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, 518 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, 519 520 // The first 8 MMX vector arguments are passed in XMM registers on Darwin. 521 CCIfType<[x86mmx], 522 CCIfSubtarget<"isTargetDarwin()", 523 CCIfSubtarget<"hasSSE2()", 524 CCPromoteToType<v2i64>>>>, 525 526 // Boolean vectors of AVX-512 are passed in SIMD registers. 527 // The call from AVX to AVX-512 function should work, 528 // since the boolean types in AVX/AVX2 are promoted by default. 529 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 530 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 531 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 532 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 533 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 534 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 535 536 // The first 8 FP/Vector arguments are passed in XMM registers. 537 CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 538 CCIfSubtarget<"hasSSE1()", 539 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 540 541 // The first 8 256-bit vector arguments are passed in YMM registers, unless 542 // this is a vararg function. 543 // FIXME: This isn't precisely correct; the x86-64 ABI document says that 544 // fixed arguments to vararg functions are supposed to be passed in 545 // registers. Actually modeling that would be a lot of work, though. 546 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 547 CCIfSubtarget<"hasAVX()", 548 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, 549 YMM4, YMM5, YMM6, YMM7]>>>>, 550 551 // The first 8 512-bit vector arguments are passed in ZMM registers. 552 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 553 CCIfSubtarget<"hasAVX512()", 554 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>, 555 556 // Integer/FP values get stored in stack slots that are 8 bytes in size and 557 // 8-byte aligned if there are no more registers to hold them. 558 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, 559 560 // Long doubles get stack slots whose size and alignment depends on the 561 // subtarget. 562 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 563 564 // Vectors get 16-byte stack slots that are 16-byte aligned. 565 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, 566 567 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 568 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 569 CCAssignToStack<32, 32>>, 570 571 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 572 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 573 CCAssignToStack<64, 64>> 574]>; 575 576// Calling convention for X86-64 HHVM. 577def CC_X86_64_HHVM : CallingConv<[ 578 // Use all/any GP registers for args, except RSP. 579 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15, 580 RDI, RSI, RDX, RCX, R8, R9, 581 RAX, R10, R11, R13, R14]>> 582]>; 583 584// Calling convention for helper functions in HHVM. 585def CC_X86_64_HHVM_C : CallingConv<[ 586 // Pass the first argument in RBP. 587 CCIfType<[i64], CCAssignToReg<[RBP]>>, 588 589 // Otherwise it's the same as the regular C calling convention. 590 CCDelegateTo<CC_X86_64_C> 591]>; 592 593// Calling convention used on Win64 594def CC_X86_Win64_C : CallingConv<[ 595 // FIXME: Handle varargs. 596 597 // Byval aggregates are passed by pointer 598 CCIfByVal<CCPassIndirect<i64>>, 599 600 // Promote i1/v1i1 arguments to i8. 601 CCIfType<[i1, v1i1], CCPromoteToType<i8>>, 602 603 // The 'nest' parameter, if any, is passed in R10. 604 CCIfNest<CCAssignToReg<[R10]>>, 605 606 // A SwiftError is passed in R12. 607 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 608 609 // 128 bit vectors are passed by pointer 610 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>, 611 612 613 // 256 bit vectors are passed by pointer 614 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>, 615 616 // 512 bit vectors are passed by pointer 617 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>, 618 619 // Long doubles are passed by pointer 620 CCIfType<[f80], CCPassIndirect<i64>>, 621 622 // The first 4 MMX vector arguments are passed in GPRs. 623 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 624 625 // The first 4 integer arguments are passed in integer registers. 626 CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ], 627 [XMM0, XMM1, XMM2, XMM3]>>, 628 CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ], 629 [XMM0, XMM1, XMM2, XMM3]>>, 630 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], 631 [XMM0, XMM1, XMM2, XMM3]>>, 632 633 // Do not pass the sret argument in RCX, the Win64 thiscall calling 634 // convention requires "this" to be passed in RCX. 635 CCIfCC<"CallingConv::X86_ThisCall", 636 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ], 637 [XMM1, XMM2, XMM3]>>>>, 638 639 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], 640 [XMM0, XMM1, XMM2, XMM3]>>, 641 642 // The first 4 FP/Vector arguments are passed in XMM registers. 643 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 644 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3], 645 [RCX , RDX , R8 , R9 ]>>, 646 647 // Integer/FP values get stored in stack slots that are 8 bytes in size and 648 // 8-byte aligned if there are no more registers to hold them. 649 CCIfType<[i8, i16, i32, i64, f32, f64], CCAssignToStack<8, 8>> 650]>; 651 652def CC_X86_Win64_VectorCall : CallingConv<[ 653 CCCustom<"CC_X86_64_VectorCall">, 654 655 // Delegate to fastcall to handle integer types. 656 CCDelegateTo<CC_X86_Win64_C> 657]>; 658 659 660def CC_X86_64_GHC : CallingConv<[ 661 // Promote i8/i16/i32 arguments to i64. 662 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 663 664 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 665 CCIfType<[i64], 666 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>, 667 668 // Pass in STG registers: F1, F2, F3, F4, D1, D2 669 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 670 CCIfSubtarget<"hasSSE1()", 671 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, 672 // AVX 673 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 674 CCIfSubtarget<"hasAVX()", 675 CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>, 676 // AVX-512 677 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 678 CCIfSubtarget<"hasAVX512()", 679 CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>> 680]>; 681 682def CC_X86_64_HiPE : CallingConv<[ 683 // Promote i8/i16/i32 arguments to i64. 684 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 685 686 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3 687 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, 688 689 // Integer/FP values get stored in stack slots that are 8 bytes in size and 690 // 8-byte aligned if there are no more registers to hold them. 691 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>> 692]>; 693 694def CC_X86_64_WebKit_JS : CallingConv<[ 695 // Promote i8/i16 arguments to i32. 696 CCIfType<[i8, i16], CCPromoteToType<i32>>, 697 698 // Only the first integer argument is passed in register. 699 CCIfType<[i32], CCAssignToReg<[EAX]>>, 700 CCIfType<[i64], CCAssignToReg<[RAX]>>, 701 702 // The remaining integer arguments are passed on the stack. 32bit integer and 703 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots. 704 // 64bit integer and floating-point arguments are aligned to 8 byte and stored 705 // in 8 byte stack slots. 706 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 707 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 708]>; 709 710// No explicit register is specified for the AnyReg calling convention. The 711// register allocator may assign the arguments to any free register. 712// 713// This calling convention is currently only supported by the stackmap and 714// patchpoint intrinsics. All other uses will result in an assert on Debug 715// builds. On Release builds we fallback to the X86 C calling convention. 716def CC_X86_64_AnyReg : CallingConv<[ 717 CCCustom<"CC_X86_AnyReg_Error"> 718]>; 719 720//===----------------------------------------------------------------------===// 721// X86 C Calling Convention 722//===----------------------------------------------------------------------===// 723 724/// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector 725/// values are spilled on the stack. 726def CC_X86_32_Vector_Common : CallingConv<[ 727 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned. 728 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, 729 730 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned. 731 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 732 CCAssignToStack<32, 32>>, 733 734 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 735 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 736 CCAssignToStack<64, 64>> 737]>; 738 739// CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in 740// vector registers 741def CC_X86_32_Vector_Standard : CallingConv<[ 742 // SSE vector arguments are passed in XMM registers. 743 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 744 CCAssignToReg<[XMM0, XMM1, XMM2]>>>, 745 746 // AVX 256-bit vector arguments are passed in YMM registers. 747 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 748 CCIfSubtarget<"hasAVX()", 749 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>, 750 751 // AVX 512-bit vector arguments are passed in ZMM registers. 752 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 753 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>, 754 755 CCDelegateTo<CC_X86_32_Vector_Common> 756]>; 757 758// CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in 759// vector registers. 760def CC_X86_32_Vector_Darwin : CallingConv<[ 761 // SSE vector arguments are passed in XMM registers. 762 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 763 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>, 764 765 // AVX 256-bit vector arguments are passed in YMM registers. 766 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 767 CCIfSubtarget<"hasAVX()", 768 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>, 769 770 // AVX 512-bit vector arguments are passed in ZMM registers. 771 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 772 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>, 773 774 CCDelegateTo<CC_X86_32_Vector_Common> 775]>; 776 777/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP 778/// values are spilled on the stack. 779def CC_X86_32_Common : CallingConv<[ 780 // Handles byval parameters. 781 CCIfByVal<CCPassByVal<4, 4>>, 782 783 // The first 3 float or double arguments, if marked 'inreg' and if the call 784 // is not a vararg call and if SSE2 is available, are passed in SSE registers. 785 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], 786 CCIfSubtarget<"hasSSE2()", 787 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>, 788 789 // The first 3 __m64 vector arguments are passed in mmx registers if the 790 // call is not a vararg call. 791 CCIfNotVarArg<CCIfType<[x86mmx], 792 CCAssignToReg<[MM0, MM1, MM2]>>>, 793 794 // Integer/Float values get stored in stack slots that are 4 bytes in 795 // size and 4-byte aligned. 796 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 797 798 // Doubles get 8-byte slots that are 4-byte aligned. 799 CCIfType<[f64], CCAssignToStack<8, 4>>, 800 801 // Long doubles get slots whose size depends on the subtarget. 802 CCIfType<[f80], CCAssignToStack<0, 4>>, 803 804 // Boolean vectors of AVX-512 are passed in SIMD registers. 805 // The call from AVX to AVX-512 function should work, 806 // since the boolean types in AVX/AVX2 are promoted by default. 807 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 808 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 809 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 810 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 811 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 812 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 813 814 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are 815 // passed in the parameter area. 816 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 817 818 // Darwin passes vectors in a form that differs from the i386 psABI 819 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>, 820 821 // Otherwise, drop to 'normal' X86-32 CC 822 CCDelegateTo<CC_X86_32_Vector_Standard> 823]>; 824 825def CC_X86_32_C : CallingConv<[ 826 // Promote i1/i8/i16/v1i1 arguments to i32. 827 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 828 829 // The 'nest' parameter, if any, is passed in ECX. 830 CCIfNest<CCAssignToReg<[ECX]>>, 831 832 // The first 3 integer arguments, if marked 'inreg' and if the call is not 833 // a vararg call, are passed in integer registers. 834 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>, 835 836 // Otherwise, same as everything else. 837 CCDelegateTo<CC_X86_32_Common> 838]>; 839 840def CC_X86_32_MCU : CallingConv<[ 841 // Handles byval parameters. Note that, like FastCC, we can't rely on 842 // the delegation to CC_X86_32_Common because that happens after code that 843 // puts arguments in registers. 844 CCIfByVal<CCPassByVal<4, 4>>, 845 846 // Promote i1/i8/i16/v1i1 arguments to i32. 847 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 848 849 // If the call is not a vararg call, some arguments may be passed 850 // in integer registers. 851 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>, 852 853 // Otherwise, same as everything else. 854 CCDelegateTo<CC_X86_32_Common> 855]>; 856 857def CC_X86_32_FastCall : CallingConv<[ 858 // Promote i1 to i8. 859 CCIfType<[i1], CCPromoteToType<i8>>, 860 861 // The 'nest' parameter, if any, is passed in EAX. 862 CCIfNest<CCAssignToReg<[EAX]>>, 863 864 // The first 2 integer arguments are passed in ECX/EDX 865 CCIfInReg<CCIfType<[ i8], CCAssignToReg<[ CL, DL]>>>, 866 CCIfInReg<CCIfType<[i16], CCAssignToReg<[ CX, DX]>>>, 867 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>, 868 869 // Otherwise, same as everything else. 870 CCDelegateTo<CC_X86_32_Common> 871]>; 872 873def CC_X86_Win32_VectorCall : CallingConv<[ 874 // Pass floating point in XMMs 875 CCCustom<"CC_X86_32_VectorCall">, 876 877 // Delegate to fastcall to handle integer types. 878 CCDelegateTo<CC_X86_32_FastCall> 879]>; 880 881def CC_X86_32_ThisCall_Common : CallingConv<[ 882 // The first integer argument is passed in ECX 883 CCIfType<[i32], CCAssignToReg<[ECX]>>, 884 885 // Otherwise, same as everything else. 886 CCDelegateTo<CC_X86_32_Common> 887]>; 888 889def CC_X86_32_ThisCall_Mingw : CallingConv<[ 890 // Promote i1/i8/i16/v1i1 arguments to i32. 891 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 892 893 CCDelegateTo<CC_X86_32_ThisCall_Common> 894]>; 895 896def CC_X86_32_ThisCall_Win : CallingConv<[ 897 // Promote i1/i8/i16/v1i1 arguments to i32. 898 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 899 900 // Pass sret arguments indirectly through stack. 901 CCIfSRet<CCAssignToStack<4, 4>>, 902 903 CCDelegateTo<CC_X86_32_ThisCall_Common> 904]>; 905 906def CC_X86_32_ThisCall : CallingConv<[ 907 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>, 908 CCDelegateTo<CC_X86_32_ThisCall_Win> 909]>; 910 911def CC_X86_32_FastCC : CallingConv<[ 912 // Handles byval parameters. Note that we can't rely on the delegation 913 // to CC_X86_32_Common for this because that happens after code that 914 // puts arguments in registers. 915 CCIfByVal<CCPassByVal<4, 4>>, 916 917 // Promote i1/i8/i16/v1i1 arguments to i32. 918 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 919 920 // The 'nest' parameter, if any, is passed in EAX. 921 CCIfNest<CCAssignToReg<[EAX]>>, 922 923 // The first 2 integer arguments are passed in ECX/EDX 924 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>, 925 926 // The first 3 float or double arguments, if the call is not a vararg 927 // call and if SSE2 is available, are passed in SSE registers. 928 CCIfNotVarArg<CCIfType<[f32,f64], 929 CCIfSubtarget<"hasSSE2()", 930 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 931 932 // Doubles get 8-byte slots that are 8-byte aligned. 933 CCIfType<[f64], CCAssignToStack<8, 8>>, 934 935 // Otherwise, same as everything else. 936 CCDelegateTo<CC_X86_32_Common> 937]>; 938 939def CC_X86_32_GHC : CallingConv<[ 940 // Promote i8/i16 arguments to i32. 941 CCIfType<[i8, i16], CCPromoteToType<i32>>, 942 943 // Pass in STG registers: Base, Sp, Hp, R1 944 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>> 945]>; 946 947def CC_X86_32_HiPE : CallingConv<[ 948 // Promote i8/i16 arguments to i32. 949 CCIfType<[i8, i16], CCPromoteToType<i32>>, 950 951 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2 952 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>, 953 954 // Integer/Float values get stored in stack slots that are 4 bytes in 955 // size and 4-byte aligned. 956 CCIfType<[i32, f32], CCAssignToStack<4, 4>> 957]>; 958 959// X86-64 Intel OpenCL built-ins calling convention. 960def CC_Intel_OCL_BI : CallingConv<[ 961 962 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>, 963 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>, 964 965 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>, 966 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>, 967 968 CCIfType<[i32], CCAssignToStack<4, 4>>, 969 970 // The SSE vector arguments are passed in XMM registers. 971 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 972 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 973 974 // The 256-bit vector arguments are passed in YMM registers. 975 CCIfType<[v8f32, v4f64, v8i32, v4i64], 976 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>, 977 978 // The 512-bit vector arguments are passed in ZMM registers. 979 CCIfType<[v16f32, v8f64, v16i32, v8i64], 980 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>, 981 982 // Pass masks in mask registers 983 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>, 984 985 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 986 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>, 987 CCDelegateTo<CC_X86_32_C> 988]>; 989 990//===----------------------------------------------------------------------===// 991// X86 Root Argument Calling Conventions 992//===----------------------------------------------------------------------===// 993 994// This is the root argument convention for the X86-32 backend. 995def CC_X86_32 : CallingConv<[ 996 // X86_INTR calling convention is valid in MCU target and should override the 997 // MCU calling convention. Thus, this should be checked before isTargetMCU(). 998 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 999 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>, 1000 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>, 1001 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win32_VectorCall>>, 1002 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>, 1003 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>, 1004 CCIfCC<"CallingConv::Tail", CCDelegateTo<CC_X86_32_FastCC>>, 1005 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>, 1006 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>, 1007 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>, 1008 1009 // Otherwise, drop to normal X86-32 CC 1010 CCDelegateTo<CC_X86_32_C> 1011]>; 1012 1013// This is the root argument convention for the X86-64 backend. 1014def CC_X86_64 : CallingConv<[ 1015 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>, 1016 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>, 1017 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>, 1018 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>, 1019 CCIfCC<"CallingConv::Win64", CCDelegateTo<CC_X86_Win64_C>>, 1020 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>, 1021 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>, 1022 CCIfCC<"CallingConv::HHVM", CCDelegateTo<CC_X86_64_HHVM>>, 1023 CCIfCC<"CallingConv::HHVM_C", CCDelegateTo<CC_X86_64_HHVM_C>>, 1024 CCIfCC<"CallingConv::X86_RegCall", 1025 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_RegCall>>>, 1026 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_SysV64_RegCall>>, 1027 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1028 1029 // Mingw64 and native Win64 use Win64 CC 1030 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1031 1032 // Otherwise, drop to normal X86-64 CC 1033 CCDelegateTo<CC_X86_64_C> 1034]>; 1035 1036// This is the argument convention used for the entire X86 backend. 1037let Entry = 1 in 1038def CC_X86 : CallingConv<[ 1039 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>, 1040 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>, 1041 CCDelegateTo<CC_X86_32> 1042]>; 1043 1044//===----------------------------------------------------------------------===// 1045// Callee-saved Registers. 1046//===----------------------------------------------------------------------===// 1047 1048def CSR_NoRegs : CalleeSavedRegs<(add)>; 1049 1050def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1051def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>; 1052 1053def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>; 1054 1055def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>; 1056def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>; 1057 1058def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>; 1059 1060def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE, 1061 (sequence "XMM%u", 6, 15))>; 1062 1063def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>; 1064 1065// The function used by Darwin to obtain the address of a thread-local variable 1066// uses rdi to pass a single parameter and rax for the return value. All other 1067// GPRs are preserved. 1068def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI, 1069 R8, R9, R10, R11)>; 1070 1071// CSRs that are handled by prologue, epilogue. 1072def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>; 1073 1074// CSRs that are handled explicitly via copies. 1075def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>; 1076 1077// All GPRs - except r11 1078def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, 1079 R8, R9, R10, RSP)>; 1080 1081// All registers - except r11 1082def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1083 (sequence "XMM%u", 0, 15))>; 1084def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1085 (sequence "YMM%u", 0, 15))>; 1086 1087def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10, 1088 R11, R12, R13, R14, R15, RBP, 1089 (sequence "XMM%u", 0, 15))>; 1090 1091def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI, 1092 EDI)>; 1093def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs, 1094 (sequence "XMM%u", 0, 7))>; 1095def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs, 1096 (sequence "YMM%u", 0, 7))>; 1097def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs, 1098 (sequence "ZMM%u", 0, 7), 1099 (sequence "K%u", 0, 7))>; 1100 1101def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>; 1102def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9, 1103 R10, R11, R12, R13, R14, R15, RBP)>; 1104def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1105 (sequence "YMM%u", 0, 15)), 1106 (sequence "XMM%u", 0, 15))>; 1107def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1108 (sequence "ZMM%u", 0, 31), 1109 (sequence "K%u", 0, 7)), 1110 (sequence "XMM%u", 0, 15))>; 1111 1112// Standard C + YMM6-15 1113def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, 1114 R13, R14, R15, 1115 (sequence "YMM%u", 6, 15))>; 1116 1117def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, 1118 R12, R13, R14, R15, 1119 (sequence "ZMM%u", 6, 21), 1120 K4, K5, K6, K7)>; 1121//Standard C + XMM 8-15 1122def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64, 1123 (sequence "XMM%u", 8, 15))>; 1124 1125//Standard C + YMM 8-15 1126def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64, 1127 (sequence "YMM%u", 8, 15))>; 1128 1129def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15, 1130 (sequence "ZMM%u", 16, 31), 1131 K4, K5, K6, K7)>; 1132 1133// Only R12 is preserved for PHP calls in HHVM. 1134def CSR_64_HHVM : CalleeSavedRegs<(add R12)>; 1135 1136// Register calling convention preserves few GPR and XMM8-15 1137def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP, ESP)>; 1138def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, 1139 (sequence "XMM%u", 4, 7))>; 1140def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP, 1141 (sequence "R%u", 10, 15))>; 1142def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE, 1143 (sequence "XMM%u", 8, 15))>; 1144def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP, 1145 (sequence "R%u", 12, 15))>; 1146def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE, 1147 (sequence "XMM%u", 8, 15))>; 1148 1149